[linux-block.git] / drivers / media / i2c / vpx3220.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * vpx3220a, vpx3216b & vpx3214c video decoder driver version 0.0.1
 *
 * Copyright (C) 2001 Laurent Pinchart <lpinchart@freegates.be>
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <linux/i2c.h>
#include <linux/videodev2.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ctrls.h>

MODULE_DESCRIPTION("vpx3220a/vpx3216b/vpx3214c video decoder driver");
MODULE_AUTHOR("Laurent Pinchart");
MODULE_LICENSE("GPL");

static int debug;
module_param(debug, int, 0);
MODULE_PARM_DESC(debug, "Debug level (0-1)");


#define VPX_TIMEOUT_COUNT  10

/* ----------------------------------------------------------------------- */

struct vpx3220 {
	struct v4l2_subdev sd;
	struct v4l2_ctrl_handler hdl;
	unsigned char reg[255];

	v4l2_std_id norm;
	int input;
	int enable;
};

static inline struct vpx3220 *to_vpx3220(struct v4l2_subdev *sd)
{
	return container_of(sd, struct vpx3220, sd);
}

static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
{
	return &container_of(ctrl->handler, struct vpx3220, hdl)->sd;
}

static char *inputs[] = { "internal", "composite", "svideo" };

/* ----------------------------------------------------------------------- */

static inline int vpx3220_write(struct v4l2_subdev *sd, u8 reg, u8 value)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);
	struct vpx3220 *decoder = i2c_get_clientdata(client);

	decoder->reg[reg] = value;
	return i2c_smbus_write_byte_data(client, reg, value);
}

static inline int vpx3220_read(struct v4l2_subdev *sd, u8 reg)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);

	return i2c_smbus_read_byte_data(client, reg);
}

static int vpx3220_fp_status(struct v4l2_subdev *sd)
{
	unsigned char status;
	unsigned int i;

	for (i = 0; i < VPX_TIMEOUT_COUNT; i++) {
		status = vpx3220_read(sd, 0x29);

		if (!(status & 4))
			return 0;

		udelay(10);

		if (need_resched())
			cond_resched();
	}

	return -1;
}

static int vpx3220_fp_write(struct v4l2_subdev *sd, u8 fpaddr, u16 data)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);

	/* Write the 16-bit address to the FPWR register */
	if (i2c_smbus_write_word_data(client, 0x27, swab16(fpaddr)) == -1) {
		v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
		return -1;
	}

	if (vpx3220_fp_status(sd) < 0)
		return -1;

	/* Write the 16-bit data to the FPDAT register */
	if (i2c_smbus_write_word_data(client, 0x28, swab16(data)) == -1) {
		v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
		return -1;
	}

	return 0;
}

static int vpx3220_fp_read(struct v4l2_subdev *sd, u16 fpaddr)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);
	s16 data;

	/* Write the 16-bit address to the FPRD register */
	if (i2c_smbus_write_word_data(client, 0x26, swab16(fpaddr)) == -1) {
		v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
		return -1;
	}

	if (vpx3220_fp_status(sd) < 0)
		return -1;

	/* Read the 16-bit data from the FPDAT register */
	data = i2c_smbus_read_word_data(client, 0x28);
	if (data == -1) {
		v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
		return -1;
	}

	return swab16(data);
}

static int vpx3220_write_block(struct v4l2_subdev *sd, const u8 *data, unsigned int len)
{
	u8 reg;
	int ret = -1;

	while (len >= 2) {
		reg = *data++;
		ret = vpx3220_write(sd, reg, *data++);
		if (ret < 0)
			break;
		len -= 2;
	}

	return ret;
}

static int vpx3220_write_fp_block(struct v4l2_subdev *sd,
		const u16 *data, unsigned int len)
{
	u8 reg;
	int ret = 0;

	while (len > 1) {
		reg = *data++;
		ret |= vpx3220_fp_write(sd, reg, *data++);
		len -= 2;
	}

	return ret;
}

/* ---------------------------------------------------------------------- */

static const unsigned short init_ntsc[] = {
	0x1c, 0x00,		/* NTSC tint angle */
	0x88, 17,		/* Window 1 vertical */
	0x89, 240,		/* Vertical lines in */
	0x8a, 240,		/* Vertical lines out */
	0x8b, 000,		/* Horizontal begin */
	0x8c, 640,		/* Horizontal length */
	0x8d, 640,		/* Number of pixels */
	0x8f, 0xc00,		/* Disable window 2 */
	0xf0, 0x73,		/* 13.5 MHz transport, Forced
				 * mode, latch windows */
	0xf2, 0x13,		/* NTSC M, composite input */
	0xe7, 0x1e1,		/* Enable vertical standard
				 * locking @ 240 lines */
};

static const unsigned short init_pal[] = {
	0x88, 23,		/* Window 1 vertical begin */
	0x89, 288,		/* Vertical lines in (16 lines
				 * skipped by the VFE) */
	0x8a, 288,		/* Vertical lines out (16 lines
				 * skipped by the VFE) */
	0x8b, 16,		/* Horizontal begin */
	0x8c, 768,		/* Horizontal length */
	0x8d, 784,		/* Number of pixels
				 * Must be >= Horizontal begin + Horizontal length */
	0x8f, 0xc00,		/* Disable window 2 */
	0xf0, 0x77,		/* 13.5 MHz transport, Forced
				 * mode, latch windows */
	0xf2, 0x3d1,		/* PAL B,G,H,I, composite input */
	0xe7, 0x241,		/* PAL/SECAM set to 288 lines */
};

static const unsigned short init_secam[] = {
	0x88, 23,		/* Window 1 vertical begin */
	0x89, 288,		/* Vertical lines in (16 lines
				 * skipped by the VFE) */
	0x8a, 288,		/* Vertical lines out (16 lines
				 * skipped by the VFE) */
	0x8b, 16,		/* Horizontal begin */
	0x8c, 768,		/* Horizontal length */
	0x8d, 784,		/* Number of pixels
				 * Must be >= Horizontal begin + Horizontal length */
	0x8f, 0xc00,		/* Disable window 2 */
	0xf0, 0x77,		/* 13.5 MHz transport, Forced
				 * mode, latch windows */
	0xf2, 0x3d5,		/* SECAM, composite input */
	0xe7, 0x241,		/* PAL/SECAM set to 288 lines */
};

static const unsigned char init_common[] = {
	0xf2, 0x00,		/* Disable all outputs */
	0x33, 0x0d,		/* Luma : VIN2, Chroma : CIN
				 * (clamp off) */
	0xd8, 0xa8,		/* HREF/VREF active high, VREF
				 * pulse = 2, Odd/Even flag */
	0x20, 0x03,		/* IF compensation 0dB/oct */
	0xe0, 0xff,		/* Open up all comparators */
	0xe1, 0x00,
	0xe2, 0x7f,
	0xe3, 0x80,
	0xe4, 0x7f,
	0xe5, 0x80,
	0xe6, 0x00,		/* Brightness set to 0 */
	0xe7, 0xe0,		/* Contrast to 1.0, noise shaping
				 * 10 to 8 2-bit error diffusion */
	0xe8, 0xf8,		/* YUV422, CbCr binary offset,
				 * ... (p.32) */
	0xea, 0x18,		/* LLC2 connected, output FIFO
				 * reset with VACTintern */
	0xf0, 0x8a,		/* Half full level to 10, bus
				 * shuffler [7:0, 23:16, 15:8] */
	0xf1, 0x18,		/* Single clock, sync mode, no
				 * FE delay, no HLEN counter */
	0xf8, 0x12,		/* Port A, PIXCLK, HF# & FE#
				 * strength to 2 */
	0xf9, 0x24,		/* Port B, HREF, VREF, PREF &
				 * ALPHA strength to 4 */
};

static const unsigned short init_fp[] = {
	0x59, 0,
	0xa0, 2070,		/* ACC reference */
	0xa3, 0,
	0xa4, 0,
	0xa8, 30,
	0xb2, 768,
	0xbe, 27,
	0x58, 0,
	0x26, 0,
	0x4b, 0x298,		/* PLL gain */
};


static int vpx3220_init(struct v4l2_subdev *sd, u32 val)
{
	struct vpx3220 *decoder = to_vpx3220(sd);

	vpx3220_write_block(sd, init_common, sizeof(init_common));
	vpx3220_write_fp_block(sd, init_fp, sizeof(init_fp) >> 1);
	if (decoder->norm & V4L2_STD_NTSC)
		vpx3220_write_fp_block(sd, init_ntsc, sizeof(init_ntsc) >> 1);
	else if (decoder->norm & V4L2_STD_PAL)
		vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
	else if (decoder->norm & V4L2_STD_SECAM)
		vpx3220_write_fp_block(sd, init_secam, sizeof(init_secam) >> 1);
	else
		vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
	return 0;
}

static int vpx3220_status(struct v4l2_subdev *sd, u32 *pstatus, v4l2_std_id *pstd)
{
	int res = V4L2_IN_ST_NO_SIGNAL, status;
	v4l2_std_id std = pstd ? *pstd : V4L2_STD_ALL;

	status = vpx3220_fp_read(sd, 0x0f3);

	v4l2_dbg(1, debug, sd, "status: 0x%04x\n", status);

	if (status < 0)
		return status;

	if ((status & 0x20) == 0) {
		res = 0;

		switch (status & 0x18) {
		case 0x00:
		case 0x10:
		case 0x14:
		case 0x18:
			std &= V4L2_STD_PAL;
			break;

		case 0x08:
			std &= V4L2_STD_SECAM;
			break;

		case 0x04:
		case 0x0c:
		case 0x1c:
			std &= V4L2_STD_NTSC;
			break;
		}
	} else {
		std = V4L2_STD_UNKNOWN;
	}
	if (pstd)
		*pstd = std;
	if (pstatus)
		*pstatus = res;
	return 0;
}

static int vpx3220_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
{
	v4l2_dbg(1, debug, sd, "querystd\n");
	return vpx3220_status(sd, NULL, std);
}

static int vpx3220_g_input_status(struct v4l2_subdev *sd, u32 *status)
{
	v4l2_dbg(1, debug, sd, "g_input_status\n");
	return vpx3220_status(sd, status, NULL);
}

static int vpx3220_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
{
	struct vpx3220 *decoder = to_vpx3220(sd);
	int temp_input;

	/* Here we back up the input selection because it gets
	   overwritten when we fill the registers with the
	   chosen video norm */
	temp_input = vpx3220_fp_read(sd, 0xf2);

	v4l2_dbg(1, debug, sd, "s_std %llx\n", (unsigned long long)std);
	if (std & V4L2_STD_NTSC) {
		vpx3220_write_fp_block(sd, init_ntsc, sizeof(init_ntsc) >> 1);
		v4l2_dbg(1, debug, sd, "norm switched to NTSC\n");
	} else if (std & V4L2_STD_PAL) {
		vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
		v4l2_dbg(1, debug, sd, "norm switched to PAL\n");
	} else if (std & V4L2_STD_SECAM) {
		vpx3220_write_fp_block(sd, init_secam, sizeof(init_secam) >> 1);
		v4l2_dbg(1, debug, sd, "norm switched to SECAM\n");
	} else {
		return -EINVAL;
	}

	decoder->norm = std;

	/* And here we set the backed up video input again */
	vpx3220_fp_write(sd, 0xf2, temp_input | 0x0010);
	udelay(10);
	return 0;
}

static int vpx3220_s_routing(struct v4l2_subdev *sd,
			     u32 input, u32 output, u32 config)
{
	int data;

	/* RJ:   input = 0: ST8 (PCTV) input
		 input = 1: COMPOSITE  input
		 input = 2: SVHS       input  */

	static const int input_vals[3][2] = {
		{0x0c, 0},
		{0x0d, 0},
		{0x0e, 1}
	};

	if (input > 2)
		return -EINVAL;

	v4l2_dbg(1, debug, sd, "input switched to %s\n", inputs[input]);

	vpx3220_write(sd, 0x33, input_vals[input][0]);

	data = vpx3220_fp_read(sd, 0xf2) & ~(0x0020);
	if (data < 0)
		return data;
	/* 0x0010 is required to latch the setting */
	vpx3220_fp_write(sd, 0xf2,
			data | (input_vals[input][1] << 5) | 0x0010);

	udelay(10);
	return 0;
}

static int vpx3220_s_stream(struct v4l2_subdev *sd, int enable)
{
	v4l2_dbg(1, debug, sd, "s_stream %s\n", enable ? "on" : "off");

	vpx3220_write(sd, 0xf2, (enable ? 0x1b : 0x00));
	return 0;
}

static int vpx3220_s_ctrl(struct v4l2_ctrl *ctrl)
{
	struct v4l2_subdev *sd = to_sd(ctrl);

	switch (ctrl->id) {
	case V4L2_CID_BRIGHTNESS:
		vpx3220_write(sd, 0xe6, ctrl->val);
		return 0;
	case V4L2_CID_CONTRAST:
		/* Bit 7 and 8 is for noise shaping */
		vpx3220_write(sd, 0xe7, ctrl->val + 192);
		return 0;
	case V4L2_CID_SATURATION:
		vpx3220_fp_write(sd, 0xa0, ctrl->val);
		return 0;
	case V4L2_CID_HUE:
		vpx3220_fp_write(sd, 0x1c, ctrl->val);
		return 0;
	}
	return -EINVAL;
}

/* ----------------------------------------------------------------------- */

static const struct v4l2_ctrl_ops vpx3220_ctrl_ops = {
	.s_ctrl = vpx3220_s_ctrl,
};

static const struct v4l2_subdev_core_ops vpx3220_core_ops = {
	.init = vpx3220_init,
};

static const struct v4l2_subdev_video_ops vpx3220_video_ops = {
	.s_std = vpx3220_s_std,
	.s_routing = vpx3220_s_routing,
	.s_stream = vpx3220_s_stream,
	.querystd = vpx3220_querystd,
	.g_input_status = vpx3220_g_input_status,
};

static const struct v4l2_subdev_ops vpx3220_ops = {
	.core = &vpx3220_core_ops,
	.video = &vpx3220_video_ops,
};

/* -----------------------------------------------------------------------
 * Client management code
 */

static int vpx3220_probe(struct i2c_client *client)
{
	struct vpx3220 *decoder;
	struct v4l2_subdev *sd;
	const char *name = NULL;
	u8 ver;
	u16 pn;

	/* Check if the adapter supports the needed features */
	if (!i2c_check_functionality(client->adapter,
		I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA))
		return -ENODEV;

	decoder = devm_kzalloc(&client->dev, sizeof(*decoder), GFP_KERNEL);
	if (decoder == NULL)
		return -ENOMEM;
	sd = &decoder->sd;
	v4l2_i2c_subdev_init(sd, client, &vpx3220_ops);
	decoder->norm = V4L2_STD_PAL;
	decoder->input = 0;
	decoder->enable = 1;
	v4l2_ctrl_handler_init(&decoder->hdl, 4);
	v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
		V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
	v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
		V4L2_CID_CONTRAST, 0, 63, 1, 32);
	v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
		V4L2_CID_SATURATION, 0, 4095, 1, 2048);
	v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
		V4L2_CID_HUE, -512, 511, 1, 0);
	sd->ctrl_handler = &decoder->hdl;
	if (decoder->hdl.error) {
		int err = decoder->hdl.error;

		v4l2_ctrl_handler_free(&decoder->hdl);
		return err;
	}
	v4l2_ctrl_handler_setup(&decoder->hdl);

	ver = i2c_smbus_read_byte_data(client, 0x00);
	pn = (i2c_smbus_read_byte_data(client, 0x02) << 8) +
		i2c_smbus_read_byte_data(client, 0x01);
	if (ver == 0xec) {
		switch (pn) {
		case 0x4680:
			name = "vpx3220a";
			break;
		case 0x4260:
			name = "vpx3216b";
			break;
		case 0x4280:
			name = "vpx3214c";
			break;
		}
	}
	if (name)
		v4l2_info(sd, "%s found @ 0x%x (%s)\n", name,
			client->addr << 1, client->adapter->name);
	else
		v4l2_info(sd, "chip (%02x:%04x) found @ 0x%x (%s)\n",
			ver, pn, client->addr << 1, client->adapter->name);

	vpx3220_write_block(sd, init_common, sizeof(init_common));
	vpx3220_write_fp_block(sd, init_fp, sizeof(init_fp) >> 1);
	/* Default to PAL */
	vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
	return 0;
}

static void vpx3220_remove(struct i2c_client *client)
{
	struct v4l2_subdev *sd = i2c_get_clientdata(client);
	struct vpx3220 *decoder = to_vpx3220(sd);

	v4l2_device_unregister_subdev(sd);
	v4l2_ctrl_handler_free(&decoder->hdl);
}

static const struct i2c_device_id vpx3220_id[] = {
	{ "vpx3220a" },
	{ "vpx3216b" },
	{ "vpx3214c" },
	{ }
};
MODULE_DEVICE_TABLE(i2c, vpx3220_id);

static struct i2c_driver vpx3220_driver = {
	.driver = {
		.name	= "vpx3220",
	},
	.probe		= vpx3220_probe,
	.remove		= vpx3220_remove,
	.id_table	= vpx3220_id,
};

module_i2c_driver(vpx3220_driver);
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
d56410e0	2	/*
1da177e4 LT	3	* vpx3220a, vpx3216b & vpx3214c video decoder driver version 0.0.1
	4	*
	5	* Copyright (C) 2001 Laurent Pinchart <lpinchart@freegates.be>
1da177e4 LT	6	*/
	7
	8	#include <linux/module.h>
	9	#include <linux/init.h>
	10	#include <linux/delay.h>
	11	#include <linux/types.h>
5a0e3ad6	12	#include <linux/slab.h>
7c0f6ba6	13	#include <linux/uaccess.h>
1da177e4	14	#include <linux/i2c.h>
107063c6	15	#include <linux/videodev2.h>
7e5eaadc	16	#include <media/v4l2-device.h>
9a775323	17	#include <media/v4l2-ctrls.h>
1da177e4	18
23848b65 HV	19	MODULE_DESCRIPTION("vpx3220a/vpx3216b/vpx3214c video decoder driver");
	20	MODULE_AUTHOR("Laurent Pinchart");
	21	MODULE_LICENSE("GPL");
1da177e4	22
ff699e6b	23	static int debug;
1da177e4 LT	24	module_param(debug, int, 0);
	25	MODULE_PARM_DESC(debug, "Debug level (0-1)");
	26
7e5eaadc	27
1da177e4 LT	28	#define VPX_TIMEOUT_COUNT 10
	29
	30	/* ----------------------------------------------------------------------- */
	31
	32	struct vpx3220 {
7e5eaadc	33	struct v4l2_subdev sd;
9a775323	34	struct v4l2_ctrl_handler hdl;
1da177e4 LT	35	unsigned char reg[255];
1da177e4 LT	36
107063c6	37	v4l2_std_id norm;
1da177e4 LT	38	int input;
1da177e4 LT	39	int enable;
1da177e4 LT	40	};
1da177e4 LT	41
7e5eaadc HV	42	static inline struct vpx3220 to_vpx3220(struct v4l2_subdev sd)
	43	{
	44	return container_of(sd, struct vpx3220, sd);
	45	}
	46
9a775323 HV	47	static inline struct v4l2_subdev to_sd(struct v4l2_ctrl ctrl)
	48	{
	49	return &container_of(ctrl->handler, struct vpx3220, hdl)->sd;
	50	}
	51
1da177e4 LT	52	static char *inputs[] = { "internal", "composite", "svideo" };
	53
	54	/* ----------------------------------------------------------------------- */
23848b65	55
7e5eaadc	56	static inline int vpx3220_write(struct v4l2_subdev *sd, u8 reg, u8 value)
1da177e4	57	{
7e5eaadc	58	struct i2c_client *client = v4l2_get_subdevdata(sd);
1da177e4 LT	59	struct vpx3220 *decoder = i2c_get_clientdata(client);
	60
	61	decoder->reg[reg] = value;
	62	return i2c_smbus_write_byte_data(client, reg, value);
	63	}
	64
7e5eaadc	65	static inline int vpx3220_read(struct v4l2_subdev *sd, u8 reg)
1da177e4	66	{
7e5eaadc HV	67	struct i2c_client *client = v4l2_get_subdevdata(sd);
7e5eaadc HV	68
1da177e4 LT	69	return i2c_smbus_read_byte_data(client, reg);
	70	}
	71
7e5eaadc	72	static int vpx3220_fp_status(struct v4l2_subdev *sd)
1da177e4 LT	73	{
	74	unsigned char status;
	75	unsigned int i;
	76
	77	for (i = 0; i < VPX_TIMEOUT_COUNT; i++) {
7e5eaadc	78	status = vpx3220_read(sd, 0x29);
1da177e4 LT	79
	80	if (!(status & 4))
	81	return 0;
	82
	83	udelay(10);
	84
	85	if (need_resched())
	86	cond_resched();
	87	}
	88
	89	return -1;
	90	}
	91
7e5eaadc	92	static int vpx3220_fp_write(struct v4l2_subdev *sd, u8 fpaddr, u16 data)
1da177e4	93	{
7e5eaadc HV	94	struct i2c_client *client = v4l2_get_subdevdata(sd);
7e5eaadc HV	95
1da177e4 LT	96	/* Write the 16-bit address to the FPWR register */
1da177e4 LT	97	if (i2c_smbus_write_word_data(client, 0x27, swab16(fpaddr)) == -1) {
7e5eaadc	98	v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
1da177e4 LT	99	return -1;
	100	}
	101
7e5eaadc	102	if (vpx3220_fp_status(sd) < 0)
1da177e4 LT	103	return -1;
	104
	105	/* Write the 16-bit data to the FPDAT register */
	106	if (i2c_smbus_write_word_data(client, 0x28, swab16(data)) == -1) {
7e5eaadc	107	v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
1da177e4 LT	108	return -1;
	109	}
	110
	111	return 0;
	112	}
	113
39de7d95	114	static int vpx3220_fp_read(struct v4l2_subdev *sd, u16 fpaddr)
1da177e4	115	{
7e5eaadc	116	struct i2c_client *client = v4l2_get_subdevdata(sd);
1da177e4 LT	117	s16 data;
	118
	119	/* Write the 16-bit address to the FPRD register */
	120	if (i2c_smbus_write_word_data(client, 0x26, swab16(fpaddr)) == -1) {
7e5eaadc	121	v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
1da177e4 LT	122	return -1;
	123	}
	124
7e5eaadc	125	if (vpx3220_fp_status(sd) < 0)
1da177e4 LT	126	return -1;
	127
	128	/* Read the 16-bit data from the FPDAT register */
	129	data = i2c_smbus_read_word_data(client, 0x28);
	130	if (data == -1) {
7e5eaadc	131	v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
1da177e4 LT	132	return -1;
	133	}
	134
	135	return swab16(data);
	136	}
	137
7e5eaadc	138	static int vpx3220_write_block(struct v4l2_subdev sd, const u8 data, unsigned int len)
1da177e4 LT	139	{
	140	u8 reg;
	141	int ret = -1;
	142
	143	while (len >= 2) {
	144	reg = *data++;
7e5eaadc	145	ret = vpx3220_write(sd, reg, *data++);
23848b65	146	if (ret < 0)
1da177e4 LT	147	break;
	148	len -= 2;
	149	}
	150
	151	return ret;
	152	}
	153
7e5eaadc	154	static int vpx3220_write_fp_block(struct v4l2_subdev *sd,
23848b65	155	const u16 *data, unsigned int len)
1da177e4 LT	156	{
	157	u8 reg;
	158	int ret = 0;
	159
	160	while (len > 1) {
	161	reg = *data++;
7e5eaadc	162	ret \|= vpx3220_fp_write(sd, reg, *data++);
1da177e4 LT	163	len -= 2;
	164	}
	165
	166	return ret;
	167	}
	168
	169	/* ---------------------------------------------------------------------- */
	170
	171	static const unsigned short init_ntsc[] = {
	172	0x1c, 0x00, /* NTSC tint angle */
	173	0x88, 17, /* Window 1 vertical */
	174	0x89, 240, /* Vertical lines in */
	175	0x8a, 240, /* Vertical lines out */
	176	0x8b, 000, /* Horizontal begin */
	177	0x8c, 640, /* Horizontal length */
	178	0x8d, 640, /* Number of pixels */
	179	0x8f, 0xc00, /* Disable window 2 */
9b3acc21	180	0xf0, 0x73, /* 13.5 MHz transport, Forced
1da177e4 LT	181	* mode, latch windows */
	182	0xf2, 0x13, /* NTSC M, composite input */
	183	0xe7, 0x1e1, /* Enable vertical standard
	184	* locking @ 240 lines */
	185	};
	186
	187	static const unsigned short init_pal[] = {
	188	0x88, 23, /* Window 1 vertical begin */
9b3acc21	189	0x89, 288, /* Vertical lines in (16 lines
1da177e4	190	* skipped by the VFE) */
9b3acc21	191	0x8a, 288, /* Vertical lines out (16 lines
1da177e4 LT	192	* skipped by the VFE) */
	193	0x8b, 16, /* Horizontal begin */
	194	0x8c, 768, /* Horizontal length */
6e6a8b5a	195	0x8d, 784, /* Number of pixels
1da177e4 LT	196	* Must be >= Horizontal begin + Horizontal length */
1da177e4 LT	197	0x8f, 0xc00, /* Disable window 2 */
9b3acc21	198	0xf0, 0x77, /* 13.5 MHz transport, Forced
1da177e4 LT	199	* mode, latch windows */
1da177e4 LT	200	0xf2, 0x3d1, /* PAL B,G,H,I, composite input */
9b3acc21	201	0xe7, 0x241, /* PAL/SECAM set to 288 lines */
1da177e4 LT	202	};
	203
	204	static const unsigned short init_secam[] = {
9b3acc21 RB	205	0x88, 23, /* Window 1 vertical begin */
9b3acc21 RB	206	0x89, 288, /* Vertical lines in (16 lines
1da177e4	207	* skipped by the VFE) */
9b3acc21	208	0x8a, 288, /* Vertical lines out (16 lines
1da177e4 LT	209	* skipped by the VFE) */
	210	0x8b, 16, /* Horizontal begin */
	211	0x8c, 768, /* Horizontal length */
	212	0x8d, 784, /* Number of pixels
	213	* Must be >= Horizontal begin + Horizontal length */
	214	0x8f, 0xc00, /* Disable window 2 */
9b3acc21	215	0xf0, 0x77, /* 13.5 MHz transport, Forced
1da177e4 LT	216	* mode, latch windows */
1da177e4 LT	217	0xf2, 0x3d5, /* SECAM, composite input */
9b3acc21	218	0xe7, 0x241, /* PAL/SECAM set to 288 lines */
1da177e4 LT	219	};
	220
	221	static const unsigned char init_common[] = {
	222	0xf2, 0x00, /* Disable all outputs */
	223	0x33, 0x0d, /* Luma : VIN2, Chroma : CIN
	224	* (clamp off) */
	225	0xd8, 0xa8, /* HREF/VREF active high, VREF
	226	* pulse = 2, Odd/Even flag */
	227	0x20, 0x03, /* IF compensation 0dB/oct */
	228	0xe0, 0xff, /* Open up all comparators */
	229	0xe1, 0x00,
	230	0xe2, 0x7f,
	231	0xe3, 0x80,
	232	0xe4, 0x7f,
	233	0xe5, 0x80,
	234	0xe6, 0x00, /* Brightness set to 0 */
	235	0xe7, 0xe0, /* Contrast to 1.0, noise shaping
	236	* 10 to 8 2-bit error diffusion */
	237	0xe8, 0xf8, /* YUV422, CbCr binary offset,
	238	* ... (p.32) */
	239	0xea, 0x18, /* LLC2 connected, output FIFO
	240	* reset with VACTintern */
	241	0xf0, 0x8a, /* Half full level to 10, bus
	242	* shuffler [7:0, 23:16, 15:8] */
	243	0xf1, 0x18, /* Single clock, sync mode, no
	244	* FE delay, no HLEN counter */
	245	0xf8, 0x12, /* Port A, PIXCLK, HF# & FE#
	246	* strength to 2 */
	247	0xf9, 0x24, /* Port B, HREF, VREF, PREF &
	248	* ALPHA strength to 4 */
	249	};
	250
	251	static const unsigned short init_fp[] = {
	252	0x59, 0,
	253	0xa0, 2070, /* ACC reference */
	254	0xa3, 0,
	255	0xa4, 0,
	256	0xa8, 30,
	257	0xb2, 768,
	258	0xbe, 27,
	259	0x58, 0,
	260	0x26, 0,
	261	0x4b, 0x298, /* PLL gain */
	262	};
	263
1da177e4	264
7e5eaadc	265	static int vpx3220_init(struct v4l2_subdev *sd, u32 val)
1da177e4	266	{
7e5eaadc HV	267	struct vpx3220 *decoder = to_vpx3220(sd);
	268
	269	vpx3220_write_block(sd, init_common, sizeof(init_common));
	270	vpx3220_write_fp_block(sd, init_fp, sizeof(init_fp) >> 1);
	271	if (decoder->norm & V4L2_STD_NTSC)
	272	vpx3220_write_fp_block(sd, init_ntsc, sizeof(init_ntsc) >> 1);
	273	else if (decoder->norm & V4L2_STD_PAL)
	274	vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
	275	else if (decoder->norm & V4L2_STD_SECAM)
	276	vpx3220_write_fp_block(sd, init_secam, sizeof(init_secam) >> 1);
	277	else
	278	vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
	279	return 0;
	280	}
1da177e4	281
7e5eaadc HV	282	static int vpx3220_status(struct v4l2_subdev sd, u32 pstatus, v4l2_std_id *pstd)
	283	{
	284	int res = V4L2_IN_ST_NO_SIGNAL, status;
32cb3b09	285	v4l2_std_id std = pstd ? *pstd : V4L2_STD_ALL;
1da177e4	286
7e5eaadc	287	status = vpx3220_fp_read(sd, 0x0f3);
1da177e4	288
7e5eaadc	289	v4l2_dbg(1, debug, sd, "status: 0x%04x\n", status);
1da177e4	290
7e5eaadc HV	291	if (status < 0)
7e5eaadc HV	292	return status;
1da177e4	293
7e5eaadc HV	294	if ((status & 0x20) == 0) {
7e5eaadc HV	295	res = 0;
1da177e4	296
7e5eaadc HV	297	switch (status & 0x18) {
	298	case 0x00:
	299	case 0x10:
	300	case 0x14:
	301	case 0x18:
32cb3b09	302	std &= V4L2_STD_PAL;
7e5eaadc	303	break;
1da177e4	304
7e5eaadc	305	case 0x08:
32cb3b09	306	std &= V4L2_STD_SECAM;
7e5eaadc	307	break;
1da177e4	308
7e5eaadc HV	309	case 0x04:
	310	case 0x0c:
	311	case 0x1c:
32cb3b09	312	std &= V4L2_STD_NTSC;
7e5eaadc	313	break;
1da177e4	314	}
32cb3b09 HV	315	} else {
32cb3b09 HV	316	std = V4L2_STD_UNKNOWN;
23848b65	317	}
7e5eaadc HV	318	if (pstd)
	319	*pstd = std;
	320	if (pstatus)
ba08831b	321	*pstatus = res;
7e5eaadc HV	322	return 0;
7e5eaadc HV	323	}
1da177e4	324
7e5eaadc HV	325	static int vpx3220_querystd(struct v4l2_subdev sd, v4l2_std_id std)
7e5eaadc HV	326	{
bccfa449	327	v4l2_dbg(1, debug, sd, "querystd\n");
7e5eaadc HV	328	return vpx3220_status(sd, NULL, std);
7e5eaadc HV	329	}
107063c6	330
7e5eaadc HV	331	static int vpx3220_g_input_status(struct v4l2_subdev sd, u32 status)
7e5eaadc HV	332	{
bccfa449	333	v4l2_dbg(1, debug, sd, "g_input_status\n");
7e5eaadc HV	334	return vpx3220_status(sd, status, NULL);
7e5eaadc HV	335	}
de21eb63	336
7e5eaadc HV	337	static int vpx3220_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
	338	{
	339	struct vpx3220 *decoder = to_vpx3220(sd);
	340	int temp_input;
	341
	342	/* Here we back up the input selection because it gets
	343	overwritten when we fill the registers with the
25985edc	344	chosen video norm */
7e5eaadc HV	345	temp_input = vpx3220_fp_read(sd, 0xf2);
7e5eaadc HV	346
bccfa449	347	v4l2_dbg(1, debug, sd, "s_std %llx\n", (unsigned long long)std);
7e5eaadc HV	348	if (std & V4L2_STD_NTSC) {
	349	vpx3220_write_fp_block(sd, init_ntsc, sizeof(init_ntsc) >> 1);
	350	v4l2_dbg(1, debug, sd, "norm switched to NTSC\n");
	351	} else if (std & V4L2_STD_PAL) {
	352	vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
	353	v4l2_dbg(1, debug, sd, "norm switched to PAL\n");
	354	} else if (std & V4L2_STD_SECAM) {
	355	vpx3220_write_fp_block(sd, init_secam, sizeof(init_secam) >> 1);
	356	v4l2_dbg(1, debug, sd, "norm switched to SECAM\n");
	357	} else {
	358	return -EINVAL;
23848b65	359	}
1da177e4	360
7e5eaadc	361	decoder->norm = std;
1da177e4	362
7e5eaadc HV	363	/* And here we set the backed up video input again */
	364	vpx3220_fp_write(sd, 0xf2, temp_input \| 0x0010);
	365	udelay(10);
	366	return 0;
	367	}
1da177e4	368
5325b427 HV	369	static int vpx3220_s_routing(struct v4l2_subdev *sd,
5325b427 HV	370	u32 input, u32 output, u32 config)
7e5eaadc HV	371	{
7e5eaadc HV	372	int data;
1da177e4	373
5325b427 HV	374	/* RJ: input = 0: ST8 (PCTV) input
	375	input = 1: COMPOSITE input
	376	input = 2: SVHS input */
1da177e4	377
9ecb6718	378	static const int input_vals[3][2] = {
7e5eaadc HV	379	{0x0c, 0},
	380	{0x0d, 0},
	381	{0x0e, 1}
	382	};
1da177e4	383
f14a2972	384	if (input > 2)
7e5eaadc	385	return -EINVAL;
1da177e4	386
5325b427	387	v4l2_dbg(1, debug, sd, "input switched to %s\n", inputs[input]);
1da177e4	388
5325b427	389	vpx3220_write(sd, 0x33, input_vals[input][0]);
1da177e4	390
7e5eaadc HV	391	data = vpx3220_fp_read(sd, 0xf2) & ~(0x0020);
	392	if (data < 0)
	393	return data;
	394	/* 0x0010 is required to latch the setting */
	395	vpx3220_fp_write(sd, 0xf2,
5325b427	396	data \| (input_vals[input][1] << 5) \| 0x0010);
1da177e4	397
7e5eaadc HV	398	udelay(10);
	399	return 0;
	400	}
1da177e4	401
7e5eaadc HV	402	static int vpx3220_s_stream(struct v4l2_subdev *sd, int enable)
7e5eaadc HV	403	{
bccfa449	404	v4l2_dbg(1, debug, sd, "s_stream %s\n", enable ? "on" : "off");
1da177e4	405
7e5eaadc HV	406	vpx3220_write(sd, 0xf2, (enable ? 0x1b : 0x00));
	407	return 0;
	408	}
107063c6	409
9a775323	410	static int vpx3220_s_ctrl(struct v4l2_ctrl *ctrl)
7e5eaadc	411	{
9a775323	412	struct v4l2_subdev *sd = to_sd(ctrl);
1da177e4	413
7e5eaadc HV	414	switch (ctrl->id) {
7e5eaadc HV	415	case V4L2_CID_BRIGHTNESS:
9a775323 HV	416	vpx3220_write(sd, 0xe6, ctrl->val);
9a775323 HV	417	return 0;
7e5eaadc	418	case V4L2_CID_CONTRAST:
9a775323 HV	419	/* Bit 7 and 8 is for noise shaping */
	420	vpx3220_write(sd, 0xe7, ctrl->val + 192);
	421	return 0;
7e5eaadc	422	case V4L2_CID_SATURATION:
9a775323 HV	423	vpx3220_fp_write(sd, 0xa0, ctrl->val);
9a775323 HV	424	return 0;
7e5eaadc	425	case V4L2_CID_HUE:
9a775323 HV	426	vpx3220_fp_write(sd, 0x1c, ctrl->val);
9a775323 HV	427	return 0;
107063c6	428	}
9a775323	429	return -EINVAL;
1da177e4 LT	430	}
1da177e4 LT	431
7e5eaadc HV	432	/* ----------------------------------------------------------------------- */
7e5eaadc HV	433
9a775323 HV	434	static const struct v4l2_ctrl_ops vpx3220_ctrl_ops = {
	435	.s_ctrl = vpx3220_s_ctrl,
	436	};
	437
7e5eaadc	438	static const struct v4l2_subdev_core_ops vpx3220_core_ops = {
7e5eaadc	439	.init = vpx3220_init,
7e5eaadc HV	440	};
	441
	442	static const struct v4l2_subdev_video_ops vpx3220_video_ops = {
8774bed9	443	.s_std = vpx3220_s_std,
7e5eaadc HV	444	.s_routing = vpx3220_s_routing,
	445	.s_stream = vpx3220_s_stream,
	446	.querystd = vpx3220_querystd,
	447	.g_input_status = vpx3220_g_input_status,
	448	};
	449
	450	static const struct v4l2_subdev_ops vpx3220_ops = {
	451	.core = &vpx3220_core_ops,
7e5eaadc HV	452	.video = &vpx3220_video_ops,
	453	};
	454
1da177e4	455	/* -----------------------------------------------------------------------
c84e6036	456	* Client management code
1da177e4 LT	457	*/
1da177e4 LT	458
b7a45a22	459	static int vpx3220_probe(struct i2c_client *client)
1da177e4	460	{
1da177e4	461	struct vpx3220 *decoder;
7e5eaadc	462	struct v4l2_subdev *sd;
23848b65 HV	463	const char *name = NULL;
	464	u8 ver;
	465	u16 pn;
1da177e4 LT	466
1da177e4 LT	467	/* Check if the adapter supports the needed features */
23848b65 HV	468	if (!i2c_check_functionality(client->adapter,
	469	I2C_FUNC_SMBUS_BYTE_DATA \| I2C_FUNC_SMBUS_WORD_DATA))
	470	return -ENODEV;
1da177e4	471
c02b211d	472	decoder = devm_kzalloc(&client->dev, sizeof(*decoder), GFP_KERNEL);
23848b65	473	if (decoder == NULL)
1da177e4	474	return -ENOMEM;
7e5eaadc HV	475	sd = &decoder->sd;
7e5eaadc HV	476	v4l2_i2c_subdev_init(sd, client, &vpx3220_ops);
107063c6	477	decoder->norm = V4L2_STD_PAL;
1da177e4 LT	478	decoder->input = 0;
1da177e4 LT	479	decoder->enable = 1;
9a775323 HV	480	v4l2_ctrl_handler_init(&decoder->hdl, 4);
	481	v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
	482	V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
	483	v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
	484	V4L2_CID_CONTRAST, 0, 63, 1, 32);
	485	v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
	486	V4L2_CID_SATURATION, 0, 4095, 1, 2048);
	487	v4l2_ctrl_new_std(&decoder->hdl, &vpx3220_ctrl_ops,
	488	V4L2_CID_HUE, -512, 511, 1, 0);
	489	sd->ctrl_handler = &decoder->hdl;
	490	if (decoder->hdl.error) {
	491	int err = decoder->hdl.error;
	492
	493	v4l2_ctrl_handler_free(&decoder->hdl);
9a775323 HV	494	return err;
	495	}
	496	v4l2_ctrl_handler_setup(&decoder->hdl);
1da177e4	497
23848b65 HV	498	ver = i2c_smbus_read_byte_data(client, 0x00);
	499	pn = (i2c_smbus_read_byte_data(client, 0x02) << 8) +
	500	i2c_smbus_read_byte_data(client, 0x01);
	501	if (ver == 0xec) {
	502	switch (pn) {
	503	case 0x4680:
	504	name = "vpx3220a";
	505	break;
	506	case 0x4260:
	507	name = "vpx3216b";
	508	break;
	509	case 0x4280:
	510	name = "vpx3214c";
	511	break;
	512	}
1da177e4	513	}
23848b65	514	if (name)
7e5eaadc	515	v4l2_info(sd, "%s found @ 0x%x (%s)\n", name,
23848b65 HV	516	client->addr << 1, client->adapter->name);
23848b65 HV	517	else
7e5eaadc	518	v4l2_info(sd, "chip (%02x:%04x) found @ 0x%x (%s)\n",
23848b65	519	ver, pn, client->addr << 1, client->adapter->name);
1da177e4	520
7e5eaadc HV	521	vpx3220_write_block(sd, init_common, sizeof(init_common));
	522	vpx3220_write_fp_block(sd, init_fp, sizeof(init_fp) >> 1);
	523	/* Default to PAL */
	524	vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
1da177e4 LT	525	return 0;
	526	}
	527
ed5c2f5f	528	static void vpx3220_remove(struct i2c_client *client)
1da177e4	529	{
7e5eaadc	530	struct v4l2_subdev *sd = i2c_get_clientdata(client);
9a775323	531	struct vpx3220 *decoder = to_vpx3220(sd);
7e5eaadc HV	532
7e5eaadc HV	533	v4l2_device_unregister_subdev(sd);
9a775323	534	v4l2_ctrl_handler_free(&decoder->hdl);
1da177e4 LT	535	}
1da177e4 LT	536
23848b65	537	static const struct i2c_device_id vpx3220_id[] = {
cc4cbd4b UKK	538	{ "vpx3220a" },
	539	{ "vpx3216b" },
	540	{ "vpx3214c" },
23848b65 HV	541	{ }
	542	};
	543	MODULE_DEVICE_TABLE(i2c, vpx3220_id);
1da177e4	544
c2d999f3 HV	545	static struct i2c_driver vpx3220_driver = {
c2d999f3 HV	546	.driver = {
c2d999f3 HV	547	.name = "vpx3220",
c2d999f3 HV	548	},
aaeb31c0	549	.probe = vpx3220_probe,
c2d999f3 HV	550	.remove = vpx3220_remove,
c2d999f3 HV	551	.id_table = vpx3220_id,
1da177e4	552	};
c2d999f3	553
c6e8d86f	554	module_i2c_driver(vpx3220_driver);