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[linux-block.git] / drivers / media / i2c / tvp5150.c
CommitLineData
459ee17c
MCC		 1// SPDX-License-Identifier: GPL-2.0
2//
3// tvp5150 - Texas Instruments TVP5150A/AM1 and TVP5151 video decoder driver
4//
5// Copyright (c) 2005,2006 Mauro Carvalho Chehab <mchehab@infradead.org>
cd4665c5 6
b802fb99 7#include <dt-bindings/media/tvp5150.h>
cd4665c5 8#include <linux/i2c.h>
5a0e3ad6 9#include <linux/slab.h>
33b687cf 10#include <linux/videodev2.h>
cd4665c5 11#include <linux/delay.h>
09aa2609 12#include <linux/gpio/consumer.h>
7a707b89 13#include <linux/module.h>
859969b3 14#include <linux/of_graph.h>
c7d97499 15#include <media/v4l2-async.h>
6b8fe025 16#include <media/v4l2-device.h>
6c45ec71 17#include <media/v4l2-ctrls.h>
859969b3 18#include <media/v4l2-fwnode.h>
55606310 19#include <media/v4l2-mc.h>
cd4665c5
MCC		 20
21#include "tvp5150_reg.h"
22
785a3de1
PZ		 23#define TVP5150_H_MAX 720U
24#define TVP5150_V_MAX_525_60 480U
25#define TVP5150_V_MAX_OTHERS 576U
963ddc63
JM		 26#define TVP5150_MAX_CROP_LEFT 511
27#define TVP5150_MAX_CROP_TOP 127
28#define TVP5150_CROP_SHIFT 2
29
c43875f6 30MODULE_DESCRIPTION("Texas Instruments TVP5150A/TVP5150AM1/TVP5151 video decoder driver");
cd4665c5 31MODULE_AUTHOR("Mauro Carvalho Chehab");
459ee17c 32MODULE_LICENSE("GPL v2");
cd4665c5 33
cd4665c5 34
ff699e6b 35static int debug;
2a0489d3 36module_param(debug, int, 0644);
6b8fe025 37MODULE_PARM_DESC(debug, "Debug level (0-2)");
cd4665c5 38
ad0e3744
MCC		 39#define dprintk0(__dev, __arg...) dev_dbg_lvl(__dev, 0, 0, __arg)
40
cd4665c5 41struct tvp5150 {
6b8fe025 42 struct v4l2_subdev sd;
55606310
MCC		 43#ifdef CONFIG_MEDIA_CONTROLLER
44 struct media_pad pads[DEMOD_NUM_PADS];
f7b4b54e
JMC		 45 struct media_entity input_ent[TVP5150_INPUT_NUM];
46 struct media_pad input_pad[TVP5150_INPUT_NUM];
55606310 47#endif
6c45ec71 48 struct v4l2_ctrl_handler hdl;
963ddc63 49 struct v4l2_rect rect;
84486d53 50
3ad96835 51 v4l2_std_id norm; /* Current set standard */
5325b427
HV		 52 u32 input;
53 u32 output;
84486d53 54 int enable;
a2e5f1b3 55
82275133
JMC		 56 u16 dev_id;
57 u16 rom_ver;
58
a2e5f1b3 59 enum v4l2_mbus_type mbus_type;
cd4665c5
MCC		 60};
61
6b8fe025 62static inline struct tvp5150 *to_tvp5150(struct v4l2_subdev *sd)
cd4665c5 63{
6b8fe025
HV		 64 return container_of(sd, struct tvp5150, sd);
65}
66
6c45ec71
HV		 67static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
68{
69 return &container_of(ctrl->handler, struct tvp5150, hdl)->sd;
70}
71
6b8fe025
HV		 72static int tvp5150_read(struct v4l2_subdev *sd, unsigned char addr)
73{
74 struct i2c_client *c = v4l2_get_subdevdata(sd);
cd4665c5 75 int rc;
e35ce2e4
LP		 76
77 rc = i2c_smbus_read_byte_data(c, addr);
78 if (rc < 0) {
257e29f8 79 dev_err(sd->dev, "i2c i/o error: rc == %d\n", rc);
e35ce2e4 80 return rc;
8cd0d4ca 81 }
e1bc80ad 82
257e29f8 83 dev_dbg_lvl(sd->dev, 2, debug, "tvp5150: read 0x%02x = %02x\n", addr, rc);
cd4665c5 84
e35ce2e4 85 return rc;
cd4665c5
MCC		 86}
87
cacdd6a4 88static int tvp5150_write(struct v4l2_subdev *sd, unsigned char addr,
84486d53 89 unsigned char value)
cd4665c5 90{
6b8fe025 91 struct i2c_client *c = v4l2_get_subdevdata(sd);
cd4665c5 92 int rc;
cd4665c5 93
257e29f8 94 dev_dbg_lvl(sd->dev, 2, debug, "tvp5150: writing %02x %02x\n", addr, value);
e35ce2e4
LP		 95 rc = i2c_smbus_write_byte_data(c, addr, value);
96 if (rc < 0)
257e29f8 97 dev_err(sd->dev, "i2c i/o error: rc == %d\n", rc);
cacdd6a4
JMC		 98
99 return rc;
cd4665c5
MCC		 100}
101
6b8fe025
HV		 102static void dump_reg_range(struct v4l2_subdev *sd, char *s, u8 init,
103 const u8 end, int max_line)
3ad96835 104{
e5134114
MCC		 105 u8 buf[16];
106 int i = 0, j, len;
107
108 if (max_line > 16) {
109 dprintk0(sd->dev, "too much data to dump\n");
110 return;
111 }
112
113 for (i = init; i < end; i += max_line) {
114 len = (end - i > max_line) ? max_line : end - i;
115
116 for (j = 0; j < len; j++)
117 buf[j] = tvp5150_read(sd, i + j);
118
119 dprintk0(sd->dev, "%s reg %02x = %*ph\n", s, i, len, buf);
3ad96835 120 }
3ad96835
MCC		 121}
122
6b8fe025 123static int tvp5150_log_status(struct v4l2_subdev *sd)
cd4665c5 124{
ad0e3744
MCC		 125 dprintk0(sd->dev, "tvp5150: Video input source selection #1 = 0x%02x\n",
126 tvp5150_read(sd, TVP5150_VD_IN_SRC_SEL_1));
127 dprintk0(sd->dev, "tvp5150: Analog channel controls = 0x%02x\n",
128 tvp5150_read(sd, TVP5150_ANAL_CHL_CTL));
129 dprintk0(sd->dev, "tvp5150: Operation mode controls = 0x%02x\n",
130 tvp5150_read(sd, TVP5150_OP_MODE_CTL));
131 dprintk0(sd->dev, "tvp5150: Miscellaneous controls = 0x%02x\n",
132 tvp5150_read(sd, TVP5150_MISC_CTL));
133 dprintk0(sd->dev, "tvp5150: Autoswitch mask= 0x%02x\n",
134 tvp5150_read(sd, TVP5150_AUTOSW_MSK));
135 dprintk0(sd->dev, "tvp5150: Color killer threshold control = 0x%02x\n",
136 tvp5150_read(sd, TVP5150_COLOR_KIL_THSH_CTL));
137 dprintk0(sd->dev, "tvp5150: Luminance processing controls #1 #2 and #3 = %02x %02x %02x\n",
138 tvp5150_read(sd, TVP5150_LUMA_PROC_CTL_1),
139 tvp5150_read(sd, TVP5150_LUMA_PROC_CTL_2),
140 tvp5150_read(sd, TVP5150_LUMA_PROC_CTL_3));
141 dprintk0(sd->dev, "tvp5150: Brightness control = 0x%02x\n",
142 tvp5150_read(sd, TVP5150_BRIGHT_CTL));
143 dprintk0(sd->dev, "tvp5150: Color saturation control = 0x%02x\n",
144 tvp5150_read(sd, TVP5150_SATURATION_CTL));
145 dprintk0(sd->dev, "tvp5150: Hue control = 0x%02x\n",
146 tvp5150_read(sd, TVP5150_HUE_CTL));
147 dprintk0(sd->dev, "tvp5150: Contrast control = 0x%02x\n",
148 tvp5150_read(sd, TVP5150_CONTRAST_CTL));
149 dprintk0(sd->dev, "tvp5150: Outputs and data rates select = 0x%02x\n",
150 tvp5150_read(sd, TVP5150_DATA_RATE_SEL));
151 dprintk0(sd->dev, "tvp5150: Configuration shared pins = 0x%02x\n",
152 tvp5150_read(sd, TVP5150_CONF_SHARED_PIN));
153 dprintk0(sd->dev, "tvp5150: Active video cropping start = 0x%02x%02x\n",
154 tvp5150_read(sd, TVP5150_ACT_VD_CROP_ST_MSB),
155 tvp5150_read(sd, TVP5150_ACT_VD_CROP_ST_LSB));
156 dprintk0(sd->dev, "tvp5150: Active video cropping stop = 0x%02x%02x\n",
157 tvp5150_read(sd, TVP5150_ACT_VD_CROP_STP_MSB),
158 tvp5150_read(sd, TVP5150_ACT_VD_CROP_STP_LSB));
159 dprintk0(sd->dev, "tvp5150: Genlock/RTC = 0x%02x\n",
160 tvp5150_read(sd, TVP5150_GENLOCK));
161 dprintk0(sd->dev, "tvp5150: Horizontal sync start = 0x%02x\n",
162 tvp5150_read(sd, TVP5150_HORIZ_SYNC_START));
163 dprintk0(sd->dev, "tvp5150: Vertical blanking start = 0x%02x\n",
164 tvp5150_read(sd, TVP5150_VERT_BLANKING_START));
165 dprintk0(sd->dev, "tvp5150: Vertical blanking stop = 0x%02x\n",
166 tvp5150_read(sd, TVP5150_VERT_BLANKING_STOP));
167 dprintk0(sd->dev, "tvp5150: Chrominance processing control #1 and #2 = %02x %02x\n",
168 tvp5150_read(sd, TVP5150_CHROMA_PROC_CTL_1),
169 tvp5150_read(sd, TVP5150_CHROMA_PROC_CTL_2));
170 dprintk0(sd->dev, "tvp5150: Interrupt reset register B = 0x%02x\n",
171 tvp5150_read(sd, TVP5150_INT_RESET_REG_B));
172 dprintk0(sd->dev, "tvp5150: Interrupt enable register B = 0x%02x\n",
173 tvp5150_read(sd, TVP5150_INT_ENABLE_REG_B));
174 dprintk0(sd->dev, "tvp5150: Interrupt configuration register B = 0x%02x\n",
175 tvp5150_read(sd, TVP5150_INTT_CONFIG_REG_B));
176 dprintk0(sd->dev, "tvp5150: Video standard = 0x%02x\n",
177 tvp5150_read(sd, TVP5150_VIDEO_STD));
178 dprintk0(sd->dev, "tvp5150: Chroma gain factor: Cb=0x%02x Cr=0x%02x\n",
179 tvp5150_read(sd, TVP5150_CB_GAIN_FACT),
180 tvp5150_read(sd, TVP5150_CR_GAIN_FACTOR));
181 dprintk0(sd->dev, "tvp5150: Macrovision on counter = 0x%02x\n",
182 tvp5150_read(sd, TVP5150_MACROVISION_ON_CTR));
183 dprintk0(sd->dev, "tvp5150: Macrovision off counter = 0x%02x\n",
184 tvp5150_read(sd, TVP5150_MACROVISION_OFF_CTR));
185 dprintk0(sd->dev, "tvp5150: ITU-R BT.656.%d timing(TVP5150AM1 only)\n",
186 (tvp5150_read(sd, TVP5150_REV_SELECT) & 1) ? 3 : 4);
187 dprintk0(sd->dev, "tvp5150: Device ID = %02x%02x\n",
188 tvp5150_read(sd, TVP5150_MSB_DEV_ID),
189 tvp5150_read(sd, TVP5150_LSB_DEV_ID));
190 dprintk0(sd->dev, "tvp5150: ROM version = (hex) %02x.%02x\n",
191 tvp5150_read(sd, TVP5150_ROM_MAJOR_VER),
192 tvp5150_read(sd, TVP5150_ROM_MINOR_VER));
193 dprintk0(sd->dev, "tvp5150: Vertical line count = 0x%02x%02x\n",
194 tvp5150_read(sd, TVP5150_VERT_LN_COUNT_MSB),
195 tvp5150_read(sd, TVP5150_VERT_LN_COUNT_LSB));
196 dprintk0(sd->dev, "tvp5150: Interrupt status register B = 0x%02x\n",
197 tvp5150_read(sd, TVP5150_INT_STATUS_REG_B));
198 dprintk0(sd->dev, "tvp5150: Interrupt active register B = 0x%02x\n",
199 tvp5150_read(sd, TVP5150_INT_ACTIVE_REG_B));
200 dprintk0(sd->dev, "tvp5150: Status regs #1 to #5 = %02x %02x %02x %02x %02x\n",
201 tvp5150_read(sd, TVP5150_STATUS_REG_1),
202 tvp5150_read(sd, TVP5150_STATUS_REG_2),
203 tvp5150_read(sd, TVP5150_STATUS_REG_3),
204 tvp5150_read(sd, TVP5150_STATUS_REG_4),
205 tvp5150_read(sd, TVP5150_STATUS_REG_5));
3ad96835 206
6b8fe025
HV		 207 dump_reg_range(sd, "Teletext filter 1", TVP5150_TELETEXT_FIL1_INI,
208 TVP5150_TELETEXT_FIL1_END, 8);
209 dump_reg_range(sd, "Teletext filter 2", TVP5150_TELETEXT_FIL2_INI,
210 TVP5150_TELETEXT_FIL2_END, 8);
3ad96835 211
ad0e3744
MCC		 212 dprintk0(sd->dev, "tvp5150: Teletext filter enable = 0x%02x\n",
213 tvp5150_read(sd, TVP5150_TELETEXT_FIL_ENA));
214 dprintk0(sd->dev, "tvp5150: Interrupt status register A = 0x%02x\n",
215 tvp5150_read(sd, TVP5150_INT_STATUS_REG_A));
216 dprintk0(sd->dev, "tvp5150: Interrupt enable register A = 0x%02x\n",
217 tvp5150_read(sd, TVP5150_INT_ENABLE_REG_A));
218 dprintk0(sd->dev, "tvp5150: Interrupt configuration = 0x%02x\n",
219 tvp5150_read(sd, TVP5150_INT_CONF));
220 dprintk0(sd->dev, "tvp5150: VDP status register = 0x%02x\n",
221 tvp5150_read(sd, TVP5150_VDP_STATUS_REG));
222 dprintk0(sd->dev, "tvp5150: FIFO word count = 0x%02x\n",
223 tvp5150_read(sd, TVP5150_FIFO_WORD_COUNT));
224 dprintk0(sd->dev, "tvp5150: FIFO interrupt threshold = 0x%02x\n",
225 tvp5150_read(sd, TVP5150_FIFO_INT_THRESHOLD));
226 dprintk0(sd->dev, "tvp5150: FIFO reset = 0x%02x\n",
227 tvp5150_read(sd, TVP5150_FIFO_RESET));
228 dprintk0(sd->dev, "tvp5150: Line number interrupt = 0x%02x\n",
229 tvp5150_read(sd, TVP5150_LINE_NUMBER_INT));
230 dprintk0(sd->dev, "tvp5150: Pixel alignment register = 0x%02x%02x\n",
231 tvp5150_read(sd, TVP5150_PIX_ALIGN_REG_HIGH),
232 tvp5150_read(sd, TVP5150_PIX_ALIGN_REG_LOW));
233 dprintk0(sd->dev, "tvp5150: FIFO output control = 0x%02x\n",
234 tvp5150_read(sd, TVP5150_FIFO_OUT_CTRL));
235 dprintk0(sd->dev, "tvp5150: Full field enable = 0x%02x\n",
236 tvp5150_read(sd, TVP5150_FULL_FIELD_ENA));
237 dprintk0(sd->dev, "tvp5150: Full field mode register = 0x%02x\n",
238 tvp5150_read(sd, TVP5150_FULL_FIELD_MODE_REG));
3ad96835 239
6b8fe025
HV		 240 dump_reg_range(sd, "CC data", TVP5150_CC_DATA_INI,
241 TVP5150_CC_DATA_END, 8);
3ad96835 242
6b8fe025
HV		 243 dump_reg_range(sd, "WSS data", TVP5150_WSS_DATA_INI,
244 TVP5150_WSS_DATA_END, 8);
3ad96835 245
6b8fe025
HV		 246 dump_reg_range(sd, "VPS data", TVP5150_VPS_DATA_INI,
247 TVP5150_VPS_DATA_END, 8);
3ad96835 248
6b8fe025
HV		 249 dump_reg_range(sd, "VITC data", TVP5150_VITC_DATA_INI,
250 TVP5150_VITC_DATA_END, 10);
3ad96835 251
6b8fe025
HV		 252 dump_reg_range(sd, "Line mode", TVP5150_LINE_MODE_INI,
253 TVP5150_LINE_MODE_END, 8);
254 return 0;
cd4665c5
MCC		 255}
256
257/****************************************************************************
258 Basic functions
259 ****************************************************************************/
cd4665c5 260
6e98bee2 261static void tvp5150_selmux(struct v4l2_subdev *sd)
cd4665c5 262{
2962fc01 263 int opmode = 0;
6b8fe025 264 struct tvp5150 *decoder = to_tvp5150(sd);
c7c0b34c 265 int input = 0;
afcc8e8c 266 int val;
84486d53 267
c43875f6
MCC		 268 /* Only tvp5150am1 and tvp5151 have signal generator support */
269 if ((decoder->dev_id == 0x5150 && decoder->rom_ver == 0x0400) ||
270 (decoder->dev_id == 0x5151 && decoder->rom_ver == 0x0100)) {
271 if (!decoder->enable)
272 input = 8;
273 }
4c86f973 274
5325b427 275 switch (decoder->input) {
c7c0b34c
HV		 276 case TVP5150_COMPOSITE1:
277 input |= 2;
278 /* fall through */
279 case TVP5150_COMPOSITE0:
c0477ad9 280 break;
c7c0b34c 281 case TVP5150_SVIDEO:
c0477ad9 282 default:
c7c0b34c 283 input |= 1;
c0477ad9
MCC		 284 break;
285 }
286
257e29f8 287 dev_dbg_lvl(sd->dev, 1, debug, "Selecting video route: route input=%i, output=%i => tvp5150 input=%i, opmode=%i\n",
5325b427
HV		 288 decoder->input, decoder->output,
289 input, opmode);
12500f07 290
6b8fe025
HV		 291 tvp5150_write(sd, TVP5150_OP_MODE_CTL, opmode);
292 tvp5150_write(sd, TVP5150_VD_IN_SRC_SEL_1, input);
f4b8b3ae 293
b4b2de38
LP		 294 /*
295 * Setup the FID/GLCO/VLK/HVLK and INTREQ/GPCL/VBLK output signals. For
296 * S-Video we output the vertical lock (VLK) signal on FID/GLCO/VLK/HVLK
297 * and set INTREQ/GPCL/VBLK to logic 0. For composite we output the
298 * field indicator (FID) signal on FID/GLCO/VLK/HVLK and set
299 * INTREQ/GPCL/VBLK to logic 1.
f4b8b3ae 300 */
6b8fe025 301 val = tvp5150_read(sd, TVP5150_MISC_CTL);
8cd0d4ca 302 if (val < 0) {
257e29f8 303 dev_err(sd->dev, "%s: failed with error = %d\n", __func__, val);
8cd0d4ca
DL		 304 return;
305 }
306
5325b427 307 if (decoder->input == TVP5150_SVIDEO)
b4b2de38 308 val = (val & ~TVP5150_MISC_CTL_GPCL) | TVP5150_MISC_CTL_HVLK;
f4b8b3ae 309 else
b4b2de38 310 val = (val & ~TVP5150_MISC_CTL_HVLK) | TVP5150_MISC_CTL_GPCL;
6b8fe025 311 tvp5150_write(sd, TVP5150_MISC_CTL, val);
cd4665c5
MCC		 312};
313
e1bc80ad
MCC		 314struct i2c_reg_value {
315 unsigned char reg;
316 unsigned char value;
317};
318
319/* Default values as sugested at TVP5150AM1 datasheet */
320static const struct i2c_reg_value tvp5150_init_default[] = {
321 { /* 0x00 */
322 TVP5150_VD_IN_SRC_SEL_1,0x00
323 },
324 { /* 0x01 */
325 TVP5150_ANAL_CHL_CTL,0x15
326 },
327 { /* 0x02 */
328 TVP5150_OP_MODE_CTL,0x00
329 },
330 { /* 0x03 */
331 TVP5150_MISC_CTL,0x01
332 },
333 { /* 0x06 */
334 TVP5150_COLOR_KIL_THSH_CTL,0x10
335 },
336 { /* 0x07 */
337 TVP5150_LUMA_PROC_CTL_1,0x60
338 },
339 { /* 0x08 */
340 TVP5150_LUMA_PROC_CTL_2,0x00
341 },
342 { /* 0x09 */
343 TVP5150_BRIGHT_CTL,0x80
344 },
345 { /* 0x0a */
346 TVP5150_SATURATION_CTL,0x80
347 },
348 { /* 0x0b */
349 TVP5150_HUE_CTL,0x00
350 },
351 { /* 0x0c */
352 TVP5150_CONTRAST_CTL,0x80
353 },
354 { /* 0x0d */
355 TVP5150_DATA_RATE_SEL,0x47
356 },
357 { /* 0x0e */
358 TVP5150_LUMA_PROC_CTL_3,0x00
359 },
360 { /* 0x0f */
361 TVP5150_CONF_SHARED_PIN,0x08
362 },
363 { /* 0x11 */
364 TVP5150_ACT_VD_CROP_ST_MSB,0x00
365 },
366 { /* 0x12 */
367 TVP5150_ACT_VD_CROP_ST_LSB,0x00
368 },
369 { /* 0x13 */
370 TVP5150_ACT_VD_CROP_STP_MSB,0x00
371 },
372 { /* 0x14 */
373 TVP5150_ACT_VD_CROP_STP_LSB,0x00
374 },
375 { /* 0x15 */
376 TVP5150_GENLOCK,0x01
377 },
378 { /* 0x16 */
379 TVP5150_HORIZ_SYNC_START,0x80
380 },
381 { /* 0x18 */
382 TVP5150_VERT_BLANKING_START,0x00
383 },
384 { /* 0x19 */
385 TVP5150_VERT_BLANKING_STOP,0x00
386 },
387 { /* 0x1a */
388 TVP5150_CHROMA_PROC_CTL_1,0x0c
389 },
390 { /* 0x1b */
391 TVP5150_CHROMA_PROC_CTL_2,0x14
392 },
393 { /* 0x1c */
394 TVP5150_INT_RESET_REG_B,0x00
395 },
396 { /* 0x1d */
397 TVP5150_INT_ENABLE_REG_B,0x00
398 },
399 { /* 0x1e */
400 TVP5150_INTT_CONFIG_REG_B,0x00
401 },
402 { /* 0x28 */
403 TVP5150_VIDEO_STD,0x00
404 },
405 { /* 0x2e */
406 TVP5150_MACROVISION_ON_CTR,0x0f
407 },
408 { /* 0x2f */
409 TVP5150_MACROVISION_OFF_CTR,0x01
410 },
411 { /* 0xbb */
412 TVP5150_TELETEXT_FIL_ENA,0x00
413 },
414 { /* 0xc0 */
415 TVP5150_INT_STATUS_REG_A,0x00
416 },
417 { /* 0xc1 */
418 TVP5150_INT_ENABLE_REG_A,0x00
419 },
420 { /* 0xc2 */
421 TVP5150_INT_CONF,0x04
422 },
423 { /* 0xc8 */
424 TVP5150_FIFO_INT_THRESHOLD,0x80
425 },
426 { /* 0xc9 */
427 TVP5150_FIFO_RESET,0x00
428 },
429 { /* 0xca */
430 TVP5150_LINE_NUMBER_INT,0x00
431 },
432 { /* 0xcb */
433 TVP5150_PIX_ALIGN_REG_LOW,0x4e
434 },
435 { /* 0xcc */
436 TVP5150_PIX_ALIGN_REG_HIGH,0x00
437 },
438 { /* 0xcd */
439 TVP5150_FIFO_OUT_CTRL,0x01
440 },
441 { /* 0xcf */
3ad96835 442 TVP5150_FULL_FIELD_ENA,0x00
e1bc80ad
MCC		 443 },
444 { /* 0xd0 */
3ad96835 445 TVP5150_LINE_MODE_INI,0x00
e1bc80ad
MCC		 446 },
447 { /* 0xfc */
448 TVP5150_FULL_FIELD_MODE_REG,0x7f
449 },
450 { /* end of data */
451 0xff,0xff
452 }
453};
454
455/* Default values as sugested at TVP5150AM1 datasheet */
456static const struct i2c_reg_value tvp5150_init_enable[] = {
457 {
458 TVP5150_CONF_SHARED_PIN, 2
459 },{ /* Automatic offset and AGC enabled */
460 TVP5150_ANAL_CHL_CTL, 0x15
461 },{ /* Activate YCrCb output 0x9 or 0xd ? */
b4b2de38
LP		 462 TVP5150_MISC_CTL, TVP5150_MISC_CTL_GPCL |
463 TVP5150_MISC_CTL_INTREQ_OE |
464 TVP5150_MISC_CTL_YCBCR_OE |
465 TVP5150_MISC_CTL_SYNC_OE |
466 TVP5150_MISC_CTL_VBLANK |
467 TVP5150_MISC_CTL_CLOCK_OE,
e1bc80ad
MCC		 468 },{ /* Activates video std autodetection for all standards */
469 TVP5150_AUTOSW_MSK, 0x0
470 },{ /* Default format: 0x47. For 4:2:2: 0x40 */
471 TVP5150_DATA_RATE_SEL, 0x47
472 },{
473 TVP5150_CHROMA_PROC_CTL_1, 0x0c
474 },{
475 TVP5150_CHROMA_PROC_CTL_2, 0x54
476 },{ /* Non documented, but initialized on WinTV USB2 */
477 0x27, 0x20
478 },{
479 0xff,0xff
480 }
481};
482
6ac48b45
MCC		 483struct tvp5150_vbi_type {
484 unsigned int vbi_type;
485 unsigned int ini_line;
486 unsigned int end_line;
487 unsigned int by_field :1;
488};
489
e1bc80ad
MCC		 490struct i2c_vbi_ram_value {
491 u16 reg;
6ac48b45
MCC		 492 struct tvp5150_vbi_type type;
493 unsigned char values[16];
e1bc80ad
MCC		 494};
495
6ac48b45
MCC		 496/* This struct have the values for each supported VBI Standard
497 * by
498 tvp5150_vbi_types should follow the same order as vbi_ram_default
3ad96835
MCC		 499 * value 0 means rom position 0x10, value 1 means rom position 0x30
500 * and so on. There are 16 possible locations from 0 to 15.
501 */
3ad96835 502
a9cff90e 503static struct i2c_vbi_ram_value vbi_ram_default[] =
cd4665c5 504{
9bc7400a
HV		 505 /* FIXME: Current api doesn't handle all VBI types, those not
506 yet supported are placed under #if 0 */
507#if 0
3dd6b560 508 [0] = {0x010, /* Teletext, SECAM, WST System A */
6ac48b45
MCC		 509 {V4L2_SLICED_TELETEXT_SECAM,6,23,1},
510 { 0xaa, 0xaa, 0xff, 0xff, 0xe7, 0x2e, 0x20, 0x26,
511 0xe6, 0xb4, 0x0e, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 512 },
9bc7400a 513#endif
3dd6b560 514 [1] = {0x030, /* Teletext, PAL, WST System B */
9bc7400a 515 {V4L2_SLICED_TELETEXT_B,6,22,1},
6ac48b45
MCC		 516 { 0xaa, 0xaa, 0xff, 0xff, 0x27, 0x2e, 0x20, 0x2b,
517 0xa6, 0x72, 0x10, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 518 },
9bc7400a 519#if 0
3dd6b560 520 [2] = {0x050, /* Teletext, PAL, WST System C */
6ac48b45
MCC		 521 {V4L2_SLICED_TELETEXT_PAL_C,6,22,1},
522 { 0xaa, 0xaa, 0xff, 0xff, 0xe7, 0x2e, 0x20, 0x22,
523 0xa6, 0x98, 0x0d, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 524 },
3dd6b560 525 [3] = {0x070, /* Teletext, NTSC, WST System B */
6ac48b45
MCC		 526 {V4L2_SLICED_TELETEXT_NTSC_B,10,21,1},
527 { 0xaa, 0xaa, 0xff, 0xff, 0x27, 0x2e, 0x20, 0x23,
528 0x69, 0x93, 0x0d, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 529 },
3dd6b560 530 [4] = {0x090, /* Tetetext, NTSC NABTS System C */
6ac48b45
MCC		 531 {V4L2_SLICED_TELETEXT_NTSC_C,10,21,1},
532 { 0xaa, 0xaa, 0xff, 0xff, 0xe7, 0x2e, 0x20, 0x22,
533 0x69, 0x93, 0x0d, 0x00, 0x00, 0x00, 0x15, 0x00 }
e1bc80ad 534 },
3dd6b560 535 [5] = {0x0b0, /* Teletext, NTSC-J, NABTS System D */
6ac48b45
MCC		 536 {V4L2_SLICED_TELETEXT_NTSC_D,10,21,1},
537 { 0xaa, 0xaa, 0xff, 0xff, 0xa7, 0x2e, 0x20, 0x23,
538 0x69, 0x93, 0x0d, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 539 },
3dd6b560 540 [6] = {0x0d0, /* Closed Caption, PAL/SECAM */
6ac48b45
MCC		 541 {V4L2_SLICED_CAPTION_625,22,22,1},
542 { 0xaa, 0x2a, 0xff, 0x3f, 0x04, 0x51, 0x6e, 0x02,
543 0xa6, 0x7b, 0x09, 0x00, 0x00, 0x00, 0x27, 0x00 }
e1bc80ad 544 },
9bc7400a 545#endif
3dd6b560 546 [7] = {0x0f0, /* Closed Caption, NTSC */
6ac48b45
MCC		 547 {V4L2_SLICED_CAPTION_525,21,21,1},
548 { 0xaa, 0x2a, 0xff, 0x3f, 0x04, 0x51, 0x6e, 0x02,
549 0x69, 0x8c, 0x09, 0x00, 0x00, 0x00, 0x27, 0x00 }
e1bc80ad 550 },
3dd6b560 551 [8] = {0x110, /* Wide Screen Signal, PAL/SECAM */
12db5607 552 {V4L2_SLICED_WSS_625,23,23,1},
6ac48b45
MCC		 553 { 0x5b, 0x55, 0xc5, 0xff, 0x00, 0x71, 0x6e, 0x42,
554 0xa6, 0xcd, 0x0f, 0x00, 0x00, 0x00, 0x3a, 0x00 }
e1bc80ad 555 },
9bc7400a 556#if 0
3dd6b560 557 [9] = {0x130, /* Wide Screen Signal, NTSC C */
6ac48b45
MCC		 558 {V4L2_SLICED_WSS_525,20,20,1},
559 { 0x38, 0x00, 0x3f, 0x00, 0x00, 0x71, 0x6e, 0x43,
560 0x69, 0x7c, 0x08, 0x00, 0x00, 0x00, 0x39, 0x00 }
e1bc80ad 561 },
3dd6b560 562 [10] = {0x150, /* Vertical Interval Timecode (VITC), PAL/SECAM */
6ac48b45
MCC		 563 {V4l2_SLICED_VITC_625,6,22,0},
564 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x8f, 0x6d, 0x49,
565 0xa6, 0x85, 0x08, 0x00, 0x00, 0x00, 0x4c, 0x00 }
e1bc80ad 566 },
3dd6b560 567 [11] = {0x170, /* Vertical Interval Timecode (VITC), NTSC */
6ac48b45
MCC		 568 {V4l2_SLICED_VITC_525,10,20,0},
569 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x8f, 0x6d, 0x49,
570 0x69, 0x94, 0x08, 0x00, 0x00, 0x00, 0x4c, 0x00 }
e1bc80ad 571 },
9bc7400a 572#endif
3dd6b560 573 [12] = {0x190, /* Video Program System (VPS), PAL */
6ac48b45
MCC		 574 {V4L2_SLICED_VPS,16,16,0},
575 { 0xaa, 0xaa, 0xff, 0xff, 0xba, 0xce, 0x2b, 0x0d,
576 0xa6, 0xda, 0x0b, 0x00, 0x00, 0x00, 0x60, 0x00 }
3ad96835 577 },
6ac48b45 578 /* 0x1d0 User programmable */
e1bc80ad 579};
4c86f973 580
6b8fe025 581static int tvp5150_write_inittab(struct v4l2_subdev *sd,
6ac48b45 582 const struct i2c_reg_value *regs)
e1bc80ad
MCC		 583{
584 while (regs->reg != 0xff) {
6b8fe025 585 tvp5150_write(sd, regs->reg, regs->value);
e1bc80ad
MCC		 586 regs++;
587 }
588 return 0;
589}
84486d53 590
3dd6b560 591static int tvp5150_vdp_init(struct v4l2_subdev *sd)
e1bc80ad
MCC		 592{
593 unsigned int i;
3dd6b560 594 int j;
cd4665c5 595
e1bc80ad 596 /* Disable Full Field */
6b8fe025 597 tvp5150_write(sd, TVP5150_FULL_FIELD_ENA, 0);
cd4665c5 598
e1bc80ad 599 /* Before programming, Line mode should be at 0xff */
6b8fe025
HV		 600 for (i = TVP5150_LINE_MODE_INI; i <= TVP5150_LINE_MODE_END; i++)
601 tvp5150_write(sd, i, 0xff);
cd4665c5 602
e1bc80ad 603 /* Load Ram Table */
3dd6b560
MCC		 604 for (j = 0; j < ARRAY_SIZE(vbi_ram_default); j++) {
605 const struct i2c_vbi_ram_value *regs = &vbi_ram_default[j];
606
607 if (!regs->type.vbi_type)
608 continue;
609
6b8fe025
HV		 610 tvp5150_write(sd, TVP5150_CONF_RAM_ADDR_HIGH, regs->reg >> 8);
611 tvp5150_write(sd, TVP5150_CONF_RAM_ADDR_LOW, regs->reg);
cd4665c5 612
6b8fe025
HV		 613 for (i = 0; i < 16; i++)
614 tvp5150_write(sd, TVP5150_VDP_CONF_RAM_DATA, regs->values[i]);
e1bc80ad
MCC		 615 }
616 return 0;
617}
cd4665c5 618
6ac48b45 619/* Fills VBI capabilities based on i2c_vbi_ram_value struct */
6b8fe025 620static int tvp5150_g_sliced_vbi_cap(struct v4l2_subdev *sd,
6ac48b45
MCC		 621 struct v4l2_sliced_vbi_cap *cap)
622{
3dd6b560 623 int line, i;
6ac48b45 624
257e29f8 625 dev_dbg_lvl(sd->dev, 1, debug, "g_sliced_vbi_cap\n");
6ac48b45
MCC		 626 memset(cap, 0, sizeof *cap);
627
3dd6b560
MCC		 628 for (i = 0; i < ARRAY_SIZE(vbi_ram_default); i++) {
629 const struct i2c_vbi_ram_value *regs = &vbi_ram_default[i];
630
631 if (!regs->type.vbi_type)
632 continue;
633
634 for (line = regs->type.ini_line;
635 line <= regs->type.end_line;
636 line++) {
6ac48b45
MCC		 637 cap->service_lines[0][line] |= regs->type.vbi_type;
638 }
639 cap->service_set |= regs->type.vbi_type;
6ac48b45 640 }
6b8fe025 641 return 0;
6ac48b45
MCC		 642}
643
3ad96835
MCC		 644/* Set vbi processing
645 * type - one of tvp5150_vbi_types
646 * line - line to gather data
647 * fields: bit 0 field1, bit 1, field2
648 * flags (default=0xf0) is a bitmask, were set means:
649 * bit 7: enable filtering null bytes on CC
650 * bit 6: send data also to FIFO
651 * bit 5: don't allow data with errors on FIFO
652 * bit 4: enable ECC when possible
653 * pix_align = pix alignment:
654 * LSB = field1
655 * MSB = field2
656 */
6b8fe025 657static int tvp5150_set_vbi(struct v4l2_subdev *sd,
2701dacb
MCC		 658 unsigned int type,u8 flags, int line,
659 const int fields)
3ad96835 660{
6b8fe025
HV		 661 struct tvp5150 *decoder = to_tvp5150(sd);
662 v4l2_std_id std = decoder->norm;
3ad96835 663 u8 reg;
3dd6b560 664 int i, pos = 0;
3ad96835
MCC		 665
666 if (std == V4L2_STD_ALL) {
257e29f8 667 dev_err(sd->dev, "VBI can't be configured without knowing number of lines\n");
12db5607 668 return 0;
7d5b7b98 669 } else if (std & V4L2_STD_625_50) {
3ad96835
MCC		 670 /* Don't follow NTSC Line number convension */
671 line += 3;
672 }
673
b3d930aa 674 if (line < 6 || line > 27)
2701dacb
MCC		 675 return 0;
676
3dd6b560
MCC		 677 for (i = 0; i < ARRAY_SIZE(vbi_ram_default); i++) {
678 const struct i2c_vbi_ram_value *regs = &vbi_ram_default[i];
679
680 if (!regs->type.vbi_type)
681 continue;
682
2701dacb 683 if ((type & regs->type.vbi_type) &&
b3d930aa
GS		 684 (line >= regs->type.ini_line) &&
685 (line <= regs->type.end_line))
2701dacb 686 break;
2701dacb
MCC		 687 pos++;
688 }
b3d930aa 689
b3d930aa
GS		 690 type = pos | (flags & 0xf0);
691 reg = ((line - 6) << 1) + TVP5150_LINE_MODE_INI;
3ad96835 692
b3d930aa 693 if (fields & 1)
6b8fe025 694 tvp5150_write(sd, reg, type);
3ad96835 695
b3d930aa
GS		 696 if (fields & 2)
697 tvp5150_write(sd, reg + 1, type);
3ad96835 698
2701dacb 699 return type;
3ad96835
MCC		 700}
701
3dd6b560 702static int tvp5150_get_vbi(struct v4l2_subdev *sd, int line)
12db5607 703{
6b8fe025
HV		 704 struct tvp5150 *decoder = to_tvp5150(sd);
705 v4l2_std_id std = decoder->norm;
12db5607 706 u8 reg;
6b8fe025 707 int pos, type = 0;
8cd0d4ca 708 int i, ret = 0;
12db5607
MCC		 709
710 if (std == V4L2_STD_ALL) {
257e29f8 711 dev_err(sd->dev, "VBI can't be configured without knowing number of lines\n");
12db5607 712 return 0;
7d5b7b98 713 } else if (std & V4L2_STD_625_50) {
12db5607
MCC		 714 /* Don't follow NTSC Line number convension */
715 line += 3;
716 }
717
6b8fe025 718 if (line < 6 || line > 27)
12db5607
MCC		 719 return 0;
720
6b8fe025 721 reg = ((line - 6) << 1) + TVP5150_LINE_MODE_INI;
12db5607 722
8cd0d4ca
DL		 723 for (i = 0; i <= 1; i++) {
724 ret = tvp5150_read(sd, reg + i);
725 if (ret < 0) {
257e29f8 726 dev_err(sd->dev, "%s: failed with error = %d\n",
8cd0d4ca
DL		 727 __func__, ret);
728 return 0;
729 }
730 pos = ret & 0x0f;
3dd6b560
MCC		 731 if (pos < ARRAY_SIZE(vbi_ram_default))
732 type |= vbi_ram_default[pos].type.vbi_type;
8cd0d4ca 733 }
12db5607
MCC		 734
735 return type;
736}
6b8fe025
HV		 737
738static int tvp5150_set_std(struct v4l2_subdev *sd, v4l2_std_id std)
e1bc80ad 739{
6b8fe025
HV		 740 struct tvp5150 *decoder = to_tvp5150(sd);
741 int fmt = 0;
e1bc80ad 742
6b8fe025 743 decoder->norm = std;
e1bc80ad
MCC		 744
745 /* First tests should be against specific std */
746
26811ae0 747 if (std == V4L2_STD_NTSC_443) {
2da12fcb 748 fmt = VIDEO_STD_NTSC_4_43_BIT;
26811ae0 749 } else if (std == V4L2_STD_PAL_M) {
2da12fcb 750 fmt = VIDEO_STD_PAL_M_BIT;
26811ae0 751 } else if (std == V4L2_STD_PAL_N || std == V4L2_STD_PAL_Nc) {
2da12fcb 752 fmt = VIDEO_STD_PAL_COMBINATION_N_BIT;
e1bc80ad
MCC		 753 } else {
754 /* Then, test against generic ones */
6b8fe025 755 if (std & V4L2_STD_NTSC)
2da12fcb 756 fmt = VIDEO_STD_NTSC_MJ_BIT;
6b8fe025 757 else if (std & V4L2_STD_PAL)
2da12fcb 758 fmt = VIDEO_STD_PAL_BDGHIN_BIT;
6b8fe025 759 else if (std & V4L2_STD_SECAM)
2da12fcb 760 fmt = VIDEO_STD_SECAM_BIT;
e1bc80ad 761 }
84486d53 762
257e29f8 763 dev_dbg_lvl(sd->dev, 1, debug, "Set video std register to %d.\n", fmt);
6b8fe025 764 tvp5150_write(sd, TVP5150_VIDEO_STD, fmt);
e1bc80ad
MCC		 765 return 0;
766}
767
6b8fe025
HV		 768static int tvp5150_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
769{
770 struct tvp5150 *decoder = to_tvp5150(sd);
771
772 if (decoder->norm == std)
773 return 0;
774
963ddc63
JM		 775 /* Change cropping height limits */
776 if (std & V4L2_STD_525_60)
777 decoder->rect.height = TVP5150_V_MAX_525_60;
778 else
779 decoder->rect.height = TVP5150_V_MAX_OTHERS;
780
781
6b8fe025
HV		 782 return tvp5150_set_std(sd, std);
783}
784
785static int tvp5150_reset(struct v4l2_subdev *sd, u32 val)
e1bc80ad 786{
6b8fe025 787 struct tvp5150 *decoder = to_tvp5150(sd);
84486d53 788
e1bc80ad 789 /* Initializes TVP5150 to its default values */
6b8fe025 790 tvp5150_write_inittab(sd, tvp5150_init_default);
e1bc80ad
MCC		 791
792 /* Initializes VDP registers */
3dd6b560 793 tvp5150_vdp_init(sd);
e1bc80ad
MCC		 794
795 /* Selects decoder input */
6b8fe025 796 tvp5150_selmux(sd);
e1bc80ad
MCC		 797
798 /* Initializes TVP5150 to stream enabled values */
6b8fe025 799 tvp5150_write_inittab(sd, tvp5150_init_enable);
e1bc80ad
MCC		 800
801 /* Initialize image preferences */
6c45ec71 802 v4l2_ctrl_handler_setup(&decoder->hdl);
e1bc80ad 803
6b8fe025 804 tvp5150_set_std(sd, decoder->norm);
a2e5f1b3
JMC		 805
806 if (decoder->mbus_type == V4L2_MBUS_PARALLEL)
807 tvp5150_write(sd, TVP5150_DATA_RATE_SEL, 0x40);
808
6b8fe025 809 return 0;
cd4665c5
MCC		 810};
811
6c45ec71 812static int tvp5150_s_ctrl(struct v4l2_ctrl *ctrl)
a6c2ba28 813{
6c45ec71 814 struct v4l2_subdev *sd = to_sd(ctrl);
c43875f6 815 struct tvp5150 *decoder = to_tvp5150(sd);
a6c2ba28 816
817 switch (ctrl->id) {
818 case V4L2_CID_BRIGHTNESS:
6c45ec71 819 tvp5150_write(sd, TVP5150_BRIGHT_CTL, ctrl->val);
a6c2ba28 820 return 0;
821 case V4L2_CID_CONTRAST:
6c45ec71 822 tvp5150_write(sd, TVP5150_CONTRAST_CTL, ctrl->val);
a6c2ba28 823 return 0;
824 case V4L2_CID_SATURATION:
6c45ec71 825 tvp5150_write(sd, TVP5150_SATURATION_CTL, ctrl->val);
a6c2ba28 826 return 0;
827 case V4L2_CID_HUE:
6c45ec71 828 tvp5150_write(sd, TVP5150_HUE_CTL, ctrl->val);
d183e4ef 829 break;
c43875f6
MCC		 830 case V4L2_CID_TEST_PATTERN:
831 decoder->enable = ctrl->val ? false : true;
832 tvp5150_selmux(sd);
a6c2ba28 833 return 0;
a6c2ba28 834 }
c0477ad9 835 return -EINVAL;
a6c2ba28 836}
837
ec2c4f3f
JM		 838static v4l2_std_id tvp5150_read_std(struct v4l2_subdev *sd)
839{
840 int val = tvp5150_read(sd, TVP5150_STATUS_REG_5);
841
842 switch (val & 0x0F) {
843 case 0x01:
844 return V4L2_STD_NTSC;
845 case 0x03:
846 return V4L2_STD_PAL;
847 case 0x05:
848 return V4L2_STD_PAL_M;
849 case 0x07:
850 return V4L2_STD_PAL_N | V4L2_STD_PAL_Nc;
851 case 0x09:
852 return V4L2_STD_NTSC_443;
853 case 0xb:
854 return V4L2_STD_SECAM;
855 default:
856 return V4L2_STD_UNKNOWN;
857 }
858}
859
da298c6d
HV		 860static int tvp5150_fill_fmt(struct v4l2_subdev *sd,
861 struct v4l2_subdev_pad_config *cfg,
862 struct v4l2_subdev_format *format)
ec2c4f3f 863{
da298c6d 864 struct v4l2_mbus_framefmt *f;
ec2c4f3f 865 struct tvp5150 *decoder = to_tvp5150(sd);
ec2c4f3f 866
f6f0e2f5 867 if (!format || (format->pad != DEMOD_PAD_VID_OUT))
ec2c4f3f
JM		 868 return -EINVAL;
869
da298c6d
HV		 870 f = &format->format;
871
963ddc63 872 f->width = decoder->rect.width;
0866df8d 873 f->height = decoder->rect.height;
ec2c4f3f 874
f5fe58fd 875 f->code = MEDIA_BUS_FMT_UYVY8_2X8;
4f57d27b 876 f->field = V4L2_FIELD_ALTERNATE;
ec2c4f3f
JM		 877 f->colorspace = V4L2_COLORSPACE_SMPTE170M;
878
257e29f8 879 dev_dbg_lvl(sd->dev, 1, debug, "width = %d, height = %d\n", f->width,
ec2c4f3f
JM		 880 f->height);
881 return 0;
882}
883
10d5509c
HV		 884static int tvp5150_set_selection(struct v4l2_subdev *sd,
885 struct v4l2_subdev_pad_config *cfg,
886 struct v4l2_subdev_selection *sel)
963ddc63 887{
963ddc63 888 struct tvp5150 *decoder = to_tvp5150(sd);
10d5509c 889 struct v4l2_rect rect = sel->r;
963ddc63 890 v4l2_std_id std;
10d5509c
HV		 891 int hmax;
892
893 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE ||
894 sel->target != V4L2_SEL_TGT_CROP)
895 return -EINVAL;
963ddc63 896
257e29f8 897 dev_dbg_lvl(sd->dev, 1, debug, "%s left=%d, top=%d, width=%d, height=%d\n",
963ddc63
JM		 898 __func__, rect.left, rect.top, rect.width, rect.height);
899
963ddc63
JM		 900 /* tvp5150 has some special limits */
901 rect.left = clamp(rect.left, 0, TVP5150_MAX_CROP_LEFT);
f90580ca
RR		 902 rect.width = clamp_t(unsigned int, rect.width,
903 TVP5150_H_MAX - TVP5150_MAX_CROP_LEFT - rect.left,
904 TVP5150_H_MAX - rect.left);
963ddc63
JM		 905 rect.top = clamp(rect.top, 0, TVP5150_MAX_CROP_TOP);
906
907 /* Calculate height based on current standard */
908 if (decoder->norm == V4L2_STD_ALL)
909 std = tvp5150_read_std(sd);
910 else
911 std = decoder->norm;
912
913 if (std & V4L2_STD_525_60)
914 hmax = TVP5150_V_MAX_525_60;
915 else
916 hmax = TVP5150_V_MAX_OTHERS;
917
f90580ca
RR		 918 rect.height = clamp_t(unsigned int, rect.height,
919 hmax - TVP5150_MAX_CROP_TOP - rect.top,
920 hmax - rect.top);
963ddc63
JM		 921
922 tvp5150_write(sd, TVP5150_VERT_BLANKING_START, rect.top);
923 tvp5150_write(sd, TVP5150_VERT_BLANKING_STOP,
924 rect.top + rect.height - hmax);
925 tvp5150_write(sd, TVP5150_ACT_VD_CROP_ST_MSB,
926 rect.left >> TVP5150_CROP_SHIFT);
927 tvp5150_write(sd, TVP5150_ACT_VD_CROP_ST_LSB,
928 rect.left | (1 << TVP5150_CROP_SHIFT));
929 tvp5150_write(sd, TVP5150_ACT_VD_CROP_STP_MSB,
930 (rect.left + rect.width - TVP5150_MAX_CROP_LEFT) >>
931 TVP5150_CROP_SHIFT);
932 tvp5150_write(sd, TVP5150_ACT_VD_CROP_STP_LSB,
933 rect.left + rect.width - TVP5150_MAX_CROP_LEFT);
934
935 decoder->rect = rect;
936
937 return 0;
938}
939
10d5509c
HV		 940static int tvp5150_get_selection(struct v4l2_subdev *sd,
941 struct v4l2_subdev_pad_config *cfg,
942 struct v4l2_subdev_selection *sel)
963ddc63 943{
10d5509c 944 struct tvp5150 *decoder = container_of(sd, struct tvp5150, sd);
963ddc63
JM		 945 v4l2_std_id std;
946
10d5509c 947 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
963ddc63
JM		 948 return -EINVAL;
949
10d5509c
HV		 950 switch (sel->target) {
951 case V4L2_SEL_TGT_CROP_BOUNDS:
952 case V4L2_SEL_TGT_CROP_DEFAULT:
953 sel->r.left = 0;
954 sel->r.top = 0;
955 sel->r.width = TVP5150_H_MAX;
956
957 /* Calculate height based on current standard */
958 if (decoder->norm == V4L2_STD_ALL)
959 std = tvp5150_read_std(sd);
960 else
961 std = decoder->norm;
962 if (std & V4L2_STD_525_60)
963 sel->r.height = TVP5150_V_MAX_525_60;
964 else
965 sel->r.height = TVP5150_V_MAX_OTHERS;
966 return 0;
967 case V4L2_SEL_TGT_CROP:
968 sel->r = decoder->rect;
969 return 0;
970 default:
971 return -EINVAL;
972 }
963ddc63
JM		 973}
974
dd3a46bb
LP		 975static int tvp5150_g_mbus_config(struct v4l2_subdev *sd,
976 struct v4l2_mbus_config *cfg)
977{
a2e5f1b3
JMC		 978 struct tvp5150 *decoder = to_tvp5150(sd);
979
980 cfg->type = decoder->mbus_type;
dd3a46bb
LP		 981 cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING
982 | V4L2_MBUS_FIELD_EVEN_LOW | V4L2_MBUS_DATA_ACTIVE_HIGH;
983
984 return 0;
985}
986
e545ac87
LP		 987/****************************************************************************
988 V4L2 subdev pad ops
989 ****************************************************************************/
990static int tvp5150_enum_mbus_code(struct v4l2_subdev *sd,
991 struct v4l2_subdev_pad_config *cfg,
992 struct v4l2_subdev_mbus_code_enum *code)
993{
994 if (code->pad || code->index)
995 return -EINVAL;
996
997 code->code = MEDIA_BUS_FMT_UYVY8_2X8;
998 return 0;
999}
1000
1001static int tvp5150_enum_frame_size(struct v4l2_subdev *sd,
1002 struct v4l2_subdev_pad_config *cfg,
1003 struct v4l2_subdev_frame_size_enum *fse)
1004{
1005 struct tvp5150 *decoder = to_tvp5150(sd);
1006
1007 if (fse->index >= 8 || fse->code != MEDIA_BUS_FMT_UYVY8_2X8)
1008 return -EINVAL;
1009
1010 fse->code = MEDIA_BUS_FMT_UYVY8_2X8;
1011 fse->min_width = decoder->rect.width;
1012 fse->max_width = decoder->rect.width;
1013 fse->min_height = decoder->rect.height / 2;
1014 fse->max_height = decoder->rect.height / 2;
1015
1016 return 0;
1017}
1018
f7b4b54e
JMC		 1019/****************************************************************************
1020 Media entity ops
1021 ****************************************************************************/
1022
406ff67d 1023#ifdef CONFIG_MEDIA_CONTROLLER
f7b4b54e
JMC		 1024static int tvp5150_link_setup(struct media_entity *entity,
1025 const struct media_pad *local,
1026 const struct media_pad *remote, u32 flags)
1027{
f7b4b54e
JMC		 1028 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
1029 struct tvp5150 *decoder = to_tvp5150(sd);
1030 int i;
1031
1032 for (i = 0; i < TVP5150_INPUT_NUM; i++) {
1033 if (remote->entity == &decoder->input_ent[i])
1034 break;
1035 }
1036
1037 /* Do nothing for entities that are not input connectors */
1038 if (i == TVP5150_INPUT_NUM)
1039 return 0;
1040
1041 decoder->input = i;
1042
f7b4b54e 1043 tvp5150_selmux(sd);
f7b4b54e
JMC		 1044
1045 return 0;
1046}
1047
1048static const struct media_entity_operations tvp5150_sd_media_ops = {
1049 .link_setup = tvp5150_link_setup,
1050};
406ff67d 1051#endif
f7b4b54e 1052
84486d53
MCC		 1053/****************************************************************************
1054 I2C Command
1055 ****************************************************************************/
c7c0b34c 1056
460b6c08
LP		 1057static int tvp5150_s_stream(struct v4l2_subdev *sd, int enable)
1058{
a2e5f1b3 1059 struct tvp5150 *decoder = to_tvp5150(sd);
79d6205a 1060 int val;
a2e5f1b3 1061
79d6205a
LP		 1062 /* Enable or disable the video output signals. */
1063 val = tvp5150_read(sd, TVP5150_MISC_CTL);
1064 if (val < 0)
1065 return val;
1066
1067 val &= ~(TVP5150_MISC_CTL_YCBCR_OE | TVP5150_MISC_CTL_SYNC_OE |
1068 TVP5150_MISC_CTL_CLOCK_OE);
1069
1070 if (enable) {
1071 /*
1072 * Enable the YCbCr and clock outputs. In discrete sync mode
1073 * (non-BT.656) additionally enable the the sync outputs.
1074 */
1075 val |= TVP5150_MISC_CTL_YCBCR_OE | TVP5150_MISC_CTL_CLOCK_OE;
1076 if (decoder->mbus_type == V4L2_MBUS_PARALLEL)
1077 val |= TVP5150_MISC_CTL_SYNC_OE;
1078 }
460b6c08 1079
79d6205a 1080 tvp5150_write(sd, TVP5150_MISC_CTL, val);
460b6c08
LP		 1081
1082 return 0;
1083}
1084
5325b427
HV		 1085static int tvp5150_s_routing(struct v4l2_subdev *sd,
1086 u32 input, u32 output, u32 config)
6b8fe025
HV		 1087{
1088 struct tvp5150 *decoder = to_tvp5150(sd);
84486d53 1089
5325b427
HV		 1090 decoder->input = input;
1091 decoder->output = output;
c43875f6
MCC		 1092
1093 if (output == TVP5150_BLACK_SCREEN)
1094 decoder->enable = false;
1095 else
1096 decoder->enable = true;
1097
6b8fe025
HV		 1098 tvp5150_selmux(sd);
1099 return 0;
1100}
6ac48b45 1101
d37dad49
HV		 1102static int tvp5150_s_raw_fmt(struct v4l2_subdev *sd, struct v4l2_vbi_format *fmt)
1103{
1104 /* this is for capturing 36 raw vbi lines
1105 if there's a way to cut off the beginning 2 vbi lines
1106 with the tvp5150 then the vbi line count could be lowered
1107 to 17 lines/field again, although I couldn't find a register
1108 which could do that cropping */
1109 if (fmt->sample_format == V4L2_PIX_FMT_GREY)
1110 tvp5150_write(sd, TVP5150_LUMA_PROC_CTL_1, 0x70);
1111 if (fmt->count[0] == 18 && fmt->count[1] == 18) {
1112 tvp5150_write(sd, TVP5150_VERT_BLANKING_START, 0x00);
1113 tvp5150_write(sd, TVP5150_VERT_BLANKING_STOP, 0x01);
1114 }
1115 return 0;
1116}
1117
1118static int tvp5150_s_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *svbi)
6b8fe025 1119{
6b8fe025
HV		 1120 int i;
1121
6b8fe025
HV		 1122 if (svbi->service_set != 0) {
1123 for (i = 0; i <= 23; i++) {
1124 svbi->service_lines[1][i] = 0;
1125 svbi->service_lines[0][i] =
3dd6b560
MCC		 1126 tvp5150_set_vbi(sd, svbi->service_lines[0][i],
1127 0xf0, i, 3);
2c5aacc6 1128 }
6b8fe025
HV		 1129 /* Enables FIFO */
1130 tvp5150_write(sd, TVP5150_FIFO_OUT_CTRL, 1);
1131 } else {
1132 /* Disables FIFO*/
1133 tvp5150_write(sd, TVP5150_FIFO_OUT_CTRL, 0);
12db5607 1134
6b8fe025
HV		 1135 /* Disable Full Field */
1136 tvp5150_write(sd, TVP5150_FULL_FIELD_ENA, 0);
12db5607 1137
6b8fe025
HV		 1138 /* Disable Line modes */
1139 for (i = TVP5150_LINE_MODE_INI; i <= TVP5150_LINE_MODE_END; i++)
1140 tvp5150_write(sd, i, 0xff);
12db5607 1141 }
6b8fe025
HV		 1142 return 0;
1143}
12db5607 1144
d37dad49
HV		 1145static int tvp5150_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *svbi)
1146{
1147 int i, mask = 0;
1148
30634e8e 1149 memset(svbi->service_lines, 0, sizeof(svbi->service_lines));
12db5607 1150
6b8fe025
HV		 1151 for (i = 0; i <= 23; i++) {
1152 svbi->service_lines[0][i] =
3dd6b560 1153 tvp5150_get_vbi(sd, i);
6b8fe025 1154 mask |= svbi->service_lines[0][i];
2701dacb 1155 }
6b8fe025
HV		 1156 svbi->service_set = mask;
1157 return 0;
1158}
1159
21dcd8cc 1160#ifdef CONFIG_VIDEO_ADV_DEBUG
aecde8b5 1161static int tvp5150_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
6b8fe025 1162{
8cd0d4ca
DL		 1163 int res;
1164
8cd0d4ca
DL		 1165 res = tvp5150_read(sd, reg->reg & 0xff);
1166 if (res < 0) {
257e29f8 1167 dev_err(sd->dev, "%s: failed with error = %d\n", __func__, res);
8cd0d4ca
DL		 1168 return res;
1169 }
1170
1171 reg->val = res;
aecde8b5 1172 reg->size = 1;
6b8fe025
HV		 1173 return 0;
1174}
84486d53 1175
977ba3b1 1176static int tvp5150_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
6b8fe025 1177{
eca4ca84 1178 return tvp5150_write(sd, reg->reg & 0xff, reg->val & 0xff);
6b8fe025
HV		 1179}
1180#endif
a6c2ba28 1181
6b8fe025
HV		 1182static int tvp5150_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1183{
1184 int status = tvp5150_read(sd, 0x88);
a6c2ba28 1185
6b8fe025
HV		 1186 vt->signal = ((status & 0x04) && (status & 0x02)) ? 0xffff : 0x0;
1187 return 0;
1188}
a6c2ba28 1189
5a08bc00 1190static int tvp5150_registered(struct v4l2_subdev *sd)
f7b4b54e
JMC		 1191{
1192#ifdef CONFIG_MEDIA_CONTROLLER
1193 struct tvp5150 *decoder = to_tvp5150(sd);
1194 int ret = 0;
1195 int i;
1196
1197 for (i = 0; i < TVP5150_INPUT_NUM; i++) {
1198 struct media_entity *input = &decoder->input_ent[i];
1199 struct media_pad *pad = &decoder->input_pad[i];
1200
1201 if (!input->name)
1202 continue;
1203
1204 decoder->input_pad[i].flags = MEDIA_PAD_FL_SOURCE;
1205
1206 ret = media_entity_pads_init(input, 1, pad);
1207 if (ret < 0)
1208 return ret;
1209
1210 ret = media_device_register_entity(sd->v4l2_dev->mdev, input);
1211 if (ret < 0)
1212 return ret;
1213
1214 ret = media_create_pad_link(input, 0, &sd->entity,
1215 DEMOD_PAD_IF_INPUT, 0);
1216 if (ret < 0) {
1217 media_device_unregister_entity(input);
1218 return ret;
1219 }
1220 }
1221#endif
1222
1223 return 0;
1224}
1225
6b8fe025
HV		 1226/* ----------------------------------------------------------------------- */
1227
6c45ec71
HV		 1228static const struct v4l2_ctrl_ops tvp5150_ctrl_ops = {
1229 .s_ctrl = tvp5150_s_ctrl,
1230};
1231
6b8fe025
HV		 1232static const struct v4l2_subdev_core_ops tvp5150_core_ops = {
1233 .log_status = tvp5150_log_status,
6b8fe025
HV		 1234 .reset = tvp5150_reset,
1235#ifdef CONFIG_VIDEO_ADV_DEBUG
1236 .g_register = tvp5150_g_register,
1237 .s_register = tvp5150_s_register,
1238#endif
1239};
1240
1241static const struct v4l2_subdev_tuner_ops tvp5150_tuner_ops = {
6b8fe025
HV		 1242 .g_tuner = tvp5150_g_tuner,
1243};
1244
1245static const struct v4l2_subdev_video_ops tvp5150_video_ops = {
8774bed9 1246 .s_std = tvp5150_s_std,
460b6c08 1247 .s_stream = tvp5150_s_stream,
6b8fe025 1248 .s_routing = tvp5150_s_routing,
dd3a46bb 1249 .g_mbus_config = tvp5150_g_mbus_config,
32cd527f
HV		 1250};
1251
1252static const struct v4l2_subdev_vbi_ops tvp5150_vbi_ops = {
6b8fe025 1253 .g_sliced_vbi_cap = tvp5150_g_sliced_vbi_cap,
d37dad49
HV		 1254 .g_sliced_fmt = tvp5150_g_sliced_fmt,
1255 .s_sliced_fmt = tvp5150_s_sliced_fmt,
1256 .s_raw_fmt = tvp5150_s_raw_fmt,
6b8fe025
HV		 1257};
1258
ebcff5fc
HV		 1259static const struct v4l2_subdev_pad_ops tvp5150_pad_ops = {
1260 .enum_mbus_code = tvp5150_enum_mbus_code,
e545ac87 1261 .enum_frame_size = tvp5150_enum_frame_size,
da298c6d
HV		 1262 .set_fmt = tvp5150_fill_fmt,
1263 .get_fmt = tvp5150_fill_fmt,
10d5509c
HV		 1264 .get_selection = tvp5150_get_selection,
1265 .set_selection = tvp5150_set_selection,
ebcff5fc
HV		 1266};
1267
6b8fe025
HV		 1268static const struct v4l2_subdev_ops tvp5150_ops = {
1269 .core = &tvp5150_core_ops,
1270 .tuner = &tvp5150_tuner_ops,
1271 .video = &tvp5150_video_ops,
32cd527f 1272 .vbi = &tvp5150_vbi_ops,
ebcff5fc 1273 .pad = &tvp5150_pad_ops,
6b8fe025
HV		 1274};
1275
5a08bc00
JMC		 1276static const struct v4l2_subdev_internal_ops tvp5150_internal_ops = {
1277 .registered = tvp5150_registered,
1278};
1279
6b8fe025 1280
cd4665c5
MCC		 1281/****************************************************************************
1282 I2C Client & Driver
1283 ****************************************************************************/
cd4665c5 1284
7871597a
LP		 1285static int tvp5150_detect_version(struct tvp5150 *core)
1286{
1287 struct v4l2_subdev *sd = &core->sd;
1288 struct i2c_client *c = v4l2_get_subdevdata(sd);
1289 unsigned int i;
7871597a
LP		 1290 u8 regs[4];
1291 int res;
1292
1293 /*
1294 * Read consequent registers - TVP5150_MSB_DEV_ID, TVP5150_LSB_DEV_ID,
1295 * TVP5150_ROM_MAJOR_VER, TVP5150_ROM_MINOR_VER
1296 */
1297 for (i = 0; i < 4; i++) {
1298 res = tvp5150_read(sd, TVP5150_MSB_DEV_ID + i);
1299 if (res < 0)
1300 return res;
1301 regs[i] = res;
1302 }
1303
82275133
JMC		 1304 core->dev_id = (regs[0] << 8) | regs[1];
1305 core->rom_ver = (regs[2] << 8) | regs[3];
7871597a 1306
257e29f8 1307 dev_info(sd->dev, "tvp%04x (%u.%u) chip found @ 0x%02x (%s)\n",
82275133
JMC		 1308 core->dev_id, regs[2], regs[3], c->addr << 1,
1309 c->adapter->name);
7871597a 1310
82275133 1311 if (core->dev_id == 0x5150 && core->rom_ver == 0x0321) {
257e29f8 1312 dev_info(sd->dev, "tvp5150a detected.\n");
82275133 1313 } else if (core->dev_id == 0x5150 && core->rom_ver == 0x0400) {
257e29f8 1314 dev_info(sd->dev, "tvp5150am1 detected.\n");
7871597a
LP		 1315
1316 /* ITU-T BT.656.4 timing */
1317 tvp5150_write(sd, TVP5150_REV_SELECT, 0);
82275133 1318 } else if (core->dev_id == 0x5151 && core->rom_ver == 0x0100) {
257e29f8 1319 dev_info(sd->dev, "tvp5151 detected.\n");
7871597a 1320 } else {
257e29f8 1321 dev_info(sd->dev, "*** unknown tvp%04x chip detected.\n",
82275133 1322 core->dev_id);
7871597a
LP		 1323 }
1324
1325 return 0;
1326}
1327
09aa2609
JMC		 1328static int tvp5150_init(struct i2c_client *c)
1329{
1330 struct gpio_desc *pdn_gpio;
1331 struct gpio_desc *reset_gpio;
1332
1333 pdn_gpio = devm_gpiod_get_optional(&c->dev, "pdn", GPIOD_OUT_HIGH);
1334 if (IS_ERR(pdn_gpio))
1335 return PTR_ERR(pdn_gpio);
1336
1337 if (pdn_gpio) {
1338 gpiod_set_value_cansleep(pdn_gpio, 0);
1339 /* Delay time between power supplies active and reset */
1340 msleep(20);
1341 }
1342
1343 reset_gpio = devm_gpiod_get_optional(&c->dev, "reset", GPIOD_OUT_HIGH);
1344 if (IS_ERR(reset_gpio))
1345 return PTR_ERR(reset_gpio);
1346
1347 if (reset_gpio) {
1348 /* RESETB pulse duration */
1349 ndelay(500);
1350 gpiod_set_value_cansleep(reset_gpio, 0);
1351 /* Delay time between end of reset to I2C active */
1352 usleep_range(200, 250);
1353 }
1354
1355 return 0;
1356}
1357
a2e5f1b3
JMC		 1358static int tvp5150_parse_dt(struct tvp5150 *decoder, struct device_node *np)
1359{
859969b3 1360 struct v4l2_fwnode_endpoint bus_cfg;
a2e5f1b3 1361 struct device_node *ep;
f7b4b54e
JMC		 1362#ifdef CONFIG_MEDIA_CONTROLLER
1363 struct device_node *connectors, *child;
1364 struct media_entity *input;
1365 const char *name;
1366 u32 input_type;
1367#endif
a2e5f1b3
JMC		 1368 unsigned int flags;
1369 int ret = 0;
1370
1371 ep = of_graph_get_next_endpoint(np, NULL);
1372 if (!ep)
1373 return -EINVAL;
1374
859969b3 1375 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &bus_cfg);
a2e5f1b3
JMC		 1376 if (ret)
1377 goto err;
1378
1379 flags = bus_cfg.bus.parallel.flags;
1380
1381 if (bus_cfg.bus_type == V4L2_MBUS_PARALLEL &&
1382 !(flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH &&
1383 flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH &&
2bd5e437
JMC		 1384 flags & V4L2_MBUS_FIELD_EVEN_LOW)) {
1385 ret = -EINVAL;
1386 goto err;
1387 }
a2e5f1b3
JMC		 1388
1389 decoder->mbus_type = bus_cfg.bus_type;
1390
f7b4b54e
JMC		 1391#ifdef CONFIG_MEDIA_CONTROLLER
1392 connectors = of_get_child_by_name(np, "connectors");
1393
1394 if (!connectors)
1395 goto err;
1396
1397 for_each_available_child_of_node(connectors, child) {
1398 ret = of_property_read_u32(child, "input", &input_type);
1399 if (ret) {
257e29f8 1400 dev_err(decoder->sd.dev,
f7b4b54e
JMC		 1401 "missing type property in node %s\n",
1402 child->name);
1403 goto err_connector;
1404 }
1405
60ad7689 1406 if (input_type >= TVP5150_INPUT_NUM) {
f7b4b54e
JMC		 1407 ret = -EINVAL;
1408 goto err_connector;
1409 }
1410
1411 input = &decoder->input_ent[input_type];
1412
1413 /* Each input connector can only be defined once */
1414 if (input->name) {
257e29f8 1415 dev_err(decoder->sd.dev,
f7b4b54e
JMC		 1416 "input %s with same type already exists\n",
1417 input->name);
1418 ret = -EINVAL;
1419 goto err_connector;
1420 }
1421
1422 switch (input_type) {
1423 case TVP5150_COMPOSITE0:
1424 case TVP5150_COMPOSITE1:
1425 input->function = MEDIA_ENT_F_CONN_COMPOSITE;
1426 break;
1427 case TVP5150_SVIDEO:
1428 input->function = MEDIA_ENT_F_CONN_SVIDEO;
1429 break;
f7b4b54e
JMC		 1430 }
1431
1432 input->flags = MEDIA_ENT_FL_CONNECTOR;
1433
1434 ret = of_property_read_string(child, "label", &name);
1435 if (ret < 0) {
257e29f8 1436 dev_err(decoder->sd.dev,
f7b4b54e
JMC		 1437 "missing label property in node %s\n",
1438 child->name);
1439 goto err_connector;
1440 }
1441
1442 input->name = name;
1443 }
1444
1445err_connector:
1446 of_node_put(connectors);
1447#endif
a2e5f1b3
JMC		 1448err:
1449 of_node_put(ep);
1450 return ret;
1451}
1452
c43875f6
MCC		 1453static const char * const tvp5150_test_patterns[2] = {
1454 "Disabled",
1455 "Black screen"
1456};
1457
6b8fe025
HV		 1458static int tvp5150_probe(struct i2c_client *c,
1459 const struct i2c_device_id *id)
cd4665c5 1460{
cd4665c5 1461 struct tvp5150 *core;
6b8fe025 1462 struct v4l2_subdev *sd;
a2e5f1b3 1463 struct device_node *np = c->dev.of_node;
7871597a 1464 int res;
cd4665c5
MCC		 1465
1466 /* Check if the adapter supports the needed features */
6b8fe025 1467 if (!i2c_check_functionality(c->adapter,
cd4665c5 1468 I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
6b8fe025 1469 return -EIO;
cd4665c5 1470
09aa2609
JMC		 1471 res = tvp5150_init(c);
1472 if (res)
1473 return res;
1474
c02b211d
LP		 1475 core = devm_kzalloc(&c->dev, sizeof(*core), GFP_KERNEL);
1476 if (!core)
cd4665c5 1477 return -ENOMEM;
a2e5f1b3 1478
6b8fe025 1479 sd = &core->sd;
a2e5f1b3
JMC		 1480
1481 if (IS_ENABLED(CONFIG_OF) && np) {
1482 res = tvp5150_parse_dt(core, np);
1483 if (res) {
257e29f8 1484 dev_err(sd->dev, "DT parsing error: %d\n", res);
a2e5f1b3
JMC		 1485 return res;
1486 }
1487 } else {
1488 /* Default to BT.656 embedded sync */
1489 core->mbus_type = V4L2_MBUS_BT656;
1490 }
1491
6b8fe025 1492 v4l2_i2c_subdev_init(sd, c, &tvp5150_ops);
5a08bc00 1493 sd->internal_ops = &tvp5150_internal_ops;
e545ac87
LP		 1494 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1495
1496#if defined(CONFIG_MEDIA_CONTROLLER)
55606310
MCC		 1497 core->pads[DEMOD_PAD_IF_INPUT].flags = MEDIA_PAD_FL_SINK;
1498 core->pads[DEMOD_PAD_VID_OUT].flags = MEDIA_PAD_FL_SOURCE;
1499 core->pads[DEMOD_PAD_VBI_OUT].flags = MEDIA_PAD_FL_SOURCE;
f92c70ad
MCC		 1500
1501 sd->entity.function = MEDIA_ENT_F_ATV_DECODER;
1502
55606310 1503 res = media_entity_pads_init(&sd->entity, DEMOD_NUM_PADS, core->pads);
e545ac87
LP		 1504 if (res < 0)
1505 return res;
f7b4b54e
JMC		 1506
1507 sd->entity.ops = &tvp5150_sd_media_ops;
e545ac87 1508#endif
8cd0d4ca 1509
7871597a
LP		 1510 res = tvp5150_detect_version(core);
1511 if (res < 0)
1512 return res;
0e09a3c9 1513
3ad96835 1514 core->norm = V4L2_STD_ALL; /* Default is autodetect */
5325b427 1515 core->input = TVP5150_COMPOSITE1;
c43875f6 1516 core->enable = true;
6c45ec71 1517
b1950b8d 1518 v4l2_ctrl_handler_init(&core->hdl, 5);
6c45ec71
HV		 1519 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1520 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1521 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1522 V4L2_CID_CONTRAST, 0, 255, 1, 128);
1523 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1524 V4L2_CID_SATURATION, 0, 255, 1, 128);
1525 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1526 V4L2_CID_HUE, -128, 127, 1, 0);
b1950b8d
LP		 1527 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1528 V4L2_CID_PIXEL_RATE, 27000000,
1529 27000000, 1, 27000000);
c43875f6
MCC		 1530 v4l2_ctrl_new_std_menu_items(&core->hdl, &tvp5150_ctrl_ops,
1531 V4L2_CID_TEST_PATTERN,
1532 ARRAY_SIZE(tvp5150_test_patterns),
1533 0, 0, tvp5150_test_patterns);
6c45ec71
HV		 1534 sd->ctrl_handler = &core->hdl;
1535 if (core->hdl.error) {
8cd0d4ca 1536 res = core->hdl.error;
c7d97499 1537 goto err;
6c45ec71 1538 }
4c86f973 1539
963ddc63
JM		 1540 /* Default is no cropping */
1541 core->rect.top = 0;
1542 if (tvp5150_read_std(sd) & V4L2_STD_525_60)
1543 core->rect.height = TVP5150_V_MAX_525_60;
1544 else
1545 core->rect.height = TVP5150_V_MAX_OTHERS;
1546 core->rect.left = 0;
1547 core->rect.width = TVP5150_H_MAX;
1548
aff808e8
LP		 1549 tvp5150_reset(sd, 0); /* Calls v4l2_ctrl_handler_setup() */
1550
c7d97499
JMC		 1551 res = v4l2_async_register_subdev(sd);
1552 if (res < 0)
1553 goto err;
1554
f1e5ee45 1555 if (debug > 1)
6b8fe025 1556 tvp5150_log_status(sd);
cd4665c5 1557 return 0;
c7d97499
JMC		 1558
1559err:
1560 v4l2_ctrl_handler_free(&core->hdl);
1561 return res;
cd4665c5
MCC		 1562}
1563
6b8fe025 1564static int tvp5150_remove(struct i2c_client *c)
cd4665c5 1565{
6b8fe025 1566 struct v4l2_subdev *sd = i2c_get_clientdata(c);
6c45ec71 1567 struct tvp5150 *decoder = to_tvp5150(sd);
cd4665c5 1568
257e29f8 1569 dev_dbg_lvl(sd->dev, 1, debug,
e1bc80ad
MCC		 1570 "tvp5150.c: removing tvp5150 adapter on address 0x%x\n",
1571 c->addr << 1);
1572
c7d97499 1573 v4l2_async_unregister_subdev(sd);
6c45ec71 1574 v4l2_ctrl_handler_free(&decoder->hdl);
cd4665c5
MCC		 1575 return 0;
1576}
1577
1578/* ----------------------------------------------------------------------- */
1579
6b8fe025
HV		 1580static const struct i2c_device_id tvp5150_id[] = {
1581 { "tvp5150", 0 },
1582 { }
1583};
1584MODULE_DEVICE_TABLE(i2c, tvp5150_id);
84486d53 1585
7ef930a7
EG		 1586#if IS_ENABLED(CONFIG_OF)
1587static const struct of_device_id tvp5150_of_match[] = {
1588 { .compatible = "ti,tvp5150", },
1589 { /* sentinel */ },
1590};
1591MODULE_DEVICE_TABLE(of, tvp5150_of_match);
1592#endif
1593
c771145b
HV		 1594static struct i2c_driver tvp5150_driver = {
1595 .driver = {
7ef930a7 1596 .of_match_table = of_match_ptr(tvp5150_of_match),
c771145b
HV		 1597 .name = "tvp5150",
1598 },
1599 .probe = tvp5150_probe,
1600 .remove = tvp5150_remove,
1601 .id_table = tvp5150_id,
cd4665c5 1602};
c771145b 1603
c6e8d86f 1604module_i2c_driver(tvp5150_driver);
Linux 6.x block layer and io_uring tree(s)