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59d8bf5d | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
9ac0038d TH |
2 | /* |
3 | * Copyright (C) 2018 Gateworks Corporation | |
4 | */ | |
5 | ||
6 | /* Page 0x00 - General Control */ | |
7 | #define REG_VERSION 0x0000 | |
8 | #define REG_INPUT_SEL 0x0001 | |
9 | #define REG_SVC_MODE 0x0002 | |
10 | #define REG_HPD_MAN_CTRL 0x0003 | |
11 | #define REG_RT_MAN_CTRL 0x0004 | |
12 | #define REG_STANDBY_SOFT_RST 0x000A | |
13 | #define REG_HDMI_SOFT_RST 0x000B | |
14 | #define REG_HDMI_INFO_RST 0x000C | |
15 | #define REG_INT_FLG_CLR_TOP 0x000E | |
16 | #define REG_INT_FLG_CLR_SUS 0x000F | |
17 | #define REG_INT_FLG_CLR_DDC 0x0010 | |
18 | #define REG_INT_FLG_CLR_RATE 0x0011 | |
19 | #define REG_INT_FLG_CLR_MODE 0x0012 | |
20 | #define REG_INT_FLG_CLR_INFO 0x0013 | |
21 | #define REG_INT_FLG_CLR_AUDIO 0x0014 | |
22 | #define REG_INT_FLG_CLR_HDCP 0x0015 | |
23 | #define REG_INT_FLG_CLR_AFE 0x0016 | |
24 | #define REG_INT_MASK_TOP 0x0017 | |
25 | #define REG_INT_MASK_SUS 0x0018 | |
26 | #define REG_INT_MASK_DDC 0x0019 | |
27 | #define REG_INT_MASK_RATE 0x001A | |
28 | #define REG_INT_MASK_MODE 0x001B | |
29 | #define REG_INT_MASK_INFO 0x001C | |
30 | #define REG_INT_MASK_AUDIO 0x001D | |
31 | #define REG_INT_MASK_HDCP 0x001E | |
32 | #define REG_INT_MASK_AFE 0x001F | |
33 | #define REG_DETECT_5V 0x0020 | |
34 | #define REG_SUS_STATUS 0x0021 | |
35 | #define REG_V_PER 0x0022 | |
36 | #define REG_H_PER 0x0025 | |
37 | #define REG_HS_WIDTH 0x0027 | |
38 | #define REG_FMT_H_TOT 0x0029 | |
39 | #define REG_FMT_H_ACT 0x002b | |
40 | #define REG_FMT_H_FRONT 0x002d | |
41 | #define REG_FMT_H_SYNC 0x002f | |
42 | #define REG_FMT_H_BACK 0x0031 | |
43 | #define REG_FMT_V_TOT 0x0033 | |
44 | #define REG_FMT_V_ACT 0x0035 | |
45 | #define REG_FMT_V_FRONT_F1 0x0037 | |
46 | #define REG_FMT_V_FRONT_F2 0x0038 | |
47 | #define REG_FMT_V_SYNC 0x0039 | |
48 | #define REG_FMT_V_BACK_F1 0x003a | |
49 | #define REG_FMT_V_BACK_F2 0x003b | |
50 | #define REG_FMT_DE_ACT 0x003c | |
51 | #define REG_RATE_CTRL 0x0040 | |
52 | #define REG_CLK_MIN_RATE 0x0043 | |
53 | #define REG_CLK_MAX_RATE 0x0046 | |
54 | #define REG_CLK_A_STATUS 0x0049 | |
55 | #define REG_CLK_A_RATE 0x004A | |
56 | #define REG_DRIFT_CLK_A_REG 0x004D | |
57 | #define REG_CLK_B_STATUS 0x004E | |
58 | #define REG_CLK_B_RATE 0x004F | |
59 | #define REG_DRIFT_CLK_B_REG 0x0052 | |
60 | #define REG_HDCP_CTRL 0x0060 | |
61 | #define REG_HDCP_KDS 0x0061 | |
62 | #define REG_HDCP_BCAPS 0x0063 | |
63 | #define REG_HDCP_KEY_CTRL 0x0064 | |
64 | #define REG_INFO_CTRL 0x0076 | |
65 | #define REG_INFO_EXCEED 0x0077 | |
66 | #define REG_PIX_REPEAT 0x007B | |
67 | #define REG_AUDIO_PATH 0x007C | |
68 | #define REG_AUDCFG 0x007D | |
69 | #define REG_AUDIO_OUT_ENABLE 0x007E | |
70 | #define REG_AUDIO_OUT_HIZ 0x007F | |
71 | #define REG_VDP_CTRL 0x0080 | |
72 | #define REG_VDP_MATRIX 0x0081 | |
73 | #define REG_VHREF_CTRL 0x00A0 | |
74 | #define REG_PXCNT_PR 0x00A2 | |
75 | #define REG_PXCNT_NPIX 0x00A4 | |
76 | #define REG_LCNT_PR 0x00A6 | |
77 | #define REG_LCNT_NLIN 0x00A8 | |
78 | #define REG_HREF_S 0x00AA | |
79 | #define REG_HREF_E 0x00AC | |
80 | #define REG_HS_S 0x00AE | |
81 | #define REG_HS_E 0x00B0 | |
82 | #define REG_VREF_F1_S 0x00B2 | |
83 | #define REG_VREF_F1_WIDTH 0x00B4 | |
84 | #define REG_VREF_F2_S 0x00B5 | |
85 | #define REG_VREF_F2_WIDTH 0x00B7 | |
86 | #define REG_VS_F1_LINE_S 0x00B8 | |
87 | #define REG_VS_F1_LINE_WIDTH 0x00BA | |
88 | #define REG_VS_F2_LINE_S 0x00BB | |
89 | #define REG_VS_F2_LINE_WIDTH 0x00BD | |
90 | #define REG_VS_F1_PIX_S 0x00BE | |
91 | #define REG_VS_F1_PIX_E 0x00C0 | |
92 | #define REG_VS_F2_PIX_S 0x00C2 | |
93 | #define REG_VS_F2_PIX_E 0x00C4 | |
94 | #define REG_FREF_F1_S 0x00C6 | |
95 | #define REG_FREF_F2_S 0x00C8 | |
96 | #define REG_FDW_S 0x00ca | |
97 | #define REG_FDW_E 0x00cc | |
98 | #define REG_BLK_GY 0x00da | |
99 | #define REG_BLK_BU 0x00dc | |
100 | #define REG_BLK_RV 0x00de | |
101 | #define REG_FILTERS_CTRL 0x00e0 | |
102 | #define REG_DITHERING_CTRL 0x00E9 | |
103 | #define REG_OF 0x00EA | |
104 | #define REG_PCLK 0x00EB | |
105 | #define REG_HS_HREF 0x00EC | |
106 | #define REG_VS_VREF 0x00ED | |
107 | #define REG_DE_FREF 0x00EE | |
108 | #define REG_VP35_32_CTRL 0x00EF | |
109 | #define REG_VP31_28_CTRL 0x00F0 | |
110 | #define REG_VP27_24_CTRL 0x00F1 | |
111 | #define REG_VP23_20_CTRL 0x00F2 | |
112 | #define REG_VP19_16_CTRL 0x00F3 | |
113 | #define REG_VP15_12_CTRL 0x00F4 | |
114 | #define REG_VP11_08_CTRL 0x00F5 | |
115 | #define REG_VP07_04_CTRL 0x00F6 | |
116 | #define REG_VP03_00_CTRL 0x00F7 | |
117 | #define REG_CURPAGE_00H 0xFF | |
118 | ||
119 | #define MASK_VPER 0x3fffff | |
d64a7709 | 120 | #define MASK_VPER_SYNC_POS 0x800000 |
9ac0038d TH |
121 | #define MASK_VHREF 0x3fff |
122 | #define MASK_HPER 0x0fff | |
d64a7709 | 123 | #define MASK_HPER_SYNC_POS 0x8000 |
9ac0038d | 124 | #define MASK_HSWIDTH 0x03ff |
d64a7709 | 125 | #define MASK_HSWIDTH_INTERLACED 0x8000 |
9ac0038d TH |
126 | |
127 | /* HPD Detection */ | |
128 | #define DETECT_UTIL BIT(7) /* utility of HDMI level */ | |
129 | #define DETECT_HPD BIT(6) /* HPD of HDMI level */ | |
130 | #define DETECT_5V_SEL BIT(2) /* 5V present on selected input */ | |
131 | #define DETECT_5V_B BIT(1) /* 5V present on input B */ | |
132 | #define DETECT_5V_A BIT(0) /* 5V present on input A */ | |
133 | ||
134 | /* Input Select */ | |
135 | #define INPUT_SEL_RST_FMT BIT(7) /* 1=reset format measurement */ | |
136 | #define INPUT_SEL_RST_VDP BIT(2) /* 1=reset video data path */ | |
137 | #define INPUT_SEL_OUT_MODE BIT(1) /* 0=loop 1=bypass */ | |
138 | #define INPUT_SEL_B BIT(0) /* 0=inputA 1=inputB */ | |
139 | ||
140 | /* Service Mode */ | |
141 | #define SVC_MODE_CLK2_MASK 0xc0 | |
142 | #define SVC_MODE_CLK2_SHIFT 6 | |
143 | #define SVC_MODE_CLK2_XTL 0L | |
144 | #define SVC_MODE_CLK2_XTLDIV2 1L | |
145 | #define SVC_MODE_CLK2_HDMIX2 3L | |
146 | #define SVC_MODE_CLK1_MASK 0x30 | |
147 | #define SVC_MODE_CLK1_SHIFT 4 | |
148 | #define SVC_MODE_CLK1_XTAL 0L | |
149 | #define SVC_MODE_CLK1_XTLDIV2 1L | |
150 | #define SVC_MODE_CLK1_HDMI 3L | |
151 | #define SVC_MODE_RAMP BIT(3) /* 0=colorbar 1=ramp */ | |
152 | #define SVC_MODE_PAL BIT(2) /* 0=NTSC(480i/p) 1=PAL(576i/p) */ | |
153 | #define SVC_MODE_INT_PROG BIT(1) /* 0=interlaced 1=progressive */ | |
154 | #define SVC_MODE_SM_ON BIT(0) /* Enable color bars and tone gen */ | |
155 | ||
156 | /* HDP Manual Control */ | |
157 | #define HPD_MAN_CTRL_HPD_PULSE BIT(7) /* HPD Pulse low 110ms */ | |
158 | #define HPD_MAN_CTRL_5VEN BIT(2) /* Output 5V */ | |
159 | #define HPD_MAN_CTRL_HPD_B BIT(1) /* Assert HPD High for Input A */ | |
160 | #define HPD_MAN_CTRL_HPD_A BIT(0) /* Assert HPD High for Input A */ | |
161 | ||
162 | /* RT_MAN_CTRL */ | |
163 | #define RT_MAN_CTRL_RT_AUTO BIT(7) | |
164 | #define RT_MAN_CTRL_RT BIT(6) | |
165 | #define RT_MAN_CTRL_RT_B BIT(1) /* enable TMDS pull-up on Input B */ | |
166 | #define RT_MAN_CTRL_RT_A BIT(0) /* enable TMDS pull-up on Input A */ | |
167 | ||
168 | /* VDP_CTRL */ | |
169 | #define VDP_CTRL_COMPDEL_BP BIT(5) /* bypass compdel */ | |
170 | #define VDP_CTRL_FORMATTER_BP BIT(4) /* bypass formatter */ | |
171 | #define VDP_CTRL_PREFILTER_BP BIT(1) /* bypass prefilter */ | |
172 | #define VDP_CTRL_MATRIX_BP BIT(0) /* bypass matrix conversion */ | |
173 | ||
174 | /* REG_VHREF_CTRL */ | |
175 | #define VHREF_INT_DET BIT(7) /* interlace detect: 1=alt 0=frame */ | |
176 | #define VHREF_VSYNC_MASK 0x60 | |
177 | #define VHREF_VSYNC_SHIFT 6 | |
178 | #define VHREF_VSYNC_AUTO 0L | |
179 | #define VHREF_VSYNC_FDW 1L | |
180 | #define VHREF_VSYNC_EVEN 2L | |
181 | #define VHREF_VSYNC_ODD 3L | |
182 | #define VHREF_STD_DET_MASK 0x18 | |
183 | #define VHREF_STD_DET_SHIFT 3 | |
184 | #define VHREF_STD_DET_PAL 0L | |
185 | #define VHREF_STD_DET_NTSC 1L | |
186 | #define VHREF_STD_DET_AUTO 2L | |
187 | #define VHREF_STD_DET_OFF 3L | |
188 | #define VHREF_VREF_SRC_STD BIT(2) /* 1=from standard 0=manual */ | |
189 | #define VHREF_HREF_SRC_STD BIT(1) /* 1=from standard 0=manual */ | |
190 | #define VHREF_HSYNC_SEL_HS BIT(0) /* 1=HS 0=VS */ | |
191 | ||
192 | /* AUDIO_OUT_ENABLE */ | |
193 | #define AUDIO_OUT_ENABLE_ACLK BIT(5) | |
194 | #define AUDIO_OUT_ENABLE_WS BIT(4) | |
195 | #define AUDIO_OUT_ENABLE_AP3 BIT(3) | |
196 | #define AUDIO_OUT_ENABLE_AP2 BIT(2) | |
197 | #define AUDIO_OUT_ENABLE_AP1 BIT(1) | |
198 | #define AUDIO_OUT_ENABLE_AP0 BIT(0) | |
199 | ||
200 | /* Prefilter Control */ | |
201 | #define FILTERS_CTRL_BU_MASK 0x0c | |
202 | #define FILTERS_CTRL_BU_SHIFT 2 | |
203 | #define FILTERS_CTRL_RV_MASK 0x03 | |
204 | #define FILTERS_CTRL_RV_SHIFT 0 | |
205 | #define FILTERS_CTRL_OFF 0L /* off */ | |
206 | #define FILTERS_CTRL_2TAP 1L /* 2 Taps */ | |
207 | #define FILTERS_CTRL_7TAP 2L /* 7 Taps */ | |
208 | #define FILTERS_CTRL_2_7TAP 3L /* 2/7 Taps */ | |
209 | ||
210 | /* PCLK Configuration */ | |
211 | #define PCLK_DELAY_MASK 0x70 | |
212 | #define PCLK_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */ | |
213 | #define PCLK_INV_SHIFT 2 | |
214 | #define PCLK_SEL_MASK 0x03 /* clock scaler */ | |
215 | #define PCLK_SEL_SHIFT 0 | |
216 | #define PCLK_SEL_X1 0L | |
217 | #define PCLK_SEL_X2 1L | |
218 | #define PCLK_SEL_DIV2 2L | |
219 | #define PCLK_SEL_DIV4 3L | |
220 | ||
221 | /* Pixel Repeater */ | |
222 | #define PIX_REPEAT_MASK_UP_SEL 0x30 | |
223 | #define PIX_REPEAT_MASK_REP 0x0f | |
224 | #define PIX_REPEAT_SHIFT 4 | |
225 | #define PIX_REPEAT_CHROMA 1 | |
226 | ||
227 | /* Page 0x01 - HDMI info and packets */ | |
228 | #define REG_HDMI_FLAGS 0x0100 | |
229 | #define REG_DEEP_COLOR_MODE 0x0101 | |
230 | #define REG_AUDIO_FLAGS 0x0108 | |
231 | #define REG_AUDIO_FREQ 0x0109 | |
232 | #define REG_ACP_PACKET_TYPE 0x0141 | |
233 | #define REG_ISRC1_PACKET_TYPE 0x0161 | |
234 | #define REG_ISRC2_PACKET_TYPE 0x0181 | |
235 | #define REG_GBD_PACKET_TYPE 0x01a1 | |
236 | ||
237 | /* HDMI_FLAGS */ | |
238 | #define HDMI_FLAGS_AUDIO BIT(7) /* Audio packet in last videoframe */ | |
239 | #define HDMI_FLAGS_HDMI BIT(6) /* HDMI detected */ | |
240 | #define HDMI_FLAGS_EESS BIT(5) /* EESS detected */ | |
241 | #define HDMI_FLAGS_HDCP BIT(4) /* HDCP detected */ | |
242 | #define HDMI_FLAGS_AVMUTE BIT(3) /* AVMUTE */ | |
243 | #define HDMI_FLAGS_AUD_LAYOUT BIT(2) /* Layout status Audio sample packet */ | |
244 | #define HDMI_FLAGS_AUD_FIFO_OF BIT(1) /* FIFO read/write pointers crossed */ | |
245 | #define HDMI_FLAGS_AUD_FIFO_LOW BIT(0) /* FIFO read ptr within 2 of write */ | |
246 | ||
247 | /* Page 0x12 - HDMI Extra control and debug */ | |
248 | #define REG_CLK_CFG 0x1200 | |
249 | #define REG_CLK_OUT_CFG 0x1201 | |
250 | #define REG_CFG1 0x1202 | |
251 | #define REG_CFG2 0x1203 | |
252 | #define REG_WDL_CFG 0x1210 | |
253 | #define REG_DELOCK_DELAY 0x1212 | |
254 | #define REG_PON_OVR_EN 0x12A0 | |
255 | #define REG_PON_CBIAS 0x12A1 | |
256 | #define REG_PON_RESCAL 0x12A2 | |
257 | #define REG_PON_RES 0x12A3 | |
258 | #define REG_PON_CLK 0x12A4 | |
259 | #define REG_PON_PLL 0x12A5 | |
260 | #define REG_PON_EQ 0x12A6 | |
261 | #define REG_PON_DES 0x12A7 | |
262 | #define REG_PON_OUT 0x12A8 | |
263 | #define REG_PON_MUX 0x12A9 | |
264 | #define REG_MODE_REC_CFG1 0x12F8 | |
265 | #define REG_MODE_REC_CFG2 0x12F9 | |
266 | #define REG_MODE_REC_STS 0x12FA | |
267 | #define REG_AUDIO_LAYOUT 0x12D0 | |
268 | ||
269 | #define PON_EN 1 | |
270 | #define PON_DIS 0 | |
271 | ||
272 | /* CLK CFG */ | |
273 | #define CLK_CFG_INV_OUT_CLK BIT(7) | |
274 | #define CLK_CFG_INV_BUS_CLK BIT(6) | |
275 | #define CLK_CFG_SEL_ACLK_EN BIT(1) | |
276 | #define CLK_CFG_SEL_ACLK BIT(0) | |
277 | #define CLK_CFG_DIS 0 | |
278 | ||
279 | /* Page 0x13 - HDMI Extra control and debug */ | |
280 | #define REG_DEEP_COLOR_CTRL 0x1300 | |
281 | #define REG_CGU_DBG_SEL 0x1305 | |
282 | #define REG_HDCP_DDC_ADDR 0x1310 | |
283 | #define REG_HDCP_KIDX 0x1316 | |
284 | #define REG_DEEP_PLL7_BYP 0x1347 | |
285 | #define REG_HDCP_DE_CTRL 0x1370 | |
286 | #define REG_HDCP_EP_FILT_CTRL 0x1371 | |
287 | #define REG_HDMI_CTRL 0x1377 | |
288 | #define REG_HMTP_CTRL 0x137a | |
289 | #define REG_TIMER_D 0x13CF | |
290 | #define REG_SUS_SET_RGB0 0x13E1 | |
291 | #define REG_SUS_SET_RGB1 0x13E2 | |
292 | #define REG_SUS_SET_RGB2 0x13E3 | |
293 | #define REG_SUS_SET_RGB3 0x13E4 | |
294 | #define REG_SUS_SET_RGB4 0x13E5 | |
295 | #define REG_MAN_SUS_HDMI_SEL 0x13E8 | |
296 | #define REG_MAN_HDMI_SET 0x13E9 | |
297 | #define REG_SUS_CLOCK_GOOD 0x13EF | |
298 | ||
299 | /* HDCP DE Control */ | |
300 | #define HDCP_DE_MODE_MASK 0xc0 /* DE Measurement mode */ | |
301 | #define HDCP_DE_MODE_SHIFT 6 | |
302 | #define HDCP_DE_REGEN_EN BIT(5) /* enable regen mode */ | |
303 | #define HDCP_DE_FILTER_MASK 0x18 /* DE filter sensitivity */ | |
304 | #define HDCP_DE_FILTER_SHIFT 3 | |
305 | #define HDCP_DE_COMP_MASK 0x07 /* DE Composition mode */ | |
306 | #define HDCP_DE_COMP_MIXED 6L | |
307 | #define HDCP_DE_COMP_OR 5L | |
308 | #define HDCP_DE_COMP_AND 4L | |
309 | #define HDCP_DE_COMP_CH3 3L | |
310 | #define HDCP_DE_COMP_CH2 2L | |
311 | #define HDCP_DE_COMP_CH1 1L | |
312 | #define HDCP_DE_COMP_CH0 0L | |
313 | ||
314 | /* HDCP EP Filter Control */ | |
315 | #define HDCP_EP_FIL_CTL_MASK 0x30 | |
316 | #define HDCP_EP_FIL_CTL_SHIFT 4 | |
317 | #define HDCP_EP_FIL_VS_MASK 0x0c | |
318 | #define HDCP_EP_FIL_VS_SHIFT 2 | |
319 | #define HDCP_EP_FIL_HS_MASK 0x03 | |
320 | #define HDCP_EP_FIL_HS_SHIFT 0 | |
321 | ||
322 | /* HDMI_CTRL */ | |
323 | #define HDMI_CTRL_MUTE_MASK 0x0c | |
324 | #define HDMI_CTRL_MUTE_SHIFT 2 | |
325 | #define HDMI_CTRL_MUTE_AUTO 0L | |
326 | #define HDMI_CTRL_MUTE_OFF 1L | |
327 | #define HDMI_CTRL_MUTE_ON 2L | |
328 | #define HDMI_CTRL_HDCP_MASK 0x03 | |
329 | #define HDMI_CTRL_HDCP_SHIFT 0 | |
330 | #define HDMI_CTRL_HDCP_EESS 2L | |
331 | #define HDMI_CTRL_HDCP_OESS 1L | |
332 | #define HDMI_CTRL_HDCP_AUTO 0L | |
333 | ||
334 | /* CGU_DBG_SEL bits */ | |
335 | #define CGU_DBG_CLK_SEL_MASK 0x18 | |
336 | #define CGU_DBG_CLK_SEL_SHIFT 3 | |
337 | #define CGU_DBG_XO_FRO_SEL BIT(2) | |
338 | #define CGU_DBG_VDP_CLK_SEL BIT(1) | |
339 | #define CGU_DBG_PIX_CLK_SEL BIT(0) | |
340 | ||
341 | /* REG_MAN_SUS_HDMI_SEL / REG_MAN_HDMI_SET bits */ | |
342 | #define MAN_DIS_OUT_BUF BIT(7) | |
343 | #define MAN_DIS_ANA_PATH BIT(6) | |
344 | #define MAN_DIS_HDCP BIT(5) | |
345 | #define MAN_DIS_TMDS_ENC BIT(4) | |
346 | #define MAN_DIS_TMDS_FLOW BIT(3) | |
347 | #define MAN_RST_HDCP BIT(2) | |
348 | #define MAN_RST_TMDS_ENC BIT(1) | |
349 | #define MAN_RST_TMDS_FLOW BIT(0) | |
350 | ||
351 | /* Page 0x14 - Audio Extra control and debug */ | |
352 | #define REG_FIFO_LATENCY_VAL 0x1403 | |
353 | #define REG_AUDIO_CLOCK 0x1411 | |
354 | #define REG_TEST_NCTS_CTRL 0x1415 | |
355 | #define REG_TEST_AUDIO_FREQ 0x1426 | |
356 | #define REG_TEST_MODE 0x1437 | |
357 | ||
358 | /* Audio Clock Configuration */ | |
359 | #define AUDIO_CLOCK_PLL_PD BIT(7) /* powerdown PLL */ | |
360 | #define AUDIO_CLOCK_SEL_MASK 0x7f | |
361 | #define AUDIO_CLOCK_SEL_16FS 0L /* 16*fs */ | |
362 | #define AUDIO_CLOCK_SEL_32FS 1L /* 32*fs */ | |
363 | #define AUDIO_CLOCK_SEL_64FS 2L /* 64*fs */ | |
364 | #define AUDIO_CLOCK_SEL_128FS 3L /* 128*fs */ | |
365 | #define AUDIO_CLOCK_SEL_256FS 4L /* 256*fs */ | |
366 | #define AUDIO_CLOCK_SEL_512FS 5L /* 512*fs */ | |
367 | ||
368 | /* Page 0x20: EDID and Hotplug Detect */ | |
369 | #define REG_EDID_IN_BYTE0 0x2000 /* EDID base */ | |
370 | #define REG_EDID_IN_VERSION 0x2080 | |
371 | #define REG_EDID_ENABLE 0x2081 | |
372 | #define REG_HPD_POWER 0x2084 | |
373 | #define REG_HPD_AUTO_CTRL 0x2085 | |
374 | #define REG_HPD_DURATION 0x2086 | |
375 | #define REG_RX_HPD_HEAC 0x2087 | |
376 | ||
377 | /* EDID_ENABLE */ | |
378 | #define EDID_ENABLE_NACK_OFF BIT(7) | |
379 | #define EDID_ENABLE_EDID_ONLY BIT(6) | |
380 | #define EDID_ENABLE_B_EN BIT(1) | |
381 | #define EDID_ENABLE_A_EN BIT(0) | |
382 | ||
383 | /* HPD Power */ | |
384 | #define HPD_POWER_BP_MASK 0x0c | |
385 | #define HPD_POWER_BP_SHIFT 2 | |
386 | #define HPD_POWER_BP_LOW 0L | |
387 | #define HPD_POWER_BP_HIGH 1L | |
388 | #define HPD_POWER_EDID_ONLY BIT(1) | |
389 | ||
390 | /* HPD Auto control */ | |
391 | #define HPD_AUTO_READ_EDID BIT(7) | |
392 | #define HPD_AUTO_HPD_F3TECH BIT(5) | |
393 | #define HPD_AUTO_HP_OTHER BIT(4) | |
394 | #define HPD_AUTO_HPD_UNSEL BIT(3) | |
395 | #define HPD_AUTO_HPD_ALL_CH BIT(2) | |
396 | #define HPD_AUTO_HPD_PRV_CH BIT(1) | |
397 | #define HPD_AUTO_HPD_NEW_CH BIT(0) | |
398 | ||
399 | /* Page 0x21 - EDID content */ | |
400 | #define REG_EDID_IN_BYTE128 0x2100 /* CEA Extension block */ | |
401 | #define REG_EDID_IN_SPA_SUB 0x2180 | |
402 | #define REG_EDID_IN_SPA_AB_A 0x2181 | |
403 | #define REG_EDID_IN_SPA_CD_A 0x2182 | |
404 | #define REG_EDID_IN_CKSUM_A 0x2183 | |
405 | #define REG_EDID_IN_SPA_AB_B 0x2184 | |
406 | #define REG_EDID_IN_SPA_CD_B 0x2185 | |
407 | #define REG_EDID_IN_CKSUM_B 0x2186 | |
408 | ||
409 | /* Page 0x30 - NV Configuration */ | |
410 | #define REG_RT_AUTO_CTRL 0x3000 | |
411 | #define REG_EQ_MAN_CTRL0 0x3001 | |
412 | #define REG_EQ_MAN_CTRL1 0x3002 | |
413 | #define REG_OUTPUT_CFG 0x3003 | |
414 | #define REG_MUTE_CTRL 0x3004 | |
415 | #define REG_SLAVE_ADDR 0x3005 | |
416 | #define REG_CMTP_REG6 0x3006 | |
417 | #define REG_CMTP_REG7 0x3007 | |
418 | #define REG_CMTP_REG8 0x3008 | |
419 | #define REG_CMTP_REG9 0x3009 | |
420 | #define REG_CMTP_REGA 0x300A | |
421 | #define REG_CMTP_REGB 0x300B | |
422 | #define REG_CMTP_REGC 0x300C | |
423 | #define REG_CMTP_REGD 0x300D | |
424 | #define REG_CMTP_REGE 0x300E | |
425 | #define REG_CMTP_REGF 0x300F | |
426 | #define REG_CMTP_REG10 0x3010 | |
427 | #define REG_CMTP_REG11 0x3011 | |
428 | ||
429 | /* Page 0x80 - CEC */ | |
430 | #define REG_PWR_CONTROL 0x80F4 | |
431 | #define REG_OSC_DIVIDER 0x80F5 | |
432 | #define REG_EN_OSC_PERIOD_LSB 0x80F8 | |
433 | #define REG_CONTROL 0x80FF | |
434 | ||
435 | /* global interrupt flags (INT_FLG_CRL_TOP) */ | |
436 | #define INTERRUPT_AFE BIT(7) /* AFE module */ | |
437 | #define INTERRUPT_HDCP BIT(6) /* HDCP module */ | |
438 | #define INTERRUPT_AUDIO BIT(5) /* Audio module */ | |
439 | #define INTERRUPT_INFO BIT(4) /* Infoframe module */ | |
440 | #define INTERRUPT_MODE BIT(3) /* HDMI mode module */ | |
441 | #define INTERRUPT_RATE BIT(2) /* rate module */ | |
442 | #define INTERRUPT_DDC BIT(1) /* DDC module */ | |
443 | #define INTERRUPT_SUS BIT(0) /* SUS module */ | |
444 | ||
445 | /* INT_FLG_CLR_HDCP bits */ | |
446 | #define MASK_HDCP_MTP BIT(7) /* HDCP MTP busy */ | |
447 | #define MASK_HDCP_DLMTP BIT(4) /* HDCP end download MTP to SRAM */ | |
448 | #define MASK_HDCP_DLRAM BIT(3) /* HDCP end download keys from SRAM */ | |
449 | #define MASK_HDCP_ENC BIT(2) /* HDCP ENC */ | |
450 | #define MASK_STATE_C5 BIT(1) /* HDCP State C5 reached */ | |
451 | #define MASK_AKSV BIT(0) /* AKSV received (start of auth) */ | |
452 | ||
453 | /* INT_FLG_CLR_RATE bits */ | |
454 | #define MASK_RATE_B_DRIFT BIT(7) /* Rate measurement drifted */ | |
455 | #define MASK_RATE_B_ST BIT(6) /* Rate measurement stability change */ | |
456 | #define MASK_RATE_B_ACT BIT(5) /* Rate measurement activity change */ | |
457 | #define MASK_RATE_B_PST BIT(4) /* Rate measreument presence change */ | |
458 | #define MASK_RATE_A_DRIFT BIT(3) /* Rate measurement drifted */ | |
459 | #define MASK_RATE_A_ST BIT(2) /* Rate measurement stability change */ | |
460 | #define MASK_RATE_A_ACT BIT(1) /* Rate measurement presence change */ | |
461 | #define MASK_RATE_A_PST BIT(0) /* Rate measreument presence change */ | |
462 | ||
463 | /* INT_FLG_CLR_SUS (Start Up Sequencer) bits */ | |
464 | #define MASK_MPT BIT(7) /* Config MTP end of process */ | |
465 | #define MASK_FMT BIT(5) /* Video format changed */ | |
466 | #define MASK_RT_PULSE BIT(4) /* End of termination resistance pulse */ | |
467 | #define MASK_SUS_END BIT(3) /* SUS last state reached */ | |
468 | #define MASK_SUS_ACT BIT(2) /* Activity of selected input changed */ | |
469 | #define MASK_SUS_CH BIT(1) /* Selected input changed */ | |
470 | #define MASK_SUS_ST BIT(0) /* SUS state changed */ | |
471 | ||
472 | /* INT_FLG_CLR_DDC bits */ | |
473 | #define MASK_EDID_MTP BIT(7) /* EDID MTP end of process */ | |
474 | #define MASK_DDC_ERR BIT(6) /* master DDC error */ | |
475 | #define MASK_DDC_CMD_DONE BIT(5) /* master DDC cmd send correct */ | |
476 | #define MASK_READ_DONE BIT(4) /* End of down EDID read */ | |
477 | #define MASK_RX_DDC_SW BIT(3) /* Output DDC switching finished */ | |
478 | #define MASK_HDCP_DDC_SW BIT(2) /* HDCP DDC switching finished */ | |
479 | #define MASK_HDP_PULSE_END BIT(1) /* End of Hot Plug Detect pulse */ | |
480 | #define MASK_DET_5V BIT(0) /* Detection of +5V */ | |
481 | ||
482 | /* INT_FLG_CLR_MODE bits */ | |
483 | #define MASK_HDMI_FLG BIT(7) /* HDMI mode/avmute/encrypt/FIFO fail */ | |
484 | #define MASK_GAMUT BIT(6) /* Gamut packet */ | |
485 | #define MASK_ISRC2 BIT(5) /* ISRC2 packet */ | |
486 | #define MASK_ISRC1 BIT(4) /* ISRC1 packet */ | |
487 | #define MASK_ACP BIT(3) /* Audio Content Protection packet */ | |
488 | #define MASK_DC_NO_GCP BIT(2) /* GCP not received in 5 frames */ | |
489 | #define MASK_DC_PHASE BIT(1) /* deepcolor pixel phase needs update */ | |
490 | #define MASK_DC_MODE BIT(0) /* deepcolor color depth changed */ | |
491 | ||
492 | /* INT_FLG_CLR_INFO bits (Infoframe Change Status) */ | |
493 | #define MASK_MPS_IF BIT(6) /* MPEG Source Product */ | |
494 | #define MASK_AUD_IF BIT(5) /* Audio */ | |
495 | #define MASK_SPD_IF BIT(4) /* Source Product Descriptor */ | |
496 | #define MASK_AVI_IF BIT(3) /* Auxiliary Video IF */ | |
497 | #define MASK_VS_IF_OTHER_BK2 BIT(2) /* Vendor Specific (bank2) */ | |
498 | #define MASK_VS_IF_OTHER_BK1 BIT(1) /* Vendor Specific (bank1) */ | |
499 | #define MASK_VS_IF_HDMI BIT(0) /* Vendor Specific (w/ HDMI LLC code) */ | |
500 | ||
501 | /* INT_FLG_CLR_AUDIO bits */ | |
502 | #define MASK_AUDIO_FREQ_FLG BIT(5) /* Audio freq change */ | |
503 | #define MASK_AUDIO_FLG BIT(4) /* DST, OBA, HBR, ASP change */ | |
504 | #define MASK_MUTE_FLG BIT(3) /* Audio Mute */ | |
505 | #define MASK_CH_STATE BIT(2) /* Channel status */ | |
506 | #define MASK_UNMUTE_FIFO BIT(1) /* Audio Unmute */ | |
507 | #define MASK_ERROR_FIFO_PT BIT(0) /* Audio FIFO pointer error */ | |
508 | ||
509 | /* INT_FLG_CLR_AFE bits */ | |
510 | #define MASK_AFE_WDL_UNLOCKED BIT(7) /* Wordlocker was unlocked */ | |
511 | #define MASK_AFE_GAIN_DONE BIT(6) /* Gain calibration done */ | |
512 | #define MASK_AFE_OFFSET_DONE BIT(5) /* Offset calibration done */ | |
513 | #define MASK_AFE_ACTIVITY_DET BIT(4) /* Activity detected on data */ | |
514 | #define MASK_AFE_PLL_LOCK BIT(3) /* TMDS PLL is locked */ | |
515 | #define MASK_AFE_TRMCAL_DONE BIT(2) /* Termination calibration done */ | |
516 | #define MASK_AFE_ASU_STATE BIT(1) /* ASU state is reached */ | |
517 | #define MASK_AFE_ASU_READY BIT(0) /* AFE calibration done: TMDS ready */ | |
518 | ||
519 | /* Audio Output */ | |
520 | #define AUDCFG_CLK_INVERT BIT(7) /* invert A_CLK polarity */ | |
521 | #define AUDCFG_TEST_TONE BIT(6) /* enable test tone generator */ | |
522 | #define AUDCFG_BUS_SHIFT 5 | |
523 | #define AUDCFG_BUS_I2S 0L | |
524 | #define AUDCFG_BUS_SPDIF 1L | |
525 | #define AUDCFG_I2SW_SHIFT 4 | |
526 | #define AUDCFG_I2SW_16 0L | |
527 | #define AUDCFG_I2SW_32 1L | |
528 | #define AUDCFG_AUTO_MUTE_EN BIT(3) /* Enable Automatic audio mute */ | |
529 | #define AUDCFG_HBR_SHIFT 2 | |
530 | #define AUDCFG_HBR_STRAIGHT 0L /* straight via AP0 */ | |
531 | #define AUDCFG_HBR_DEMUX 1L /* demuxed via AP0:AP3 */ | |
532 | #define AUDCFG_TYPE_MASK 0x03 | |
533 | #define AUDCFG_TYPE_SHIFT 0 | |
534 | #define AUDCFG_TYPE_DST 3L /* Direct Stream Transfer (DST) */ | |
535 | #define AUDCFG_TYPE_OBA 2L /* One Bit Audio (OBA) */ | |
536 | #define AUDCFG_TYPE_HBR 1L /* High Bit Rate (HBR) */ | |
537 | #define AUDCFG_TYPE_PCM 0L /* Audio samples */ | |
538 | ||
539 | /* Video Formatter */ | |
540 | #define OF_VP_ENABLE BIT(7) /* VP[35:0]/HS/VS/DE/CLK */ | |
541 | #define OF_BLK BIT(4) /* blanking codes */ | |
542 | #define OF_TRC BIT(3) /* timing codes (SAV/EAV) */ | |
543 | #define OF_FMT_MASK 0x3 | |
544 | #define OF_FMT_444 0L /* RGB444/YUV444 */ | |
545 | #define OF_FMT_422_SMPT 1L /* YUV422 semi-planar */ | |
546 | #define OF_FMT_422_CCIR 2L /* YUV422 CCIR656 */ | |
547 | ||
548 | /* HS/HREF output control */ | |
549 | #define HS_HREF_DELAY_MASK 0xf0 | |
550 | #define HS_HREF_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */ | |
551 | #define HS_HREF_PXQ_SHIFT 3 /* Timing codes from HREF */ | |
552 | #define HS_HREF_INV_SHIFT 2 /* polarity (1=invert) */ | |
553 | #define HS_HREF_SEL_MASK 0x03 | |
554 | #define HS_HREF_SEL_SHIFT 0 | |
555 | #define HS_HREF_SEL_HS_VHREF 0L /* HS from VHREF */ | |
556 | #define HS_HREF_SEL_HREF_VHREF 1L /* HREF from VHREF */ | |
557 | #define HS_HREF_SEL_HREF_HDMI 2L /* HREF from HDMI */ | |
558 | #define HS_HREF_SEL_NONE 3L /* not generated */ | |
559 | ||
560 | /* VS output control */ | |
561 | #define VS_VREF_DELAY_MASK 0xf0 | |
562 | #define VS_VREF_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */ | |
563 | #define VS_VREF_INV_SHIFT 2 /* polarity (1=invert) */ | |
564 | #define VS_VREF_SEL_MASK 0x03 | |
565 | #define VS_VREF_SEL_SHIFT 0 | |
566 | #define VS_VREF_SEL_VS_VHREF 0L /* VS from VHREF */ | |
567 | #define VS_VREF_SEL_VREF_VHREF 1L /* VREF from VHREF */ | |
568 | #define VS_VREF_SEL_VREF_HDMI 2L /* VREF from HDMI */ | |
569 | #define VS_VREF_SEL_NONE 3L /* not generated */ | |
570 | ||
571 | /* DE/FREF output control */ | |
572 | #define DE_FREF_DELAY_MASK 0xf0 | |
573 | #define DE_FREF_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */ | |
574 | #define DE_FREF_DE_PXQ_SHIFT 3 /* Timing codes from DE */ | |
575 | #define DE_FREF_INV_SHIFT 2 /* polarity (1=invert) */ | |
576 | #define DE_FREF_SEL_MASK 0x03 | |
577 | #define DE_FREF_SEL_SHIFT 0 | |
578 | #define DE_FREF_SEL_DE_VHREF 0L /* DE from VHREF (HREF and not(VREF) */ | |
579 | #define DE_FREF_SEL_FREF_VHREF 1L /* FREF from VHREF */ | |
580 | #define DE_FREF_SEL_FREF_HDMI 2L /* FREF from HDMI */ | |
581 | #define DE_FREF_SEL_NONE 3L /* not generated */ | |
582 | ||
583 | /* HDMI_SOFT_RST bits */ | |
584 | #define RESET_DC BIT(7) /* Reset deep color module */ | |
585 | #define RESET_HDCP BIT(6) /* Reset HDCP module */ | |
586 | #define RESET_KSV BIT(5) /* Reset KSV-FIFO */ | |
587 | #define RESET_SCFG BIT(4) /* Reset HDCP and repeater function */ | |
588 | #define RESET_HCFG BIT(3) /* Reset HDCP DDC part */ | |
589 | #define RESET_PA BIT(2) /* Reset polarity adjust */ | |
590 | #define RESET_EP BIT(1) /* Reset Error protection */ | |
591 | #define RESET_TMDS BIT(0) /* Reset TMDS (calib, encoding, flow) */ | |
592 | ||
593 | /* HDMI_INFO_RST bits */ | |
594 | #define NACK_HDCP BIT(7) /* No ACK on HDCP request */ | |
595 | #define RESET_FIFO BIT(4) /* Reset Audio FIFO control */ | |
596 | #define RESET_GAMUT BIT(3) /* Clear Gamut packet */ | |
597 | #define RESET_AI BIT(2) /* Clear ACP and ISRC packets */ | |
598 | #define RESET_IF BIT(1) /* Clear all Audio infoframe packets */ | |
599 | #define RESET_AUDIO BIT(0) /* Reset Audio FIFO control */ | |
600 | ||
601 | /* HDCP_BCAPS bits */ | |
f8a7647d | 602 | #define HDCP_HDMI BIT(7) /* HDCP supports HDMI (vs DVI only) */ |
9ac0038d TH |
603 | #define HDCP_REPEATER BIT(6) /* HDCP supports repeater function */ |
604 | #define HDCP_READY BIT(5) /* set by repeater function */ | |
605 | #define HDCP_FAST BIT(4) /* Up to 400kHz */ | |
606 | #define HDCP_11 BIT(1) /* HDCP 1.1 supported */ | |
607 | #define HDCP_FAST_REAUTH BIT(0) /* fast reauthentication supported */ | |
608 | ||
609 | /* Audio output formatter */ | |
610 | #define AUDIO_LAYOUT_SP_FLAG BIT(2) /* sp flag used by FIFO */ | |
611 | #define AUDIO_LAYOUT_MANUAL BIT(1) /* manual layout (vs per pkt) */ | |
612 | #define AUDIO_LAYOUT_LAYOUT1 BIT(0) /* Layout1: AP0-3 vs Layout0:AP0 */ | |
613 | ||
614 | /* masks for interrupt status registers */ | |
615 | #define MASK_SUS_STATUS 0x1F | |
616 | #define LAST_STATE_REACHED 0x1B | |
617 | #define MASK_CLK_STABLE 0x04 | |
618 | #define MASK_CLK_ACTIVE 0x02 | |
619 | #define MASK_SUS_STATE 0x10 | |
620 | #define MASK_SR_FIFO_FIFO_CTRL 0x30 | |
621 | #define MASK_AUDIO_FLAG 0x10 | |
622 | ||
623 | /* Rate measurement */ | |
624 | #define RATE_REFTIM_ENABLE 0x01 | |
625 | #define CLK_MIN_RATE 0x0057e4 | |
626 | #define CLK_MAX_RATE 0x0395f8 | |
627 | #define WDL_CFG_VAL 0x82 | |
628 | #define DC_FILTER_VAL 0x31 | |
629 | ||
630 | /* Infoframe */ | |
631 | #define VS_HDMI_IF_UPDATE 0x0200 | |
632 | #define VS_HDMI_IF 0x0201 | |
633 | #define VS_BK1_IF_UPDATE 0x0220 | |
634 | #define VS_BK1_IF 0x0221 | |
635 | #define VS_BK2_IF_UPDATE 0x0240 | |
636 | #define VS_BK2_IF 0x0241 | |
637 | #define AVI_IF_UPDATE 0x0260 | |
638 | #define AVI_IF 0x0261 | |
639 | #define SPD_IF_UPDATE 0x0280 | |
640 | #define SPD_IF 0x0281 | |
641 | #define AUD_IF_UPDATE 0x02a0 | |
642 | #define AUD_IF 0x02a1 | |
643 | #define MPS_IF_UPDATE 0x02c0 | |
644 | #define MPS_IF 0x02c1 |