Commit | Line | Data |
---|---|---|
77110abb | 1 | /* |
c8cf078e | 2 | * Driver for MT9M111/MT9M112/MT9M131 CMOS Image Sensor from Micron/Aptina |
77110abb RJ |
3 | * |
4 | * Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #include <linux/videodev2.h> | |
11 | #include <linux/slab.h> | |
12 | #include <linux/i2c.h> | |
13 | #include <linux/log2.h> | |
14 | #include <linux/gpio.h> | |
15 | #include <linux/delay.h> | |
95d20109 | 16 | #include <linux/v4l2-mediabus.h> |
7a707b89 | 17 | #include <linux/module.h> |
77110abb | 18 | |
0c0b446d | 19 | #include <media/soc_camera.h> |
9aea470b | 20 | #include <media/v4l2-clk.h> |
77110abb | 21 | #include <media/v4l2-common.h> |
af8425c5 | 22 | #include <media/v4l2-ctrls.h> |
77110abb RJ |
23 | |
24 | /* | |
c8cf078e PW |
25 | * MT9M111, MT9M112 and MT9M131: |
26 | * i2c address is 0x48 or 0x5d (depending on SADDR pin) | |
25a34811 GL |
27 | * The platform has to define struct i2c_board_info objects and link to them |
28 | * from struct soc_camera_host_desc | |
77110abb RJ |
29 | */ |
30 | ||
c8cf078e PW |
31 | /* |
32 | * Sensor core register addresses (0x000..0x0ff) | |
33 | */ | |
77110abb RJ |
34 | #define MT9M111_CHIP_VERSION 0x000 |
35 | #define MT9M111_ROW_START 0x001 | |
36 | #define MT9M111_COLUMN_START 0x002 | |
37 | #define MT9M111_WINDOW_HEIGHT 0x003 | |
38 | #define MT9M111_WINDOW_WIDTH 0x004 | |
39 | #define MT9M111_HORIZONTAL_BLANKING_B 0x005 | |
40 | #define MT9M111_VERTICAL_BLANKING_B 0x006 | |
41 | #define MT9M111_HORIZONTAL_BLANKING_A 0x007 | |
42 | #define MT9M111_VERTICAL_BLANKING_A 0x008 | |
43 | #define MT9M111_SHUTTER_WIDTH 0x009 | |
44 | #define MT9M111_ROW_SPEED 0x00a | |
45 | #define MT9M111_EXTRA_DELAY 0x00b | |
46 | #define MT9M111_SHUTTER_DELAY 0x00c | |
47 | #define MT9M111_RESET 0x00d | |
48 | #define MT9M111_READ_MODE_B 0x020 | |
49 | #define MT9M111_READ_MODE_A 0x021 | |
50 | #define MT9M111_FLASH_CONTROL 0x023 | |
51 | #define MT9M111_GREEN1_GAIN 0x02b | |
52 | #define MT9M111_BLUE_GAIN 0x02c | |
53 | #define MT9M111_RED_GAIN 0x02d | |
54 | #define MT9M111_GREEN2_GAIN 0x02e | |
55 | #define MT9M111_GLOBAL_GAIN 0x02f | |
56 | #define MT9M111_CONTEXT_CONTROL 0x0c8 | |
57 | #define MT9M111_PAGE_MAP 0x0f0 | |
58 | #define MT9M111_BYTE_WISE_ADDR 0x0f1 | |
59 | ||
60 | #define MT9M111_RESET_SYNC_CHANGES (1 << 15) | |
61 | #define MT9M111_RESET_RESTART_BAD_FRAME (1 << 9) | |
62 | #define MT9M111_RESET_SHOW_BAD_FRAMES (1 << 8) | |
63 | #define MT9M111_RESET_RESET_SOC (1 << 5) | |
64 | #define MT9M111_RESET_OUTPUT_DISABLE (1 << 4) | |
65 | #define MT9M111_RESET_CHIP_ENABLE (1 << 3) | |
66 | #define MT9M111_RESET_ANALOG_STANDBY (1 << 2) | |
67 | #define MT9M111_RESET_RESTART_FRAME (1 << 1) | |
68 | #define MT9M111_RESET_RESET_MODE (1 << 0) | |
69 | ||
7c58e7d0 MG |
70 | #define MT9M111_RM_FULL_POWER_RD (0 << 10) |
71 | #define MT9M111_RM_LOW_POWER_RD (1 << 10) | |
72 | #define MT9M111_RM_COL_SKIP_4X (1 << 5) | |
73 | #define MT9M111_RM_ROW_SKIP_4X (1 << 4) | |
74 | #define MT9M111_RM_COL_SKIP_2X (1 << 3) | |
75 | #define MT9M111_RM_ROW_SKIP_2X (1 << 2) | |
77110abb RJ |
76 | #define MT9M111_RMB_MIRROR_COLS (1 << 1) |
77 | #define MT9M111_RMB_MIRROR_ROWS (1 << 0) | |
78 | #define MT9M111_CTXT_CTRL_RESTART (1 << 15) | |
79 | #define MT9M111_CTXT_CTRL_DEFECTCOR_B (1 << 12) | |
80 | #define MT9M111_CTXT_CTRL_RESIZE_B (1 << 10) | |
81 | #define MT9M111_CTXT_CTRL_CTRL2_B (1 << 9) | |
82 | #define MT9M111_CTXT_CTRL_GAMMA_B (1 << 8) | |
83 | #define MT9M111_CTXT_CTRL_XENON_EN (1 << 7) | |
84 | #define MT9M111_CTXT_CTRL_READ_MODE_B (1 << 3) | |
85 | #define MT9M111_CTXT_CTRL_LED_FLASH_EN (1 << 2) | |
86 | #define MT9M111_CTXT_CTRL_VBLANK_SEL_B (1 << 1) | |
87 | #define MT9M111_CTXT_CTRL_HBLANK_SEL_B (1 << 0) | |
c8cf078e | 88 | |
77110abb | 89 | /* |
c8cf078e | 90 | * Colorpipe register addresses (0x100..0x1ff) |
77110abb RJ |
91 | */ |
92 | #define MT9M111_OPER_MODE_CTRL 0x106 | |
93 | #define MT9M111_OUTPUT_FORMAT_CTRL 0x108 | |
94 | #define MT9M111_REDUCER_XZOOM_B 0x1a0 | |
95 | #define MT9M111_REDUCER_XSIZE_B 0x1a1 | |
96 | #define MT9M111_REDUCER_YZOOM_B 0x1a3 | |
97 | #define MT9M111_REDUCER_YSIZE_B 0x1a4 | |
98 | #define MT9M111_REDUCER_XZOOM_A 0x1a6 | |
99 | #define MT9M111_REDUCER_XSIZE_A 0x1a7 | |
100 | #define MT9M111_REDUCER_YZOOM_A 0x1a9 | |
101 | #define MT9M111_REDUCER_YSIZE_A 0x1aa | |
102 | ||
103 | #define MT9M111_OUTPUT_FORMAT_CTRL2_A 0x13a | |
104 | #define MT9M111_OUTPUT_FORMAT_CTRL2_B 0x19b | |
105 | ||
106 | #define MT9M111_OPMODE_AUTOEXPO_EN (1 << 14) | |
39bf372f | 107 | #define MT9M111_OPMODE_AUTOWHITEBAL_EN (1 << 1) |
7c58e7d0 MG |
108 | #define MT9M111_OUTFMT_FLIP_BAYER_COL (1 << 9) |
109 | #define MT9M111_OUTFMT_FLIP_BAYER_ROW (1 << 8) | |
77110abb RJ |
110 | #define MT9M111_OUTFMT_PROCESSED_BAYER (1 << 14) |
111 | #define MT9M111_OUTFMT_BYPASS_IFP (1 << 10) | |
112 | #define MT9M111_OUTFMT_INV_PIX_CLOCK (1 << 9) | |
113 | #define MT9M111_OUTFMT_RGB (1 << 8) | |
ec73365b MG |
114 | #define MT9M111_OUTFMT_RGB565 (0 << 6) |
115 | #define MT9M111_OUTFMT_RGB555 (1 << 6) | |
116 | #define MT9M111_OUTFMT_RGB444x (2 << 6) | |
117 | #define MT9M111_OUTFMT_RGBx444 (3 << 6) | |
118 | #define MT9M111_OUTFMT_TST_RAMP_OFF (0 << 4) | |
119 | #define MT9M111_OUTFMT_TST_RAMP_COL (1 << 4) | |
120 | #define MT9M111_OUTFMT_TST_RAMP_ROW (2 << 4) | |
121 | #define MT9M111_OUTFMT_TST_RAMP_FRAME (3 << 4) | |
77110abb RJ |
122 | #define MT9M111_OUTFMT_SHIFT_3_UP (1 << 3) |
123 | #define MT9M111_OUTFMT_AVG_CHROMA (1 << 2) | |
7c58e7d0 MG |
124 | #define MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN (1 << 1) |
125 | #define MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B (1 << 0) | |
c8cf078e | 126 | |
77110abb | 127 | /* |
c8cf078e | 128 | * Camera control register addresses (0x200..0x2ff not implemented) |
77110abb RJ |
129 | */ |
130 | ||
9538e1c2 GL |
131 | #define reg_read(reg) mt9m111_reg_read(client, MT9M111_##reg) |
132 | #define reg_write(reg, val) mt9m111_reg_write(client, MT9M111_##reg, (val)) | |
133 | #define reg_set(reg, val) mt9m111_reg_set(client, MT9M111_##reg, (val)) | |
134 | #define reg_clear(reg, val) mt9m111_reg_clear(client, MT9M111_##reg, (val)) | |
7c58e7d0 MG |
135 | #define reg_mask(reg, val, mask) mt9m111_reg_mask(client, MT9M111_##reg, \ |
136 | (val), (mask)) | |
77110abb RJ |
137 | |
138 | #define MT9M111_MIN_DARK_ROWS 8 | |
669470a8 | 139 | #define MT9M111_MIN_DARK_COLS 26 |
77110abb RJ |
140 | #define MT9M111_MAX_HEIGHT 1024 |
141 | #define MT9M111_MAX_WIDTH 1280 | |
142 | ||
47921932 GL |
143 | struct mt9m111_context { |
144 | u16 read_mode; | |
145 | u16 blanking_h; | |
146 | u16 blanking_v; | |
147 | u16 reducer_xzoom; | |
148 | u16 reducer_yzoom; | |
149 | u16 reducer_xsize; | |
150 | u16 reducer_ysize; | |
151 | u16 output_fmt_ctrl2; | |
152 | u16 control; | |
153 | }; | |
154 | ||
155 | static struct mt9m111_context context_a = { | |
156 | .read_mode = MT9M111_READ_MODE_A, | |
157 | .blanking_h = MT9M111_HORIZONTAL_BLANKING_A, | |
158 | .blanking_v = MT9M111_VERTICAL_BLANKING_A, | |
159 | .reducer_xzoom = MT9M111_REDUCER_XZOOM_A, | |
160 | .reducer_yzoom = MT9M111_REDUCER_YZOOM_A, | |
161 | .reducer_xsize = MT9M111_REDUCER_XSIZE_A, | |
162 | .reducer_ysize = MT9M111_REDUCER_YSIZE_A, | |
163 | .output_fmt_ctrl2 = MT9M111_OUTPUT_FORMAT_CTRL2_A, | |
164 | .control = MT9M111_CTXT_CTRL_RESTART, | |
165 | }; | |
166 | ||
167 | static struct mt9m111_context context_b = { | |
168 | .read_mode = MT9M111_READ_MODE_B, | |
169 | .blanking_h = MT9M111_HORIZONTAL_BLANKING_B, | |
170 | .blanking_v = MT9M111_VERTICAL_BLANKING_B, | |
171 | .reducer_xzoom = MT9M111_REDUCER_XZOOM_B, | |
172 | .reducer_yzoom = MT9M111_REDUCER_YZOOM_B, | |
173 | .reducer_xsize = MT9M111_REDUCER_XSIZE_B, | |
174 | .reducer_ysize = MT9M111_REDUCER_YSIZE_B, | |
175 | .output_fmt_ctrl2 = MT9M111_OUTPUT_FORMAT_CTRL2_B, | |
176 | .control = MT9M111_CTXT_CTRL_RESTART | | |
177 | MT9M111_CTXT_CTRL_DEFECTCOR_B | MT9M111_CTXT_CTRL_RESIZE_B | | |
178 | MT9M111_CTXT_CTRL_CTRL2_B | MT9M111_CTXT_CTRL_GAMMA_B | | |
179 | MT9M111_CTXT_CTRL_READ_MODE_B | MT9M111_CTXT_CTRL_VBLANK_SEL_B | | |
180 | MT9M111_CTXT_CTRL_HBLANK_SEL_B, | |
181 | }; | |
182 | ||
760697be GL |
183 | /* MT9M111 has only one fixed colorspace per pixelcode */ |
184 | struct mt9m111_datafmt { | |
f5fe58fd | 185 | u32 code; |
760697be GL |
186 | enum v4l2_colorspace colorspace; |
187 | }; | |
188 | ||
760697be | 189 | static const struct mt9m111_datafmt mt9m111_colour_fmts[] = { |
f5fe58fd BB |
190 | {MEDIA_BUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_JPEG}, |
191 | {MEDIA_BUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_JPEG}, | |
192 | {MEDIA_BUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_JPEG}, | |
193 | {MEDIA_BUS_FMT_VYUY8_2X8, V4L2_COLORSPACE_JPEG}, | |
194 | {MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB}, | |
195 | {MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE, V4L2_COLORSPACE_SRGB}, | |
196 | {MEDIA_BUS_FMT_RGB565_2X8_LE, V4L2_COLORSPACE_SRGB}, | |
197 | {MEDIA_BUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_SRGB}, | |
198 | {MEDIA_BUS_FMT_BGR565_2X8_LE, V4L2_COLORSPACE_SRGB}, | |
199 | {MEDIA_BUS_FMT_BGR565_2X8_BE, V4L2_COLORSPACE_SRGB}, | |
200 | {MEDIA_BUS_FMT_SBGGR8_1X8, V4L2_COLORSPACE_SRGB}, | |
201 | {MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB}, | |
77110abb RJ |
202 | }; |
203 | ||
77110abb | 204 | struct mt9m111 { |
979ea1dd | 205 | struct v4l2_subdev subdev; |
af8425c5 HV |
206 | struct v4l2_ctrl_handler hdl; |
207 | struct v4l2_ctrl *gain; | |
47921932 | 208 | struct mt9m111_context *ctx; |
da673e60 | 209 | struct v4l2_rect rect; /* cropping rectangle */ |
9aea470b | 210 | struct v4l2_clk *clk; |
f90580ca RR |
211 | unsigned int width; /* output */ |
212 | unsigned int height; /* sizes */ | |
14c5ea9b GL |
213 | struct mutex power_lock; /* lock to protect power_count */ |
214 | int power_count; | |
760697be | 215 | const struct mt9m111_datafmt *fmt; |
096b703f | 216 | int lastpage; /* PageMap cache value */ |
77110abb RJ |
217 | }; |
218 | ||
da673e60 GL |
219 | /* Find a data format by a pixel code */ |
220 | static const struct mt9m111_datafmt *mt9m111_find_datafmt(struct mt9m111 *mt9m111, | |
f5fe58fd | 221 | u32 code) |
da673e60 GL |
222 | { |
223 | int i; | |
224 | for (i = 0; i < ARRAY_SIZE(mt9m111_colour_fmts); i++) | |
225 | if (mt9m111_colour_fmts[i].code == code) | |
226 | return mt9m111_colour_fmts + i; | |
227 | ||
228 | return mt9m111->fmt; | |
229 | } | |
230 | ||
979ea1dd GL |
231 | static struct mt9m111 *to_mt9m111(const struct i2c_client *client) |
232 | { | |
233 | return container_of(i2c_get_clientdata(client), struct mt9m111, subdev); | |
234 | } | |
235 | ||
77110abb RJ |
236 | static int reg_page_map_set(struct i2c_client *client, const u16 reg) |
237 | { | |
238 | int ret; | |
239 | u16 page; | |
096b703f | 240 | struct mt9m111 *mt9m111 = to_mt9m111(client); |
77110abb RJ |
241 | |
242 | page = (reg >> 8); | |
096b703f | 243 | if (page == mt9m111->lastpage) |
77110abb RJ |
244 | return 0; |
245 | if (page > 2) | |
246 | return -EINVAL; | |
247 | ||
3f877045 | 248 | ret = i2c_smbus_write_word_swapped(client, MT9M111_PAGE_MAP, page); |
506c629a | 249 | if (!ret) |
096b703f | 250 | mt9m111->lastpage = page; |
77110abb RJ |
251 | return ret; |
252 | } | |
253 | ||
9538e1c2 | 254 | static int mt9m111_reg_read(struct i2c_client *client, const u16 reg) |
77110abb | 255 | { |
77110abb RJ |
256 | int ret; |
257 | ||
258 | ret = reg_page_map_set(client, reg); | |
259 | if (!ret) | |
3f877045 | 260 | ret = i2c_smbus_read_word_swapped(client, reg & 0xff); |
77110abb | 261 | |
9538e1c2 | 262 | dev_dbg(&client->dev, "read reg.%03x -> %04x\n", reg, ret); |
77110abb RJ |
263 | return ret; |
264 | } | |
265 | ||
9538e1c2 | 266 | static int mt9m111_reg_write(struct i2c_client *client, const u16 reg, |
77110abb RJ |
267 | const u16 data) |
268 | { | |
77110abb RJ |
269 | int ret; |
270 | ||
271 | ret = reg_page_map_set(client, reg); | |
506c629a | 272 | if (!ret) |
3f877045 | 273 | ret = i2c_smbus_write_word_swapped(client, reg & 0xff, data); |
9538e1c2 | 274 | dev_dbg(&client->dev, "write reg.%03x = %04x -> %d\n", reg, data, ret); |
77110abb RJ |
275 | return ret; |
276 | } | |
277 | ||
9538e1c2 | 278 | static int mt9m111_reg_set(struct i2c_client *client, const u16 reg, |
77110abb RJ |
279 | const u16 data) |
280 | { | |
281 | int ret; | |
282 | ||
9538e1c2 | 283 | ret = mt9m111_reg_read(client, reg); |
77110abb | 284 | if (ret >= 0) |
9538e1c2 | 285 | ret = mt9m111_reg_write(client, reg, ret | data); |
77110abb RJ |
286 | return ret; |
287 | } | |
288 | ||
9538e1c2 | 289 | static int mt9m111_reg_clear(struct i2c_client *client, const u16 reg, |
77110abb RJ |
290 | const u16 data) |
291 | { | |
292 | int ret; | |
293 | ||
9538e1c2 | 294 | ret = mt9m111_reg_read(client, reg); |
9c56cbf9 MG |
295 | if (ret >= 0) |
296 | ret = mt9m111_reg_write(client, reg, ret & ~data); | |
297 | return ret; | |
77110abb RJ |
298 | } |
299 | ||
7c58e7d0 MG |
300 | static int mt9m111_reg_mask(struct i2c_client *client, const u16 reg, |
301 | const u16 data, const u16 mask) | |
302 | { | |
303 | int ret; | |
304 | ||
305 | ret = mt9m111_reg_read(client, reg); | |
306 | if (ret >= 0) | |
307 | ret = mt9m111_reg_write(client, reg, (ret & ~mask) | data); | |
308 | return ret; | |
309 | } | |
310 | ||
2768cbbb | 311 | static int mt9m111_set_context(struct mt9m111 *mt9m111, |
47921932 | 312 | struct mt9m111_context *ctx) |
77110abb | 313 | { |
2768cbbb | 314 | struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); |
47921932 GL |
315 | return reg_write(CONTEXT_CONTROL, ctx->control); |
316 | } | |
317 | ||
318 | static int mt9m111_setup_rect_ctx(struct mt9m111 *mt9m111, | |
da673e60 GL |
319 | struct mt9m111_context *ctx, struct v4l2_rect *rect, |
320 | unsigned int width, unsigned int height) | |
47921932 GL |
321 | { |
322 | struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); | |
da673e60 | 323 | int ret = mt9m111_reg_write(client, ctx->reducer_xzoom, rect->width); |
47921932 | 324 | if (!ret) |
da673e60 | 325 | ret = mt9m111_reg_write(client, ctx->reducer_yzoom, rect->height); |
47921932 | 326 | if (!ret) |
da673e60 | 327 | ret = mt9m111_reg_write(client, ctx->reducer_xsize, width); |
47921932 | 328 | if (!ret) |
da673e60 | 329 | ret = mt9m111_reg_write(client, ctx->reducer_ysize, height); |
47921932 | 330 | return ret; |
77110abb RJ |
331 | } |
332 | ||
da673e60 | 333 | static int mt9m111_setup_geometry(struct mt9m111 *mt9m111, struct v4l2_rect *rect, |
f5fe58fd | 334 | int width, int height, u32 code) |
77110abb | 335 | { |
2768cbbb | 336 | struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); |
47921932 | 337 | int ret; |
77110abb | 338 | |
09e231b3 | 339 | ret = reg_write(COLUMN_START, rect->left); |
506c629a | 340 | if (!ret) |
09e231b3 | 341 | ret = reg_write(ROW_START, rect->top); |
77110abb | 342 | |
da673e60 GL |
343 | if (!ret) |
344 | ret = reg_write(WINDOW_WIDTH, rect->width); | |
345 | if (!ret) | |
346 | ret = reg_write(WINDOW_HEIGHT, rect->height); | |
347 | ||
f5fe58fd | 348 | if (code != MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE) { |
da673e60 | 349 | /* IFP in use, down-scaling possible */ |
506c629a | 350 | if (!ret) |
da673e60 GL |
351 | ret = mt9m111_setup_rect_ctx(mt9m111, &context_b, |
352 | rect, width, height); | |
506c629a | 353 | if (!ret) |
da673e60 GL |
354 | ret = mt9m111_setup_rect_ctx(mt9m111, &context_a, |
355 | rect, width, height); | |
77110abb RJ |
356 | } |
357 | ||
da673e60 GL |
358 | dev_dbg(&client->dev, "%s(%x): %ux%u@%u:%u -> %ux%u = %d\n", |
359 | __func__, code, rect->width, rect->height, rect->left, rect->top, | |
360 | width, height, ret); | |
361 | ||
77110abb RJ |
362 | return ret; |
363 | } | |
364 | ||
2768cbbb | 365 | static int mt9m111_enable(struct mt9m111 *mt9m111) |
77110abb | 366 | { |
2768cbbb | 367 | struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); |
a650bf1e | 368 | return reg_write(RESET, MT9M111_RESET_CHIP_ENABLE); |
77110abb RJ |
369 | } |
370 | ||
2768cbbb | 371 | static int mt9m111_reset(struct mt9m111 *mt9m111) |
77110abb | 372 | { |
2768cbbb | 373 | struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); |
77110abb RJ |
374 | int ret; |
375 | ||
376 | ret = reg_set(RESET, MT9M111_RESET_RESET_MODE); | |
506c629a | 377 | if (!ret) |
77110abb | 378 | ret = reg_set(RESET, MT9M111_RESET_RESET_SOC); |
506c629a | 379 | if (!ret) |
77110abb RJ |
380 | ret = reg_clear(RESET, MT9M111_RESET_RESET_MODE |
381 | | MT9M111_RESET_RESET_SOC); | |
afb13683 | 382 | |
77110abb RJ |
383 | return ret; |
384 | } | |
385 | ||
4f996594 | 386 | static int mt9m111_s_crop(struct v4l2_subdev *sd, const struct v4l2_crop *a) |
6a6c8786 | 387 | { |
da673e60 GL |
388 | struct v4l2_rect rect = a->c; |
389 | struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); | |
390 | int width, height; | |
391 | int ret; | |
392 | ||
393 | if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
394 | return -EINVAL; | |
395 | ||
f5fe58fd BB |
396 | if (mt9m111->fmt->code == MEDIA_BUS_FMT_SBGGR8_1X8 || |
397 | mt9m111->fmt->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE) { | |
6a6c8786 | 398 | /* Bayer format - even size lengths */ |
da673e60 GL |
399 | rect.width = ALIGN(rect.width, 2); |
400 | rect.height = ALIGN(rect.height, 2); | |
6a6c8786 GL |
401 | /* Let the user play with the starting pixel */ |
402 | } | |
403 | ||
404 | /* FIXME: the datasheet doesn't specify minimum sizes */ | |
da673e60 | 405 | soc_camera_limit_side(&rect.left, &rect.width, |
6a6c8786 GL |
406 | MT9M111_MIN_DARK_COLS, 2, MT9M111_MAX_WIDTH); |
407 | ||
da673e60 | 408 | soc_camera_limit_side(&rect.top, &rect.height, |
6a6c8786 GL |
409 | MT9M111_MIN_DARK_ROWS, 2, MT9M111_MAX_HEIGHT); |
410 | ||
da673e60 GL |
411 | width = min(mt9m111->width, rect.width); |
412 | height = min(mt9m111->height, rect.height); | |
09e231b3 | 413 | |
da673e60 GL |
414 | ret = mt9m111_setup_geometry(mt9m111, &rect, width, height, mt9m111->fmt->code); |
415 | if (!ret) { | |
6a6c8786 | 416 | mt9m111->rect = rect; |
da673e60 GL |
417 | mt9m111->width = width; |
418 | mt9m111->height = height; | |
419 | } | |
420 | ||
09e231b3 GL |
421 | return ret; |
422 | } | |
423 | ||
6a6c8786 GL |
424 | static int mt9m111_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) |
425 | { | |
2768cbbb | 426 | struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); |
6a6c8786 GL |
427 | |
428 | a->c = mt9m111->rect; | |
429 | a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; | |
430 | ||
431 | return 0; | |
432 | } | |
433 | ||
434 | static int mt9m111_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a) | |
435 | { | |
6b6d33c7 MG |
436 | if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) |
437 | return -EINVAL; | |
438 | ||
6a6c8786 GL |
439 | a->bounds.left = MT9M111_MIN_DARK_COLS; |
440 | a->bounds.top = MT9M111_MIN_DARK_ROWS; | |
441 | a->bounds.width = MT9M111_MAX_WIDTH; | |
442 | a->bounds.height = MT9M111_MAX_HEIGHT; | |
443 | a->defrect = a->bounds; | |
6a6c8786 GL |
444 | a->pixelaspect.numerator = 1; |
445 | a->pixelaspect.denominator = 1; | |
446 | ||
447 | return 0; | |
448 | } | |
449 | ||
da298c6d HV |
450 | static int mt9m111_get_fmt(struct v4l2_subdev *sd, |
451 | struct v4l2_subdev_pad_config *cfg, | |
452 | struct v4l2_subdev_format *format) | |
6a6c8786 | 453 | { |
da298c6d | 454 | struct v4l2_mbus_framefmt *mf = &format->format; |
2768cbbb | 455 | struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); |
6a6c8786 | 456 | |
da298c6d HV |
457 | if (format->pad) |
458 | return -EINVAL; | |
459 | ||
da673e60 GL |
460 | mf->width = mt9m111->width; |
461 | mf->height = mt9m111->height; | |
760697be | 462 | mf->code = mt9m111->fmt->code; |
01f5a394 | 463 | mf->colorspace = mt9m111->fmt->colorspace; |
760697be | 464 | mf->field = V4L2_FIELD_NONE; |
6a6c8786 GL |
465 | |
466 | return 0; | |
467 | } | |
468 | ||
2768cbbb | 469 | static int mt9m111_set_pixfmt(struct mt9m111 *mt9m111, |
f5fe58fd | 470 | u32 code) |
77110abb | 471 | { |
7c58e7d0 MG |
472 | struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); |
473 | u16 data_outfmt2, mask_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER | | |
474 | MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB | | |
475 | MT9M111_OUTFMT_RGB565 | MT9M111_OUTFMT_RGB555 | | |
476 | MT9M111_OUTFMT_RGB444x | MT9M111_OUTFMT_RGBx444 | | |
477 | MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN | | |
478 | MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B; | |
506c629a | 479 | int ret; |
77110abb | 480 | |
760697be | 481 | switch (code) { |
f5fe58fd | 482 | case MEDIA_BUS_FMT_SBGGR8_1X8: |
7c58e7d0 MG |
483 | data_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER | |
484 | MT9M111_OUTFMT_RGB; | |
77110abb | 485 | break; |
f5fe58fd | 486 | case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE: |
7c58e7d0 | 487 | data_outfmt2 = MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB; |
77110abb | 488 | break; |
f5fe58fd | 489 | case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE: |
7c58e7d0 MG |
490 | data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555 | |
491 | MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN; | |
492 | break; | |
f5fe58fd | 493 | case MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE: |
7c58e7d0 | 494 | data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555; |
77110abb | 495 | break; |
f5fe58fd | 496 | case MEDIA_BUS_FMT_RGB565_2X8_LE: |
7c58e7d0 MG |
497 | data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 | |
498 | MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN; | |
499 | break; | |
f5fe58fd | 500 | case MEDIA_BUS_FMT_RGB565_2X8_BE: |
7c58e7d0 MG |
501 | data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565; |
502 | break; | |
f5fe58fd | 503 | case MEDIA_BUS_FMT_BGR565_2X8_BE: |
7c58e7d0 MG |
504 | data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 | |
505 | MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B; | |
506 | break; | |
f5fe58fd | 507 | case MEDIA_BUS_FMT_BGR565_2X8_LE: |
7c58e7d0 MG |
508 | data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 | |
509 | MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN | | |
510 | MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B; | |
77110abb | 511 | break; |
f5fe58fd | 512 | case MEDIA_BUS_FMT_UYVY8_2X8: |
7c58e7d0 | 513 | data_outfmt2 = 0; |
88f4b899 | 514 | break; |
f5fe58fd | 515 | case MEDIA_BUS_FMT_VYUY8_2X8: |
7c58e7d0 | 516 | data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B; |
88f4b899 | 517 | break; |
f5fe58fd | 518 | case MEDIA_BUS_FMT_YUYV8_2X8: |
7c58e7d0 | 519 | data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN; |
88f4b899 | 520 | break; |
f5fe58fd | 521 | case MEDIA_BUS_FMT_YVYU8_2X8: |
7c58e7d0 MG |
522 | data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN | |
523 | MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B; | |
77110abb RJ |
524 | break; |
525 | default: | |
7c58e7d0 MG |
526 | dev_err(&client->dev, "Pixel format not handled: %x\n", code); |
527 | return -EINVAL; | |
77110abb RJ |
528 | } |
529 | ||
47921932 GL |
530 | ret = mt9m111_reg_mask(client, context_a.output_fmt_ctrl2, |
531 | data_outfmt2, mask_outfmt2); | |
7c58e7d0 | 532 | if (!ret) |
47921932 GL |
533 | ret = mt9m111_reg_mask(client, context_b.output_fmt_ctrl2, |
534 | data_outfmt2, mask_outfmt2); | |
7c58e7d0 | 535 | |
77110abb RJ |
536 | return ret; |
537 | } | |
538 | ||
717fd5b4 HV |
539 | static int mt9m111_set_fmt(struct v4l2_subdev *sd, |
540 | struct v4l2_subdev_pad_config *cfg, | |
541 | struct v4l2_subdev_format *format) | |
77110abb | 542 | { |
717fd5b4 | 543 | struct v4l2_mbus_framefmt *mf = &format->format; |
da673e60 | 544 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
2768cbbb | 545 | struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); |
760697be | 546 | const struct mt9m111_datafmt *fmt; |
da673e60 GL |
547 | struct v4l2_rect *rect = &mt9m111->rect; |
548 | bool bayer; | |
717fd5b4 HV |
549 | int ret; |
550 | ||
551 | if (format->pad) | |
552 | return -EINVAL; | |
da673e60 GL |
553 | |
554 | fmt = mt9m111_find_datafmt(mt9m111, mf->code); | |
555 | ||
f5fe58fd BB |
556 | bayer = fmt->code == MEDIA_BUS_FMT_SBGGR8_1X8 || |
557 | fmt->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE; | |
6a6c8786 GL |
558 | |
559 | /* | |
560 | * With Bayer format enforce even side lengths, but let the user play | |
561 | * with the starting pixel | |
562 | */ | |
da673e60 GL |
563 | if (bayer) { |
564 | rect->width = ALIGN(rect->width, 2); | |
565 | rect->height = ALIGN(rect->height, 2); | |
566 | } | |
64f5905e | 567 | |
f5fe58fd | 568 | if (fmt->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE) { |
da673e60 GL |
569 | /* IFP bypass mode, no scaling */ |
570 | mf->width = rect->width; | |
571 | mf->height = rect->height; | |
572 | } else { | |
573 | /* No upscaling */ | |
574 | if (mf->width > rect->width) | |
575 | mf->width = rect->width; | |
576 | if (mf->height > rect->height) | |
577 | mf->height = rect->height; | |
578 | } | |
6a6c8786 | 579 | |
da673e60 GL |
580 | dev_dbg(&client->dev, "%s(): %ux%u, code=%x\n", __func__, |
581 | mf->width, mf->height, fmt->code); | |
760697be | 582 | |
da673e60 | 583 | mf->code = fmt->code; |
760697be | 584 | mf->colorspace = fmt->colorspace; |
77110abb | 585 | |
717fd5b4 HV |
586 | if (format->which == V4L2_SUBDEV_FORMAT_TRY) { |
587 | cfg->try_fmt = *mf; | |
588 | return 0; | |
589 | } | |
da673e60 GL |
590 | |
591 | ret = mt9m111_setup_geometry(mt9m111, rect, mf->width, mf->height, mf->code); | |
592 | if (!ret) | |
593 | ret = mt9m111_set_pixfmt(mt9m111, mf->code); | |
594 | if (!ret) { | |
595 | mt9m111->width = mf->width; | |
596 | mt9m111->height = mf->height; | |
597 | mt9m111->fmt = fmt; | |
598 | } | |
599 | ||
600 | return ret; | |
601 | } | |
602 | ||
77110abb | 603 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
979ea1dd GL |
604 | static int mt9m111_g_register(struct v4l2_subdev *sd, |
605 | struct v4l2_dbg_register *reg) | |
77110abb | 606 | { |
c4ce6d14 | 607 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
77110abb | 608 | int val; |
77110abb | 609 | |
6be89daa | 610 | if (reg->reg > 0x2ff) |
77110abb | 611 | return -EINVAL; |
77110abb | 612 | |
9538e1c2 | 613 | val = mt9m111_reg_read(client, reg->reg); |
aecde8b5 | 614 | reg->size = 2; |
77110abb RJ |
615 | reg->val = (u64)val; |
616 | ||
617 | if (reg->val > 0xffff) | |
618 | return -EIO; | |
619 | ||
620 | return 0; | |
621 | } | |
622 | ||
979ea1dd | 623 | static int mt9m111_s_register(struct v4l2_subdev *sd, |
977ba3b1 | 624 | const struct v4l2_dbg_register *reg) |
77110abb | 625 | { |
c4ce6d14 | 626 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
77110abb | 627 | |
6be89daa | 628 | if (reg->reg > 0x2ff) |
77110abb RJ |
629 | return -EINVAL; |
630 | ||
9538e1c2 | 631 | if (mt9m111_reg_write(client, reg->reg, reg->val) < 0) |
77110abb RJ |
632 | return -EIO; |
633 | ||
634 | return 0; | |
635 | } | |
636 | #endif | |
637 | ||
2768cbbb | 638 | static int mt9m111_set_flip(struct mt9m111 *mt9m111, int flip, int mask) |
77110abb | 639 | { |
2768cbbb | 640 | struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); |
77110abb RJ |
641 | int ret; |
642 | ||
47921932 GL |
643 | if (flip) |
644 | ret = mt9m111_reg_set(client, mt9m111->ctx->read_mode, mask); | |
645 | else | |
646 | ret = mt9m111_reg_clear(client, mt9m111->ctx->read_mode, mask); | |
77110abb RJ |
647 | |
648 | return ret; | |
649 | } | |
650 | ||
2768cbbb | 651 | static int mt9m111_get_global_gain(struct mt9m111 *mt9m111) |
77110abb | 652 | { |
2768cbbb | 653 | struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); |
0f28b793 | 654 | int data; |
77110abb RJ |
655 | |
656 | data = reg_read(GLOBAL_GAIN); | |
657 | if (data >= 0) | |
0f28b793 | 658 | return (data & 0x2f) * (1 << ((data >> 10) & 1)) * |
659 | (1 << ((data >> 9) & 1)); | |
660 | return data; | |
77110abb | 661 | } |
0f28b793 | 662 | |
2768cbbb | 663 | static int mt9m111_set_global_gain(struct mt9m111 *mt9m111, int gain) |
77110abb | 664 | { |
2768cbbb | 665 | struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); |
77110abb RJ |
666 | u16 val; |
667 | ||
668 | if (gain > 63 * 2 * 2) | |
669 | return -EINVAL; | |
670 | ||
77110abb RJ |
671 | if ((gain >= 64 * 2) && (gain < 63 * 2 * 2)) |
672 | val = (1 << 10) | (1 << 9) | (gain / 4); | |
673 | else if ((gain >= 64) && (gain < 64 * 2)) | |
506c629a | 674 | val = (1 << 9) | (gain / 2); |
77110abb RJ |
675 | else |
676 | val = gain; | |
677 | ||
678 | return reg_write(GLOBAL_GAIN, val); | |
679 | } | |
680 | ||
cbaa5c54 | 681 | static int mt9m111_set_autoexposure(struct mt9m111 *mt9m111, int val) |
77110abb | 682 | { |
2768cbbb | 683 | struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); |
77110abb | 684 | |
cbaa5c54 | 685 | if (val == V4L2_EXPOSURE_AUTO) |
af8425c5 HV |
686 | return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN); |
687 | return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN); | |
77110abb | 688 | } |
39bf372f | 689 | |
2768cbbb | 690 | static int mt9m111_set_autowhitebalance(struct mt9m111 *mt9m111, int on) |
39bf372f | 691 | { |
2768cbbb | 692 | struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); |
39bf372f RJ |
693 | |
694 | if (on) | |
af8425c5 HV |
695 | return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN); |
696 | return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN); | |
39bf372f RJ |
697 | } |
698 | ||
af8425c5 | 699 | static int mt9m111_s_ctrl(struct v4l2_ctrl *ctrl) |
77110abb | 700 | { |
af8425c5 HV |
701 | struct mt9m111 *mt9m111 = container_of(ctrl->handler, |
702 | struct mt9m111, hdl); | |
77110abb RJ |
703 | |
704 | switch (ctrl->id) { | |
705 | case V4L2_CID_VFLIP: | |
af8425c5 | 706 | return mt9m111_set_flip(mt9m111, ctrl->val, |
77110abb | 707 | MT9M111_RMB_MIRROR_ROWS); |
77110abb | 708 | case V4L2_CID_HFLIP: |
af8425c5 | 709 | return mt9m111_set_flip(mt9m111, ctrl->val, |
77110abb | 710 | MT9M111_RMB_MIRROR_COLS); |
77110abb | 711 | case V4L2_CID_GAIN: |
af8425c5 | 712 | return mt9m111_set_global_gain(mt9m111, ctrl->val); |
77110abb | 713 | case V4L2_CID_EXPOSURE_AUTO: |
af8425c5 | 714 | return mt9m111_set_autoexposure(mt9m111, ctrl->val); |
39bf372f | 715 | case V4L2_CID_AUTO_WHITE_BALANCE: |
af8425c5 | 716 | return mt9m111_set_autowhitebalance(mt9m111, ctrl->val); |
77110abb RJ |
717 | } |
718 | ||
af8425c5 | 719 | return -EINVAL; |
77110abb RJ |
720 | } |
721 | ||
14c5ea9b | 722 | static int mt9m111_suspend(struct mt9m111 *mt9m111) |
96c75399 | 723 | { |
a650bf1e GL |
724 | struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); |
725 | int ret; | |
726 | ||
af8425c5 | 727 | v4l2_ctrl_s_ctrl(mt9m111->gain, mt9m111_get_global_gain(mt9m111)); |
96c75399 | 728 | |
a650bf1e GL |
729 | ret = reg_set(RESET, MT9M111_RESET_RESET_MODE); |
730 | if (!ret) | |
731 | ret = reg_set(RESET, MT9M111_RESET_RESET_SOC | | |
732 | MT9M111_RESET_OUTPUT_DISABLE | | |
733 | MT9M111_RESET_ANALOG_STANDBY); | |
734 | if (!ret) | |
735 | ret = reg_clear(RESET, MT9M111_RESET_CHIP_ENABLE); | |
736 | ||
737 | return ret; | |
96c75399 GL |
738 | } |
739 | ||
2768cbbb | 740 | static void mt9m111_restore_state(struct mt9m111 *mt9m111) |
77110abb | 741 | { |
47921932 | 742 | mt9m111_set_context(mt9m111, mt9m111->ctx); |
2768cbbb | 743 | mt9m111_set_pixfmt(mt9m111, mt9m111->fmt->code); |
da673e60 GL |
744 | mt9m111_setup_geometry(mt9m111, &mt9m111->rect, |
745 | mt9m111->width, mt9m111->height, mt9m111->fmt->code); | |
af8425c5 | 746 | v4l2_ctrl_handler_setup(&mt9m111->hdl); |
77110abb RJ |
747 | } |
748 | ||
14c5ea9b | 749 | static int mt9m111_resume(struct mt9m111 *mt9m111) |
77110abb | 750 | { |
a650bf1e GL |
751 | int ret = mt9m111_enable(mt9m111); |
752 | if (!ret) | |
753 | ret = mt9m111_reset(mt9m111); | |
754 | if (!ret) | |
755 | mt9m111_restore_state(mt9m111); | |
77110abb | 756 | |
77110abb RJ |
757 | return ret; |
758 | } | |
759 | ||
2768cbbb | 760 | static int mt9m111_init(struct mt9m111 *mt9m111) |
77110abb | 761 | { |
2768cbbb | 762 | struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); |
77110abb RJ |
763 | int ret; |
764 | ||
2768cbbb | 765 | ret = mt9m111_enable(mt9m111); |
506c629a | 766 | if (!ret) |
2768cbbb | 767 | ret = mt9m111_reset(mt9m111); |
506c629a | 768 | if (!ret) |
47921932 | 769 | ret = mt9m111_set_context(mt9m111, mt9m111->ctx); |
506c629a | 770 | if (ret) |
c8cf078e | 771 | dev_err(&client->dev, "mt9m111 init failed: %d\n", ret); |
506c629a | 772 | return ret; |
77110abb RJ |
773 | } |
774 | ||
4ec10bac LP |
775 | static int mt9m111_power_on(struct mt9m111 *mt9m111) |
776 | { | |
777 | struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); | |
25a34811 | 778 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
4ec10bac LP |
779 | int ret; |
780 | ||
9aea470b | 781 | ret = soc_camera_power_on(&client->dev, ssdd, mt9m111->clk); |
4ec10bac LP |
782 | if (ret < 0) |
783 | return ret; | |
784 | ||
785 | ret = mt9m111_resume(mt9m111); | |
786 | if (ret < 0) { | |
787 | dev_err(&client->dev, "Failed to resume the sensor: %d\n", ret); | |
9aea470b | 788 | soc_camera_power_off(&client->dev, ssdd, mt9m111->clk); |
4ec10bac LP |
789 | } |
790 | ||
791 | return ret; | |
792 | } | |
793 | ||
794 | static void mt9m111_power_off(struct mt9m111 *mt9m111) | |
795 | { | |
796 | struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); | |
25a34811 | 797 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
4ec10bac LP |
798 | |
799 | mt9m111_suspend(mt9m111); | |
9aea470b | 800 | soc_camera_power_off(&client->dev, ssdd, mt9m111->clk); |
4ec10bac LP |
801 | } |
802 | ||
14c5ea9b GL |
803 | static int mt9m111_s_power(struct v4l2_subdev *sd, int on) |
804 | { | |
805 | struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); | |
14c5ea9b GL |
806 | int ret = 0; |
807 | ||
808 | mutex_lock(&mt9m111->power_lock); | |
809 | ||
810 | /* | |
811 | * If the power count is modified from 0 to != 0 or from != 0 to 0, | |
812 | * update the power state. | |
813 | */ | |
814 | if (mt9m111->power_count == !on) { | |
4ec10bac LP |
815 | if (on) |
816 | ret = mt9m111_power_on(mt9m111); | |
817 | else | |
818 | mt9m111_power_off(mt9m111); | |
14c5ea9b GL |
819 | } |
820 | ||
4ec10bac LP |
821 | if (!ret) { |
822 | /* Update the power count. */ | |
823 | mt9m111->power_count += on ? 1 : -1; | |
824 | WARN_ON(mt9m111->power_count < 0); | |
825 | } | |
14c5ea9b | 826 | |
14c5ea9b GL |
827 | mutex_unlock(&mt9m111->power_lock); |
828 | return ret; | |
829 | } | |
830 | ||
af8425c5 HV |
831 | static const struct v4l2_ctrl_ops mt9m111_ctrl_ops = { |
832 | .s_ctrl = mt9m111_s_ctrl, | |
833 | }; | |
834 | ||
979ea1dd | 835 | static struct v4l2_subdev_core_ops mt9m111_subdev_core_ops = { |
14c5ea9b | 836 | .s_power = mt9m111_s_power, |
979ea1dd GL |
837 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
838 | .g_register = mt9m111_g_register, | |
839 | .s_register = mt9m111_s_register, | |
840 | #endif | |
841 | }; | |
842 | ||
ebcff5fc HV |
843 | static int mt9m111_enum_mbus_code(struct v4l2_subdev *sd, |
844 | struct v4l2_subdev_pad_config *cfg, | |
845 | struct v4l2_subdev_mbus_code_enum *code) | |
760697be | 846 | { |
ebcff5fc | 847 | if (code->pad || code->index >= ARRAY_SIZE(mt9m111_colour_fmts)) |
760697be GL |
848 | return -EINVAL; |
849 | ||
ebcff5fc | 850 | code->code = mt9m111_colour_fmts[code->index].code; |
760697be GL |
851 | return 0; |
852 | } | |
853 | ||
0c0b446d GL |
854 | static int mt9m111_g_mbus_config(struct v4l2_subdev *sd, |
855 | struct v4l2_mbus_config *cfg) | |
856 | { | |
857 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
25a34811 | 858 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
0c0b446d GL |
859 | |
860 | cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING | | |
861 | V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_HIGH | | |
862 | V4L2_MBUS_DATA_ACTIVE_HIGH; | |
863 | cfg->type = V4L2_MBUS_PARALLEL; | |
25a34811 | 864 | cfg->flags = soc_camera_apply_board_flags(ssdd, cfg); |
0c0b446d GL |
865 | |
866 | return 0; | |
867 | } | |
868 | ||
979ea1dd | 869 | static struct v4l2_subdev_video_ops mt9m111_subdev_video_ops = { |
08590b96 | 870 | .s_crop = mt9m111_s_crop, |
6a6c8786 GL |
871 | .g_crop = mt9m111_g_crop, |
872 | .cropcap = mt9m111_cropcap, | |
0c0b446d | 873 | .g_mbus_config = mt9m111_g_mbus_config, |
979ea1dd GL |
874 | }; |
875 | ||
ebcff5fc HV |
876 | static const struct v4l2_subdev_pad_ops mt9m111_subdev_pad_ops = { |
877 | .enum_mbus_code = mt9m111_enum_mbus_code, | |
da298c6d | 878 | .get_fmt = mt9m111_get_fmt, |
717fd5b4 | 879 | .set_fmt = mt9m111_set_fmt, |
ebcff5fc HV |
880 | }; |
881 | ||
979ea1dd GL |
882 | static struct v4l2_subdev_ops mt9m111_subdev_ops = { |
883 | .core = &mt9m111_subdev_core_ops, | |
884 | .video = &mt9m111_subdev_video_ops, | |
ebcff5fc | 885 | .pad = &mt9m111_subdev_pad_ops, |
979ea1dd GL |
886 | }; |
887 | ||
4bbc6d52 LP |
888 | /* |
889 | * Interface active, can use i2c. If it fails, it can indeed mean, that | |
890 | * this wasn't our capture interface, so, we wait for the right one | |
891 | */ | |
892 | static int mt9m111_video_probe(struct i2c_client *client) | |
893 | { | |
894 | struct mt9m111 *mt9m111 = to_mt9m111(client); | |
895 | s32 data; | |
896 | int ret; | |
897 | ||
898 | ret = mt9m111_s_power(&mt9m111->subdev, 1); | |
899 | if (ret < 0) | |
900 | return ret; | |
901 | ||
902 | data = reg_read(CHIP_VERSION); | |
903 | ||
904 | switch (data) { | |
905 | case 0x143a: /* MT9M111 or MT9M131 */ | |
4bbc6d52 LP |
906 | dev_info(&client->dev, |
907 | "Detected a MT9M111/MT9M131 chip ID %x\n", data); | |
908 | break; | |
909 | case 0x148c: /* MT9M112 */ | |
4bbc6d52 LP |
910 | dev_info(&client->dev, "Detected a MT9M112 chip ID %x\n", data); |
911 | break; | |
912 | default: | |
913 | dev_err(&client->dev, | |
914 | "No MT9M111/MT9M112/MT9M131 chip detected register read %x\n", | |
915 | data); | |
916 | ret = -ENODEV; | |
917 | goto done; | |
918 | } | |
919 | ||
920 | ret = mt9m111_init(mt9m111); | |
921 | if (ret) | |
922 | goto done; | |
923 | ||
924 | ret = v4l2_ctrl_handler_setup(&mt9m111->hdl); | |
925 | ||
926 | done: | |
927 | mt9m111_s_power(&mt9m111->subdev, 0); | |
928 | return ret; | |
929 | } | |
930 | ||
77110abb RJ |
931 | static int mt9m111_probe(struct i2c_client *client, |
932 | const struct i2c_device_id *did) | |
933 | { | |
934 | struct mt9m111 *mt9m111; | |
77110abb | 935 | struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); |
25a34811 | 936 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
77110abb RJ |
937 | int ret; |
938 | ||
c5f176dc RJ |
939 | if (client->dev.of_node) { |
940 | ssdd = devm_kzalloc(&client->dev, sizeof(*ssdd), GFP_KERNEL); | |
941 | if (!ssdd) | |
942 | return -ENOMEM; | |
943 | client->dev.platform_data = ssdd; | |
944 | } | |
25a34811 | 945 | if (!ssdd) { |
c8cf078e | 946 | dev_err(&client->dev, "mt9m111: driver needs platform data\n"); |
77110abb RJ |
947 | return -EINVAL; |
948 | } | |
949 | ||
950 | if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) { | |
951 | dev_warn(&adapter->dev, | |
952 | "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n"); | |
953 | return -EIO; | |
954 | } | |
955 | ||
70e176a5 | 956 | mt9m111 = devm_kzalloc(&client->dev, sizeof(struct mt9m111), GFP_KERNEL); |
77110abb RJ |
957 | if (!mt9m111) |
958 | return -ENOMEM; | |
959 | ||
ef6672ea GL |
960 | mt9m111->clk = v4l2_clk_get(&client->dev, "mclk"); |
961 | if (IS_ERR(mt9m111->clk)) | |
962 | return -EPROBE_DEFER; | |
963 | ||
4a1313c4 GL |
964 | /* Default HIGHPOWER context */ |
965 | mt9m111->ctx = &context_b; | |
966 | ||
979ea1dd | 967 | v4l2_i2c_subdev_init(&mt9m111->subdev, client, &mt9m111_subdev_ops); |
af8425c5 HV |
968 | v4l2_ctrl_handler_init(&mt9m111->hdl, 5); |
969 | v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops, | |
970 | V4L2_CID_VFLIP, 0, 1, 1, 0); | |
971 | v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops, | |
972 | V4L2_CID_HFLIP, 0, 1, 1, 0); | |
973 | v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops, | |
974 | V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1); | |
975 | mt9m111->gain = v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops, | |
976 | V4L2_CID_GAIN, 0, 63 * 2 * 2, 1, 32); | |
977 | v4l2_ctrl_new_std_menu(&mt9m111->hdl, | |
978 | &mt9m111_ctrl_ops, V4L2_CID_EXPOSURE_AUTO, 1, 0, | |
979 | V4L2_EXPOSURE_AUTO); | |
980 | mt9m111->subdev.ctrl_handler = &mt9m111->hdl; | |
ef6672ea GL |
981 | if (mt9m111->hdl.error) { |
982 | ret = mt9m111->hdl.error; | |
983 | goto out_clkput; | |
984 | } | |
77110abb | 985 | |
af8425c5 | 986 | /* Second stage probe - when a capture adapter is there */ |
6a6c8786 GL |
987 | mt9m111->rect.left = MT9M111_MIN_DARK_COLS; |
988 | mt9m111->rect.top = MT9M111_MIN_DARK_ROWS; | |
989 | mt9m111->rect.width = MT9M111_MAX_WIDTH; | |
990 | mt9m111->rect.height = MT9M111_MAX_HEIGHT; | |
760697be | 991 | mt9m111->fmt = &mt9m111_colour_fmts[0]; |
14178aa5 | 992 | mt9m111->lastpage = -1; |
6b806e30 | 993 | mutex_init(&mt9m111->power_lock); |
6a6c8786 | 994 | |
ef6672ea GL |
995 | ret = soc_camera_power_init(&client->dev, ssdd); |
996 | if (ret < 0) | |
997 | goto out_hdlfree; | |
9aea470b | 998 | |
14178aa5 | 999 | ret = mt9m111_video_probe(client); |
ef6672ea GL |
1000 | if (ret < 0) |
1001 | goto out_hdlfree; | |
1002 | ||
1003 | mt9m111->subdev.dev = &client->dev; | |
1004 | ret = v4l2_async_register_subdev(&mt9m111->subdev); | |
1005 | if (ret < 0) | |
1006 | goto out_hdlfree; | |
1007 | ||
1008 | return 0; | |
1009 | ||
1010 | out_hdlfree: | |
1011 | v4l2_ctrl_handler_free(&mt9m111->hdl); | |
1012 | out_clkput: | |
1013 | v4l2_clk_put(mt9m111->clk); | |
77110abb | 1014 | |
77110abb RJ |
1015 | return ret; |
1016 | } | |
1017 | ||
1018 | static int mt9m111_remove(struct i2c_client *client) | |
1019 | { | |
979ea1dd | 1020 | struct mt9m111 *mt9m111 = to_mt9m111(client); |
40e2e092 | 1021 | |
ef6672ea | 1022 | v4l2_async_unregister_subdev(&mt9m111->subdev); |
9aea470b | 1023 | v4l2_clk_put(mt9m111->clk); |
af8425c5 | 1024 | v4l2_ctrl_handler_free(&mt9m111->hdl); |
77110abb RJ |
1025 | |
1026 | return 0; | |
1027 | } | |
c5f176dc RJ |
1028 | static const struct of_device_id mt9m111_of_match[] = { |
1029 | { .compatible = "micron,mt9m111", }, | |
1030 | {}, | |
1031 | }; | |
1032 | MODULE_DEVICE_TABLE(of, mt9m111_of_match); | |
77110abb RJ |
1033 | |
1034 | static const struct i2c_device_id mt9m111_id[] = { | |
1035 | { "mt9m111", 0 }, | |
1036 | { } | |
1037 | }; | |
1038 | MODULE_DEVICE_TABLE(i2c, mt9m111_id); | |
1039 | ||
1040 | static struct i2c_driver mt9m111_i2c_driver = { | |
1041 | .driver = { | |
1042 | .name = "mt9m111", | |
c5f176dc | 1043 | .of_match_table = of_match_ptr(mt9m111_of_match), |
77110abb RJ |
1044 | }, |
1045 | .probe = mt9m111_probe, | |
1046 | .remove = mt9m111_remove, | |
1047 | .id_table = mt9m111_id, | |
1048 | }; | |
1049 | ||
c6e8d86f | 1050 | module_i2c_driver(mt9m111_i2c_driver); |
77110abb | 1051 | |
c8cf078e | 1052 | MODULE_DESCRIPTION("Micron/Aptina MT9M111/MT9M112/MT9M131 Camera driver"); |
77110abb RJ |
1053 | MODULE_AUTHOR("Robert Jarzmik"); |
1054 | MODULE_LICENSE("GPL"); |