[linux-2.6-block.git] / drivers / media / i2c / smiapp-pll.h

/*
 * drivers/media/i2c/smiapp-pll.h
 *
 * Generic driver for SMIA/SMIA++ compliant camera modules
 *
 * Copyright (C) 2012 Nokia Corporation
 * Contact: Sakari Ailus <sakari.ailus@iki.fi>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 */

#ifndef SMIAPP_PLL_H
#define SMIAPP_PLL_H

/* CSI-2 or CCP-2 */
#define SMIAPP_PLL_BUS_TYPE_CSI2				0x00
#define SMIAPP_PLL_BUS_TYPE_PARALLEL				0x01

/* op pix clock is for all lanes in total normally */
#define SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE			(1 << 0)
#define SMIAPP_PLL_FLAG_NO_OP_CLOCKS				(1 << 1)

struct smiapp_pll_branch {
	uint16_t sys_clk_div;
	uint16_t pix_clk_div;
	uint32_t sys_clk_freq_hz;
	uint32_t pix_clk_freq_hz;
};

struct smiapp_pll {
	/* input values */
	uint8_t bus_type;
	union {
		struct {
			uint8_t lanes;
		} csi2;
		struct {
			uint8_t bus_width;
		} parallel;
	};
	unsigned long flags;
	uint8_t binning_horizontal;
	uint8_t binning_vertical;
	uint8_t scale_m;
	uint8_t scale_n;
	uint8_t bits_per_pixel;
	uint32_t link_freq;
	uint32_t ext_clk_freq_hz;

	/* output values */
	uint16_t pre_pll_clk_div;
	uint16_t pll_multiplier;
	uint32_t pll_ip_clk_freq_hz;
	uint32_t pll_op_clk_freq_hz;
	struct smiapp_pll_branch vt;
	struct smiapp_pll_branch op;

	uint32_t pixel_rate_csi;
	uint32_t pixel_rate_pixel_array;
};

struct smiapp_pll_branch_limits {
	uint16_t min_sys_clk_div;
	uint16_t max_sys_clk_div;
	uint32_t min_sys_clk_freq_hz;
	uint32_t max_sys_clk_freq_hz;
	uint16_t min_pix_clk_div;
	uint16_t max_pix_clk_div;
	uint32_t min_pix_clk_freq_hz;
	uint32_t max_pix_clk_freq_hz;
};

struct smiapp_pll_limits {
	/* Strict PLL limits */
	uint32_t min_ext_clk_freq_hz;
	uint32_t max_ext_clk_freq_hz;
	uint16_t min_pre_pll_clk_div;
	uint16_t max_pre_pll_clk_div;
	uint32_t min_pll_ip_freq_hz;
	uint32_t max_pll_ip_freq_hz;
	uint16_t min_pll_multiplier;
	uint16_t max_pll_multiplier;
	uint32_t min_pll_op_freq_hz;
	uint32_t max_pll_op_freq_hz;

	struct smiapp_pll_branch_limits vt;
	struct smiapp_pll_branch_limits op;

	/* Other relevant limits */
	uint32_t min_line_length_pck_bin;
	uint32_t min_line_length_pck;
};

struct device;

int smiapp_pll_calculate(struct device *dev,
			 const struct smiapp_pll_limits *limits,
			 struct smiapp_pll *pll);

#endif /* SMIAPP_PLL_H */
Commit	Line	Data
cf1c5fae	1	/*
cb7a01ac	2	* drivers/media/i2c/smiapp-pll.h
cf1c5fae SA	3	*
	4	* Generic driver for SMIA/SMIA++ compliant camera modules
	5	*
	6	* Copyright (C) 2012 Nokia Corporation
8c5dff90	7	* Contact: Sakari Ailus <sakari.ailus@iki.fi>
cf1c5fae SA	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* version 2 as published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope that it will be useful, but
	14	* WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	16	* General Public License for more details.
cf1c5fae SA	17	*/
	18
	19	#ifndef SMIAPP_PLL_H
	20	#define SMIAPP_PLL_H
	21
f5984bbd SA	22	/* CSI-2 or CCP-2 */
	23	#define SMIAPP_PLL_BUS_TYPE_CSI2 0x00
	24	#define SMIAPP_PLL_BUS_TYPE_PARALLEL 0x01
	25
	26	/* op pix clock is for all lanes in total normally */
	27	#define SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0)
	28	#define SMIAPP_PLL_FLAG_NO_OP_CLOCKS (1 << 1)
	29
e3f8bc8c SA	30	struct smiapp_pll_branch {
	31	uint16_t sys_clk_div;
	32	uint16_t pix_clk_div;
	33	uint32_t sys_clk_freq_hz;
	34	uint32_t pix_clk_freq_hz;
	35	};
	36
cf1c5fae	37	struct smiapp_pll {
f5984bbd SA	38	/* input values */
	39	uint8_t bus_type;
	40	union {
	41	struct {
	42	uint8_t lanes;
	43	} csi2;
	44	struct {
	45	uint8_t bus_width;
	46	} parallel;
	47	};
19e9f5f5	48	unsigned long flags;
cf1c5fae SA	49	uint8_t binning_horizontal;
	50	uint8_t binning_vertical;
	51	uint8_t scale_m;
	52	uint8_t scale_n;
	53	uint8_t bits_per_pixel;
cf1c5fae	54	uint32_t link_freq;
fff888c7	55	uint32_t ext_clk_freq_hz;
cf1c5fae	56
f5984bbd	57	/* output values */
cf1c5fae SA	58	uint16_t pre_pll_clk_div;
cf1c5fae SA	59	uint16_t pll_multiplier;
cf1c5fae SA	60	uint32_t pll_ip_clk_freq_hz;
cf1c5fae SA	61	uint32_t pll_op_clk_freq_hz;
e3f8bc8c SA	62	struct smiapp_pll_branch vt;
e3f8bc8c SA	63	struct smiapp_pll_branch op;
cf1c5fae SA	64
cf1c5fae SA	65	uint32_t pixel_rate_csi;
e7c329a0	66	uint32_t pixel_rate_pixel_array;
cf1c5fae SA	67	};
cf1c5fae SA	68
6ec84a28 LP	69	struct smiapp_pll_branch_limits {
	70	uint16_t min_sys_clk_div;
	71	uint16_t max_sys_clk_div;
	72	uint32_t min_sys_clk_freq_hz;
	73	uint32_t max_sys_clk_freq_hz;
	74	uint16_t min_pix_clk_div;
	75	uint16_t max_pix_clk_div;
	76	uint32_t min_pix_clk_freq_hz;
	77	uint32_t max_pix_clk_freq_hz;
	78	};
	79
cf1c5fae SA	80	struct smiapp_pll_limits {
	81	/* Strict PLL limits */
	82	uint32_t min_ext_clk_freq_hz;
	83	uint32_t max_ext_clk_freq_hz;
	84	uint16_t min_pre_pll_clk_div;
	85	uint16_t max_pre_pll_clk_div;
	86	uint32_t min_pll_ip_freq_hz;
	87	uint32_t max_pll_ip_freq_hz;
	88	uint16_t min_pll_multiplier;
	89	uint16_t max_pll_multiplier;
	90	uint32_t min_pll_op_freq_hz;
	91	uint32_t max_pll_op_freq_hz;
	92
6ec84a28 LP	93	struct smiapp_pll_branch_limits vt;
6ec84a28 LP	94	struct smiapp_pll_branch_limits op;
cf1c5fae SA	95
	96	/* Other relevant limits */
	97	uint32_t min_line_length_pck_bin;
	98	uint32_t min_line_length_pck;
	99	};
	100
cf1c5fae SA	101	struct device;
cf1c5fae SA	102
8f7e91a3 LP	103	int smiapp_pll_calculate(struct device *dev,
8f7e91a3 LP	104	const struct smiapp_pll_limits *limits,
cf1c5fae SA	105	struct smiapp_pll *pll);
	106
	107	#endif /* SMIAPP_PLL_H */