Commit | Line | Data |
---|---|---|
1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
cf1c5fae | 2 | /* |
cb7a01ac | 3 | * drivers/media/i2c/smiapp-pll.c |
cf1c5fae SA |
4 | * |
5 | * Generic driver for SMIA/SMIA++ compliant camera modules | |
6 | * | |
7 | * Copyright (C) 2011--2012 Nokia Corporation | |
8c5dff90 | 8 | * Contact: Sakari Ailus <sakari.ailus@iki.fi> |
cf1c5fae SA |
9 | */ |
10 | ||
8c20ee6e | 11 | #include <linux/device.h> |
cf1c5fae SA |
12 | #include <linux/gcd.h> |
13 | #include <linux/lcm.h> | |
14 | #include <linux/module.h> | |
15 | ||
16 | #include "smiapp-pll.h" | |
17 | ||
18 | /* Return an even number or one. */ | |
19 | static inline uint32_t clk_div_even(uint32_t a) | |
20 | { | |
21 | return max_t(uint32_t, 1, a & ~1); | |
22 | } | |
23 | ||
24 | /* Return an even number or one. */ | |
25 | static inline uint32_t clk_div_even_up(uint32_t a) | |
26 | { | |
27 | if (a == 1) | |
28 | return 1; | |
29 | return (a + 1) & ~1; | |
30 | } | |
31 | ||
32 | static inline uint32_t is_one_or_even(uint32_t a) | |
33 | { | |
34 | if (a == 1) | |
35 | return 1; | |
36 | if (a & 1) | |
37 | return 0; | |
38 | ||
39 | return 1; | |
40 | } | |
41 | ||
42 | static int bounds_check(struct device *dev, uint32_t val, | |
43 | uint32_t min, uint32_t max, char *str) | |
44 | { | |
45 | if (val >= min && val <= max) | |
46 | return 0; | |
47 | ||
6de1b143 | 48 | dev_dbg(dev, "%s out of bounds: %d (%d--%d)\n", str, val, min, max); |
cf1c5fae SA |
49 | |
50 | return -EINVAL; | |
51 | } | |
52 | ||
53 | static void print_pll(struct device *dev, struct smiapp_pll *pll) | |
54 | { | |
c37f9bf9 SA |
55 | dev_dbg(dev, "pre_pll_clk_div\t%u\n", pll->pre_pll_clk_div); |
56 | dev_dbg(dev, "pll_multiplier \t%u\n", pll->pll_multiplier); | |
bc47150a | 57 | if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) { |
e3f8bc8c SA |
58 | dev_dbg(dev, "op_sys_clk_div \t%u\n", pll->op.sys_clk_div); |
59 | dev_dbg(dev, "op_pix_clk_div \t%u\n", pll->op.pix_clk_div); | |
cf1c5fae | 60 | } |
e3f8bc8c SA |
61 | dev_dbg(dev, "vt_sys_clk_div \t%u\n", pll->vt.sys_clk_div); |
62 | dev_dbg(dev, "vt_pix_clk_div \t%u\n", pll->vt.pix_clk_div); | |
cf1c5fae | 63 | |
c37f9bf9 SA |
64 | dev_dbg(dev, "ext_clk_freq_hz \t%u\n", pll->ext_clk_freq_hz); |
65 | dev_dbg(dev, "pll_ip_clk_freq_hz \t%u\n", pll->pll_ip_clk_freq_hz); | |
66 | dev_dbg(dev, "pll_op_clk_freq_hz \t%u\n", pll->pll_op_clk_freq_hz); | |
bc47150a | 67 | if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) { |
c37f9bf9 | 68 | dev_dbg(dev, "op_sys_clk_freq_hz \t%u\n", |
e3f8bc8c | 69 | pll->op.sys_clk_freq_hz); |
c37f9bf9 | 70 | dev_dbg(dev, "op_pix_clk_freq_hz \t%u\n", |
e3f8bc8c | 71 | pll->op.pix_clk_freq_hz); |
cf1c5fae | 72 | } |
e3f8bc8c SA |
73 | dev_dbg(dev, "vt_sys_clk_freq_hz \t%u\n", pll->vt.sys_clk_freq_hz); |
74 | dev_dbg(dev, "vt_pix_clk_freq_hz \t%u\n", pll->vt.pix_clk_freq_hz); | |
cf1c5fae SA |
75 | } |
76 | ||
c859470a SA |
77 | static int check_all_bounds(struct device *dev, |
78 | const struct smiapp_pll_limits *limits, | |
974abe44 SA |
79 | const struct smiapp_pll_branch_limits *op_limits, |
80 | struct smiapp_pll *pll, | |
81 | struct smiapp_pll_branch *op_pll) | |
c859470a SA |
82 | { |
83 | int rval; | |
84 | ||
85 | rval = bounds_check(dev, pll->pll_ip_clk_freq_hz, | |
86 | limits->min_pll_ip_freq_hz, | |
87 | limits->max_pll_ip_freq_hz, | |
88 | "pll_ip_clk_freq_hz"); | |
89 | if (!rval) | |
90 | rval = bounds_check( | |
91 | dev, pll->pll_multiplier, | |
92 | limits->min_pll_multiplier, limits->max_pll_multiplier, | |
93 | "pll_multiplier"); | |
94 | if (!rval) | |
95 | rval = bounds_check( | |
96 | dev, pll->pll_op_clk_freq_hz, | |
97 | limits->min_pll_op_freq_hz, limits->max_pll_op_freq_hz, | |
98 | "pll_op_clk_freq_hz"); | |
99 | if (!rval) | |
100 | rval = bounds_check( | |
974abe44 SA |
101 | dev, op_pll->sys_clk_div, |
102 | op_limits->min_sys_clk_div, op_limits->max_sys_clk_div, | |
c859470a | 103 | "op_sys_clk_div"); |
c859470a SA |
104 | if (!rval) |
105 | rval = bounds_check( | |
974abe44 SA |
106 | dev, op_pll->sys_clk_freq_hz, |
107 | op_limits->min_sys_clk_freq_hz, | |
108 | op_limits->max_sys_clk_freq_hz, | |
c859470a SA |
109 | "op_sys_clk_freq_hz"); |
110 | if (!rval) | |
111 | rval = bounds_check( | |
974abe44 SA |
112 | dev, op_pll->pix_clk_freq_hz, |
113 | op_limits->min_pix_clk_freq_hz, | |
114 | op_limits->max_pix_clk_freq_hz, | |
c859470a | 115 | "op_pix_clk_freq_hz"); |
63516b55 SA |
116 | |
117 | /* | |
118 | * If there are no OP clocks, the VT clocks are contained in | |
119 | * the OP clock struct. | |
120 | */ | |
121 | if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) | |
122 | return rval; | |
123 | ||
c859470a SA |
124 | if (!rval) |
125 | rval = bounds_check( | |
e3f8bc8c | 126 | dev, pll->vt.sys_clk_freq_hz, |
c859470a SA |
127 | limits->vt.min_sys_clk_freq_hz, |
128 | limits->vt.max_sys_clk_freq_hz, | |
129 | "vt_sys_clk_freq_hz"); | |
130 | if (!rval) | |
131 | rval = bounds_check( | |
e3f8bc8c | 132 | dev, pll->vt.pix_clk_freq_hz, |
c859470a SA |
133 | limits->vt.min_pix_clk_freq_hz, |
134 | limits->vt.max_pix_clk_freq_hz, | |
135 | "vt_pix_clk_freq_hz"); | |
136 | ||
137 | return rval; | |
138 | } | |
139 | ||
367da7a3 SA |
140 | /* |
141 | * Heuristically guess the PLL tree for a given common multiplier and | |
142 | * divisor. Begin with the operational timing and continue to video | |
143 | * timing once operational timing has been verified. | |
144 | * | |
145 | * @mul is the PLL multiplier and @div is the common divisor | |
146 | * (pre_pll_clk_div and op_sys_clk_div combined). The final PLL | |
147 | * multiplier will be a multiple of @mul. | |
148 | * | |
149 | * @return Zero on success, error code on error. | |
150 | */ | |
974abe44 SA |
151 | static int __smiapp_pll_calculate( |
152 | struct device *dev, const struct smiapp_pll_limits *limits, | |
153 | const struct smiapp_pll_branch_limits *op_limits, | |
154 | struct smiapp_pll *pll, struct smiapp_pll_branch *op_pll, uint32_t mul, | |
155 | uint32_t div, uint32_t lane_op_clock_ratio) | |
cf1c5fae SA |
156 | { |
157 | uint32_t sys_div; | |
158 | uint32_t best_pix_div = INT_MAX >> 1; | |
159 | uint32_t vt_op_binning_div; | |
367da7a3 SA |
160 | /* |
161 | * Higher multipliers (and divisors) are often required than | |
162 | * necessitated by the external clock and the output clocks. | |
163 | * There are limits for all values in the clock tree. These | |
164 | * are the minimum and maximum multiplier for mul. | |
165 | */ | |
cf1c5fae SA |
166 | uint32_t more_mul_min, more_mul_max; |
167 | uint32_t more_mul_factor; | |
168 | uint32_t min_vt_div, max_vt_div, vt_div; | |
169 | uint32_t min_sys_div, max_sys_div; | |
170 | unsigned int i; | |
cf1c5fae | 171 | |
cf1c5fae SA |
172 | /* |
173 | * Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be | |
174 | * too high. | |
175 | */ | |
c37f9bf9 | 176 | dev_dbg(dev, "pre_pll_clk_div %u\n", pll->pre_pll_clk_div); |
cf1c5fae SA |
177 | |
178 | /* Don't go above max pll multiplier. */ | |
179 | more_mul_max = limits->max_pll_multiplier / mul; | |
c37f9bf9 | 180 | dev_dbg(dev, "more_mul_max: max_pll_multiplier check: %u\n", |
cf1c5fae SA |
181 | more_mul_max); |
182 | /* Don't go above max pll op frequency. */ | |
183 | more_mul_max = | |
c2ebca00 | 184 | min_t(uint32_t, |
cf1c5fae SA |
185 | more_mul_max, |
186 | limits->max_pll_op_freq_hz | |
187 | / (pll->ext_clk_freq_hz / pll->pre_pll_clk_div * mul)); | |
c37f9bf9 | 188 | dev_dbg(dev, "more_mul_max: max_pll_op_freq_hz check: %u\n", |
cf1c5fae SA |
189 | more_mul_max); |
190 | /* Don't go above the division capability of op sys clock divider. */ | |
191 | more_mul_max = min(more_mul_max, | |
974abe44 | 192 | op_limits->max_sys_clk_div * pll->pre_pll_clk_div |
cf1c5fae | 193 | / div); |
c37f9bf9 | 194 | dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n", |
cf1c5fae SA |
195 | more_mul_max); |
196 | /* Ensure we won't go above min_pll_multiplier. */ | |
197 | more_mul_max = min(more_mul_max, | |
198 | DIV_ROUND_UP(limits->max_pll_multiplier, mul)); | |
c37f9bf9 | 199 | dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n", |
cf1c5fae SA |
200 | more_mul_max); |
201 | ||
202 | /* Ensure we won't go below min_pll_op_freq_hz. */ | |
203 | more_mul_min = DIV_ROUND_UP(limits->min_pll_op_freq_hz, | |
204 | pll->ext_clk_freq_hz / pll->pre_pll_clk_div | |
205 | * mul); | |
c37f9bf9 | 206 | dev_dbg(dev, "more_mul_min: min_pll_op_freq_hz check: %u\n", |
cf1c5fae SA |
207 | more_mul_min); |
208 | /* Ensure we won't go below min_pll_multiplier. */ | |
209 | more_mul_min = max(more_mul_min, | |
210 | DIV_ROUND_UP(limits->min_pll_multiplier, mul)); | |
c37f9bf9 | 211 | dev_dbg(dev, "more_mul_min: min_pll_multiplier check: %u\n", |
cf1c5fae SA |
212 | more_mul_min); |
213 | ||
214 | if (more_mul_min > more_mul_max) { | |
6de1b143 SA |
215 | dev_dbg(dev, |
216 | "unable to compute more_mul_min and more_mul_max\n"); | |
cf1c5fae SA |
217 | return -EINVAL; |
218 | } | |
219 | ||
220 | more_mul_factor = lcm(div, pll->pre_pll_clk_div) / div; | |
c37f9bf9 | 221 | dev_dbg(dev, "more_mul_factor: %u\n", more_mul_factor); |
974abe44 SA |
222 | more_mul_factor = lcm(more_mul_factor, op_limits->min_sys_clk_div); |
223 | dev_dbg(dev, "more_mul_factor: min_op_sys_clk_div: %d\n", | |
cf1c5fae SA |
224 | more_mul_factor); |
225 | i = roundup(more_mul_min, more_mul_factor); | |
226 | if (!is_one_or_even(i)) | |
227 | i <<= 1; | |
228 | ||
c37f9bf9 | 229 | dev_dbg(dev, "final more_mul: %u\n", i); |
cf1c5fae | 230 | if (i > more_mul_max) { |
c37f9bf9 | 231 | dev_dbg(dev, "final more_mul is bad, max %u\n", more_mul_max); |
cf1c5fae SA |
232 | return -EINVAL; |
233 | } | |
234 | ||
235 | pll->pll_multiplier = mul * i; | |
974abe44 SA |
236 | op_pll->sys_clk_div = div * i / pll->pre_pll_clk_div; |
237 | dev_dbg(dev, "op_sys_clk_div: %u\n", op_pll->sys_clk_div); | |
cf1c5fae SA |
238 | |
239 | pll->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz | |
240 | / pll->pre_pll_clk_div; | |
241 | ||
242 | pll->pll_op_clk_freq_hz = pll->pll_ip_clk_freq_hz | |
243 | * pll->pll_multiplier; | |
244 | ||
245 | /* Derive pll_op_clk_freq_hz. */ | |
974abe44 SA |
246 | op_pll->sys_clk_freq_hz = |
247 | pll->pll_op_clk_freq_hz / op_pll->sys_clk_div; | |
cf1c5fae | 248 | |
974abe44 SA |
249 | op_pll->pix_clk_div = pll->bits_per_pixel; |
250 | dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll->pix_clk_div); | |
cf1c5fae | 251 | |
974abe44 SA |
252 | op_pll->pix_clk_freq_hz = |
253 | op_pll->sys_clk_freq_hz / op_pll->pix_clk_div; | |
254 | ||
255 | if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) { | |
256 | /* No OP clocks --- VT clocks are used instead. */ | |
257 | goto out_skip_vt_calc; | |
258 | } | |
cf1c5fae SA |
259 | |
260 | /* | |
261 | * Some sensors perform analogue binning and some do this | |
262 | * digitally. The ones doing this digitally can be roughly be | |
263 | * found out using this formula. The ones doing this digitally | |
264 | * should run at higher clock rate, so smaller divisor is used | |
265 | * on video timing side. | |
266 | */ | |
267 | if (limits->min_line_length_pck_bin > limits->min_line_length_pck | |
268 | / pll->binning_horizontal) | |
269 | vt_op_binning_div = pll->binning_horizontal; | |
270 | else | |
271 | vt_op_binning_div = 1; | |
c37f9bf9 | 272 | dev_dbg(dev, "vt_op_binning_div: %u\n", vt_op_binning_div); |
cf1c5fae SA |
273 | |
274 | /* | |
275 | * Profile 2 supports vt_pix_clk_div E [4, 10] | |
276 | * | |
277 | * Horizontal binning can be used as a base for difference in | |
278 | * divisors. One must make sure that horizontal blanking is | |
279 | * enough to accommodate the CSI-2 sync codes. | |
280 | * | |
281 | * Take scaling factor into account as well. | |
282 | * | |
283 | * Find absolute limits for the factor of vt divider. | |
284 | */ | |
c37f9bf9 | 285 | dev_dbg(dev, "scale_m: %u\n", pll->scale_m); |
974abe44 | 286 | min_vt_div = DIV_ROUND_UP(op_pll->pix_clk_div * op_pll->sys_clk_div |
cf1c5fae SA |
287 | * pll->scale_n, |
288 | lane_op_clock_ratio * vt_op_binning_div | |
289 | * pll->scale_m); | |
290 | ||
291 | /* Find smallest and biggest allowed vt divisor. */ | |
c37f9bf9 | 292 | dev_dbg(dev, "min_vt_div: %u\n", min_vt_div); |
cf1c5fae SA |
293 | min_vt_div = max(min_vt_div, |
294 | DIV_ROUND_UP(pll->pll_op_clk_freq_hz, | |
6ec84a28 | 295 | limits->vt.max_pix_clk_freq_hz)); |
c37f9bf9 | 296 | dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n", |
cf1c5fae SA |
297 | min_vt_div); |
298 | min_vt_div = max_t(uint32_t, min_vt_div, | |
6ec84a28 LP |
299 | limits->vt.min_pix_clk_div |
300 | * limits->vt.min_sys_clk_div); | |
c37f9bf9 | 301 | dev_dbg(dev, "min_vt_div: min_vt_clk_div: %u\n", min_vt_div); |
cf1c5fae | 302 | |
6ec84a28 | 303 | max_vt_div = limits->vt.max_sys_clk_div * limits->vt.max_pix_clk_div; |
c37f9bf9 | 304 | dev_dbg(dev, "max_vt_div: %u\n", max_vt_div); |
cf1c5fae SA |
305 | max_vt_div = min(max_vt_div, |
306 | DIV_ROUND_UP(pll->pll_op_clk_freq_hz, | |
6ec84a28 | 307 | limits->vt.min_pix_clk_freq_hz)); |
c37f9bf9 | 308 | dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n", |
cf1c5fae SA |
309 | max_vt_div); |
310 | ||
311 | /* | |
312 | * Find limitsits for sys_clk_div. Not all values are possible | |
313 | * with all values of pix_clk_div. | |
314 | */ | |
6ec84a28 | 315 | min_sys_div = limits->vt.min_sys_clk_div; |
c37f9bf9 | 316 | dev_dbg(dev, "min_sys_div: %u\n", min_sys_div); |
cf1c5fae SA |
317 | min_sys_div = max(min_sys_div, |
318 | DIV_ROUND_UP(min_vt_div, | |
6ec84a28 | 319 | limits->vt.max_pix_clk_div)); |
c37f9bf9 | 320 | dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", min_sys_div); |
cf1c5fae SA |
321 | min_sys_div = max(min_sys_div, |
322 | pll->pll_op_clk_freq_hz | |
6ec84a28 | 323 | / limits->vt.max_sys_clk_freq_hz); |
c37f9bf9 | 324 | dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", min_sys_div); |
cf1c5fae | 325 | min_sys_div = clk_div_even_up(min_sys_div); |
c37f9bf9 | 326 | dev_dbg(dev, "min_sys_div: one or even: %u\n", min_sys_div); |
cf1c5fae | 327 | |
6ec84a28 | 328 | max_sys_div = limits->vt.max_sys_clk_div; |
c37f9bf9 | 329 | dev_dbg(dev, "max_sys_div: %u\n", max_sys_div); |
cf1c5fae SA |
330 | max_sys_div = min(max_sys_div, |
331 | DIV_ROUND_UP(max_vt_div, | |
6ec84a28 | 332 | limits->vt.min_pix_clk_div)); |
c37f9bf9 | 333 | dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", max_sys_div); |
cf1c5fae SA |
334 | max_sys_div = min(max_sys_div, |
335 | DIV_ROUND_UP(pll->pll_op_clk_freq_hz, | |
6ec84a28 | 336 | limits->vt.min_pix_clk_freq_hz)); |
c37f9bf9 | 337 | dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", max_sys_div); |
cf1c5fae SA |
338 | |
339 | /* | |
340 | * Find pix_div such that a legal pix_div * sys_div results | |
341 | * into a value which is not smaller than div, the desired | |
342 | * divisor. | |
343 | */ | |
344 | for (vt_div = min_vt_div; vt_div <= max_vt_div; | |
345 | vt_div += 2 - (vt_div & 1)) { | |
346 | for (sys_div = min_sys_div; | |
347 | sys_div <= max_sys_div; | |
348 | sys_div += 2 - (sys_div & 1)) { | |
c2ebca00 | 349 | uint16_t pix_div = DIV_ROUND_UP(vt_div, sys_div); |
cf1c5fae | 350 | |
6ec84a28 LP |
351 | if (pix_div < limits->vt.min_pix_clk_div |
352 | || pix_div > limits->vt.max_pix_clk_div) { | |
cf1c5fae | 353 | dev_dbg(dev, |
c37f9bf9 | 354 | "pix_div %u too small or too big (%u--%u)\n", |
cf1c5fae | 355 | pix_div, |
6ec84a28 LP |
356 | limits->vt.min_pix_clk_div, |
357 | limits->vt.max_pix_clk_div); | |
cf1c5fae SA |
358 | continue; |
359 | } | |
360 | ||
361 | /* Check if this one is better. */ | |
362 | if (pix_div * sys_div | |
363 | <= roundup(min_vt_div, best_pix_div)) | |
364 | best_pix_div = pix_div; | |
365 | } | |
366 | if (best_pix_div < INT_MAX >> 1) | |
367 | break; | |
368 | } | |
369 | ||
e3f8bc8c SA |
370 | pll->vt.sys_clk_div = DIV_ROUND_UP(min_vt_div, best_pix_div); |
371 | pll->vt.pix_clk_div = best_pix_div; | |
cf1c5fae | 372 | |
e3f8bc8c SA |
373 | pll->vt.sys_clk_freq_hz = |
374 | pll->pll_op_clk_freq_hz / pll->vt.sys_clk_div; | |
375 | pll->vt.pix_clk_freq_hz = | |
376 | pll->vt.sys_clk_freq_hz / pll->vt.pix_clk_div; | |
cf1c5fae | 377 | |
974abe44 | 378 | out_skip_vt_calc: |
cf1c5fae | 379 | pll->pixel_rate_csi = |
974abe44 | 380 | op_pll->pix_clk_freq_hz * lane_op_clock_ratio; |
e7c329a0 | 381 | pll->pixel_rate_pixel_array = pll->vt.pix_clk_freq_hz; |
cf1c5fae | 382 | |
974abe44 | 383 | return check_all_bounds(dev, limits, op_limits, pll, op_pll); |
cf1c5fae | 384 | } |
6de1b143 | 385 | |
8f7e91a3 LP |
386 | int smiapp_pll_calculate(struct device *dev, |
387 | const struct smiapp_pll_limits *limits, | |
6de1b143 SA |
388 | struct smiapp_pll *pll) |
389 | { | |
974abe44 SA |
390 | const struct smiapp_pll_branch_limits *op_limits = &limits->op; |
391 | struct smiapp_pll_branch *op_pll = &pll->op; | |
8f7e91a3 LP |
392 | uint16_t min_pre_pll_clk_div; |
393 | uint16_t max_pre_pll_clk_div; | |
6de1b143 SA |
394 | uint32_t lane_op_clock_ratio; |
395 | uint32_t mul, div; | |
396 | unsigned int i; | |
397 | int rval = -EINVAL; | |
398 | ||
974abe44 SA |
399 | if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) { |
400 | /* | |
401 | * If there's no OP PLL at all, use the VT values | |
402 | * instead. The OP values are ignored for the rest of | |
403 | * the PLL calculation. | |
404 | */ | |
405 | op_limits = &limits->vt; | |
406 | op_pll = &pll->vt; | |
407 | } | |
408 | ||
6de1b143 | 409 | if (pll->flags & SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE) |
f5984bbd | 410 | lane_op_clock_ratio = pll->csi2.lanes; |
6de1b143 SA |
411 | else |
412 | lane_op_clock_ratio = 1; | |
c37f9bf9 | 413 | dev_dbg(dev, "lane_op_clock_ratio: %u\n", lane_op_clock_ratio); |
6de1b143 | 414 | |
c37f9bf9 | 415 | dev_dbg(dev, "binning: %ux%u\n", pll->binning_horizontal, |
6de1b143 SA |
416 | pll->binning_vertical); |
417 | ||
f5984bbd SA |
418 | switch (pll->bus_type) { |
419 | case SMIAPP_PLL_BUS_TYPE_CSI2: | |
420 | /* CSI transfers 2 bits per clock per lane; thus times 2 */ | |
421 | pll->pll_op_clk_freq_hz = pll->link_freq * 2 | |
422 | * (pll->csi2.lanes / lane_op_clock_ratio); | |
423 | break; | |
424 | case SMIAPP_PLL_BUS_TYPE_PARALLEL: | |
425 | pll->pll_op_clk_freq_hz = pll->link_freq * pll->bits_per_pixel | |
426 | / DIV_ROUND_UP(pll->bits_per_pixel, | |
427 | pll->parallel.bus_width); | |
428 | break; | |
429 | default: | |
430 | return -EINVAL; | |
431 | } | |
6de1b143 SA |
432 | |
433 | /* Figure out limits for pre-pll divider based on extclk */ | |
c37f9bf9 | 434 | dev_dbg(dev, "min / max pre_pll_clk_div: %u / %u\n", |
6de1b143 | 435 | limits->min_pre_pll_clk_div, limits->max_pre_pll_clk_div); |
8f7e91a3 | 436 | max_pre_pll_clk_div = |
6de1b143 SA |
437 | min_t(uint16_t, limits->max_pre_pll_clk_div, |
438 | clk_div_even(pll->ext_clk_freq_hz / | |
439 | limits->min_pll_ip_freq_hz)); | |
8f7e91a3 | 440 | min_pre_pll_clk_div = |
6de1b143 SA |
441 | max_t(uint16_t, limits->min_pre_pll_clk_div, |
442 | clk_div_even_up( | |
443 | DIV_ROUND_UP(pll->ext_clk_freq_hz, | |
444 | limits->max_pll_ip_freq_hz))); | |
c37f9bf9 | 445 | dev_dbg(dev, "pre-pll check: min / max pre_pll_clk_div: %u / %u\n", |
8f7e91a3 | 446 | min_pre_pll_clk_div, max_pre_pll_clk_div); |
6de1b143 SA |
447 | |
448 | i = gcd(pll->pll_op_clk_freq_hz, pll->ext_clk_freq_hz); | |
449 | mul = div_u64(pll->pll_op_clk_freq_hz, i); | |
450 | div = pll->ext_clk_freq_hz / i; | |
c37f9bf9 | 451 | dev_dbg(dev, "mul %u / div %u\n", mul, div); |
6de1b143 | 452 | |
8f7e91a3 LP |
453 | min_pre_pll_clk_div = |
454 | max_t(uint16_t, min_pre_pll_clk_div, | |
6de1b143 SA |
455 | clk_div_even_up( |
456 | DIV_ROUND_UP(mul * pll->ext_clk_freq_hz, | |
457 | limits->max_pll_op_freq_hz))); | |
c37f9bf9 | 458 | dev_dbg(dev, "pll_op check: min / max pre_pll_clk_div: %u / %u\n", |
8f7e91a3 | 459 | min_pre_pll_clk_div, max_pre_pll_clk_div); |
6de1b143 | 460 | |
8f7e91a3 LP |
461 | for (pll->pre_pll_clk_div = min_pre_pll_clk_div; |
462 | pll->pre_pll_clk_div <= max_pre_pll_clk_div; | |
6de1b143 | 463 | pll->pre_pll_clk_div += 2 - (pll->pre_pll_clk_div & 1)) { |
974abe44 SA |
464 | rval = __smiapp_pll_calculate(dev, limits, op_limits, pll, |
465 | op_pll, mul, div, | |
6de1b143 SA |
466 | lane_op_clock_ratio); |
467 | if (rval) | |
468 | continue; | |
469 | ||
470 | print_pll(dev, pll); | |
471 | return 0; | |
472 | } | |
473 | ||
b08726bf SA |
474 | dev_dbg(dev, "unable to compute pre_pll divisor\n"); |
475 | ||
6de1b143 SA |
476 | return rval; |
477 | } | |
cf1c5fae SA |
478 | EXPORT_SYMBOL_GPL(smiapp_pll_calculate); |
479 | ||
8c5dff90 | 480 | MODULE_AUTHOR("Sakari Ailus <sakari.ailus@iki.fi>"); |
cf1c5fae SA |
481 | MODULE_DESCRIPTION("Generic SMIA/SMIA++ PLL calculator"); |
482 | MODULE_LICENSE("GPL"); |