Commit | Line | Data |
---|---|---|
cf1c5fae | 1 | /* |
cb7a01ac | 2 | * drivers/media/i2c/smiapp-pll.c |
cf1c5fae SA |
3 | * |
4 | * Generic driver for SMIA/SMIA++ compliant camera modules | |
5 | * | |
6 | * Copyright (C) 2011--2012 Nokia Corporation | |
8c5dff90 | 7 | * Contact: Sakari Ailus <sakari.ailus@iki.fi> |
cf1c5fae SA |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * version 2 as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
cf1c5fae SA |
17 | */ |
18 | ||
8c20ee6e | 19 | #include <linux/device.h> |
cf1c5fae SA |
20 | #include <linux/gcd.h> |
21 | #include <linux/lcm.h> | |
22 | #include <linux/module.h> | |
23 | ||
24 | #include "smiapp-pll.h" | |
25 | ||
26 | /* Return an even number or one. */ | |
27 | static inline uint32_t clk_div_even(uint32_t a) | |
28 | { | |
29 | return max_t(uint32_t, 1, a & ~1); | |
30 | } | |
31 | ||
32 | /* Return an even number or one. */ | |
33 | static inline uint32_t clk_div_even_up(uint32_t a) | |
34 | { | |
35 | if (a == 1) | |
36 | return 1; | |
37 | return (a + 1) & ~1; | |
38 | } | |
39 | ||
40 | static inline uint32_t is_one_or_even(uint32_t a) | |
41 | { | |
42 | if (a == 1) | |
43 | return 1; | |
44 | if (a & 1) | |
45 | return 0; | |
46 | ||
47 | return 1; | |
48 | } | |
49 | ||
50 | static int bounds_check(struct device *dev, uint32_t val, | |
51 | uint32_t min, uint32_t max, char *str) | |
52 | { | |
53 | if (val >= min && val <= max) | |
54 | return 0; | |
55 | ||
6de1b143 | 56 | dev_dbg(dev, "%s out of bounds: %d (%d--%d)\n", str, val, min, max); |
cf1c5fae SA |
57 | |
58 | return -EINVAL; | |
59 | } | |
60 | ||
61 | static void print_pll(struct device *dev, struct smiapp_pll *pll) | |
62 | { | |
c37f9bf9 SA |
63 | dev_dbg(dev, "pre_pll_clk_div\t%u\n", pll->pre_pll_clk_div); |
64 | dev_dbg(dev, "pll_multiplier \t%u\n", pll->pll_multiplier); | |
bc47150a | 65 | if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) { |
e3f8bc8c SA |
66 | dev_dbg(dev, "op_sys_clk_div \t%u\n", pll->op.sys_clk_div); |
67 | dev_dbg(dev, "op_pix_clk_div \t%u\n", pll->op.pix_clk_div); | |
cf1c5fae | 68 | } |
e3f8bc8c SA |
69 | dev_dbg(dev, "vt_sys_clk_div \t%u\n", pll->vt.sys_clk_div); |
70 | dev_dbg(dev, "vt_pix_clk_div \t%u\n", pll->vt.pix_clk_div); | |
cf1c5fae | 71 | |
c37f9bf9 SA |
72 | dev_dbg(dev, "ext_clk_freq_hz \t%u\n", pll->ext_clk_freq_hz); |
73 | dev_dbg(dev, "pll_ip_clk_freq_hz \t%u\n", pll->pll_ip_clk_freq_hz); | |
74 | dev_dbg(dev, "pll_op_clk_freq_hz \t%u\n", pll->pll_op_clk_freq_hz); | |
bc47150a | 75 | if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) { |
c37f9bf9 | 76 | dev_dbg(dev, "op_sys_clk_freq_hz \t%u\n", |
e3f8bc8c | 77 | pll->op.sys_clk_freq_hz); |
c37f9bf9 | 78 | dev_dbg(dev, "op_pix_clk_freq_hz \t%u\n", |
e3f8bc8c | 79 | pll->op.pix_clk_freq_hz); |
cf1c5fae | 80 | } |
e3f8bc8c SA |
81 | dev_dbg(dev, "vt_sys_clk_freq_hz \t%u\n", pll->vt.sys_clk_freq_hz); |
82 | dev_dbg(dev, "vt_pix_clk_freq_hz \t%u\n", pll->vt.pix_clk_freq_hz); | |
cf1c5fae SA |
83 | } |
84 | ||
c859470a SA |
85 | static int check_all_bounds(struct device *dev, |
86 | const struct smiapp_pll_limits *limits, | |
974abe44 SA |
87 | const struct smiapp_pll_branch_limits *op_limits, |
88 | struct smiapp_pll *pll, | |
89 | struct smiapp_pll_branch *op_pll) | |
c859470a SA |
90 | { |
91 | int rval; | |
92 | ||
93 | rval = bounds_check(dev, pll->pll_ip_clk_freq_hz, | |
94 | limits->min_pll_ip_freq_hz, | |
95 | limits->max_pll_ip_freq_hz, | |
96 | "pll_ip_clk_freq_hz"); | |
97 | if (!rval) | |
98 | rval = bounds_check( | |
99 | dev, pll->pll_multiplier, | |
100 | limits->min_pll_multiplier, limits->max_pll_multiplier, | |
101 | "pll_multiplier"); | |
102 | if (!rval) | |
103 | rval = bounds_check( | |
104 | dev, pll->pll_op_clk_freq_hz, | |
105 | limits->min_pll_op_freq_hz, limits->max_pll_op_freq_hz, | |
106 | "pll_op_clk_freq_hz"); | |
107 | if (!rval) | |
108 | rval = bounds_check( | |
974abe44 SA |
109 | dev, op_pll->sys_clk_div, |
110 | op_limits->min_sys_clk_div, op_limits->max_sys_clk_div, | |
c859470a | 111 | "op_sys_clk_div"); |
c859470a SA |
112 | if (!rval) |
113 | rval = bounds_check( | |
974abe44 SA |
114 | dev, op_pll->sys_clk_freq_hz, |
115 | op_limits->min_sys_clk_freq_hz, | |
116 | op_limits->max_sys_clk_freq_hz, | |
c859470a SA |
117 | "op_sys_clk_freq_hz"); |
118 | if (!rval) | |
119 | rval = bounds_check( | |
974abe44 SA |
120 | dev, op_pll->pix_clk_freq_hz, |
121 | op_limits->min_pix_clk_freq_hz, | |
122 | op_limits->max_pix_clk_freq_hz, | |
c859470a | 123 | "op_pix_clk_freq_hz"); |
63516b55 SA |
124 | |
125 | /* | |
126 | * If there are no OP clocks, the VT clocks are contained in | |
127 | * the OP clock struct. | |
128 | */ | |
129 | if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) | |
130 | return rval; | |
131 | ||
c859470a SA |
132 | if (!rval) |
133 | rval = bounds_check( | |
e3f8bc8c | 134 | dev, pll->vt.sys_clk_freq_hz, |
c859470a SA |
135 | limits->vt.min_sys_clk_freq_hz, |
136 | limits->vt.max_sys_clk_freq_hz, | |
137 | "vt_sys_clk_freq_hz"); | |
138 | if (!rval) | |
139 | rval = bounds_check( | |
e3f8bc8c | 140 | dev, pll->vt.pix_clk_freq_hz, |
c859470a SA |
141 | limits->vt.min_pix_clk_freq_hz, |
142 | limits->vt.max_pix_clk_freq_hz, | |
143 | "vt_pix_clk_freq_hz"); | |
144 | ||
145 | return rval; | |
146 | } | |
147 | ||
367da7a3 SA |
148 | /* |
149 | * Heuristically guess the PLL tree for a given common multiplier and | |
150 | * divisor. Begin with the operational timing and continue to video | |
151 | * timing once operational timing has been verified. | |
152 | * | |
153 | * @mul is the PLL multiplier and @div is the common divisor | |
154 | * (pre_pll_clk_div and op_sys_clk_div combined). The final PLL | |
155 | * multiplier will be a multiple of @mul. | |
156 | * | |
157 | * @return Zero on success, error code on error. | |
158 | */ | |
974abe44 SA |
159 | static int __smiapp_pll_calculate( |
160 | struct device *dev, const struct smiapp_pll_limits *limits, | |
161 | const struct smiapp_pll_branch_limits *op_limits, | |
162 | struct smiapp_pll *pll, struct smiapp_pll_branch *op_pll, uint32_t mul, | |
163 | uint32_t div, uint32_t lane_op_clock_ratio) | |
cf1c5fae SA |
164 | { |
165 | uint32_t sys_div; | |
166 | uint32_t best_pix_div = INT_MAX >> 1; | |
167 | uint32_t vt_op_binning_div; | |
367da7a3 SA |
168 | /* |
169 | * Higher multipliers (and divisors) are often required than | |
170 | * necessitated by the external clock and the output clocks. | |
171 | * There are limits for all values in the clock tree. These | |
172 | * are the minimum and maximum multiplier for mul. | |
173 | */ | |
cf1c5fae SA |
174 | uint32_t more_mul_min, more_mul_max; |
175 | uint32_t more_mul_factor; | |
176 | uint32_t min_vt_div, max_vt_div, vt_div; | |
177 | uint32_t min_sys_div, max_sys_div; | |
178 | unsigned int i; | |
cf1c5fae | 179 | |
cf1c5fae SA |
180 | /* |
181 | * Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be | |
182 | * too high. | |
183 | */ | |
c37f9bf9 | 184 | dev_dbg(dev, "pre_pll_clk_div %u\n", pll->pre_pll_clk_div); |
cf1c5fae SA |
185 | |
186 | /* Don't go above max pll multiplier. */ | |
187 | more_mul_max = limits->max_pll_multiplier / mul; | |
c37f9bf9 | 188 | dev_dbg(dev, "more_mul_max: max_pll_multiplier check: %u\n", |
cf1c5fae SA |
189 | more_mul_max); |
190 | /* Don't go above max pll op frequency. */ | |
191 | more_mul_max = | |
c2ebca00 | 192 | min_t(uint32_t, |
cf1c5fae SA |
193 | more_mul_max, |
194 | limits->max_pll_op_freq_hz | |
195 | / (pll->ext_clk_freq_hz / pll->pre_pll_clk_div * mul)); | |
c37f9bf9 | 196 | dev_dbg(dev, "more_mul_max: max_pll_op_freq_hz check: %u\n", |
cf1c5fae SA |
197 | more_mul_max); |
198 | /* Don't go above the division capability of op sys clock divider. */ | |
199 | more_mul_max = min(more_mul_max, | |
974abe44 | 200 | op_limits->max_sys_clk_div * pll->pre_pll_clk_div |
cf1c5fae | 201 | / div); |
c37f9bf9 | 202 | dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n", |
cf1c5fae SA |
203 | more_mul_max); |
204 | /* Ensure we won't go above min_pll_multiplier. */ | |
205 | more_mul_max = min(more_mul_max, | |
206 | DIV_ROUND_UP(limits->max_pll_multiplier, mul)); | |
c37f9bf9 | 207 | dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n", |
cf1c5fae SA |
208 | more_mul_max); |
209 | ||
210 | /* Ensure we won't go below min_pll_op_freq_hz. */ | |
211 | more_mul_min = DIV_ROUND_UP(limits->min_pll_op_freq_hz, | |
212 | pll->ext_clk_freq_hz / pll->pre_pll_clk_div | |
213 | * mul); | |
c37f9bf9 | 214 | dev_dbg(dev, "more_mul_min: min_pll_op_freq_hz check: %u\n", |
cf1c5fae SA |
215 | more_mul_min); |
216 | /* Ensure we won't go below min_pll_multiplier. */ | |
217 | more_mul_min = max(more_mul_min, | |
218 | DIV_ROUND_UP(limits->min_pll_multiplier, mul)); | |
c37f9bf9 | 219 | dev_dbg(dev, "more_mul_min: min_pll_multiplier check: %u\n", |
cf1c5fae SA |
220 | more_mul_min); |
221 | ||
222 | if (more_mul_min > more_mul_max) { | |
6de1b143 SA |
223 | dev_dbg(dev, |
224 | "unable to compute more_mul_min and more_mul_max\n"); | |
cf1c5fae SA |
225 | return -EINVAL; |
226 | } | |
227 | ||
228 | more_mul_factor = lcm(div, pll->pre_pll_clk_div) / div; | |
c37f9bf9 | 229 | dev_dbg(dev, "more_mul_factor: %u\n", more_mul_factor); |
974abe44 SA |
230 | more_mul_factor = lcm(more_mul_factor, op_limits->min_sys_clk_div); |
231 | dev_dbg(dev, "more_mul_factor: min_op_sys_clk_div: %d\n", | |
cf1c5fae SA |
232 | more_mul_factor); |
233 | i = roundup(more_mul_min, more_mul_factor); | |
234 | if (!is_one_or_even(i)) | |
235 | i <<= 1; | |
236 | ||
c37f9bf9 | 237 | dev_dbg(dev, "final more_mul: %u\n", i); |
cf1c5fae | 238 | if (i > more_mul_max) { |
c37f9bf9 | 239 | dev_dbg(dev, "final more_mul is bad, max %u\n", more_mul_max); |
cf1c5fae SA |
240 | return -EINVAL; |
241 | } | |
242 | ||
243 | pll->pll_multiplier = mul * i; | |
974abe44 SA |
244 | op_pll->sys_clk_div = div * i / pll->pre_pll_clk_div; |
245 | dev_dbg(dev, "op_sys_clk_div: %u\n", op_pll->sys_clk_div); | |
cf1c5fae SA |
246 | |
247 | pll->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz | |
248 | / pll->pre_pll_clk_div; | |
249 | ||
250 | pll->pll_op_clk_freq_hz = pll->pll_ip_clk_freq_hz | |
251 | * pll->pll_multiplier; | |
252 | ||
253 | /* Derive pll_op_clk_freq_hz. */ | |
974abe44 SA |
254 | op_pll->sys_clk_freq_hz = |
255 | pll->pll_op_clk_freq_hz / op_pll->sys_clk_div; | |
cf1c5fae | 256 | |
974abe44 SA |
257 | op_pll->pix_clk_div = pll->bits_per_pixel; |
258 | dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll->pix_clk_div); | |
cf1c5fae | 259 | |
974abe44 SA |
260 | op_pll->pix_clk_freq_hz = |
261 | op_pll->sys_clk_freq_hz / op_pll->pix_clk_div; | |
262 | ||
263 | if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) { | |
264 | /* No OP clocks --- VT clocks are used instead. */ | |
265 | goto out_skip_vt_calc; | |
266 | } | |
cf1c5fae SA |
267 | |
268 | /* | |
269 | * Some sensors perform analogue binning and some do this | |
270 | * digitally. The ones doing this digitally can be roughly be | |
271 | * found out using this formula. The ones doing this digitally | |
272 | * should run at higher clock rate, so smaller divisor is used | |
273 | * on video timing side. | |
274 | */ | |
275 | if (limits->min_line_length_pck_bin > limits->min_line_length_pck | |
276 | / pll->binning_horizontal) | |
277 | vt_op_binning_div = pll->binning_horizontal; | |
278 | else | |
279 | vt_op_binning_div = 1; | |
c37f9bf9 | 280 | dev_dbg(dev, "vt_op_binning_div: %u\n", vt_op_binning_div); |
cf1c5fae SA |
281 | |
282 | /* | |
283 | * Profile 2 supports vt_pix_clk_div E [4, 10] | |
284 | * | |
285 | * Horizontal binning can be used as a base for difference in | |
286 | * divisors. One must make sure that horizontal blanking is | |
287 | * enough to accommodate the CSI-2 sync codes. | |
288 | * | |
289 | * Take scaling factor into account as well. | |
290 | * | |
291 | * Find absolute limits for the factor of vt divider. | |
292 | */ | |
c37f9bf9 | 293 | dev_dbg(dev, "scale_m: %u\n", pll->scale_m); |
974abe44 | 294 | min_vt_div = DIV_ROUND_UP(op_pll->pix_clk_div * op_pll->sys_clk_div |
cf1c5fae SA |
295 | * pll->scale_n, |
296 | lane_op_clock_ratio * vt_op_binning_div | |
297 | * pll->scale_m); | |
298 | ||
299 | /* Find smallest and biggest allowed vt divisor. */ | |
c37f9bf9 | 300 | dev_dbg(dev, "min_vt_div: %u\n", min_vt_div); |
cf1c5fae SA |
301 | min_vt_div = max(min_vt_div, |
302 | DIV_ROUND_UP(pll->pll_op_clk_freq_hz, | |
6ec84a28 | 303 | limits->vt.max_pix_clk_freq_hz)); |
c37f9bf9 | 304 | dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n", |
cf1c5fae SA |
305 | min_vt_div); |
306 | min_vt_div = max_t(uint32_t, min_vt_div, | |
6ec84a28 LP |
307 | limits->vt.min_pix_clk_div |
308 | * limits->vt.min_sys_clk_div); | |
c37f9bf9 | 309 | dev_dbg(dev, "min_vt_div: min_vt_clk_div: %u\n", min_vt_div); |
cf1c5fae | 310 | |
6ec84a28 | 311 | max_vt_div = limits->vt.max_sys_clk_div * limits->vt.max_pix_clk_div; |
c37f9bf9 | 312 | dev_dbg(dev, "max_vt_div: %u\n", max_vt_div); |
cf1c5fae SA |
313 | max_vt_div = min(max_vt_div, |
314 | DIV_ROUND_UP(pll->pll_op_clk_freq_hz, | |
6ec84a28 | 315 | limits->vt.min_pix_clk_freq_hz)); |
c37f9bf9 | 316 | dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n", |
cf1c5fae SA |
317 | max_vt_div); |
318 | ||
319 | /* | |
320 | * Find limitsits for sys_clk_div. Not all values are possible | |
321 | * with all values of pix_clk_div. | |
322 | */ | |
6ec84a28 | 323 | min_sys_div = limits->vt.min_sys_clk_div; |
c37f9bf9 | 324 | dev_dbg(dev, "min_sys_div: %u\n", min_sys_div); |
cf1c5fae SA |
325 | min_sys_div = max(min_sys_div, |
326 | DIV_ROUND_UP(min_vt_div, | |
6ec84a28 | 327 | limits->vt.max_pix_clk_div)); |
c37f9bf9 | 328 | dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", min_sys_div); |
cf1c5fae SA |
329 | min_sys_div = max(min_sys_div, |
330 | pll->pll_op_clk_freq_hz | |
6ec84a28 | 331 | / limits->vt.max_sys_clk_freq_hz); |
c37f9bf9 | 332 | dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", min_sys_div); |
cf1c5fae | 333 | min_sys_div = clk_div_even_up(min_sys_div); |
c37f9bf9 | 334 | dev_dbg(dev, "min_sys_div: one or even: %u\n", min_sys_div); |
cf1c5fae | 335 | |
6ec84a28 | 336 | max_sys_div = limits->vt.max_sys_clk_div; |
c37f9bf9 | 337 | dev_dbg(dev, "max_sys_div: %u\n", max_sys_div); |
cf1c5fae SA |
338 | max_sys_div = min(max_sys_div, |
339 | DIV_ROUND_UP(max_vt_div, | |
6ec84a28 | 340 | limits->vt.min_pix_clk_div)); |
c37f9bf9 | 341 | dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", max_sys_div); |
cf1c5fae SA |
342 | max_sys_div = min(max_sys_div, |
343 | DIV_ROUND_UP(pll->pll_op_clk_freq_hz, | |
6ec84a28 | 344 | limits->vt.min_pix_clk_freq_hz)); |
c37f9bf9 | 345 | dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", max_sys_div); |
cf1c5fae SA |
346 | |
347 | /* | |
348 | * Find pix_div such that a legal pix_div * sys_div results | |
349 | * into a value which is not smaller than div, the desired | |
350 | * divisor. | |
351 | */ | |
352 | for (vt_div = min_vt_div; vt_div <= max_vt_div; | |
353 | vt_div += 2 - (vt_div & 1)) { | |
354 | for (sys_div = min_sys_div; | |
355 | sys_div <= max_sys_div; | |
356 | sys_div += 2 - (sys_div & 1)) { | |
c2ebca00 | 357 | uint16_t pix_div = DIV_ROUND_UP(vt_div, sys_div); |
cf1c5fae | 358 | |
6ec84a28 LP |
359 | if (pix_div < limits->vt.min_pix_clk_div |
360 | || pix_div > limits->vt.max_pix_clk_div) { | |
cf1c5fae | 361 | dev_dbg(dev, |
c37f9bf9 | 362 | "pix_div %u too small or too big (%u--%u)\n", |
cf1c5fae | 363 | pix_div, |
6ec84a28 LP |
364 | limits->vt.min_pix_clk_div, |
365 | limits->vt.max_pix_clk_div); | |
cf1c5fae SA |
366 | continue; |
367 | } | |
368 | ||
369 | /* Check if this one is better. */ | |
370 | if (pix_div * sys_div | |
371 | <= roundup(min_vt_div, best_pix_div)) | |
372 | best_pix_div = pix_div; | |
373 | } | |
374 | if (best_pix_div < INT_MAX >> 1) | |
375 | break; | |
376 | } | |
377 | ||
e3f8bc8c SA |
378 | pll->vt.sys_clk_div = DIV_ROUND_UP(min_vt_div, best_pix_div); |
379 | pll->vt.pix_clk_div = best_pix_div; | |
cf1c5fae | 380 | |
e3f8bc8c SA |
381 | pll->vt.sys_clk_freq_hz = |
382 | pll->pll_op_clk_freq_hz / pll->vt.sys_clk_div; | |
383 | pll->vt.pix_clk_freq_hz = | |
384 | pll->vt.sys_clk_freq_hz / pll->vt.pix_clk_div; | |
cf1c5fae | 385 | |
974abe44 | 386 | out_skip_vt_calc: |
cf1c5fae | 387 | pll->pixel_rate_csi = |
974abe44 | 388 | op_pll->pix_clk_freq_hz * lane_op_clock_ratio; |
e7c329a0 | 389 | pll->pixel_rate_pixel_array = pll->vt.pix_clk_freq_hz; |
cf1c5fae | 390 | |
974abe44 | 391 | return check_all_bounds(dev, limits, op_limits, pll, op_pll); |
cf1c5fae | 392 | } |
6de1b143 | 393 | |
8f7e91a3 LP |
394 | int smiapp_pll_calculate(struct device *dev, |
395 | const struct smiapp_pll_limits *limits, | |
6de1b143 SA |
396 | struct smiapp_pll *pll) |
397 | { | |
974abe44 SA |
398 | const struct smiapp_pll_branch_limits *op_limits = &limits->op; |
399 | struct smiapp_pll_branch *op_pll = &pll->op; | |
8f7e91a3 LP |
400 | uint16_t min_pre_pll_clk_div; |
401 | uint16_t max_pre_pll_clk_div; | |
6de1b143 SA |
402 | uint32_t lane_op_clock_ratio; |
403 | uint32_t mul, div; | |
404 | unsigned int i; | |
405 | int rval = -EINVAL; | |
406 | ||
974abe44 SA |
407 | if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) { |
408 | /* | |
409 | * If there's no OP PLL at all, use the VT values | |
410 | * instead. The OP values are ignored for the rest of | |
411 | * the PLL calculation. | |
412 | */ | |
413 | op_limits = &limits->vt; | |
414 | op_pll = &pll->vt; | |
415 | } | |
416 | ||
6de1b143 | 417 | if (pll->flags & SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE) |
f5984bbd | 418 | lane_op_clock_ratio = pll->csi2.lanes; |
6de1b143 SA |
419 | else |
420 | lane_op_clock_ratio = 1; | |
c37f9bf9 | 421 | dev_dbg(dev, "lane_op_clock_ratio: %u\n", lane_op_clock_ratio); |
6de1b143 | 422 | |
c37f9bf9 | 423 | dev_dbg(dev, "binning: %ux%u\n", pll->binning_horizontal, |
6de1b143 SA |
424 | pll->binning_vertical); |
425 | ||
f5984bbd SA |
426 | switch (pll->bus_type) { |
427 | case SMIAPP_PLL_BUS_TYPE_CSI2: | |
428 | /* CSI transfers 2 bits per clock per lane; thus times 2 */ | |
429 | pll->pll_op_clk_freq_hz = pll->link_freq * 2 | |
430 | * (pll->csi2.lanes / lane_op_clock_ratio); | |
431 | break; | |
432 | case SMIAPP_PLL_BUS_TYPE_PARALLEL: | |
433 | pll->pll_op_clk_freq_hz = pll->link_freq * pll->bits_per_pixel | |
434 | / DIV_ROUND_UP(pll->bits_per_pixel, | |
435 | pll->parallel.bus_width); | |
436 | break; | |
437 | default: | |
438 | return -EINVAL; | |
439 | } | |
6de1b143 SA |
440 | |
441 | /* Figure out limits for pre-pll divider based on extclk */ | |
c37f9bf9 | 442 | dev_dbg(dev, "min / max pre_pll_clk_div: %u / %u\n", |
6de1b143 | 443 | limits->min_pre_pll_clk_div, limits->max_pre_pll_clk_div); |
8f7e91a3 | 444 | max_pre_pll_clk_div = |
6de1b143 SA |
445 | min_t(uint16_t, limits->max_pre_pll_clk_div, |
446 | clk_div_even(pll->ext_clk_freq_hz / | |
447 | limits->min_pll_ip_freq_hz)); | |
8f7e91a3 | 448 | min_pre_pll_clk_div = |
6de1b143 SA |
449 | max_t(uint16_t, limits->min_pre_pll_clk_div, |
450 | clk_div_even_up( | |
451 | DIV_ROUND_UP(pll->ext_clk_freq_hz, | |
452 | limits->max_pll_ip_freq_hz))); | |
c37f9bf9 | 453 | dev_dbg(dev, "pre-pll check: min / max pre_pll_clk_div: %u / %u\n", |
8f7e91a3 | 454 | min_pre_pll_clk_div, max_pre_pll_clk_div); |
6de1b143 SA |
455 | |
456 | i = gcd(pll->pll_op_clk_freq_hz, pll->ext_clk_freq_hz); | |
457 | mul = div_u64(pll->pll_op_clk_freq_hz, i); | |
458 | div = pll->ext_clk_freq_hz / i; | |
c37f9bf9 | 459 | dev_dbg(dev, "mul %u / div %u\n", mul, div); |
6de1b143 | 460 | |
8f7e91a3 LP |
461 | min_pre_pll_clk_div = |
462 | max_t(uint16_t, min_pre_pll_clk_div, | |
6de1b143 SA |
463 | clk_div_even_up( |
464 | DIV_ROUND_UP(mul * pll->ext_clk_freq_hz, | |
465 | limits->max_pll_op_freq_hz))); | |
c37f9bf9 | 466 | dev_dbg(dev, "pll_op check: min / max pre_pll_clk_div: %u / %u\n", |
8f7e91a3 | 467 | min_pre_pll_clk_div, max_pre_pll_clk_div); |
6de1b143 | 468 | |
8f7e91a3 LP |
469 | for (pll->pre_pll_clk_div = min_pre_pll_clk_div; |
470 | pll->pre_pll_clk_div <= max_pre_pll_clk_div; | |
6de1b143 | 471 | pll->pre_pll_clk_div += 2 - (pll->pre_pll_clk_div & 1)) { |
974abe44 SA |
472 | rval = __smiapp_pll_calculate(dev, limits, op_limits, pll, |
473 | op_pll, mul, div, | |
6de1b143 SA |
474 | lane_op_clock_ratio); |
475 | if (rval) | |
476 | continue; | |
477 | ||
478 | print_pll(dev, pll); | |
479 | return 0; | |
480 | } | |
481 | ||
482 | dev_info(dev, "unable to compute pre_pll divisor\n"); | |
483 | return rval; | |
484 | } | |
cf1c5fae SA |
485 | EXPORT_SYMBOL_GPL(smiapp_pll_calculate); |
486 | ||
8c5dff90 | 487 | MODULE_AUTHOR("Sakari Ailus <sakari.ailus@iki.fi>"); |
cf1c5fae SA |
488 | MODULE_DESCRIPTION("Generic SMIA/SMIA++ PLL calculator"); |
489 | MODULE_LICENSE("GPL"); |