projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
media: ov2640: set default window and format code at probe time
[linux-2.6-block.git] / drivers / media / i2c / ov2640.c
CommitLineData
3153ac9c
AP		 1/*
2 * ov2640 Camera Driver
3 *
4 * Copyright (C) 2010 Alberto Panizzo <maramaopercheseimorto@gmail.com>
5 *
6 * Based on ov772x, ov9640 drivers and previous non merged implementations.
7 *
8 * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
9 * Copyright (C) 2006, OmniVision
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/i2c.h>
46796cfc 19#include <linux/clk.h>
3153ac9c
AP		 20#include <linux/slab.h>
21#include <linux/delay.h>
4e65172f 22#include <linux/gpio.h>
d3633329 23#include <linux/gpio/consumer.h>
4e65172f 24#include <linux/of_gpio.h>
95d20109 25#include <linux/v4l2-mediabus.h>
3153ac9c 26#include <linux/videodev2.h>
d463003b 27
34aa8879 28#include <media/v4l2-device.h>
c6545516 29#include <media/v4l2-event.h>
d463003b 30#include <media/v4l2-subdev.h>
f026671d 31#include <media/v4l2-ctrls.h>
650b1815 32#include <media/v4l2-image-sizes.h>
3153ac9c
AP		 33
34#define VAL_SET(x, mask, rshift, lshift) \
35 ((((x) >> rshift) & mask) << lshift)
36/*
37 * DSP registers
38 * register offset for BANK_SEL == BANK_SEL_DSP
39 */
40#define R_BYPASS 0x05 /* Bypass DSP */
41#define R_BYPASS_DSP_BYPAS 0x01 /* Bypass DSP, sensor out directly */
42#define R_BYPASS_USE_DSP 0x00 /* Use the internal DSP */
43#define QS 0x44 /* Quantization Scale Factor */
44#define CTRLI 0x50
45#define CTRLI_LP_DP 0x80
46#define CTRLI_ROUND 0x40
47#define CTRLI_V_DIV_SET(x) VAL_SET(x, 0x3, 0, 3)
48#define CTRLI_H_DIV_SET(x) VAL_SET(x, 0x3, 0, 0)
49#define HSIZE 0x51 /* H_SIZE[7:0] (real/4) */
50#define HSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0)
51#define VSIZE 0x52 /* V_SIZE[7:0] (real/4) */
52#define VSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0)
53#define XOFFL 0x53 /* OFFSET_X[7:0] */
54#define XOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0)
55#define YOFFL 0x54 /* OFFSET_Y[7:0] */
56#define YOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0)
57#define VHYX 0x55 /* Offset and size completion */
58#define VHYX_VSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 7)
59#define VHYX_HSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 3)
60#define VHYX_YOFF_SET(x) VAL_SET(x, 0x3, 8, 4)
61#define VHYX_XOFF_SET(x) VAL_SET(x, 0x3, 8, 0)
62#define DPRP 0x56
63#define TEST 0x57 /* Horizontal size completion */
64#define TEST_HSIZE_SET(x) VAL_SET(x, 0x1, (9+2), 7)
65#define ZMOW 0x5A /* Zoom: Out Width OUTW[7:0] (real/4) */
66#define ZMOW_OUTW_SET(x) VAL_SET(x, 0xFF, 2, 0)
67#define ZMOH 0x5B /* Zoom: Out Height OUTH[7:0] (real/4) */
68#define ZMOH_OUTH_SET(x) VAL_SET(x, 0xFF, 2, 0)
69#define ZMHH 0x5C /* Zoom: Speed and H&W completion */
70#define ZMHH_ZSPEED_SET(x) VAL_SET(x, 0x0F, 0, 4)
71#define ZMHH_OUTH_SET(x) VAL_SET(x, 0x1, (8+2), 2)
72#define ZMHH_OUTW_SET(x) VAL_SET(x, 0x3, (8+2), 0)
73#define BPADDR 0x7C /* SDE Indirect Register Access: Address */
74#define BPDATA 0x7D /* SDE Indirect Register Access: Data */
75#define CTRL2 0x86 /* DSP Module enable 2 */
76#define CTRL2_DCW_EN 0x20
77#define CTRL2_SDE_EN 0x10
78#define CTRL2_UV_ADJ_EN 0x08
79#define CTRL2_UV_AVG_EN 0x04
80#define CTRL2_CMX_EN 0x01
81#define CTRL3 0x87 /* DSP Module enable 3 */
82#define CTRL3_BPC_EN 0x80
83#define CTRL3_WPC_EN 0x40
84#define SIZEL 0x8C /* Image Size Completion */
85#define SIZEL_HSIZE8_11_SET(x) VAL_SET(x, 0x1, 11, 6)
86#define SIZEL_HSIZE8_SET(x) VAL_SET(x, 0x7, 0, 3)
87#define SIZEL_VSIZE8_SET(x) VAL_SET(x, 0x7, 0, 0)
88#define HSIZE8 0xC0 /* Image Horizontal Size HSIZE[10:3] */
89#define HSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0)
90#define VSIZE8 0xC1 /* Image Vertical Size VSIZE[10:3] */
91#define VSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0)
92#define CTRL0 0xC2 /* DSP Module enable 0 */
93#define CTRL0_AEC_EN 0x80
94#define CTRL0_AEC_SEL 0x40
95#define CTRL0_STAT_SEL 0x20
96#define CTRL0_VFIRST 0x10
97#define CTRL0_YUV422 0x08
98#define CTRL0_YUV_EN 0x04
99#define CTRL0_RGB_EN 0x02
100#define CTRL0_RAW_EN 0x01
101#define CTRL1 0xC3 /* DSP Module enable 1 */
102#define CTRL1_CIP 0x80
103#define CTRL1_DMY 0x40
104#define CTRL1_RAW_GMA 0x20
105#define CTRL1_DG 0x10
106#define CTRL1_AWB 0x08
107#define CTRL1_AWB_GAIN 0x04
108#define CTRL1_LENC 0x02
109#define CTRL1_PRE 0x01
06dd8f77
FS		 110/* REG 0xC7 (unknown name): affects Auto White Balance (AWB)
111 * AWB_OFF 0x40
112 * AWB_SIMPLE 0x10
113 * AWB_ON 0x00 (Advanced AWB ?) */
3153ac9c
AP		 114#define R_DVP_SP 0xD3 /* DVP output speed control */
115#define R_DVP_SP_AUTO_MODE 0x80
116#define R_DVP_SP_DVP_MASK 0x3F /* DVP PCLK = sysclk (48)/[6:0] (YUV0);
117 * = sysclk (48)/(2*[6:0]) (RAW);*/
118#define IMAGE_MODE 0xDA /* Image Output Format Select */
119#define IMAGE_MODE_Y8_DVP_EN 0x40
120#define IMAGE_MODE_JPEG_EN 0x10
121#define IMAGE_MODE_YUV422 0x00
122#define IMAGE_MODE_RAW10 0x04 /* (DVP) */
123#define IMAGE_MODE_RGB565 0x08
124#define IMAGE_MODE_HREF_VSYNC 0x02 /* HREF timing select in DVP JPEG output
125 * mode (0 for HREF is same as sensor) */
126#define IMAGE_MODE_LBYTE_FIRST 0x01 /* Byte swap enable for DVP
127 * 1: Low byte first UYVY (C2[4] =0)
128 * VYUY (C2[4] =1)
129 * 0: High byte first YUYV (C2[4]=0)
130 * YVYU (C2[4] = 1) */
131#define RESET 0xE0 /* Reset */
132#define RESET_MICROC 0x40
133#define RESET_SCCB 0x20
134#define RESET_JPEG 0x10
135#define RESET_DVP 0x04
136#define RESET_IPU 0x02
137#define RESET_CIF 0x01
138#define REGED 0xED /* Register ED */
139#define REGED_CLK_OUT_DIS 0x10
140#define MS_SP 0xF0 /* SCCB Master Speed */
141#define SS_ID 0xF7 /* SCCB Slave ID */
142#define SS_CTRL 0xF8 /* SCCB Slave Control */
143#define SS_CTRL_ADD_AUTO_INC 0x20
144#define SS_CTRL_EN 0x08
145#define SS_CTRL_DELAY_CLK 0x04
146#define SS_CTRL_ACC_EN 0x02
147#define SS_CTRL_SEN_PASS_THR 0x01
148#define MC_BIST 0xF9 /* Microcontroller misc register */
149#define MC_BIST_RESET 0x80 /* Microcontroller Reset */
150#define MC_BIST_BOOT_ROM_SEL 0x40
151#define MC_BIST_12KB_SEL 0x20
152#define MC_BIST_12KB_MASK 0x30
153#define MC_BIST_512KB_SEL 0x08
154#define MC_BIST_512KB_MASK 0x0C
155#define MC_BIST_BUSY_BIT_R 0x02
156#define MC_BIST_MC_RES_ONE_SH_W 0x02
157#define MC_BIST_LAUNCH 0x01
158#define BANK_SEL 0xFF /* Register Bank Select */
159#define BANK_SEL_DSP 0x00
160#define BANK_SEL_SENS 0x01
161
162/*
163 * Sensor registers
164 * register offset for BANK_SEL == BANK_SEL_SENS
165 */
166#define GAIN 0x00 /* AGC - Gain control gain setting */
167#define COM1 0x03 /* Common control 1 */
168#define COM1_1_DUMMY_FR 0x40
169#define COM1_3_DUMMY_FR 0x80
170#define COM1_7_DUMMY_FR 0xC0
171#define COM1_VWIN_LSB_UXGA 0x0F
172#define COM1_VWIN_LSB_SVGA 0x0A
173#define COM1_VWIN_LSB_CIF 0x06
174#define REG04 0x04 /* Register 04 */
175#define REG04_DEF 0x20 /* Always set */
176#define REG04_HFLIP_IMG 0x80 /* Horizontal mirror image ON/OFF */
177#define REG04_VFLIP_IMG 0x40 /* Vertical flip image ON/OFF */
178#define REG04_VREF_EN 0x10
179#define REG04_HREF_EN 0x08
180#define REG04_AEC_SET(x) VAL_SET(x, 0x3, 0, 0)
181#define REG08 0x08 /* Frame Exposure One-pin Control Pre-charge Row Num */
182#define COM2 0x09 /* Common control 2 */
183#define COM2_SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */
184 /* Output drive capability */
185#define COM2_OCAP_Nx_SET(N) (((N) - 1) & 0x03) /* N = [1x .. 4x] */
186#define PID 0x0A /* Product ID Number MSB */
187#define VER 0x0B /* Product ID Number LSB */
188#define COM3 0x0C /* Common control 3 */
189#define COM3_BAND_50H 0x04 /* 0 For Banding at 60H */
190#define COM3_BAND_AUTO 0x02 /* Auto Banding */
191#define COM3_SING_FR_SNAPSH 0x01 /* 0 For enable live video output after the
192 * snapshot sequence*/
193#define AEC 0x10 /* AEC[9:2] Exposure Value */
194#define CLKRC 0x11 /* Internal clock */
195#define CLKRC_EN 0x80
196#define CLKRC_DIV_SET(x) (((x) - 1) & 0x1F) /* CLK = XVCLK/(x) */
197#define COM7 0x12 /* Common control 7 */
198#define COM7_SRST 0x80 /* Initiates system reset. All registers are
199 * set to factory default values after which
200 * the chip resumes normal operation */
201#define COM7_RES_UXGA 0x00 /* Resolution selectors for UXGA */
202#define COM7_RES_SVGA 0x40 /* SVGA */
203#define COM7_RES_CIF 0x20 /* CIF */
204#define COM7_ZOOM_EN 0x04 /* Enable Zoom mode */
205#define COM7_COLOR_BAR_TEST 0x02 /* Enable Color Bar Test Pattern */
206#define COM8 0x13 /* Common control 8 */
534dca98 207#define COM8_DEF 0xC0
3153ac9c
AP		 208#define COM8_BNDF_EN 0x20 /* Banding filter ON/OFF */
209#define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */
210#define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */
211#define COM9 0x14 /* Common control 9
212 * Automatic gain ceiling - maximum AGC value [7:5]*/
213#define COM9_AGC_GAIN_2x 0x00 /* 000 : 2x */
214#define COM9_AGC_GAIN_4x 0x20 /* 001 : 4x */
215#define COM9_AGC_GAIN_8x 0x40 /* 010 : 8x */
216#define COM9_AGC_GAIN_16x 0x60 /* 011 : 16x */
217#define COM9_AGC_GAIN_32x 0x80 /* 100 : 32x */
218#define COM9_AGC_GAIN_64x 0xA0 /* 101 : 64x */
219#define COM9_AGC_GAIN_128x 0xC0 /* 110 : 128x */
220#define COM10 0x15 /* Common control 10 */
221#define COM10_PCLK_HREF 0x20 /* PCLK output qualified by HREF */
222#define COM10_PCLK_RISE 0x10 /* Data is updated at the rising edge of
223 * PCLK (user can latch data at the next
224 * falling edge of PCLK).
225 * 0 otherwise. */
226#define COM10_HREF_INV 0x08 /* Invert HREF polarity:
227 * HREF negative for valid data*/
228#define COM10_VSINC_INV 0x02 /* Invert VSYNC polarity */
229#define HSTART 0x17 /* Horizontal Window start MSB 8 bit */
230#define HEND 0x18 /* Horizontal Window end MSB 8 bit */
231#define VSTART 0x19 /* Vertical Window start MSB 8 bit */
232#define VEND 0x1A /* Vertical Window end MSB 8 bit */
233#define MIDH 0x1C /* Manufacturer ID byte - high */
234#define MIDL 0x1D /* Manufacturer ID byte - low */
235#define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */
236#define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */
237#define VV 0x26 /* AGC/AEC Fast mode operating region */
238#define VV_HIGH_TH_SET(x) VAL_SET(x, 0xF, 0, 4)
239#define VV_LOW_TH_SET(x) VAL_SET(x, 0xF, 0, 0)
240#define REG2A 0x2A /* Dummy pixel insert MSB */
241#define FRARL 0x2B /* Dummy pixel insert LSB */
242#define ADDVFL 0x2D /* LSB of insert dummy lines in Vertical direction */
243#define ADDVFH 0x2E /* MSB of insert dummy lines in Vertical direction */
244#define YAVG 0x2F /* Y/G Channel Average value */
245#define REG32 0x32 /* Common Control 32 */
246#define REG32_PCLK_DIV_2 0x80 /* PCLK freq divided by 2 */
247#define REG32_PCLK_DIV_4 0xC0 /* PCLK freq divided by 4 */
248#define ARCOM2 0x34 /* Zoom: Horizontal start point */
249#define REG45 0x45 /* Register 45 */
250#define FLL 0x46 /* Frame Length Adjustment LSBs */
251#define FLH 0x47 /* Frame Length Adjustment MSBs */
252#define COM19 0x48 /* Zoom: Vertical start point */
253#define ZOOMS 0x49 /* Zoom: Vertical start point */
254#define COM22 0x4B /* Flash light control */
255#define COM25 0x4E /* For Banding operations */
d81638ea
FS		 256#define COM25_50HZ_BANDING_AEC_MSBS_MASK 0xC0 /* 50Hz Bd. AEC 2 MSBs */
257#define COM25_60HZ_BANDING_AEC_MSBS_MASK 0x30 /* 60Hz Bd. AEC 2 MSBs */
258#define COM25_50HZ_BANDING_AEC_MSBS_SET(x) VAL_SET(x, 0x3, 8, 6)
259#define COM25_60HZ_BANDING_AEC_MSBS_SET(x) VAL_SET(x, 0x3, 8, 4)
3153ac9c 260#define BD50 0x4F /* 50Hz Banding AEC 8 LSBs */
d81638ea 261#define BD50_50HZ_BANDING_AEC_LSBS_SET(x) VAL_SET(x, 0xFF, 0, 0)
3153ac9c 262#define BD60 0x50 /* 60Hz Banding AEC 8 LSBs */
d81638ea
FS		 263#define BD60_60HZ_BANDING_AEC_LSBS_SET(x) VAL_SET(x, 0xFF, 0, 0)
264#define REG5A 0x5A /* 50/60Hz Banding Maximum AEC Step */
265#define BD50_MAX_AEC_STEP_MASK 0xF0 /* 50Hz Banding Max. AEC Step */
266#define BD60_MAX_AEC_STEP_MASK 0x0F /* 60Hz Banding Max. AEC Step */
267#define BD50_MAX_AEC_STEP_SET(x) VAL_SET((x - 1), 0x0F, 0, 4)
268#define BD60_MAX_AEC_STEP_SET(x) VAL_SET((x - 1), 0x0F, 0, 0)
3153ac9c
AP		 269#define REG5D 0x5D /* AVGsel[7:0], 16-zone average weight option */
270#define REG5E 0x5E /* AVGsel[15:8], 16-zone average weight option */
271#define REG5F 0x5F /* AVGsel[23:16], 16-zone average weight option */
272#define REG60 0x60 /* AVGsel[31:24], 16-zone average weight option */
273#define HISTO_LOW 0x61 /* Histogram Algorithm Low Level */
274#define HISTO_HIGH 0x62 /* Histogram Algorithm High Level */
275
276/*
277 * ID
278 */
279#define MANUFACTURER_ID 0x7FA2
280#define PID_OV2640 0x2642
281#define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF))
282
283/*
284 * Struct
285 */
286struct regval_list {
287 u8 reg_num;
288 u8 value;
289};
290
3153ac9c
AP		 291struct ov2640_win_size {
292 char *name;
650b1815
JW		 293 u32 width;
294 u32 height;
3153ac9c
AP		 295 const struct regval_list *regs;
296};
297
298
299struct ov2640_priv {
300 struct v4l2_subdev subdev;
ff0e9c1d
HV		 301#if defined(CONFIG_MEDIA_CONTROLLER)
302 struct media_pad pad;
303#endif
f026671d 304 struct v4l2_ctrl_handler hdl;
f5fe58fd 305 u32 cfmt_code;
46796cfc 306 struct clk *clk;
3153ac9c 307 const struct ov2640_win_size *win;
4e65172f 308
4e65172f
JW		 309 struct gpio_desc *resetb_gpio;
310 struct gpio_desc *pwdn_gpio;
2aae3939 311
deb9eec6 312 struct mutex lock; /* lock to protect streaming and power_count */
2aae3939 313 bool streaming;
deb9eec6 314 int power_count;
3153ac9c
AP		 315};
316
317/*
318 * Registers settings
319 */
320
321#define ENDMARKER { 0xff, 0xff }
322
323static const struct regval_list ov2640_init_regs[] = {
324 { BANK_SEL, BANK_SEL_DSP },
325 { 0x2c, 0xff },
326 { 0x2e, 0xdf },
327 { BANK_SEL, BANK_SEL_SENS },
328 { 0x3c, 0x32 },
534dca98
FS		 329 { CLKRC, CLKRC_DIV_SET(1) },
330 { COM2, COM2_OCAP_Nx_SET(3) },
331 { REG04, REG04_DEF | REG04_HREF_EN },
332 { COM8, COM8_DEF | COM8_BNDF_EN | COM8_AGC_EN | COM8_AEC_EN },
333 { COM9, COM9_AGC_GAIN_8x | 0x08},
3153ac9c
AP		 334 { 0x2c, 0x0c },
335 { 0x33, 0x78 },
336 { 0x3a, 0x33 },
337 { 0x3b, 0xfb },
338 { 0x3e, 0x00 },
339 { 0x43, 0x11 },
340 { 0x16, 0x10 },
341 { 0x39, 0x02 },
342 { 0x35, 0x88 },
343 { 0x22, 0x0a },
344 { 0x37, 0x40 },
345 { 0x23, 0x00 },
346 { ARCOM2, 0xa0 },
347 { 0x06, 0x02 },
348 { 0x06, 0x88 },
349 { 0x07, 0xc0 },
350 { 0x0d, 0xb7 },
351 { 0x0e, 0x01 },
352 { 0x4c, 0x00 },
353 { 0x4a, 0x81 },
354 { 0x21, 0x99 },
355 { AEW, 0x40 },
356 { AEB, 0x38 },
357 { VV, VV_HIGH_TH_SET(0x08) | VV_LOW_TH_SET(0x02) },
358 { 0x5c, 0x00 },
359 { 0x63, 0x00 },
360 { FLL, 0x22 },
361 { COM3, 0x38 | COM3_BAND_AUTO },
362 { REG5D, 0x55 },
363 { REG5E, 0x7d },
364 { REG5F, 0x7d },
365 { REG60, 0x55 },
366 { HISTO_LOW, 0x70 },
367 { HISTO_HIGH, 0x80 },
368 { 0x7c, 0x05 },
369 { 0x20, 0x80 },
370 { 0x28, 0x30 },
371 { 0x6c, 0x00 },
372 { 0x6d, 0x80 },
373 { 0x6e, 0x00 },
374 { 0x70, 0x02 },
375 { 0x71, 0x94 },
376 { 0x73, 0xc1 },
377 { 0x3d, 0x34 },
534dca98 378 { COM7, COM7_RES_UXGA | COM7_ZOOM_EN },
d81638ea
FS		 379 { REG5A, BD50_MAX_AEC_STEP_SET(6)
380 | BD60_MAX_AEC_STEP_SET(8) }, /* 0x57 */
381 { COM25, COM25_50HZ_BANDING_AEC_MSBS_SET(0x0bb)
382 | COM25_60HZ_BANDING_AEC_MSBS_SET(0x09c) }, /* 0x00 */
383 { BD50, BD50_50HZ_BANDING_AEC_LSBS_SET(0x0bb) }, /* 0xbb */
384 { BD60, BD60_60HZ_BANDING_AEC_LSBS_SET(0x09c) }, /* 0x9c */
534dca98 385 { BANK_SEL, BANK_SEL_DSP },
3153ac9c 386 { 0xe5, 0x7f },
534dca98 387 { MC_BIST, MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL },
3153ac9c 388 { 0x41, 0x24 },
534dca98 389 { RESET, RESET_JPEG | RESET_DVP },
3153ac9c
AP		 390 { 0x76, 0xff },
391 { 0x33, 0xa0 },
392 { 0x42, 0x20 },
393 { 0x43, 0x18 },
394 { 0x4c, 0x00 },
534dca98 395 { CTRL3, CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 },
3153ac9c
AP		 396 { 0x88, 0x3f },
397 { 0xd7, 0x03 },
398 { 0xd9, 0x10 },
534dca98 399 { R_DVP_SP, R_DVP_SP_AUTO_MODE | 0x2 },
3153ac9c
AP		 400 { 0xc8, 0x08 },
401 { 0xc9, 0x80 },
402 { BPADDR, 0x00 },
403 { BPDATA, 0x00 },
404 { BPADDR, 0x03 },
405 { BPDATA, 0x48 },
406 { BPDATA, 0x48 },
407 { BPADDR, 0x08 },
408 { BPDATA, 0x20 },
409 { BPDATA, 0x10 },
410 { BPDATA, 0x0e },
411 { 0x90, 0x00 },
412 { 0x91, 0x0e },
413 { 0x91, 0x1a },
414 { 0x91, 0x31 },
415 { 0x91, 0x5a },
416 { 0x91, 0x69 },
417 { 0x91, 0x75 },
418 { 0x91, 0x7e },
419 { 0x91, 0x88 },
420 { 0x91, 0x8f },
421 { 0x91, 0x96 },
422 { 0x91, 0xa3 },
423 { 0x91, 0xaf },
424 { 0x91, 0xc4 },
425 { 0x91, 0xd7 },
426 { 0x91, 0xe8 },
427 { 0x91, 0x20 },
428 { 0x92, 0x00 },
429 { 0x93, 0x06 },
430 { 0x93, 0xe3 },
431 { 0x93, 0x03 },
432 { 0x93, 0x03 },
433 { 0x93, 0x00 },
434 { 0x93, 0x02 },
435 { 0x93, 0x00 },
436 { 0x93, 0x00 },
437 { 0x93, 0x00 },
438 { 0x93, 0x00 },
439 { 0x93, 0x00 },
440 { 0x93, 0x00 },
441 { 0x93, 0x00 },
442 { 0x96, 0x00 },
443 { 0x97, 0x08 },
444 { 0x97, 0x19 },
445 { 0x97, 0x02 },
446 { 0x97, 0x0c },
447 { 0x97, 0x24 },
448 { 0x97, 0x30 },
449 { 0x97, 0x28 },
450 { 0x97, 0x26 },
451 { 0x97, 0x02 },
452 { 0x97, 0x98 },
453 { 0x97, 0x80 },
454 { 0x97, 0x00 },
455 { 0x97, 0x00 },
456 { 0xa4, 0x00 },
457 { 0xa8, 0x00 },
458 { 0xc5, 0x11 },
459 { 0xc6, 0x51 },
460 { 0xbf, 0x80 },
06dd8f77 461 { 0xc7, 0x10 }, /* simple AWB */
3153ac9c
AP		 462 { 0xb6, 0x66 },
463 { 0xb8, 0xA5 },
464 { 0xb7, 0x64 },
465 { 0xb9, 0x7C },
466 { 0xb3, 0xaf },
467 { 0xb4, 0x97 },
468 { 0xb5, 0xFF },
469 { 0xb0, 0xC5 },
470 { 0xb1, 0x94 },
471 { 0xb2, 0x0f },
472 { 0xc4, 0x5c },
473 { 0xa6, 0x00 },
474 { 0xa7, 0x20 },
475 { 0xa7, 0xd8 },
476 { 0xa7, 0x1b },
477 { 0xa7, 0x31 },
478 { 0xa7, 0x00 },
479 { 0xa7, 0x18 },
480 { 0xa7, 0x20 },
481 { 0xa7, 0xd8 },
482 { 0xa7, 0x19 },
483 { 0xa7, 0x31 },
484 { 0xa7, 0x00 },
485 { 0xa7, 0x18 },
486 { 0xa7, 0x20 },
487 { 0xa7, 0xd8 },
488 { 0xa7, 0x19 },
489 { 0xa7, 0x31 },
490 { 0xa7, 0x00 },
491 { 0xa7, 0x18 },
492 { 0x7f, 0x00 },
493 { 0xe5, 0x1f },
494 { 0xe1, 0x77 },
495 { 0xdd, 0x7f },
496 { CTRL0, CTRL0_YUV422 | CTRL0_YUV_EN | CTRL0_RGB_EN },
497 ENDMARKER,
498};
499
500/*
501 * Register settings for window size
502 * The preamble, setup the internal DSP to input an UXGA (1600x1200) image.
503 * Then the different zooming configurations will setup the output image size.
504 */
505static const struct regval_list ov2640_size_change_preamble_regs[] = {
506 { BANK_SEL, BANK_SEL_DSP },
507 { RESET, RESET_DVP },
2f7711b2
FS		 508 { SIZEL, SIZEL_HSIZE8_11_SET(UXGA_WIDTH) |
509 SIZEL_HSIZE8_SET(UXGA_WIDTH) |
510 SIZEL_VSIZE8_SET(UXGA_HEIGHT) },
650b1815
JW		 511 { HSIZE8, HSIZE8_SET(UXGA_WIDTH) },
512 { VSIZE8, VSIZE8_SET(UXGA_HEIGHT) },
3153ac9c
AP		 513 { CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN |
514 CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN },
650b1815
JW		 515 { HSIZE, HSIZE_SET(UXGA_WIDTH) },
516 { VSIZE, VSIZE_SET(UXGA_HEIGHT) },
3153ac9c
AP		 517 { XOFFL, XOFFL_SET(0) },
518 { YOFFL, YOFFL_SET(0) },
650b1815 519 { VHYX, VHYX_HSIZE_SET(UXGA_WIDTH) | VHYX_VSIZE_SET(UXGA_HEIGHT) |
3153ac9c 520 VHYX_XOFF_SET(0) | VHYX_YOFF_SET(0)},
650b1815 521 { TEST, TEST_HSIZE_SET(UXGA_WIDTH) },
3153ac9c
AP		 522 ENDMARKER,
523};
524
525#define PER_SIZE_REG_SEQ(x, y, v_div, h_div, pclk_div) \
526 { CTRLI, CTRLI_LP_DP | CTRLI_V_DIV_SET(v_div) | \
527 CTRLI_H_DIV_SET(h_div)}, \
528 { ZMOW, ZMOW_OUTW_SET(x) }, \
529 { ZMOH, ZMOH_OUTH_SET(y) }, \
530 { ZMHH, ZMHH_OUTW_SET(x) | ZMHH_OUTH_SET(y) }, \
531 { R_DVP_SP, pclk_div }, \
532 { RESET, 0x00}
533
534static const struct regval_list ov2640_qcif_regs[] = {
650b1815 535 PER_SIZE_REG_SEQ(QCIF_WIDTH, QCIF_HEIGHT, 3, 3, 4),
3153ac9c
AP		 536 ENDMARKER,
537};
538
539static const struct regval_list ov2640_qvga_regs[] = {
650b1815 540 PER_SIZE_REG_SEQ(QVGA_WIDTH, QVGA_HEIGHT, 2, 2, 4),
3153ac9c
AP		 541 ENDMARKER,
542};
543
544static const struct regval_list ov2640_cif_regs[] = {
650b1815 545 PER_SIZE_REG_SEQ(CIF_WIDTH, CIF_HEIGHT, 2, 2, 8),
3153ac9c
AP		 546 ENDMARKER,
547};
548
549static const struct regval_list ov2640_vga_regs[] = {
650b1815 550 PER_SIZE_REG_SEQ(VGA_WIDTH, VGA_HEIGHT, 0, 0, 2),
3153ac9c
AP		 551 ENDMARKER,
552};
553
554static const struct regval_list ov2640_svga_regs[] = {
650b1815 555 PER_SIZE_REG_SEQ(SVGA_WIDTH, SVGA_HEIGHT, 1, 1, 2),
3153ac9c
AP		 556 ENDMARKER,
557};
558
559static const struct regval_list ov2640_xga_regs[] = {
650b1815 560 PER_SIZE_REG_SEQ(XGA_WIDTH, XGA_HEIGHT, 0, 0, 2),
3153ac9c
AP		 561 { CTRLI, 0x00},
562 ENDMARKER,
563};
564
565static const struct regval_list ov2640_sxga_regs[] = {
650b1815 566 PER_SIZE_REG_SEQ(SXGA_WIDTH, SXGA_HEIGHT, 0, 0, 2),
3153ac9c
AP		 567 { CTRLI, 0x00},
568 { R_DVP_SP, 2 | R_DVP_SP_AUTO_MODE },
569 ENDMARKER,
570};
571
572static const struct regval_list ov2640_uxga_regs[] = {
650b1815 573 PER_SIZE_REG_SEQ(UXGA_WIDTH, UXGA_HEIGHT, 0, 0, 0),
3153ac9c
AP		 574 { CTRLI, 0x00},
575 { R_DVP_SP, 0 | R_DVP_SP_AUTO_MODE },
576 ENDMARKER,
577};
578
579#define OV2640_SIZE(n, w, h, r) \
580 {.name = n, .width = w , .height = h, .regs = r }
581
582static const struct ov2640_win_size ov2640_supported_win_sizes[] = {
650b1815
JW		 583 OV2640_SIZE("QCIF", QCIF_WIDTH, QCIF_HEIGHT, ov2640_qcif_regs),
584 OV2640_SIZE("QVGA", QVGA_WIDTH, QVGA_HEIGHT, ov2640_qvga_regs),
585 OV2640_SIZE("CIF", CIF_WIDTH, CIF_HEIGHT, ov2640_cif_regs),
586 OV2640_SIZE("VGA", VGA_WIDTH, VGA_HEIGHT, ov2640_vga_regs),
587 OV2640_SIZE("SVGA", SVGA_WIDTH, SVGA_HEIGHT, ov2640_svga_regs),
588 OV2640_SIZE("XGA", XGA_WIDTH, XGA_HEIGHT, ov2640_xga_regs),
589 OV2640_SIZE("SXGA", SXGA_WIDTH, SXGA_HEIGHT, ov2640_sxga_regs),
590 OV2640_SIZE("UXGA", UXGA_WIDTH, UXGA_HEIGHT, ov2640_uxga_regs),
3153ac9c
AP		 591};
592
593/*
594 * Register settings for pixel formats
595 */
596static const struct regval_list ov2640_format_change_preamble_regs[] = {
597 { BANK_SEL, BANK_SEL_DSP },
598 { R_BYPASS, R_BYPASS_USE_DSP },
599 ENDMARKER,
600};
601
d1a49eac
FS		 602static const struct regval_list ov2640_yuyv_regs[] = {
603 { IMAGE_MODE, IMAGE_MODE_YUV422 },
604 { 0xd7, 0x03 },
605 { 0x33, 0xa0 },
606 { 0xe5, 0x1f },
607 { 0xe1, 0x67 },
608 { RESET, 0x00 },
609 { R_BYPASS, R_BYPASS_USE_DSP },
610 ENDMARKER,
611};
612
613static const struct regval_list ov2640_uyvy_regs[] = {
3153ac9c 614 { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_YUV422 },
d1a49eac 615 { 0xd7, 0x01 },
3153ac9c
AP		 616 { 0x33, 0xa0 },
617 { 0xe1, 0x67 },
618 { RESET, 0x00 },
619 { R_BYPASS, R_BYPASS_USE_DSP },
620 ENDMARKER,
621};
622
d1a49eac
FS		 623static const struct regval_list ov2640_rgb565_be_regs[] = {
624 { IMAGE_MODE, IMAGE_MODE_RGB565 },
625 { 0xd7, 0x03 },
626 { RESET, 0x00 },
627 { R_BYPASS, R_BYPASS_USE_DSP },
628 ENDMARKER,
629};
630
631static const struct regval_list ov2640_rgb565_le_regs[] = {
3153ac9c
AP		 632 { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_RGB565 },
633 { 0xd7, 0x03 },
634 { RESET, 0x00 },
635 { R_BYPASS, R_BYPASS_USE_DSP },
636 ENDMARKER,
637};
638
f5fe58fd
BB		 639static u32 ov2640_codes[] = {
640 MEDIA_BUS_FMT_YUYV8_2X8,
641 MEDIA_BUS_FMT_UYVY8_2X8,
d72b196f
FS		 642 MEDIA_BUS_FMT_YVYU8_2X8,
643 MEDIA_BUS_FMT_VYUY8_2X8,
f5fe58fd
BB		 644 MEDIA_BUS_FMT_RGB565_2X8_BE,
645 MEDIA_BUS_FMT_RGB565_2X8_LE,
3153ac9c
AP		 646};
647
3153ac9c
AP		 648/*
649 * General functions
650 */
651static struct ov2640_priv *to_ov2640(const struct i2c_client *client)
652{
653 return container_of(i2c_get_clientdata(client), struct ov2640_priv,
654 subdev);
655}
656
657static int ov2640_write_array(struct i2c_client *client,
658 const struct regval_list *vals)
659{
660 int ret;
661
662 while ((vals->reg_num != 0xff) || (vals->value != 0xff)) {
663 ret = i2c_smbus_write_byte_data(client,
664 vals->reg_num, vals->value);
665 dev_vdbg(&client->dev, "array: 0x%02x, 0x%02x",
666 vals->reg_num, vals->value);
667
668 if (ret < 0)
669 return ret;
670 vals++;
671 }
672 return 0;
673}
674
675static int ov2640_mask_set(struct i2c_client *client,
676 u8 reg, u8 mask, u8 set)
677{
678 s32 val = i2c_smbus_read_byte_data(client, reg);
679 if (val < 0)
680 return val;
681
682 val &= ~mask;
683 val |= set & mask;
684
685 dev_vdbg(&client->dev, "masks: 0x%02x, 0x%02x", reg, val);
686
687 return i2c_smbus_write_byte_data(client, reg, val);
688}
689
690static int ov2640_reset(struct i2c_client *client)
691{
692 int ret;
91c158dd 693 static const struct regval_list reset_seq[] = {
3153ac9c
AP		 694 {BANK_SEL, BANK_SEL_SENS},
695 {COM7, COM7_SRST},
696 ENDMARKER,
697 };
698
699 ret = ov2640_write_array(client, reset_seq);
700 if (ret)
701 goto err;
702
703 msleep(5);
704err:
705 dev_dbg(&client->dev, "%s: (ret %d)", __func__, ret);
706 return ret;
707}
708
62105006
AM		 709static const char * const ov2640_test_pattern_menu[] = {
710 "Disabled",
711 "Eight Vertical Colour Bars",
712};
713
3153ac9c 714/*
34aa8879 715 * functions
3153ac9c 716 */
f026671d 717static int ov2640_s_ctrl(struct v4l2_ctrl *ctrl)
3153ac9c 718{
f026671d
HV		 719 struct v4l2_subdev *sd =
720 &container_of(ctrl->handler, struct ov2640_priv, hdl)->subdev;
3153ac9c 721 struct i2c_client *client = v4l2_get_subdevdata(sd);
deb9eec6 722 struct ov2640_priv *priv = to_ov2640(client);
3153ac9c 723 u8 val;
a52eb6c0
FS		 724 int ret;
725
deb9eec6
AM		 726 /* v4l2_ctrl_lock() locks our own mutex */
727
728 /*
729 * If the device is not powered up by the host driver, do not apply any
730 * controls to H/W at this time. Instead the controls will be restored
731 * when the streaming is started.
732 */
733 if (!priv->power_count)
734 return 0;
735
a52eb6c0
FS		 736 ret = i2c_smbus_write_byte_data(client, BANK_SEL, BANK_SEL_SENS);
737 if (ret < 0)
738 return ret;
3153ac9c
AP		 739
740 switch (ctrl->id) {
741 case V4L2_CID_VFLIP:
7f140fc2
FS		 742 val = ctrl->val ? REG04_VFLIP_IMG | REG04_VREF_EN : 0x00;
743 return ov2640_mask_set(client, REG04,
744 REG04_VFLIP_IMG | REG04_VREF_EN, val);
745 /* NOTE: REG04_VREF_EN: 1 line shift / even/odd line swap */
3153ac9c 746 case V4L2_CID_HFLIP:
f026671d
HV		 747 val = ctrl->val ? REG04_HFLIP_IMG : 0x00;
748 return ov2640_mask_set(client, REG04, REG04_HFLIP_IMG, val);
62105006
AM		 749 case V4L2_CID_TEST_PATTERN:
750 val = ctrl->val ? COM7_COLOR_BAR_TEST : 0x00;
751 return ov2640_mask_set(client, COM7, COM7_COLOR_BAR_TEST, val);
3153ac9c
AP		 752 }
753
f026671d 754 return -EINVAL;
3153ac9c
AP		 755}
756
3153ac9c
AP		 757#ifdef CONFIG_VIDEO_ADV_DEBUG
758static int ov2640_g_register(struct v4l2_subdev *sd,
759 struct v4l2_dbg_register *reg)
760{
761 struct i2c_client *client = v4l2_get_subdevdata(sd);
762 int ret;
763
764 reg->size = 1;
765 if (reg->reg > 0xff)
766 return -EINVAL;
767
768 ret = i2c_smbus_read_byte_data(client, reg->reg);
769 if (ret < 0)
770 return ret;
771
772 reg->val = ret;
773
774 return 0;
775}
776
777static int ov2640_s_register(struct v4l2_subdev *sd,
977ba3b1 778 const struct v4l2_dbg_register *reg)
3153ac9c
AP		 779{
780 struct i2c_client *client = v4l2_get_subdevdata(sd);
781
782 if (reg->reg > 0xff ||
783 reg->val > 0xff)
784 return -EINVAL;
785
786 return i2c_smbus_write_byte_data(client, reg->reg, reg->val);
787}
788#endif
789
deb9eec6 790static void ov2640_set_power(struct ov2640_priv *priv, int on)
4ec10bac 791{
3622d3e7 792#ifdef CONFIG_GPIOLIB
a463ea99
MCC		 793 if (priv->pwdn_gpio)
794 gpiod_direction_output(priv->pwdn_gpio, !on);
34aa8879
HV		 795 if (on && priv->resetb_gpio) {
796 /* Active the resetb pin to perform a reset pulse */
797 gpiod_direction_output(priv->resetb_gpio, 1);
798 usleep_range(3000, 5000);
3622d3e7 799 gpiod_set_value(priv->resetb_gpio, 0);
34aa8879 800 }
a463ea99 801#endif
deb9eec6
AM		 802}
803
804static int ov2640_s_power(struct v4l2_subdev *sd, int on)
805{
806 struct i2c_client *client = v4l2_get_subdevdata(sd);
807 struct ov2640_priv *priv = to_ov2640(client);
808
809 mutex_lock(&priv->lock);
810
811 /*
812 * If the power count is modified from 0 to != 0 or from != 0 to 0,
813 * update the power state.
814 */
815 if (priv->power_count == !on)
816 ov2640_set_power(priv, on);
817 priv->power_count += on ? 1 : -1;
818 WARN_ON(priv->power_count < 0);
819 mutex_unlock(&priv->lock);
820
34aa8879 821 return 0;
4ec10bac
LP		 822}
823
3153ac9c 824/* Select the nearest higher resolution for capture */
38eeb491 825static const struct ov2640_win_size *ov2640_select_win(u32 width, u32 height)
3153ac9c
AP		 826{
827 int i, default_size = ARRAY_SIZE(ov2640_supported_win_sizes) - 1;
828
829 for (i = 0; i < ARRAY_SIZE(ov2640_supported_win_sizes); i++) {
38eeb491
FS		 830 if (ov2640_supported_win_sizes[i].width >= width &&
831 ov2640_supported_win_sizes[i].height >= height)
3153ac9c 832 return &ov2640_supported_win_sizes[i];
3153ac9c
AP		 833 }
834
3153ac9c
AP		 835 return &ov2640_supported_win_sizes[default_size];
836}
837
aa23c053
HV		 838static int ov2640_set_params(struct i2c_client *client,
839 const struct ov2640_win_size *win, u32 code)
3153ac9c 840{
3153ac9c 841 const struct regval_list *selected_cfmt_regs;
d72b196f 842 u8 val;
3153ac9c
AP		 843 int ret;
844
3153ac9c 845 switch (code) {
f5fe58fd 846 case MEDIA_BUS_FMT_RGB565_2X8_BE:
d1a49eac
FS		 847 dev_dbg(&client->dev, "%s: Selected cfmt RGB565 BE", __func__);
848 selected_cfmt_regs = ov2640_rgb565_be_regs;
849 break;
f5fe58fd 850 case MEDIA_BUS_FMT_RGB565_2X8_LE:
d1a49eac
FS		 851 dev_dbg(&client->dev, "%s: Selected cfmt RGB565 LE", __func__);
852 selected_cfmt_regs = ov2640_rgb565_le_regs;
853 break;
f5fe58fd 854 case MEDIA_BUS_FMT_YUYV8_2X8:
d1a49eac
FS		 855 dev_dbg(&client->dev, "%s: Selected cfmt YUYV (YUV422)", __func__);
856 selected_cfmt_regs = ov2640_yuyv_regs;
3153ac9c 857 break;
f5fe58fd 858 case MEDIA_BUS_FMT_UYVY8_2X8:
9823f003 859 default:
d1a49eac
FS		 860 dev_dbg(&client->dev, "%s: Selected cfmt UYVY", __func__);
861 selected_cfmt_regs = ov2640_uyvy_regs;
9823f003 862 break;
d72b196f
FS		 863 case MEDIA_BUS_FMT_YVYU8_2X8:
864 dev_dbg(&client->dev, "%s: Selected cfmt YVYU", __func__);
865 selected_cfmt_regs = ov2640_yuyv_regs;
866 break;
867 case MEDIA_BUS_FMT_VYUY8_2X8:
868 dev_dbg(&client->dev, "%s: Selected cfmt VYUY", __func__);
869 selected_cfmt_regs = ov2640_uyvy_regs;
870 break;
3153ac9c
AP		 871 }
872
873 /* reset hardware */
874 ov2640_reset(client);
875
876 /* initialize the sensor with default data */
877 dev_dbg(&client->dev, "%s: Init default", __func__);
878 ret = ov2640_write_array(client, ov2640_init_regs);
879 if (ret < 0)
880 goto err;
881
882 /* select preamble */
2aae3939 883 dev_dbg(&client->dev, "%s: Set size to %s", __func__, win->name);
3153ac9c
AP		 884 ret = ov2640_write_array(client, ov2640_size_change_preamble_regs);
885 if (ret < 0)
886 goto err;
887
888 /* set size win */
2aae3939 889 ret = ov2640_write_array(client, win->regs);
3153ac9c
AP		 890 if (ret < 0)
891 goto err;
892
893 /* cfmt preamble */
894 dev_dbg(&client->dev, "%s: Set cfmt", __func__);
895 ret = ov2640_write_array(client, ov2640_format_change_preamble_regs);
896 if (ret < 0)
897 goto err;
898
899 /* set cfmt */
900 ret = ov2640_write_array(client, selected_cfmt_regs);
d72b196f
FS		 901 if (ret < 0)
902 goto err;
903 val = (code == MEDIA_BUS_FMT_YVYU8_2X8)
904 || (code == MEDIA_BUS_FMT_VYUY8_2X8) ? CTRL0_VFIRST : 0x00;
905 ret = ov2640_mask_set(client, CTRL0, CTRL0_VFIRST, val);
3153ac9c
AP		 906 if (ret < 0)
907 goto err;
908
3153ac9c
AP		 909 return 0;
910
911err:
912 dev_err(&client->dev, "%s: Error %d", __func__, ret);
913 ov2640_reset(client);
3153ac9c
AP		 914
915 return ret;
916}
917
da298c6d
HV		 918static int ov2640_get_fmt(struct v4l2_subdev *sd,
919 struct v4l2_subdev_pad_config *cfg,
920 struct v4l2_subdev_format *format)
3153ac9c 921{
da298c6d 922 struct v4l2_mbus_framefmt *mf = &format->format;
3153ac9c
AP		 923 struct i2c_client *client = v4l2_get_subdevdata(sd);
924 struct ov2640_priv *priv = to_ov2640(client);
925
da298c6d
HV		 926 if (format->pad)
927 return -EINVAL;
928
3153ac9c
AP		 929
930 mf->width = priv->win->width;
931 mf->height = priv->win->height;
932 mf->code = priv->cfmt_code;
9823f003 933 mf->colorspace = V4L2_COLORSPACE_SRGB;
3153ac9c
AP		 934 mf->field = V4L2_FIELD_NONE;
935
936 return 0;
937}
938
717fd5b4
HV		 939static int ov2640_set_fmt(struct v4l2_subdev *sd,
940 struct v4l2_subdev_pad_config *cfg,
941 struct v4l2_subdev_format *format)
3153ac9c 942{
717fd5b4 943 struct v4l2_mbus_framefmt *mf = &format->format;
3153ac9c 944 struct i2c_client *client = v4l2_get_subdevdata(sd);
2aae3939 945 struct ov2640_priv *priv = to_ov2640(client);
aa23c053 946 const struct ov2640_win_size *win;
2aae3939 947 int ret = 0;
3153ac9c 948
717fd5b4
HV		 949 if (format->pad)
950 return -EINVAL;
3153ac9c 951
2aae3939
AM		 952 mutex_lock(&priv->lock);
953
aa23c053 954 /* select suitable win */
38eeb491
FS		 955 win = ov2640_select_win(mf->width, mf->height);
956 mf->width = win->width;
957 mf->height = win->height;
3153ac9c
AP		 958
959 mf->field = V4L2_FIELD_NONE;
9823f003 960 mf->colorspace = V4L2_COLORSPACE_SRGB;
3153ac9c
AP		 961
962 switch (mf->code) {
f5fe58fd
BB		 963 case MEDIA_BUS_FMT_RGB565_2X8_BE:
964 case MEDIA_BUS_FMT_RGB565_2X8_LE:
9823f003
HV		 965 case MEDIA_BUS_FMT_YUYV8_2X8:
966 case MEDIA_BUS_FMT_UYVY8_2X8:
d72b196f
FS		 967 case MEDIA_BUS_FMT_YVYU8_2X8:
968 case MEDIA_BUS_FMT_VYUY8_2X8:
3153ac9c
AP		 969 break;
970 default:
f5fe58fd 971 mf->code = MEDIA_BUS_FMT_UYVY8_2X8;
9823f003 972 break;
3153ac9c
AP		 973 }
974
2aae3939
AM		 975 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
976 struct ov2640_priv *priv = to_ov2640(client);
977
978 if (priv->streaming) {
979 ret = -EBUSY;
980 goto out;
981 }
982 /* select win */
983 priv->win = win;
984 /* select format */
985 priv->cfmt_code = mf->code;
986 } else {
987 cfg->try_fmt = *mf;
988 }
989out:
990 mutex_unlock(&priv->lock);
991
992 return ret;
3153ac9c
AP		 993}
994
ebcff5fc
HV		 995static int ov2640_enum_mbus_code(struct v4l2_subdev *sd,
996 struct v4l2_subdev_pad_config *cfg,
997 struct v4l2_subdev_mbus_code_enum *code)
3153ac9c 998{
ebcff5fc 999 if (code->pad || code->index >= ARRAY_SIZE(ov2640_codes))
3153ac9c
AP		 1000 return -EINVAL;
1001
ebcff5fc 1002 code->code = ov2640_codes[code->index];
3153ac9c
AP		 1003 return 0;
1004}
1005
10d5509c
HV		 1006static int ov2640_get_selection(struct v4l2_subdev *sd,
1007 struct v4l2_subdev_pad_config *cfg,
1008 struct v4l2_subdev_selection *sel)
3153ac9c 1009{
10d5509c
HV		 1010 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1011 return -EINVAL;
3153ac9c 1012
10d5509c
HV		 1013 switch (sel->target) {
1014 case V4L2_SEL_TGT_CROP_BOUNDS:
10d5509c
HV		 1015 case V4L2_SEL_TGT_CROP:
1016 sel->r.left = 0;
1017 sel->r.top = 0;
1018 sel->r.width = UXGA_WIDTH;
1019 sel->r.height = UXGA_HEIGHT;
1020 return 0;
1021 default:
1022 return -EINVAL;
1023 }
3153ac9c
AP		 1024}
1025
2aae3939
AM		 1026static int ov2640_s_stream(struct v4l2_subdev *sd, int on)
1027{
1028 struct i2c_client *client = v4l2_get_subdevdata(sd);
1029 struct ov2640_priv *priv = to_ov2640(client);
1030 int ret = 0;
1031
1032 mutex_lock(&priv->lock);
1033 if (priv->streaming == !on) {
1034 if (on) {
1035 ret = ov2640_set_params(client, priv->win,
1036 priv->cfmt_code);
deb9eec6
AM		 1037 if (!ret)
1038 ret = __v4l2_ctrl_handler_setup(&priv->hdl);
2aae3939
AM		 1039 }
1040 }
1041 if (!ret)
1042 priv->streaming = on;
1043 mutex_unlock(&priv->lock);
1044
1045 return ret;
1046}
1047
14178aa5 1048static int ov2640_video_probe(struct i2c_client *client)
3153ac9c
AP		 1049{
1050 struct ov2640_priv *priv = to_ov2640(client);
1051 u8 pid, ver, midh, midl;
1052 const char *devname;
1053 int ret;
1054
4bbc6d52
LP		 1055 ret = ov2640_s_power(&priv->subdev, 1);
1056 if (ret < 0)
1057 return ret;
1058
3153ac9c
AP		 1059 /*
1060 * check and show product ID and manufacturer ID
1061 */
1062 i2c_smbus_write_byte_data(client, BANK_SEL, BANK_SEL_SENS);
1063 pid = i2c_smbus_read_byte_data(client, PID);
1064 ver = i2c_smbus_read_byte_data(client, VER);
1065 midh = i2c_smbus_read_byte_data(client, MIDH);
1066 midl = i2c_smbus_read_byte_data(client, MIDL);
1067
1068 switch (VERSION(pid, ver)) {
1069 case PID_OV2640:
1070 devname = "ov2640";
3153ac9c
AP		 1071 break;
1072 default:
1073 dev_err(&client->dev,
1074 "Product ID error %x:%x\n", pid, ver);
1075 ret = -ENODEV;
4bbc6d52 1076 goto done;
3153ac9c
AP		 1077 }
1078
1079 dev_info(&client->dev,
1080 "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
1081 devname, pid, ver, midh, midl);
1082
4bbc6d52
LP		 1083done:
1084 ov2640_s_power(&priv->subdev, 0);
3153ac9c
AP		 1085 return ret;
1086}
1087
f026671d
HV		 1088static const struct v4l2_ctrl_ops ov2640_ctrl_ops = {
1089 .s_ctrl = ov2640_s_ctrl,
3153ac9c
AP		 1090};
1091
6713c88f 1092static const struct v4l2_subdev_core_ops ov2640_subdev_core_ops = {
c6545516
AM		 1093 .log_status = v4l2_ctrl_subdev_log_status,
1094 .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1095 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
3153ac9c
AP		 1096#ifdef CONFIG_VIDEO_ADV_DEBUG
1097 .g_register = ov2640_g_register,
1098 .s_register = ov2640_s_register,
1099#endif
4ec10bac 1100 .s_power = ov2640_s_power,
3153ac9c
AP		 1101};
1102
ebcff5fc
HV		 1103static const struct v4l2_subdev_pad_ops ov2640_subdev_pad_ops = {
1104 .enum_mbus_code = ov2640_enum_mbus_code,
10d5509c 1105 .get_selection = ov2640_get_selection,
da298c6d 1106 .get_fmt = ov2640_get_fmt,
717fd5b4 1107 .set_fmt = ov2640_set_fmt,
ebcff5fc
HV		 1108};
1109
2aae3939
AM		 1110static const struct v4l2_subdev_video_ops ov2640_subdev_video_ops = {
1111 .s_stream = ov2640_s_stream,
1112};
1113
6713c88f 1114static const struct v4l2_subdev_ops ov2640_subdev_ops = {
3153ac9c 1115 .core = &ov2640_subdev_core_ops,
ebcff5fc 1116 .pad = &ov2640_subdev_pad_ops,
2aae3939 1117 .video = &ov2640_subdev_video_ops,
3153ac9c
AP		 1118};
1119
4e65172f
JW		 1120static int ov2640_probe_dt(struct i2c_client *client,
1121 struct ov2640_priv *priv)
1122{
3622d3e7
MCC		 1123 int ret;
1124
4e65172f
JW		 1125 /* Request the reset GPIO deasserted */
1126 priv->resetb_gpio = devm_gpiod_get_optional(&client->dev, "resetb",
1127 GPIOD_OUT_LOW);
3622d3e7 1128
4e65172f
JW		 1129 if (!priv->resetb_gpio)
1130 dev_dbg(&client->dev, "resetb gpio is not assigned!\n");
3622d3e7
MCC		 1131
1132 ret = PTR_ERR_OR_ZERO(priv->resetb_gpio);
1133 if (ret && ret != -ENOSYS) {
1134 dev_dbg(&client->dev,
1135 "Error %d while getting resetb gpio\n", ret);
1136 return ret;
1137 }
4e65172f
JW		 1138
1139 /* Request the power down GPIO asserted */
1140 priv->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "pwdn",
1141 GPIOD_OUT_HIGH);
3622d3e7 1142
4e65172f
JW		 1143 if (!priv->pwdn_gpio)
1144 dev_dbg(&client->dev, "pwdn gpio is not assigned!\n");
3622d3e7
MCC		 1145
1146 ret = PTR_ERR_OR_ZERO(priv->pwdn_gpio);
1147 if (ret && ret != -ENOSYS) {
1148 dev_dbg(&client->dev,
1149 "Error %d while getting pwdn gpio\n", ret);
1150 return ret;
1151 }
4e65172f 1152
4e65172f
JW		 1153 return 0;
1154}
1155
3153ac9c
AP		 1156/*
1157 * i2c_driver functions
1158 */
1159static int ov2640_probe(struct i2c_client *client,
1160 const struct i2c_device_id *did)
1161{
14178aa5 1162 struct ov2640_priv *priv;
14178aa5
GL		 1163 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
1164 int ret;
3153ac9c 1165
3153ac9c
AP		 1166 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
1167 dev_err(&adapter->dev,
1168 "OV2640: I2C-Adapter doesn't support SMBUS\n");
1169 return -EIO;
1170 }
1171
19fab6fe 1172 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
0fd58435 1173 if (!priv)
3153ac9c 1174 return -ENOMEM;
3153ac9c 1175
46796cfc
HV		 1176 if (client->dev.of_node) {
1177 priv->clk = devm_clk_get(&client->dev, "xvclk");
1178 if (IS_ERR(priv->clk))
877f1af1 1179 return PTR_ERR(priv->clk);
c3d14780
FE		 1180 ret = clk_prepare_enable(priv->clk);
1181 if (ret)
1182 return ret;
4e65172f
JW		 1183 }
1184
34aa8879
HV		 1185 ret = ov2640_probe_dt(client, priv);
1186 if (ret)
1187 goto err_clk;
4e65172f 1188
b0a7d0e1
AM		 1189 priv->win = ov2640_select_win(SVGA_WIDTH, SVGA_HEIGHT);
1190 priv->cfmt_code = MEDIA_BUS_FMT_UYVY8_2X8;
1191
3153ac9c 1192 v4l2_i2c_subdev_init(&priv->subdev, client, &ov2640_subdev_ops);
c6545516
AM		 1193 priv->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1194 V4L2_SUBDEV_FL_HAS_EVENTS;
2aae3939 1195 mutex_init(&priv->lock);
62105006 1196 v4l2_ctrl_handler_init(&priv->hdl, 3);
deb9eec6 1197 priv->hdl.lock = &priv->lock;
f026671d
HV		 1198 v4l2_ctrl_new_std(&priv->hdl, &ov2640_ctrl_ops,
1199 V4L2_CID_VFLIP, 0, 1, 1, 0);
1200 v4l2_ctrl_new_std(&priv->hdl, &ov2640_ctrl_ops,
1201 V4L2_CID_HFLIP, 0, 1, 1, 0);
62105006
AM		 1202 v4l2_ctrl_new_std_menu_items(&priv->hdl, &ov2640_ctrl_ops,
1203 V4L2_CID_TEST_PATTERN,
1204 ARRAY_SIZE(ov2640_test_pattern_menu) - 1, 0, 0,
1205 ov2640_test_pattern_menu);
f026671d 1206 priv->subdev.ctrl_handler = &priv->hdl;
f180ebae
JW		 1207 if (priv->hdl.error) {
1208 ret = priv->hdl.error;
46796cfc 1209 goto err_hdl;
9aea470b 1210 }
ff0e9c1d
HV		 1211#if defined(CONFIG_MEDIA_CONTROLLER)
1212 priv->pad.flags = MEDIA_PAD_FL_SOURCE;
1213 priv->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1214 ret = media_entity_pads_init(&priv->subdev.entity, 1, &priv->pad);
1215 if (ret < 0)
1216 goto err_hdl;
1217#endif
9aea470b 1218
14178aa5 1219 ret = ov2640_video_probe(client);
f180ebae 1220 if (ret < 0)
ff0e9c1d 1221 goto err_videoprobe;
3153ac9c 1222
f180ebae
JW		 1223 ret = v4l2_async_register_subdev(&priv->subdev);
1224 if (ret < 0)
ff0e9c1d 1225 goto err_videoprobe;
f180ebae
JW		 1226
1227 dev_info(&adapter->dev, "OV2640 Probed\n");
1228
1229 return 0;
1230
ff0e9c1d 1231err_videoprobe:
ff0e9c1d 1232 media_entity_cleanup(&priv->subdev.entity);
46796cfc 1233err_hdl:
f180ebae 1234 v4l2_ctrl_handler_free(&priv->hdl);
2aae3939 1235 mutex_destroy(&priv->lock);
f180ebae 1236err_clk:
46796cfc 1237 clk_disable_unprepare(priv->clk);
3153ac9c
AP		 1238 return ret;
1239}
1240
1241static int ov2640_remove(struct i2c_client *client)
1242{
1243 struct ov2640_priv *priv = to_ov2640(client);
3153ac9c 1244
f180ebae 1245 v4l2_async_unregister_subdev(&priv->subdev);
f026671d 1246 v4l2_ctrl_handler_free(&priv->hdl);
2aae3939 1247 mutex_destroy(&priv->lock);
ff0e9c1d 1248 media_entity_cleanup(&priv->subdev.entity);
46796cfc
HV		 1249 v4l2_device_unregister_subdev(&priv->subdev);
1250 clk_disable_unprepare(priv->clk);
3153ac9c
AP		 1251 return 0;
1252}
1253
1254static const struct i2c_device_id ov2640_id[] = {
1255 { "ov2640", 0 },
1256 { }
1257};
1258MODULE_DEVICE_TABLE(i2c, ov2640_id);
1259
4e65172f
JW		 1260static const struct of_device_id ov2640_of_match[] = {
1261 {.compatible = "ovti,ov2640", },
1262 {},
1263};
1264MODULE_DEVICE_TABLE(of, ov2640_of_match);
1265
3153ac9c
AP		 1266static struct i2c_driver ov2640_i2c_driver = {
1267 .driver = {
1268 .name = "ov2640",
4e65172f 1269 .of_match_table = of_match_ptr(ov2640_of_match),
3153ac9c
AP		 1270 },
1271 .probe = ov2640_probe,
1272 .remove = ov2640_remove,
1273 .id_table = ov2640_id,
1274};
1275
c6e8d86f 1276module_i2c_driver(ov2640_i2c_driver);
3153ac9c 1277
34aa8879 1278MODULE_DESCRIPTION("Driver for Omni Vision 2640 sensor");
3153ac9c
AP		 1279MODULE_AUTHOR("Alberto Panizzo");
1280MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)