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[media] xc5000: fix spelling mistake: "calibration"
[linux-2.6-block.git] / drivers / media / i2c / ov2640.c
CommitLineData
3153ac9c
AP		 1/*
2 * ov2640 Camera Driver
3 *
4 * Copyright (C) 2010 Alberto Panizzo <maramaopercheseimorto@gmail.com>
5 *
6 * Based on ov772x, ov9640 drivers and previous non merged implementations.
7 *
8 * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
9 * Copyright (C) 2006, OmniVision
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/i2c.h>
46796cfc 19#include <linux/clk.h>
3153ac9c
AP		 20#include <linux/slab.h>
21#include <linux/delay.h>
4e65172f 22#include <linux/gpio.h>
d3633329 23#include <linux/gpio/consumer.h>
4e65172f 24#include <linux/of_gpio.h>
95d20109 25#include <linux/v4l2-mediabus.h>
3153ac9c 26#include <linux/videodev2.h>
d463003b 27
34aa8879 28#include <media/v4l2-device.h>
d463003b 29#include <media/v4l2-subdev.h>
f026671d 30#include <media/v4l2-ctrls.h>
650b1815 31#include <media/v4l2-image-sizes.h>
3153ac9c
AP		 32
33#define VAL_SET(x, mask, rshift, lshift) \
34 ((((x) >> rshift) & mask) << lshift)
35/*
36 * DSP registers
37 * register offset for BANK_SEL == BANK_SEL_DSP
38 */
39#define R_BYPASS 0x05 /* Bypass DSP */
40#define R_BYPASS_DSP_BYPAS 0x01 /* Bypass DSP, sensor out directly */
41#define R_BYPASS_USE_DSP 0x00 /* Use the internal DSP */
42#define QS 0x44 /* Quantization Scale Factor */
43#define CTRLI 0x50
44#define CTRLI_LP_DP 0x80
45#define CTRLI_ROUND 0x40
46#define CTRLI_V_DIV_SET(x) VAL_SET(x, 0x3, 0, 3)
47#define CTRLI_H_DIV_SET(x) VAL_SET(x, 0x3, 0, 0)
48#define HSIZE 0x51 /* H_SIZE[7:0] (real/4) */
49#define HSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0)
50#define VSIZE 0x52 /* V_SIZE[7:0] (real/4) */
51#define VSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0)
52#define XOFFL 0x53 /* OFFSET_X[7:0] */
53#define XOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0)
54#define YOFFL 0x54 /* OFFSET_Y[7:0] */
55#define YOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0)
56#define VHYX 0x55 /* Offset and size completion */
57#define VHYX_VSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 7)
58#define VHYX_HSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 3)
59#define VHYX_YOFF_SET(x) VAL_SET(x, 0x3, 8, 4)
60#define VHYX_XOFF_SET(x) VAL_SET(x, 0x3, 8, 0)
61#define DPRP 0x56
62#define TEST 0x57 /* Horizontal size completion */
63#define TEST_HSIZE_SET(x) VAL_SET(x, 0x1, (9+2), 7)
64#define ZMOW 0x5A /* Zoom: Out Width OUTW[7:0] (real/4) */
65#define ZMOW_OUTW_SET(x) VAL_SET(x, 0xFF, 2, 0)
66#define ZMOH 0x5B /* Zoom: Out Height OUTH[7:0] (real/4) */
67#define ZMOH_OUTH_SET(x) VAL_SET(x, 0xFF, 2, 0)
68#define ZMHH 0x5C /* Zoom: Speed and H&W completion */
69#define ZMHH_ZSPEED_SET(x) VAL_SET(x, 0x0F, 0, 4)
70#define ZMHH_OUTH_SET(x) VAL_SET(x, 0x1, (8+2), 2)
71#define ZMHH_OUTW_SET(x) VAL_SET(x, 0x3, (8+2), 0)
72#define BPADDR 0x7C /* SDE Indirect Register Access: Address */
73#define BPDATA 0x7D /* SDE Indirect Register Access: Data */
74#define CTRL2 0x86 /* DSP Module enable 2 */
75#define CTRL2_DCW_EN 0x20
76#define CTRL2_SDE_EN 0x10
77#define CTRL2_UV_ADJ_EN 0x08
78#define CTRL2_UV_AVG_EN 0x04
79#define CTRL2_CMX_EN 0x01
80#define CTRL3 0x87 /* DSP Module enable 3 */
81#define CTRL3_BPC_EN 0x80
82#define CTRL3_WPC_EN 0x40
83#define SIZEL 0x8C /* Image Size Completion */
84#define SIZEL_HSIZE8_11_SET(x) VAL_SET(x, 0x1, 11, 6)
85#define SIZEL_HSIZE8_SET(x) VAL_SET(x, 0x7, 0, 3)
86#define SIZEL_VSIZE8_SET(x) VAL_SET(x, 0x7, 0, 0)
87#define HSIZE8 0xC0 /* Image Horizontal Size HSIZE[10:3] */
88#define HSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0)
89#define VSIZE8 0xC1 /* Image Vertical Size VSIZE[10:3] */
90#define VSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0)
91#define CTRL0 0xC2 /* DSP Module enable 0 */
92#define CTRL0_AEC_EN 0x80
93#define CTRL0_AEC_SEL 0x40
94#define CTRL0_STAT_SEL 0x20
95#define CTRL0_VFIRST 0x10
96#define CTRL0_YUV422 0x08
97#define CTRL0_YUV_EN 0x04
98#define CTRL0_RGB_EN 0x02
99#define CTRL0_RAW_EN 0x01
100#define CTRL1 0xC3 /* DSP Module enable 1 */
101#define CTRL1_CIP 0x80
102#define CTRL1_DMY 0x40
103#define CTRL1_RAW_GMA 0x20
104#define CTRL1_DG 0x10
105#define CTRL1_AWB 0x08
106#define CTRL1_AWB_GAIN 0x04
107#define CTRL1_LENC 0x02
108#define CTRL1_PRE 0x01
109#define R_DVP_SP 0xD3 /* DVP output speed control */
110#define R_DVP_SP_AUTO_MODE 0x80
111#define R_DVP_SP_DVP_MASK 0x3F /* DVP PCLK = sysclk (48)/[6:0] (YUV0);
112 * = sysclk (48)/(2*[6:0]) (RAW);*/
113#define IMAGE_MODE 0xDA /* Image Output Format Select */
114#define IMAGE_MODE_Y8_DVP_EN 0x40
115#define IMAGE_MODE_JPEG_EN 0x10
116#define IMAGE_MODE_YUV422 0x00
117#define IMAGE_MODE_RAW10 0x04 /* (DVP) */
118#define IMAGE_MODE_RGB565 0x08
119#define IMAGE_MODE_HREF_VSYNC 0x02 /* HREF timing select in DVP JPEG output
120 * mode (0 for HREF is same as sensor) */
121#define IMAGE_MODE_LBYTE_FIRST 0x01 /* Byte swap enable for DVP
122 * 1: Low byte first UYVY (C2[4] =0)
123 * VYUY (C2[4] =1)
124 * 0: High byte first YUYV (C2[4]=0)
125 * YVYU (C2[4] = 1) */
126#define RESET 0xE0 /* Reset */
127#define RESET_MICROC 0x40
128#define RESET_SCCB 0x20
129#define RESET_JPEG 0x10
130#define RESET_DVP 0x04
131#define RESET_IPU 0x02
132#define RESET_CIF 0x01
133#define REGED 0xED /* Register ED */
134#define REGED_CLK_OUT_DIS 0x10
135#define MS_SP 0xF0 /* SCCB Master Speed */
136#define SS_ID 0xF7 /* SCCB Slave ID */
137#define SS_CTRL 0xF8 /* SCCB Slave Control */
138#define SS_CTRL_ADD_AUTO_INC 0x20
139#define SS_CTRL_EN 0x08
140#define SS_CTRL_DELAY_CLK 0x04
141#define SS_CTRL_ACC_EN 0x02
142#define SS_CTRL_SEN_PASS_THR 0x01
143#define MC_BIST 0xF9 /* Microcontroller misc register */
144#define MC_BIST_RESET 0x80 /* Microcontroller Reset */
145#define MC_BIST_BOOT_ROM_SEL 0x40
146#define MC_BIST_12KB_SEL 0x20
147#define MC_BIST_12KB_MASK 0x30
148#define MC_BIST_512KB_SEL 0x08
149#define MC_BIST_512KB_MASK 0x0C
150#define MC_BIST_BUSY_BIT_R 0x02
151#define MC_BIST_MC_RES_ONE_SH_W 0x02
152#define MC_BIST_LAUNCH 0x01
153#define BANK_SEL 0xFF /* Register Bank Select */
154#define BANK_SEL_DSP 0x00
155#define BANK_SEL_SENS 0x01
156
157/*
158 * Sensor registers
159 * register offset for BANK_SEL == BANK_SEL_SENS
160 */
161#define GAIN 0x00 /* AGC - Gain control gain setting */
162#define COM1 0x03 /* Common control 1 */
163#define COM1_1_DUMMY_FR 0x40
164#define COM1_3_DUMMY_FR 0x80
165#define COM1_7_DUMMY_FR 0xC0
166#define COM1_VWIN_LSB_UXGA 0x0F
167#define COM1_VWIN_LSB_SVGA 0x0A
168#define COM1_VWIN_LSB_CIF 0x06
169#define REG04 0x04 /* Register 04 */
170#define REG04_DEF 0x20 /* Always set */
171#define REG04_HFLIP_IMG 0x80 /* Horizontal mirror image ON/OFF */
172#define REG04_VFLIP_IMG 0x40 /* Vertical flip image ON/OFF */
173#define REG04_VREF_EN 0x10
174#define REG04_HREF_EN 0x08
175#define REG04_AEC_SET(x) VAL_SET(x, 0x3, 0, 0)
176#define REG08 0x08 /* Frame Exposure One-pin Control Pre-charge Row Num */
177#define COM2 0x09 /* Common control 2 */
178#define COM2_SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */
179 /* Output drive capability */
180#define COM2_OCAP_Nx_SET(N) (((N) - 1) & 0x03) /* N = [1x .. 4x] */
181#define PID 0x0A /* Product ID Number MSB */
182#define VER 0x0B /* Product ID Number LSB */
183#define COM3 0x0C /* Common control 3 */
184#define COM3_BAND_50H 0x04 /* 0 For Banding at 60H */
185#define COM3_BAND_AUTO 0x02 /* Auto Banding */
186#define COM3_SING_FR_SNAPSH 0x01 /* 0 For enable live video output after the
187 * snapshot sequence*/
188#define AEC 0x10 /* AEC[9:2] Exposure Value */
189#define CLKRC 0x11 /* Internal clock */
190#define CLKRC_EN 0x80
191#define CLKRC_DIV_SET(x) (((x) - 1) & 0x1F) /* CLK = XVCLK/(x) */
192#define COM7 0x12 /* Common control 7 */
193#define COM7_SRST 0x80 /* Initiates system reset. All registers are
194 * set to factory default values after which
195 * the chip resumes normal operation */
196#define COM7_RES_UXGA 0x00 /* Resolution selectors for UXGA */
197#define COM7_RES_SVGA 0x40 /* SVGA */
198#define COM7_RES_CIF 0x20 /* CIF */
199#define COM7_ZOOM_EN 0x04 /* Enable Zoom mode */
200#define COM7_COLOR_BAR_TEST 0x02 /* Enable Color Bar Test Pattern */
201#define COM8 0x13 /* Common control 8 */
202#define COM8_DEF 0xC0 /* Banding filter ON/OFF */
203#define COM8_BNDF_EN 0x20 /* Banding filter ON/OFF */
204#define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */
205#define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */
206#define COM9 0x14 /* Common control 9
207 * Automatic gain ceiling - maximum AGC value [7:5]*/
208#define COM9_AGC_GAIN_2x 0x00 /* 000 : 2x */
209#define COM9_AGC_GAIN_4x 0x20 /* 001 : 4x */
210#define COM9_AGC_GAIN_8x 0x40 /* 010 : 8x */
211#define COM9_AGC_GAIN_16x 0x60 /* 011 : 16x */
212#define COM9_AGC_GAIN_32x 0x80 /* 100 : 32x */
213#define COM9_AGC_GAIN_64x 0xA0 /* 101 : 64x */
214#define COM9_AGC_GAIN_128x 0xC0 /* 110 : 128x */
215#define COM10 0x15 /* Common control 10 */
216#define COM10_PCLK_HREF 0x20 /* PCLK output qualified by HREF */
217#define COM10_PCLK_RISE 0x10 /* Data is updated at the rising edge of
218 * PCLK (user can latch data at the next
219 * falling edge of PCLK).
220 * 0 otherwise. */
221#define COM10_HREF_INV 0x08 /* Invert HREF polarity:
222 * HREF negative for valid data*/
223#define COM10_VSINC_INV 0x02 /* Invert VSYNC polarity */
224#define HSTART 0x17 /* Horizontal Window start MSB 8 bit */
225#define HEND 0x18 /* Horizontal Window end MSB 8 bit */
226#define VSTART 0x19 /* Vertical Window start MSB 8 bit */
227#define VEND 0x1A /* Vertical Window end MSB 8 bit */
228#define MIDH 0x1C /* Manufacturer ID byte - high */
229#define MIDL 0x1D /* Manufacturer ID byte - low */
230#define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */
231#define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */
232#define VV 0x26 /* AGC/AEC Fast mode operating region */
233#define VV_HIGH_TH_SET(x) VAL_SET(x, 0xF, 0, 4)
234#define VV_LOW_TH_SET(x) VAL_SET(x, 0xF, 0, 0)
235#define REG2A 0x2A /* Dummy pixel insert MSB */
236#define FRARL 0x2B /* Dummy pixel insert LSB */
237#define ADDVFL 0x2D /* LSB of insert dummy lines in Vertical direction */
238#define ADDVFH 0x2E /* MSB of insert dummy lines in Vertical direction */
239#define YAVG 0x2F /* Y/G Channel Average value */
240#define REG32 0x32 /* Common Control 32 */
241#define REG32_PCLK_DIV_2 0x80 /* PCLK freq divided by 2 */
242#define REG32_PCLK_DIV_4 0xC0 /* PCLK freq divided by 4 */
243#define ARCOM2 0x34 /* Zoom: Horizontal start point */
244#define REG45 0x45 /* Register 45 */
245#define FLL 0x46 /* Frame Length Adjustment LSBs */
246#define FLH 0x47 /* Frame Length Adjustment MSBs */
247#define COM19 0x48 /* Zoom: Vertical start point */
248#define ZOOMS 0x49 /* Zoom: Vertical start point */
249#define COM22 0x4B /* Flash light control */
250#define COM25 0x4E /* For Banding operations */
251#define BD50 0x4F /* 50Hz Banding AEC 8 LSBs */
252#define BD60 0x50 /* 60Hz Banding AEC 8 LSBs */
253#define REG5D 0x5D /* AVGsel[7:0], 16-zone average weight option */
254#define REG5E 0x5E /* AVGsel[15:8], 16-zone average weight option */
255#define REG5F 0x5F /* AVGsel[23:16], 16-zone average weight option */
256#define REG60 0x60 /* AVGsel[31:24], 16-zone average weight option */
257#define HISTO_LOW 0x61 /* Histogram Algorithm Low Level */
258#define HISTO_HIGH 0x62 /* Histogram Algorithm High Level */
259
260/*
261 * ID
262 */
263#define MANUFACTURER_ID 0x7FA2
264#define PID_OV2640 0x2642
265#define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF))
266
267/*
268 * Struct
269 */
270struct regval_list {
271 u8 reg_num;
272 u8 value;
273};
274
3153ac9c
AP		 275struct ov2640_win_size {
276 char *name;
650b1815
JW		 277 u32 width;
278 u32 height;
3153ac9c
AP		 279 const struct regval_list *regs;
280};
281
282
283struct ov2640_priv {
284 struct v4l2_subdev subdev;
ff0e9c1d
HV		 285#if defined(CONFIG_MEDIA_CONTROLLER)
286 struct media_pad pad;
287#endif
f026671d 288 struct v4l2_ctrl_handler hdl;
f5fe58fd 289 u32 cfmt_code;
46796cfc 290 struct clk *clk;
3153ac9c 291 const struct ov2640_win_size *win;
4e65172f 292
4e65172f
JW		 293 struct gpio_desc *resetb_gpio;
294 struct gpio_desc *pwdn_gpio;
3153ac9c
AP		 295};
296
297/*
298 * Registers settings
299 */
300
301#define ENDMARKER { 0xff, 0xff }
302
303static const struct regval_list ov2640_init_regs[] = {
304 { BANK_SEL, BANK_SEL_DSP },
305 { 0x2c, 0xff },
306 { 0x2e, 0xdf },
307 { BANK_SEL, BANK_SEL_SENS },
308 { 0x3c, 0x32 },
309 { CLKRC, CLKRC_DIV_SET(1) },
310 { COM2, COM2_OCAP_Nx_SET(3) },
311 { REG04, REG04_DEF | REG04_HREF_EN },
312 { COM8, COM8_DEF | COM8_BNDF_EN | COM8_AGC_EN | COM8_AEC_EN },
313 { COM9, COM9_AGC_GAIN_8x | 0x08},
314 { 0x2c, 0x0c },
315 { 0x33, 0x78 },
316 { 0x3a, 0x33 },
317 { 0x3b, 0xfb },
318 { 0x3e, 0x00 },
319 { 0x43, 0x11 },
320 { 0x16, 0x10 },
321 { 0x39, 0x02 },
322 { 0x35, 0x88 },
323 { 0x22, 0x0a },
324 { 0x37, 0x40 },
325 { 0x23, 0x00 },
326 { ARCOM2, 0xa0 },
327 { 0x06, 0x02 },
328 { 0x06, 0x88 },
329 { 0x07, 0xc0 },
330 { 0x0d, 0xb7 },
331 { 0x0e, 0x01 },
332 { 0x4c, 0x00 },
333 { 0x4a, 0x81 },
334 { 0x21, 0x99 },
335 { AEW, 0x40 },
336 { AEB, 0x38 },
337 { VV, VV_HIGH_TH_SET(0x08) | VV_LOW_TH_SET(0x02) },
338 { 0x5c, 0x00 },
339 { 0x63, 0x00 },
340 { FLL, 0x22 },
341 { COM3, 0x38 | COM3_BAND_AUTO },
342 { REG5D, 0x55 },
343 { REG5E, 0x7d },
344 { REG5F, 0x7d },
345 { REG60, 0x55 },
346 { HISTO_LOW, 0x70 },
347 { HISTO_HIGH, 0x80 },
348 { 0x7c, 0x05 },
349 { 0x20, 0x80 },
350 { 0x28, 0x30 },
351 { 0x6c, 0x00 },
352 { 0x6d, 0x80 },
353 { 0x6e, 0x00 },
354 { 0x70, 0x02 },
355 { 0x71, 0x94 },
356 { 0x73, 0xc1 },
357 { 0x3d, 0x34 },
358 { COM7, COM7_RES_UXGA | COM7_ZOOM_EN },
359 { 0x5a, 0x57 },
360 { BD50, 0xbb },
361 { BD60, 0x9c },
362 { BANK_SEL, BANK_SEL_DSP },
363 { 0xe5, 0x7f },
364 { MC_BIST, MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL },
365 { 0x41, 0x24 },
366 { RESET, RESET_JPEG | RESET_DVP },
367 { 0x76, 0xff },
368 { 0x33, 0xa0 },
369 { 0x42, 0x20 },
370 { 0x43, 0x18 },
371 { 0x4c, 0x00 },
372 { CTRL3, CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 },
373 { 0x88, 0x3f },
374 { 0xd7, 0x03 },
375 { 0xd9, 0x10 },
376 { R_DVP_SP , R_DVP_SP_AUTO_MODE | 0x2 },
377 { 0xc8, 0x08 },
378 { 0xc9, 0x80 },
379 { BPADDR, 0x00 },
380 { BPDATA, 0x00 },
381 { BPADDR, 0x03 },
382 { BPDATA, 0x48 },
383 { BPDATA, 0x48 },
384 { BPADDR, 0x08 },
385 { BPDATA, 0x20 },
386 { BPDATA, 0x10 },
387 { BPDATA, 0x0e },
388 { 0x90, 0x00 },
389 { 0x91, 0x0e },
390 { 0x91, 0x1a },
391 { 0x91, 0x31 },
392 { 0x91, 0x5a },
393 { 0x91, 0x69 },
394 { 0x91, 0x75 },
395 { 0x91, 0x7e },
396 { 0x91, 0x88 },
397 { 0x91, 0x8f },
398 { 0x91, 0x96 },
399 { 0x91, 0xa3 },
400 { 0x91, 0xaf },
401 { 0x91, 0xc4 },
402 { 0x91, 0xd7 },
403 { 0x91, 0xe8 },
404 { 0x91, 0x20 },
405 { 0x92, 0x00 },
406 { 0x93, 0x06 },
407 { 0x93, 0xe3 },
408 { 0x93, 0x03 },
409 { 0x93, 0x03 },
410 { 0x93, 0x00 },
411 { 0x93, 0x02 },
412 { 0x93, 0x00 },
413 { 0x93, 0x00 },
414 { 0x93, 0x00 },
415 { 0x93, 0x00 },
416 { 0x93, 0x00 },
417 { 0x93, 0x00 },
418 { 0x93, 0x00 },
419 { 0x96, 0x00 },
420 { 0x97, 0x08 },
421 { 0x97, 0x19 },
422 { 0x97, 0x02 },
423 { 0x97, 0x0c },
424 { 0x97, 0x24 },
425 { 0x97, 0x30 },
426 { 0x97, 0x28 },
427 { 0x97, 0x26 },
428 { 0x97, 0x02 },
429 { 0x97, 0x98 },
430 { 0x97, 0x80 },
431 { 0x97, 0x00 },
432 { 0x97, 0x00 },
433 { 0xa4, 0x00 },
434 { 0xa8, 0x00 },
435 { 0xc5, 0x11 },
436 { 0xc6, 0x51 },
437 { 0xbf, 0x80 },
438 { 0xc7, 0x10 },
439 { 0xb6, 0x66 },
440 { 0xb8, 0xA5 },
441 { 0xb7, 0x64 },
442 { 0xb9, 0x7C },
443 { 0xb3, 0xaf },
444 { 0xb4, 0x97 },
445 { 0xb5, 0xFF },
446 { 0xb0, 0xC5 },
447 { 0xb1, 0x94 },
448 { 0xb2, 0x0f },
449 { 0xc4, 0x5c },
450 { 0xa6, 0x00 },
451 { 0xa7, 0x20 },
452 { 0xa7, 0xd8 },
453 { 0xa7, 0x1b },
454 { 0xa7, 0x31 },
455 { 0xa7, 0x00 },
456 { 0xa7, 0x18 },
457 { 0xa7, 0x20 },
458 { 0xa7, 0xd8 },
459 { 0xa7, 0x19 },
460 { 0xa7, 0x31 },
461 { 0xa7, 0x00 },
462 { 0xa7, 0x18 },
463 { 0xa7, 0x20 },
464 { 0xa7, 0xd8 },
465 { 0xa7, 0x19 },
466 { 0xa7, 0x31 },
467 { 0xa7, 0x00 },
468 { 0xa7, 0x18 },
469 { 0x7f, 0x00 },
470 { 0xe5, 0x1f },
471 { 0xe1, 0x77 },
472 { 0xdd, 0x7f },
473 { CTRL0, CTRL0_YUV422 | CTRL0_YUV_EN | CTRL0_RGB_EN },
474 ENDMARKER,
475};
476
477/*
478 * Register settings for window size
479 * The preamble, setup the internal DSP to input an UXGA (1600x1200) image.
480 * Then the different zooming configurations will setup the output image size.
481 */
482static const struct regval_list ov2640_size_change_preamble_regs[] = {
483 { BANK_SEL, BANK_SEL_DSP },
484 { RESET, RESET_DVP },
650b1815
JW		 485 { HSIZE8, HSIZE8_SET(UXGA_WIDTH) },
486 { VSIZE8, VSIZE8_SET(UXGA_HEIGHT) },
3153ac9c
AP		 487 { CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN |
488 CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN },
650b1815
JW		 489 { HSIZE, HSIZE_SET(UXGA_WIDTH) },
490 { VSIZE, VSIZE_SET(UXGA_HEIGHT) },
3153ac9c
AP		 491 { XOFFL, XOFFL_SET(0) },
492 { YOFFL, YOFFL_SET(0) },
650b1815 493 { VHYX, VHYX_HSIZE_SET(UXGA_WIDTH) | VHYX_VSIZE_SET(UXGA_HEIGHT) |
3153ac9c 494 VHYX_XOFF_SET(0) | VHYX_YOFF_SET(0)},
650b1815 495 { TEST, TEST_HSIZE_SET(UXGA_WIDTH) },
3153ac9c
AP		 496 ENDMARKER,
497};
498
499#define PER_SIZE_REG_SEQ(x, y, v_div, h_div, pclk_div) \
500 { CTRLI, CTRLI_LP_DP | CTRLI_V_DIV_SET(v_div) | \
501 CTRLI_H_DIV_SET(h_div)}, \
502 { ZMOW, ZMOW_OUTW_SET(x) }, \
503 { ZMOH, ZMOH_OUTH_SET(y) }, \
504 { ZMHH, ZMHH_OUTW_SET(x) | ZMHH_OUTH_SET(y) }, \
505 { R_DVP_SP, pclk_div }, \
506 { RESET, 0x00}
507
508static const struct regval_list ov2640_qcif_regs[] = {
650b1815 509 PER_SIZE_REG_SEQ(QCIF_WIDTH, QCIF_HEIGHT, 3, 3, 4),
3153ac9c
AP		 510 ENDMARKER,
511};
512
513static const struct regval_list ov2640_qvga_regs[] = {
650b1815 514 PER_SIZE_REG_SEQ(QVGA_WIDTH, QVGA_HEIGHT, 2, 2, 4),
3153ac9c
AP		 515 ENDMARKER,
516};
517
518static const struct regval_list ov2640_cif_regs[] = {
650b1815 519 PER_SIZE_REG_SEQ(CIF_WIDTH, CIF_HEIGHT, 2, 2, 8),
3153ac9c
AP		 520 ENDMARKER,
521};
522
523static const struct regval_list ov2640_vga_regs[] = {
650b1815 524 PER_SIZE_REG_SEQ(VGA_WIDTH, VGA_HEIGHT, 0, 0, 2),
3153ac9c
AP		 525 ENDMARKER,
526};
527
528static const struct regval_list ov2640_svga_regs[] = {
650b1815 529 PER_SIZE_REG_SEQ(SVGA_WIDTH, SVGA_HEIGHT, 1, 1, 2),
3153ac9c
AP		 530 ENDMARKER,
531};
532
533static const struct regval_list ov2640_xga_regs[] = {
650b1815 534 PER_SIZE_REG_SEQ(XGA_WIDTH, XGA_HEIGHT, 0, 0, 2),
3153ac9c
AP		 535 { CTRLI, 0x00},
536 ENDMARKER,
537};
538
539static const struct regval_list ov2640_sxga_regs[] = {
650b1815 540 PER_SIZE_REG_SEQ(SXGA_WIDTH, SXGA_HEIGHT, 0, 0, 2),
3153ac9c
AP		 541 { CTRLI, 0x00},
542 { R_DVP_SP, 2 | R_DVP_SP_AUTO_MODE },
543 ENDMARKER,
544};
545
546static const struct regval_list ov2640_uxga_regs[] = {
650b1815 547 PER_SIZE_REG_SEQ(UXGA_WIDTH, UXGA_HEIGHT, 0, 0, 0),
3153ac9c
AP		 548 { CTRLI, 0x00},
549 { R_DVP_SP, 0 | R_DVP_SP_AUTO_MODE },
550 ENDMARKER,
551};
552
553#define OV2640_SIZE(n, w, h, r) \
554 {.name = n, .width = w , .height = h, .regs = r }
555
556static const struct ov2640_win_size ov2640_supported_win_sizes[] = {
650b1815
JW		 557 OV2640_SIZE("QCIF", QCIF_WIDTH, QCIF_HEIGHT, ov2640_qcif_regs),
558 OV2640_SIZE("QVGA", QVGA_WIDTH, QVGA_HEIGHT, ov2640_qvga_regs),
559 OV2640_SIZE("CIF", CIF_WIDTH, CIF_HEIGHT, ov2640_cif_regs),
560 OV2640_SIZE("VGA", VGA_WIDTH, VGA_HEIGHT, ov2640_vga_regs),
561 OV2640_SIZE("SVGA", SVGA_WIDTH, SVGA_HEIGHT, ov2640_svga_regs),
562 OV2640_SIZE("XGA", XGA_WIDTH, XGA_HEIGHT, ov2640_xga_regs),
563 OV2640_SIZE("SXGA", SXGA_WIDTH, SXGA_HEIGHT, ov2640_sxga_regs),
564 OV2640_SIZE("UXGA", UXGA_WIDTH, UXGA_HEIGHT, ov2640_uxga_regs),
3153ac9c
AP		 565};
566
567/*
568 * Register settings for pixel formats
569 */
570static const struct regval_list ov2640_format_change_preamble_regs[] = {
571 { BANK_SEL, BANK_SEL_DSP },
572 { R_BYPASS, R_BYPASS_USE_DSP },
573 ENDMARKER,
574};
575
d1a49eac
FS		 576static const struct regval_list ov2640_yuyv_regs[] = {
577 { IMAGE_MODE, IMAGE_MODE_YUV422 },
578 { 0xd7, 0x03 },
579 { 0x33, 0xa0 },
580 { 0xe5, 0x1f },
581 { 0xe1, 0x67 },
582 { RESET, 0x00 },
583 { R_BYPASS, R_BYPASS_USE_DSP },
584 ENDMARKER,
585};
586
587static const struct regval_list ov2640_uyvy_regs[] = {
3153ac9c 588 { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_YUV422 },
d1a49eac 589 { 0xd7, 0x01 },
3153ac9c
AP		 590 { 0x33, 0xa0 },
591 { 0xe1, 0x67 },
592 { RESET, 0x00 },
593 { R_BYPASS, R_BYPASS_USE_DSP },
594 ENDMARKER,
595};
596
d1a49eac
FS		 597static const struct regval_list ov2640_rgb565_be_regs[] = {
598 { IMAGE_MODE, IMAGE_MODE_RGB565 },
599 { 0xd7, 0x03 },
600 { RESET, 0x00 },
601 { R_BYPASS, R_BYPASS_USE_DSP },
602 ENDMARKER,
603};
604
605static const struct regval_list ov2640_rgb565_le_regs[] = {
3153ac9c
AP		 606 { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_RGB565 },
607 { 0xd7, 0x03 },
608 { RESET, 0x00 },
609 { R_BYPASS, R_BYPASS_USE_DSP },
610 ENDMARKER,
611};
612
f5fe58fd
BB		 613static u32 ov2640_codes[] = {
614 MEDIA_BUS_FMT_YUYV8_2X8,
615 MEDIA_BUS_FMT_UYVY8_2X8,
616 MEDIA_BUS_FMT_RGB565_2X8_BE,
617 MEDIA_BUS_FMT_RGB565_2X8_LE,
3153ac9c
AP		 618};
619
3153ac9c
AP		 620/*
621 * General functions
622 */
623static struct ov2640_priv *to_ov2640(const struct i2c_client *client)
624{
625 return container_of(i2c_get_clientdata(client), struct ov2640_priv,
626 subdev);
627}
628
629static int ov2640_write_array(struct i2c_client *client,
630 const struct regval_list *vals)
631{
632 int ret;
633
634 while ((vals->reg_num != 0xff) || (vals->value != 0xff)) {
635 ret = i2c_smbus_write_byte_data(client,
636 vals->reg_num, vals->value);
637 dev_vdbg(&client->dev, "array: 0x%02x, 0x%02x",
638 vals->reg_num, vals->value);
639
640 if (ret < 0)
641 return ret;
642 vals++;
643 }
644 return 0;
645}
646
647static int ov2640_mask_set(struct i2c_client *client,
648 u8 reg, u8 mask, u8 set)
649{
650 s32 val = i2c_smbus_read_byte_data(client, reg);
651 if (val < 0)
652 return val;
653
654 val &= ~mask;
655 val |= set & mask;
656
657 dev_vdbg(&client->dev, "masks: 0x%02x, 0x%02x", reg, val);
658
659 return i2c_smbus_write_byte_data(client, reg, val);
660}
661
662static int ov2640_reset(struct i2c_client *client)
663{
664 int ret;
665 const struct regval_list reset_seq[] = {
666 {BANK_SEL, BANK_SEL_SENS},
667 {COM7, COM7_SRST},
668 ENDMARKER,
669 };
670
671 ret = ov2640_write_array(client, reset_seq);
672 if (ret)
673 goto err;
674
675 msleep(5);
676err:
677 dev_dbg(&client->dev, "%s: (ret %d)", __func__, ret);
678 return ret;
679}
680
681/*
34aa8879 682 * functions
3153ac9c 683 */
f026671d 684static int ov2640_s_ctrl(struct v4l2_ctrl *ctrl)
3153ac9c 685{
f026671d
HV		 686 struct v4l2_subdev *sd =
687 &container_of(ctrl->handler, struct ov2640_priv, hdl)->subdev;
3153ac9c 688 struct i2c_client *client = v4l2_get_subdevdata(sd);
3153ac9c 689 u8 val;
a52eb6c0
FS		 690 int ret;
691
692 ret = i2c_smbus_write_byte_data(client, BANK_SEL, BANK_SEL_SENS);
693 if (ret < 0)
694 return ret;
3153ac9c
AP		 695
696 switch (ctrl->id) {
697 case V4L2_CID_VFLIP:
f026671d
HV		 698 val = ctrl->val ? REG04_VFLIP_IMG : 0x00;
699 return ov2640_mask_set(client, REG04, REG04_VFLIP_IMG, val);
3153ac9c 700 case V4L2_CID_HFLIP:
f026671d
HV		 701 val = ctrl->val ? REG04_HFLIP_IMG : 0x00;
702 return ov2640_mask_set(client, REG04, REG04_HFLIP_IMG, val);
3153ac9c
AP		 703 }
704
f026671d 705 return -EINVAL;
3153ac9c
AP		 706}
707
3153ac9c
AP		 708#ifdef CONFIG_VIDEO_ADV_DEBUG
709static int ov2640_g_register(struct v4l2_subdev *sd,
710 struct v4l2_dbg_register *reg)
711{
712 struct i2c_client *client = v4l2_get_subdevdata(sd);
713 int ret;
714
715 reg->size = 1;
716 if (reg->reg > 0xff)
717 return -EINVAL;
718
719 ret = i2c_smbus_read_byte_data(client, reg->reg);
720 if (ret < 0)
721 return ret;
722
723 reg->val = ret;
724
725 return 0;
726}
727
728static int ov2640_s_register(struct v4l2_subdev *sd,
977ba3b1 729 const struct v4l2_dbg_register *reg)
3153ac9c
AP		 730{
731 struct i2c_client *client = v4l2_get_subdevdata(sd);
732
733 if (reg->reg > 0xff ||
734 reg->val > 0xff)
735 return -EINVAL;
736
737 return i2c_smbus_write_byte_data(client, reg->reg, reg->val);
738}
739#endif
740
4ec10bac
LP		 741static int ov2640_s_power(struct v4l2_subdev *sd, int on)
742{
743 struct i2c_client *client = v4l2_get_subdevdata(sd);
9aea470b 744 struct ov2640_priv *priv = to_ov2640(client);
4ec10bac 745
34aa8879
HV		 746 gpiod_direction_output(priv->pwdn_gpio, !on);
747 if (on && priv->resetb_gpio) {
748 /* Active the resetb pin to perform a reset pulse */
749 gpiod_direction_output(priv->resetb_gpio, 1);
750 usleep_range(3000, 5000);
751 gpiod_direction_output(priv->resetb_gpio, 0);
752 }
753 return 0;
4ec10bac
LP		 754}
755
3153ac9c
AP		 756/* Select the nearest higher resolution for capture */
757static const struct ov2640_win_size *ov2640_select_win(u32 *width, u32 *height)
758{
759 int i, default_size = ARRAY_SIZE(ov2640_supported_win_sizes) - 1;
760
761 for (i = 0; i < ARRAY_SIZE(ov2640_supported_win_sizes); i++) {
762 if (ov2640_supported_win_sizes[i].width >= *width &&
763 ov2640_supported_win_sizes[i].height >= *height) {
764 *width = ov2640_supported_win_sizes[i].width;
765 *height = ov2640_supported_win_sizes[i].height;
766 return &ov2640_supported_win_sizes[i];
767 }
768 }
769
770 *width = ov2640_supported_win_sizes[default_size].width;
771 *height = ov2640_supported_win_sizes[default_size].height;
772 return &ov2640_supported_win_sizes[default_size];
773}
774
aa23c053
HV		 775static int ov2640_set_params(struct i2c_client *client,
776 const struct ov2640_win_size *win, u32 code)
3153ac9c
AP		 777{
778 struct ov2640_priv *priv = to_ov2640(client);
779 const struct regval_list *selected_cfmt_regs;
780 int ret;
781
782 /* select win */
aa23c053 783 priv->win = win;
3153ac9c
AP		 784
785 /* select format */
786 priv->cfmt_code = 0;
787 switch (code) {
f5fe58fd 788 case MEDIA_BUS_FMT_RGB565_2X8_BE:
d1a49eac
FS		 789 dev_dbg(&client->dev, "%s: Selected cfmt RGB565 BE", __func__);
790 selected_cfmt_regs = ov2640_rgb565_be_regs;
791 break;
f5fe58fd 792 case MEDIA_BUS_FMT_RGB565_2X8_LE:
d1a49eac
FS		 793 dev_dbg(&client->dev, "%s: Selected cfmt RGB565 LE", __func__);
794 selected_cfmt_regs = ov2640_rgb565_le_regs;
795 break;
f5fe58fd 796 case MEDIA_BUS_FMT_YUYV8_2X8:
d1a49eac
FS		 797 dev_dbg(&client->dev, "%s: Selected cfmt YUYV (YUV422)", __func__);
798 selected_cfmt_regs = ov2640_yuyv_regs;
3153ac9c 799 break;
f5fe58fd 800 case MEDIA_BUS_FMT_UYVY8_2X8:
9823f003 801 default:
d1a49eac
FS		 802 dev_dbg(&client->dev, "%s: Selected cfmt UYVY", __func__);
803 selected_cfmt_regs = ov2640_uyvy_regs;
9823f003 804 break;
3153ac9c
AP		 805 }
806
807 /* reset hardware */
808 ov2640_reset(client);
809
810 /* initialize the sensor with default data */
811 dev_dbg(&client->dev, "%s: Init default", __func__);
812 ret = ov2640_write_array(client, ov2640_init_regs);
813 if (ret < 0)
814 goto err;
815
816 /* select preamble */
817 dev_dbg(&client->dev, "%s: Set size to %s", __func__, priv->win->name);
818 ret = ov2640_write_array(client, ov2640_size_change_preamble_regs);
819 if (ret < 0)
820 goto err;
821
822 /* set size win */
823 ret = ov2640_write_array(client, priv->win->regs);
824 if (ret < 0)
825 goto err;
826
827 /* cfmt preamble */
828 dev_dbg(&client->dev, "%s: Set cfmt", __func__);
829 ret = ov2640_write_array(client, ov2640_format_change_preamble_regs);
830 if (ret < 0)
831 goto err;
832
833 /* set cfmt */
834 ret = ov2640_write_array(client, selected_cfmt_regs);
835 if (ret < 0)
836 goto err;
837
838 priv->cfmt_code = code;
3153ac9c
AP		 839
840 return 0;
841
842err:
843 dev_err(&client->dev, "%s: Error %d", __func__, ret);
844 ov2640_reset(client);
845 priv->win = NULL;
846
847 return ret;
848}
849
da298c6d
HV		 850static int ov2640_get_fmt(struct v4l2_subdev *sd,
851 struct v4l2_subdev_pad_config *cfg,
852 struct v4l2_subdev_format *format)
3153ac9c 853{
da298c6d 854 struct v4l2_mbus_framefmt *mf = &format->format;
3153ac9c
AP		 855 struct i2c_client *client = v4l2_get_subdevdata(sd);
856 struct ov2640_priv *priv = to_ov2640(client);
857
da298c6d
HV		 858 if (format->pad)
859 return -EINVAL;
860
3153ac9c 861 if (!priv->win) {
650b1815 862 u32 width = SVGA_WIDTH, height = SVGA_HEIGHT;
f9859839 863 priv->win = ov2640_select_win(&width, &height);
f5fe58fd 864 priv->cfmt_code = MEDIA_BUS_FMT_UYVY8_2X8;
3153ac9c
AP		 865 }
866
867 mf->width = priv->win->width;
868 mf->height = priv->win->height;
869 mf->code = priv->cfmt_code;
9823f003 870 mf->colorspace = V4L2_COLORSPACE_SRGB;
3153ac9c
AP		 871 mf->field = V4L2_FIELD_NONE;
872
873 return 0;
874}
875
717fd5b4
HV		 876static int ov2640_set_fmt(struct v4l2_subdev *sd,
877 struct v4l2_subdev_pad_config *cfg,
878 struct v4l2_subdev_format *format)
3153ac9c 879{
717fd5b4 880 struct v4l2_mbus_framefmt *mf = &format->format;
3153ac9c 881 struct i2c_client *client = v4l2_get_subdevdata(sd);
aa23c053 882 const struct ov2640_win_size *win;
3153ac9c 883
717fd5b4
HV		 884 if (format->pad)
885 return -EINVAL;
3153ac9c 886
aa23c053
HV		 887 /* select suitable win */
888 win = ov2640_select_win(&mf->width, &mf->height);
3153ac9c
AP		 889
890 mf->field = V4L2_FIELD_NONE;
9823f003 891 mf->colorspace = V4L2_COLORSPACE_SRGB;
3153ac9c
AP		 892
893 switch (mf->code) {
f5fe58fd
BB		 894 case MEDIA_BUS_FMT_RGB565_2X8_BE:
895 case MEDIA_BUS_FMT_RGB565_2X8_LE:
9823f003
HV		 896 case MEDIA_BUS_FMT_YUYV8_2X8:
897 case MEDIA_BUS_FMT_UYVY8_2X8:
3153ac9c
AP		 898 break;
899 default:
f5fe58fd 900 mf->code = MEDIA_BUS_FMT_UYVY8_2X8;
9823f003 901 break;
3153ac9c
AP		 902 }
903
717fd5b4 904 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
aa23c053 905 return ov2640_set_params(client, win, mf->code);
717fd5b4 906 cfg->try_fmt = *mf;
3153ac9c
AP		 907 return 0;
908}
909
ebcff5fc
HV		 910static int ov2640_enum_mbus_code(struct v4l2_subdev *sd,
911 struct v4l2_subdev_pad_config *cfg,
912 struct v4l2_subdev_mbus_code_enum *code)
3153ac9c 913{
ebcff5fc 914 if (code->pad || code->index >= ARRAY_SIZE(ov2640_codes))
3153ac9c
AP		 915 return -EINVAL;
916
ebcff5fc 917 code->code = ov2640_codes[code->index];
3153ac9c
AP		 918 return 0;
919}
920
10d5509c
HV		 921static int ov2640_get_selection(struct v4l2_subdev *sd,
922 struct v4l2_subdev_pad_config *cfg,
923 struct v4l2_subdev_selection *sel)
3153ac9c 924{
10d5509c
HV		 925 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
926 return -EINVAL;
3153ac9c 927
10d5509c
HV		 928 switch (sel->target) {
929 case V4L2_SEL_TGT_CROP_BOUNDS:
930 case V4L2_SEL_TGT_CROP_DEFAULT:
931 case V4L2_SEL_TGT_CROP:
932 sel->r.left = 0;
933 sel->r.top = 0;
934 sel->r.width = UXGA_WIDTH;
935 sel->r.height = UXGA_HEIGHT;
936 return 0;
937 default:
938 return -EINVAL;
939 }
3153ac9c
AP		 940}
941
14178aa5 942static int ov2640_video_probe(struct i2c_client *client)
3153ac9c
AP		 943{
944 struct ov2640_priv *priv = to_ov2640(client);
945 u8 pid, ver, midh, midl;
946 const char *devname;
947 int ret;
948
4bbc6d52
LP		 949 ret = ov2640_s_power(&priv->subdev, 1);
950 if (ret < 0)
951 return ret;
952
3153ac9c
AP		 953 /*
954 * check and show product ID and manufacturer ID
955 */
956 i2c_smbus_write_byte_data(client, BANK_SEL, BANK_SEL_SENS);
957 pid = i2c_smbus_read_byte_data(client, PID);
958 ver = i2c_smbus_read_byte_data(client, VER);
959 midh = i2c_smbus_read_byte_data(client, MIDH);
960 midl = i2c_smbus_read_byte_data(client, MIDL);
961
962 switch (VERSION(pid, ver)) {
963 case PID_OV2640:
964 devname = "ov2640";
3153ac9c
AP		 965 break;
966 default:
967 dev_err(&client->dev,
968 "Product ID error %x:%x\n", pid, ver);
969 ret = -ENODEV;
4bbc6d52 970 goto done;
3153ac9c
AP		 971 }
972
973 dev_info(&client->dev,
974 "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
975 devname, pid, ver, midh, midl);
976
4bbc6d52 977 ret = v4l2_ctrl_handler_setup(&priv->hdl);
3153ac9c 978
4bbc6d52
LP		 979done:
980 ov2640_s_power(&priv->subdev, 0);
3153ac9c
AP		 981 return ret;
982}
983
f026671d
HV		 984static const struct v4l2_ctrl_ops ov2640_ctrl_ops = {
985 .s_ctrl = ov2640_s_ctrl,
3153ac9c
AP		 986};
987
6713c88f 988static const struct v4l2_subdev_core_ops ov2640_subdev_core_ops = {
3153ac9c
AP		 989#ifdef CONFIG_VIDEO_ADV_DEBUG
990 .g_register = ov2640_g_register,
991 .s_register = ov2640_s_register,
992#endif
4ec10bac 993 .s_power = ov2640_s_power,
3153ac9c
AP		 994};
995
ebcff5fc
HV		 996static const struct v4l2_subdev_pad_ops ov2640_subdev_pad_ops = {
997 .enum_mbus_code = ov2640_enum_mbus_code,
10d5509c 998 .get_selection = ov2640_get_selection,
da298c6d 999 .get_fmt = ov2640_get_fmt,
717fd5b4 1000 .set_fmt = ov2640_set_fmt,
ebcff5fc
HV		 1001};
1002
6713c88f 1003static const struct v4l2_subdev_ops ov2640_subdev_ops = {
3153ac9c 1004 .core = &ov2640_subdev_core_ops,
ebcff5fc 1005 .pad = &ov2640_subdev_pad_ops,
3153ac9c
AP		 1006};
1007
4e65172f
JW		 1008static int ov2640_probe_dt(struct i2c_client *client,
1009 struct ov2640_priv *priv)
1010{
1011 /* Request the reset GPIO deasserted */
1012 priv->resetb_gpio = devm_gpiod_get_optional(&client->dev, "resetb",
1013 GPIOD_OUT_LOW);
1014 if (!priv->resetb_gpio)
1015 dev_dbg(&client->dev, "resetb gpio is not assigned!\n");
1016 else if (IS_ERR(priv->resetb_gpio))
1017 return PTR_ERR(priv->resetb_gpio);
1018
1019 /* Request the power down GPIO asserted */
1020 priv->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "pwdn",
1021 GPIOD_OUT_HIGH);
1022 if (!priv->pwdn_gpio)
1023 dev_dbg(&client->dev, "pwdn gpio is not assigned!\n");
1024 else if (IS_ERR(priv->pwdn_gpio))
1025 return PTR_ERR(priv->pwdn_gpio);
1026
4e65172f
JW		 1027 return 0;
1028}
1029
3153ac9c
AP		 1030/*
1031 * i2c_driver functions
1032 */
1033static int ov2640_probe(struct i2c_client *client,
1034 const struct i2c_device_id *did)
1035{
14178aa5 1036 struct ov2640_priv *priv;
14178aa5
GL		 1037 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
1038 int ret;
3153ac9c 1039
3153ac9c
AP		 1040 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
1041 dev_err(&adapter->dev,
1042 "OV2640: I2C-Adapter doesn't support SMBUS\n");
1043 return -EIO;
1044 }
1045
70e176a5 1046 priv = devm_kzalloc(&client->dev, sizeof(struct ov2640_priv), GFP_KERNEL);
3153ac9c
AP		 1047 if (!priv) {
1048 dev_err(&adapter->dev,
1049 "Failed to allocate memory for private data!\n");
1050 return -ENOMEM;
1051 }
1052
46796cfc
HV		 1053 if (client->dev.of_node) {
1054 priv->clk = devm_clk_get(&client->dev, "xvclk");
1055 if (IS_ERR(priv->clk))
1056 return -EPROBE_DEFER;
1057 clk_prepare_enable(priv->clk);
4e65172f
JW		 1058 }
1059
34aa8879
HV		 1060 ret = ov2640_probe_dt(client, priv);
1061 if (ret)
1062 goto err_clk;
4e65172f 1063
3153ac9c 1064 v4l2_i2c_subdev_init(&priv->subdev, client, &ov2640_subdev_ops);
ff0e9c1d 1065 priv->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
f026671d
HV		 1066 v4l2_ctrl_handler_init(&priv->hdl, 2);
1067 v4l2_ctrl_new_std(&priv->hdl, &ov2640_ctrl_ops,
1068 V4L2_CID_VFLIP, 0, 1, 1, 0);
1069 v4l2_ctrl_new_std(&priv->hdl, &ov2640_ctrl_ops,
1070 V4L2_CID_HFLIP, 0, 1, 1, 0);
1071 priv->subdev.ctrl_handler = &priv->hdl;
f180ebae
JW		 1072 if (priv->hdl.error) {
1073 ret = priv->hdl.error;
46796cfc 1074 goto err_hdl;
9aea470b 1075 }
ff0e9c1d
HV		 1076#if defined(CONFIG_MEDIA_CONTROLLER)
1077 priv->pad.flags = MEDIA_PAD_FL_SOURCE;
1078 priv->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1079 ret = media_entity_pads_init(&priv->subdev.entity, 1, &priv->pad);
1080 if (ret < 0)
1081 goto err_hdl;
1082#endif
9aea470b 1083
14178aa5 1084 ret = ov2640_video_probe(client);
f180ebae 1085 if (ret < 0)
ff0e9c1d 1086 goto err_videoprobe;
3153ac9c 1087
f180ebae
JW		 1088 ret = v4l2_async_register_subdev(&priv->subdev);
1089 if (ret < 0)
ff0e9c1d 1090 goto err_videoprobe;
f180ebae
JW		 1091
1092 dev_info(&adapter->dev, "OV2640 Probed\n");
1093
1094 return 0;
1095
ff0e9c1d
HV		 1096err_videoprobe:
1097#if defined(CONFIG_MEDIA_CONTROLLER)
1098 media_entity_cleanup(&priv->subdev.entity);
1099#endif
46796cfc 1100err_hdl:
f180ebae
JW		 1101 v4l2_ctrl_handler_free(&priv->hdl);
1102err_clk:
46796cfc 1103 clk_disable_unprepare(priv->clk);
3153ac9c
AP		 1104 return ret;
1105}
1106
1107static int ov2640_remove(struct i2c_client *client)
1108{
1109 struct ov2640_priv *priv = to_ov2640(client);
3153ac9c 1110
f180ebae 1111 v4l2_async_unregister_subdev(&priv->subdev);
f026671d 1112 v4l2_ctrl_handler_free(&priv->hdl);
ff0e9c1d
HV		 1113#if defined(CONFIG_MEDIA_CONTROLLER)
1114 media_entity_cleanup(&priv->subdev.entity);
1115#endif
46796cfc
HV		 1116 v4l2_device_unregister_subdev(&priv->subdev);
1117 clk_disable_unprepare(priv->clk);
3153ac9c
AP		 1118 return 0;
1119}
1120
1121static const struct i2c_device_id ov2640_id[] = {
1122 { "ov2640", 0 },
1123 { }
1124};
1125MODULE_DEVICE_TABLE(i2c, ov2640_id);
1126
4e65172f
JW		 1127static const struct of_device_id ov2640_of_match[] = {
1128 {.compatible = "ovti,ov2640", },
1129 {},
1130};
1131MODULE_DEVICE_TABLE(of, ov2640_of_match);
1132
3153ac9c
AP		 1133static struct i2c_driver ov2640_i2c_driver = {
1134 .driver = {
1135 .name = "ov2640",
4e65172f 1136 .of_match_table = of_match_ptr(ov2640_of_match),
3153ac9c
AP		 1137 },
1138 .probe = ov2640_probe,
1139 .remove = ov2640_remove,
1140 .id_table = ov2640_id,
1141};
1142
c6e8d86f 1143module_i2c_driver(ov2640_i2c_driver);
3153ac9c 1144
34aa8879 1145MODULE_DESCRIPTION("Driver for Omni Vision 2640 sensor");
3153ac9c
AP		 1146MODULE_AUTHOR("Alberto Panizzo");
1147MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)