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38fc5136 ST |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // Copyright (c) 2022 Intel Corporation. | |
3 | ||
4 | #include <linux/acpi.h> | |
5 | #include <linux/i2c.h> | |
6 | #include <linux/module.h> | |
7 | #include <linux/delay.h> | |
8 | #include <linux/pm_runtime.h> | |
9 | #include <media/v4l2-ctrls.h> | |
10 | #include <media/v4l2-device.h> | |
11 | #include <media/v4l2-fwnode.h> | |
12 | ||
13 | #define OV08X40_REG_VALUE_08BIT 1 | |
14 | #define OV08X40_REG_VALUE_16BIT 2 | |
15 | #define OV08X40_REG_VALUE_24BIT 3 | |
16 | ||
17 | #define OV08X40_REG_MODE_SELECT 0x0100 | |
18 | #define OV08X40_MODE_STANDBY 0x00 | |
19 | #define OV08X40_MODE_STREAMING 0x01 | |
20 | ||
21 | #define OV08X40_REG_AO_STANDBY 0x1000 | |
22 | #define OV08X40_AO_STREAMING 0x04 | |
23 | ||
24 | #define OV08X40_REG_MS_SELECT 0x1001 | |
25 | #define OV08X40_MS_STANDBY 0x00 | |
26 | #define OV08X40_MS_STREAMING 0x04 | |
27 | ||
28 | #define OV08X40_REG_SOFTWARE_RST 0x0103 | |
29 | #define OV08X40_SOFTWARE_RST 0x01 | |
30 | ||
31 | /* Chip ID */ | |
32 | #define OV08X40_REG_CHIP_ID 0x300a | |
33 | #define OV08X40_CHIP_ID 0x560858 | |
34 | ||
35 | /* V_TIMING internal */ | |
36 | #define OV08X40_REG_VTS 0x380e | |
37 | #define OV08X40_VTS_30FPS 0x1388 | |
38 | #define OV08X40_VTS_BIN_30FPS 0x115c | |
39 | #define OV08X40_VTS_MAX 0x7fff | |
40 | ||
41 | /* H TIMING internal */ | |
42 | #define OV08X40_REG_HTS 0x380c | |
43 | #define OV08X40_HTS_30FPS 0x0280 | |
44 | ||
45 | /* Exposure control */ | |
46 | #define OV08X40_REG_EXPOSURE 0x3500 | |
47 | #define OV08X40_EXPOSURE_MAX_MARGIN 31 | |
48 | #define OV08X40_EXPOSURE_MIN 1 | |
49 | #define OV08X40_EXPOSURE_STEP 1 | |
50 | #define OV08X40_EXPOSURE_DEFAULT 0x40 | |
51 | ||
52 | /* Short Exposure control */ | |
53 | #define OV08X40_REG_SHORT_EXPOSURE 0x3540 | |
54 | ||
55 | /* Analog gain control */ | |
56 | #define OV08X40_REG_ANALOG_GAIN 0x3508 | |
57 | #define OV08X40_ANA_GAIN_MIN 0x80 | |
58 | #define OV08X40_ANA_GAIN_MAX 0x07c0 | |
59 | #define OV08X40_ANA_GAIN_STEP 1 | |
60 | #define OV08X40_ANA_GAIN_DEFAULT 0x80 | |
61 | ||
62 | /* Digital gain control */ | |
63 | #define OV08X40_REG_DGTL_GAIN_H 0x350a | |
64 | #define OV08X40_REG_DGTL_GAIN_M 0x350b | |
65 | #define OV08X40_REG_DGTL_GAIN_L 0x350c | |
66 | ||
67 | #define OV08X40_DGTL_GAIN_MIN 1024 /* Min = 1 X */ | |
68 | #define OV08X40_DGTL_GAIN_MAX (4096 - 1) /* Max = 4 X */ | |
69 | #define OV08X40_DGTL_GAIN_DEFAULT 2560 /* Default gain = 2.5 X */ | |
70 | #define OV08X40_DGTL_GAIN_STEP 1 /* Each step = 1/1024 */ | |
71 | ||
72 | #define OV08X40_DGTL_GAIN_L_SHIFT 6 | |
73 | #define OV08X40_DGTL_GAIN_L_MASK 0x3 | |
74 | #define OV08X40_DGTL_GAIN_M_SHIFT 2 | |
75 | #define OV08X40_DGTL_GAIN_M_MASK 0xff | |
76 | #define OV08X40_DGTL_GAIN_H_SHIFT 10 | |
77 | #define OV08X40_DGTL_GAIN_H_MASK 0x1F | |
78 | ||
79 | /* Test Pattern Control */ | |
80 | #define OV08X40_REG_TEST_PATTERN 0x50C1 | |
81 | #define OV08X40_REG_ISP 0x5000 | |
82 | #define OV08X40_REG_SHORT_TEST_PATTERN 0x53C1 | |
83 | #define OV08X40_TEST_PATTERN_ENABLE BIT(0) | |
84 | #define OV08X40_TEST_PATTERN_MASK 0xcf | |
85 | #define OV08X40_TEST_PATTERN_BAR_SHIFT 4 | |
86 | ||
87 | /* Flip Control */ | |
88 | #define OV08X40_REG_VFLIP 0x3820 | |
89 | #define OV08X40_REG_MIRROR 0x3821 | |
90 | ||
91 | /* Horizontal Window Offset */ | |
92 | #define OV08X40_REG_H_WIN_OFFSET 0x3811 | |
93 | ||
94 | /* Vertical Window Offset */ | |
95 | #define OV08X40_REG_V_WIN_OFFSET 0x3813 | |
96 | ||
97 | enum { | |
98 | OV08X40_LINK_FREQ_400MHZ_INDEX, | |
99 | }; | |
100 | ||
101 | struct ov08x40_reg { | |
102 | u16 address; | |
103 | u8 val; | |
104 | }; | |
105 | ||
106 | struct ov08x40_reg_list { | |
107 | u32 num_of_regs; | |
108 | const struct ov08x40_reg *regs; | |
109 | }; | |
110 | ||
111 | /* Link frequency config */ | |
112 | struct ov08x40_link_freq_config { | |
113 | u32 pixels_per_line; | |
114 | ||
115 | /* registers for this link frequency */ | |
116 | struct ov08x40_reg_list reg_list; | |
117 | }; | |
118 | ||
119 | /* Mode : resolution and related config&values */ | |
120 | struct ov08x40_mode { | |
121 | /* Frame width */ | |
122 | u32 width; | |
123 | /* Frame height */ | |
124 | u32 height; | |
125 | ||
126 | u32 lanes; | |
127 | /* V-timing */ | |
128 | u32 vts_def; | |
129 | u32 vts_min; | |
130 | ||
131 | /* Index of Link frequency config to be used */ | |
132 | u32 link_freq_index; | |
133 | /* Default register values */ | |
134 | struct ov08x40_reg_list reg_list; | |
135 | }; | |
136 | ||
137 | static const struct ov08x40_reg mipi_data_rate_800mbps[] = { | |
138 | {0x0103, 0x01}, | |
139 | {0x1000, 0x00}, | |
140 | {0x1601, 0xd0}, | |
141 | {0x1001, 0x04}, | |
142 | {0x5004, 0x53}, | |
143 | {0x5110, 0x00}, | |
144 | {0x5111, 0x14}, | |
145 | {0x5112, 0x01}, | |
146 | {0x5113, 0x7b}, | |
147 | {0x5114, 0x00}, | |
148 | {0x5152, 0xa3}, | |
149 | {0x5a52, 0x1f}, | |
150 | {0x5a1a, 0x0e}, | |
151 | {0x5a1b, 0x10}, | |
152 | {0x5a1f, 0x0e}, | |
153 | {0x5a27, 0x0e}, | |
154 | {0x6002, 0x2e}, | |
155 | }; | |
156 | ||
157 | static const struct ov08x40_reg mode_3856x2416_regs[] = { | |
158 | {0x5000, 0x5d}, | |
159 | {0x5001, 0x20}, | |
160 | {0x5008, 0xb0}, | |
161 | {0x50c1, 0x00}, | |
162 | {0x53c1, 0x00}, | |
163 | {0x5f40, 0x00}, | |
164 | {0x5f41, 0x40}, | |
165 | {0x0300, 0x3a}, | |
166 | {0x0301, 0xc8}, | |
167 | {0x0302, 0x31}, | |
168 | {0x0303, 0x03}, | |
169 | {0x0304, 0x01}, | |
170 | {0x0305, 0xa1}, | |
171 | {0x0306, 0x04}, | |
172 | {0x0307, 0x01}, | |
173 | {0x0308, 0x03}, | |
174 | {0x0309, 0x03}, | |
175 | {0x0310, 0x0a}, | |
176 | {0x0311, 0x02}, | |
177 | {0x0312, 0x01}, | |
178 | {0x0313, 0x08}, | |
179 | {0x0314, 0x66}, | |
180 | {0x0315, 0x00}, | |
181 | {0x0316, 0x34}, | |
182 | {0x0320, 0x02}, | |
183 | {0x0321, 0x03}, | |
184 | {0x0323, 0x05}, | |
185 | {0x0324, 0x01}, | |
186 | {0x0325, 0xb8}, | |
187 | {0x0326, 0x4a}, | |
188 | {0x0327, 0x04}, | |
189 | {0x0329, 0x00}, | |
190 | {0x032a, 0x05}, | |
191 | {0x032b, 0x00}, | |
192 | {0x032c, 0x00}, | |
193 | {0x032d, 0x00}, | |
194 | {0x032e, 0x02}, | |
195 | {0x032f, 0xa0}, | |
196 | {0x0350, 0x00}, | |
197 | {0x0360, 0x01}, | |
198 | {0x1216, 0x60}, | |
199 | {0x1217, 0x5b}, | |
200 | {0x1218, 0x00}, | |
201 | {0x1220, 0x24}, | |
202 | {0x198a, 0x00}, | |
203 | {0x198b, 0x01}, | |
204 | {0x198e, 0x00}, | |
205 | {0x198f, 0x01}, | |
206 | {0x3009, 0x04}, | |
207 | {0x3012, 0x41}, | |
208 | {0x3015, 0x00}, | |
209 | {0x3016, 0xb0}, | |
210 | {0x3017, 0xf0}, | |
211 | {0x3018, 0xf0}, | |
212 | {0x3019, 0xd2}, | |
213 | {0x301a, 0xb0}, | |
214 | {0x301c, 0x81}, | |
215 | {0x301d, 0x02}, | |
216 | {0x301e, 0x80}, | |
217 | {0x3022, 0xf0}, | |
218 | {0x3025, 0x89}, | |
219 | {0x3030, 0x03}, | |
220 | {0x3044, 0xc2}, | |
221 | {0x3050, 0x35}, | |
222 | {0x3051, 0x60}, | |
223 | {0x3052, 0x25}, | |
224 | {0x3053, 0x00}, | |
225 | {0x3054, 0x00}, | |
226 | {0x3055, 0x02}, | |
227 | {0x3056, 0x80}, | |
228 | {0x3057, 0x80}, | |
229 | {0x3058, 0x80}, | |
230 | {0x3059, 0x00}, | |
231 | {0x3107, 0x86}, | |
232 | {0x3400, 0x1c}, | |
233 | {0x3401, 0x80}, | |
234 | {0x3402, 0x8c}, | |
235 | {0x3419, 0x13}, | |
236 | {0x341a, 0x89}, | |
237 | {0x341b, 0x30}, | |
238 | {0x3420, 0x00}, | |
239 | {0x3421, 0x00}, | |
240 | {0x3422, 0x00}, | |
241 | {0x3423, 0x00}, | |
242 | {0x3424, 0x00}, | |
243 | {0x3425, 0x00}, | |
244 | {0x3426, 0x00}, | |
245 | {0x3427, 0x00}, | |
246 | {0x3428, 0x0f}, | |
247 | {0x3429, 0x00}, | |
248 | {0x342a, 0x00}, | |
249 | {0x342b, 0x00}, | |
250 | {0x342c, 0x00}, | |
251 | {0x342d, 0x00}, | |
252 | {0x342e, 0x00}, | |
253 | {0x342f, 0x11}, | |
254 | {0x3430, 0x11}, | |
255 | {0x3431, 0x10}, | |
256 | {0x3432, 0x00}, | |
257 | {0x3433, 0x00}, | |
258 | {0x3434, 0x00}, | |
259 | {0x3435, 0x00}, | |
260 | {0x3436, 0x00}, | |
261 | {0x3437, 0x00}, | |
262 | {0x3442, 0x02}, | |
263 | {0x3443, 0x02}, | |
264 | {0x3444, 0x07}, | |
265 | {0x3450, 0x00}, | |
266 | {0x3451, 0x00}, | |
267 | {0x3452, 0x18}, | |
268 | {0x3453, 0x18}, | |
269 | {0x3454, 0x00}, | |
270 | {0x3455, 0x80}, | |
271 | {0x3456, 0x08}, | |
272 | {0x3500, 0x00}, | |
273 | {0x3501, 0x02}, | |
274 | {0x3502, 0x00}, | |
275 | {0x3504, 0x4c}, | |
276 | {0x3506, 0x30}, | |
277 | {0x3507, 0x00}, | |
278 | {0x3508, 0x01}, | |
279 | {0x3509, 0x00}, | |
280 | {0x350a, 0x01}, | |
281 | {0x350b, 0x00}, | |
282 | {0x350c, 0x00}, | |
283 | {0x3540, 0x00}, | |
284 | {0x3541, 0x01}, | |
285 | {0x3542, 0x00}, | |
286 | {0x3544, 0x4c}, | |
287 | {0x3546, 0x30}, | |
288 | {0x3547, 0x00}, | |
289 | {0x3548, 0x01}, | |
290 | {0x3549, 0x00}, | |
291 | {0x354a, 0x01}, | |
292 | {0x354b, 0x00}, | |
293 | {0x354c, 0x00}, | |
294 | {0x3688, 0x02}, | |
295 | {0x368a, 0x2e}, | |
296 | {0x368e, 0x71}, | |
297 | {0x3696, 0xd1}, | |
298 | {0x3699, 0x00}, | |
299 | {0x369a, 0x00}, | |
300 | {0x36a4, 0x00}, | |
301 | {0x36a6, 0x00}, | |
302 | {0x3711, 0x00}, | |
303 | {0x3712, 0x51}, | |
304 | {0x3713, 0x00}, | |
305 | {0x3714, 0x24}, | |
306 | {0x3716, 0x00}, | |
307 | {0x3718, 0x07}, | |
308 | {0x371a, 0x1c}, | |
309 | {0x371b, 0x00}, | |
310 | {0x3720, 0x08}, | |
311 | {0x3725, 0x32}, | |
312 | {0x3727, 0x05}, | |
313 | {0x3760, 0x02}, | |
314 | {0x3761, 0x17}, | |
315 | {0x3762, 0x02}, | |
316 | {0x3763, 0x02}, | |
317 | {0x3764, 0x02}, | |
318 | {0x3765, 0x2c}, | |
319 | {0x3766, 0x04}, | |
320 | {0x3767, 0x2c}, | |
321 | {0x3768, 0x02}, | |
322 | {0x3769, 0x00}, | |
323 | {0x376b, 0x20}, | |
324 | {0x376e, 0x03}, | |
325 | {0x37b0, 0x00}, | |
326 | {0x37b1, 0xab}, | |
327 | {0x37b2, 0x01}, | |
328 | {0x37b3, 0x82}, | |
329 | {0x37b4, 0x00}, | |
330 | {0x37b5, 0xe4}, | |
331 | {0x37b6, 0x01}, | |
332 | {0x37b7, 0xee}, | |
333 | {0x3800, 0x00}, | |
334 | {0x3801, 0x00}, | |
335 | {0x3802, 0x00}, | |
336 | {0x3803, 0x00}, | |
337 | {0x3804, 0x0f}, | |
338 | {0x3805, 0x1f}, | |
339 | {0x3806, 0x09}, | |
340 | {0x3807, 0x7f}, | |
341 | {0x3808, 0x0f}, | |
342 | {0x3809, 0x10}, | |
343 | {0x380a, 0x09}, | |
344 | {0x380b, 0x70}, | |
345 | {0x380c, 0x02}, | |
346 | {0x380d, 0x80}, | |
347 | {0x380e, 0x13}, | |
348 | {0x380f, 0x88}, | |
349 | {0x3810, 0x00}, | |
350 | {0x3811, 0x08}, | |
351 | {0x3812, 0x00}, | |
352 | {0x3813, 0x07}, | |
353 | {0x3814, 0x11}, | |
354 | {0x3815, 0x11}, | |
355 | {0x3820, 0x00}, | |
356 | {0x3821, 0x04}, | |
357 | {0x3822, 0x00}, | |
358 | {0x3823, 0x04}, | |
359 | {0x3828, 0x0f}, | |
360 | {0x382a, 0x80}, | |
361 | {0x382e, 0x41}, | |
362 | {0x3837, 0x08}, | |
363 | {0x383a, 0x81}, | |
364 | {0x383b, 0x81}, | |
365 | {0x383c, 0x11}, | |
366 | {0x383d, 0x11}, | |
367 | {0x383e, 0x00}, | |
368 | {0x383f, 0x38}, | |
369 | {0x3840, 0x00}, | |
370 | {0x3847, 0x00}, | |
371 | {0x384a, 0x00}, | |
372 | {0x384c, 0x02}, | |
373 | {0x384d, 0x80}, | |
374 | {0x3856, 0x50}, | |
375 | {0x3857, 0x30}, | |
376 | {0x3858, 0x80}, | |
377 | {0x3859, 0x40}, | |
378 | {0x3860, 0x00}, | |
379 | {0x3888, 0x00}, | |
380 | {0x3889, 0x00}, | |
381 | {0x388a, 0x00}, | |
382 | {0x388b, 0x00}, | |
383 | {0x388c, 0x00}, | |
384 | {0x388d, 0x00}, | |
385 | {0x388e, 0x00}, | |
386 | {0x388f, 0x00}, | |
387 | {0x3894, 0x00}, | |
388 | {0x3895, 0x00}, | |
389 | {0x3c84, 0x00}, | |
390 | {0x3d85, 0x8b}, | |
391 | {0x3daa, 0x80}, | |
392 | {0x3dab, 0x14}, | |
393 | {0x3dac, 0x80}, | |
394 | {0x3dad, 0xc8}, | |
395 | {0x3dae, 0x81}, | |
396 | {0x3daf, 0x7b}, | |
397 | {0x3f00, 0x10}, | |
398 | {0x3f01, 0x11}, | |
399 | {0x3f06, 0x0d}, | |
400 | {0x3f07, 0x0b}, | |
401 | {0x3f08, 0x0d}, | |
402 | {0x3f09, 0x0b}, | |
403 | {0x3f0a, 0x01}, | |
404 | {0x3f0b, 0x11}, | |
405 | {0x3f0c, 0x33}, | |
406 | {0x4001, 0x07}, | |
407 | {0x4007, 0x20}, | |
408 | {0x4008, 0x00}, | |
409 | {0x4009, 0x05}, | |
410 | {0x400a, 0x00}, | |
411 | {0x400b, 0x08}, | |
412 | {0x400c, 0x00}, | |
413 | {0x400d, 0x08}, | |
414 | {0x400e, 0x14}, | |
415 | {0x4010, 0xf4}, | |
416 | {0x4011, 0x03}, | |
417 | {0x4012, 0x55}, | |
418 | {0x4015, 0x00}, | |
419 | {0x4016, 0x2d}, | |
420 | {0x4017, 0x00}, | |
421 | {0x4018, 0x0f}, | |
422 | {0x401b, 0x08}, | |
423 | {0x401c, 0x00}, | |
424 | {0x401d, 0x10}, | |
425 | {0x401e, 0x02}, | |
426 | {0x401f, 0x00}, | |
427 | {0x4050, 0x06}, | |
428 | {0x4051, 0xff}, | |
429 | {0x4052, 0xff}, | |
430 | {0x4053, 0xff}, | |
431 | {0x4054, 0xff}, | |
432 | {0x4055, 0xff}, | |
433 | {0x4056, 0xff}, | |
434 | {0x4057, 0x7f}, | |
435 | {0x4058, 0x00}, | |
436 | {0x4059, 0x00}, | |
437 | {0x405a, 0x00}, | |
438 | {0x405b, 0x00}, | |
439 | {0x405c, 0x07}, | |
440 | {0x405d, 0xff}, | |
441 | {0x405e, 0x07}, | |
442 | {0x405f, 0xff}, | |
443 | {0x4080, 0x78}, | |
444 | {0x4081, 0x78}, | |
445 | {0x4082, 0x78}, | |
446 | {0x4083, 0x78}, | |
447 | {0x4019, 0x00}, | |
448 | {0x401a, 0x40}, | |
449 | {0x4020, 0x04}, | |
450 | {0x4021, 0x00}, | |
451 | {0x4022, 0x04}, | |
452 | {0x4023, 0x00}, | |
453 | {0x4024, 0x04}, | |
454 | {0x4025, 0x00}, | |
455 | {0x4026, 0x04}, | |
456 | {0x4027, 0x00}, | |
457 | {0x4030, 0x00}, | |
458 | {0x4031, 0x00}, | |
459 | {0x4032, 0x00}, | |
460 | {0x4033, 0x00}, | |
461 | {0x4034, 0x00}, | |
462 | {0x4035, 0x00}, | |
463 | {0x4036, 0x00}, | |
464 | {0x4037, 0x00}, | |
465 | {0x4040, 0x00}, | |
466 | {0x4041, 0x80}, | |
467 | {0x4042, 0x00}, | |
468 | {0x4043, 0x80}, | |
469 | {0x4044, 0x00}, | |
470 | {0x4045, 0x80}, | |
471 | {0x4046, 0x00}, | |
472 | {0x4047, 0x80}, | |
473 | {0x4060, 0x00}, | |
474 | {0x4061, 0x00}, | |
475 | {0x4062, 0x00}, | |
476 | {0x4063, 0x00}, | |
477 | {0x4064, 0x00}, | |
478 | {0x4065, 0x00}, | |
479 | {0x4066, 0x00}, | |
480 | {0x4067, 0x00}, | |
481 | {0x4068, 0x00}, | |
482 | {0x4069, 0x00}, | |
483 | {0x406a, 0x00}, | |
484 | {0x406b, 0x00}, | |
485 | {0x406c, 0x00}, | |
486 | {0x406d, 0x00}, | |
487 | {0x406e, 0x00}, | |
488 | {0x406f, 0x00}, | |
489 | {0x4070, 0x00}, | |
490 | {0x4071, 0x00}, | |
491 | {0x4072, 0x00}, | |
492 | {0x4073, 0x00}, | |
493 | {0x4074, 0x00}, | |
494 | {0x4075, 0x00}, | |
495 | {0x4076, 0x00}, | |
496 | {0x4077, 0x00}, | |
497 | {0x4078, 0x00}, | |
498 | {0x4079, 0x00}, | |
499 | {0x407a, 0x00}, | |
500 | {0x407b, 0x00}, | |
501 | {0x407c, 0x00}, | |
502 | {0x407d, 0x00}, | |
503 | {0x407e, 0x00}, | |
504 | {0x407f, 0x00}, | |
505 | {0x40e0, 0x00}, | |
506 | {0x40e1, 0x00}, | |
507 | {0x40e2, 0x00}, | |
508 | {0x40e3, 0x00}, | |
509 | {0x40e4, 0x00}, | |
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984 | {0x5bdd, 0x75}, | |
985 | {0x5bde, 0x75}, | |
986 | {0x5bdf, 0x75}, | |
987 | {0x5be0, 0x75}, | |
988 | {0x5be1, 0x75}, | |
989 | {0x5be2, 0x75}, | |
990 | {0x5be3, 0x75}, | |
991 | {0x5be4, 0x75}, | |
992 | {0x5be5, 0x75}, | |
993 | {0x5be6, 0x75}, | |
994 | {0x5be7, 0x75}, | |
995 | {0x5be8, 0x75}, | |
996 | {0x5be9, 0x75}, | |
997 | {0x5bea, 0x75}, | |
998 | {0x5beb, 0x75}, | |
999 | {0x5bec, 0x75}, | |
1000 | {0x5bed, 0x75}, | |
1001 | {0x5bee, 0x75}, | |
1002 | {0x5bef, 0x75}, | |
1003 | {0x5bf0, 0x75}, | |
1004 | {0x5bf1, 0x75}, | |
1005 | {0x5bf2, 0x75}, | |
1006 | {0x5bf3, 0x75}, | |
1007 | {0x5bf4, 0x75}, | |
1008 | {0x5bf5, 0x75}, | |
1009 | {0x5bf6, 0x75}, | |
1010 | {0x5bf7, 0x75}, | |
1011 | {0x5bf8, 0x75}, | |
1012 | {0x5bf9, 0x75}, | |
1013 | {0x5bfa, 0x75}, | |
1014 | {0x5bfb, 0x75}, | |
1015 | {0x5bfc, 0x75}, | |
1016 | {0x5bfd, 0x75}, | |
1017 | {0x5bfe, 0x75}, | |
1018 | {0x5bff, 0x75}, | |
1019 | {0x5c00, 0x75}, | |
1020 | {0x5c01, 0x75}, | |
1021 | {0x5c02, 0x75}, | |
1022 | {0x5c03, 0x75}, | |
1023 | {0x5c04, 0x75}, | |
1024 | {0x5c05, 0x75}, | |
1025 | {0x5c06, 0x75}, | |
1026 | {0x5c07, 0x75}, | |
1027 | {0x5c08, 0x75}, | |
1028 | {0x5c09, 0x75}, | |
1029 | {0x5c0a, 0x75}, | |
1030 | {0x5c0b, 0x75}, | |
1031 | {0x5c0c, 0x75}, | |
1032 | {0x5c0d, 0x75}, | |
1033 | {0x5c0e, 0x75}, | |
1034 | {0x5c0f, 0x75}, | |
1035 | {0x5c10, 0x75}, | |
1036 | {0x5c11, 0x75}, | |
1037 | {0x5c12, 0x75}, | |
1038 | {0x5c13, 0x75}, | |
1039 | {0x5c14, 0x75}, | |
1040 | {0x5c15, 0x75}, | |
1041 | {0x5c16, 0x75}, | |
1042 | {0x5c17, 0x75}, | |
1043 | {0x5c18, 0x75}, | |
1044 | {0x5c19, 0x75}, | |
1045 | {0x5c1a, 0x75}, | |
1046 | {0x5c1b, 0x75}, | |
1047 | {0x5c1c, 0x75}, | |
1048 | {0x5c1d, 0x75}, | |
1049 | {0x5c1e, 0x75}, | |
1050 | {0x5c1f, 0x75}, | |
1051 | {0x5c20, 0x75}, | |
1052 | {0x5c21, 0x75}, | |
1053 | {0x5c22, 0x75}, | |
1054 | {0x5c23, 0x75}, | |
1055 | {0x5c24, 0x75}, | |
1056 | {0x5c25, 0x75}, | |
1057 | {0x5c26, 0x75}, | |
1058 | {0x5c27, 0x75}, | |
1059 | {0x5c28, 0x75}, | |
1060 | {0x5c29, 0x75}, | |
1061 | {0x5c2a, 0x75}, | |
1062 | {0x5c2b, 0x75}, | |
1063 | {0x5c2c, 0x75}, | |
1064 | {0x5c2d, 0x75}, | |
1065 | {0x5c2e, 0x75}, | |
1066 | {0x5c2f, 0x75}, | |
1067 | {0x5c30, 0x75}, | |
1068 | {0x5c31, 0x75}, | |
1069 | {0x5c32, 0x75}, | |
1070 | {0x5c33, 0x75}, | |
1071 | {0x5c34, 0x75}, | |
1072 | {0x5c35, 0x75}, | |
1073 | {0x5c36, 0x75}, | |
1074 | {0x5c37, 0x75}, | |
1075 | {0x5c38, 0x75}, | |
1076 | {0x5c39, 0x75}, | |
1077 | {0x5c3a, 0x75}, | |
1078 | {0x5c3b, 0x75}, | |
1079 | {0x5c3c, 0x75}, | |
1080 | {0x5c3d, 0x75}, | |
1081 | {0x5c3e, 0x75}, | |
1082 | {0x5c3f, 0x75}, | |
1083 | {0x5c40, 0x75}, | |
1084 | {0x5c41, 0x75}, | |
1085 | {0x5c42, 0x75}, | |
1086 | {0x5c43, 0x75}, | |
1087 | {0x5c44, 0x75}, | |
1088 | {0x5c45, 0x75}, | |
1089 | {0x5c46, 0x75}, | |
1090 | {0x5c47, 0x75}, | |
1091 | {0x5c48, 0x75}, | |
1092 | {0x5c49, 0x75}, | |
1093 | {0x5c4a, 0x75}, | |
1094 | {0x5c4b, 0x75}, | |
1095 | {0x5c4c, 0x75}, | |
1096 | {0x5c4d, 0x75}, | |
1097 | {0x5c4e, 0x75}, | |
1098 | {0x5c4f, 0x75}, | |
1099 | {0x5c50, 0x75}, | |
1100 | {0x5c51, 0x75}, | |
1101 | {0x5c52, 0x75}, | |
1102 | {0x5c53, 0x75}, | |
1103 | {0x5c54, 0x75}, | |
1104 | {0x5c55, 0x75}, | |
1105 | {0x5c56, 0x75}, | |
1106 | {0x5c57, 0x75}, | |
1107 | {0x5c58, 0x75}, | |
1108 | {0x5c59, 0x75}, | |
1109 | {0x5c5a, 0x75}, | |
1110 | {0x5c5b, 0x75}, | |
1111 | {0x5c5c, 0x75}, | |
1112 | {0x5c5d, 0x75}, | |
1113 | {0x5c5e, 0x75}, | |
1114 | {0x5c5f, 0x75}, | |
1115 | {0x5c60, 0x75}, | |
1116 | {0x5c61, 0x75}, | |
1117 | {0x5c62, 0x75}, | |
1118 | {0x5c63, 0x75}, | |
1119 | {0x5c64, 0x75}, | |
1120 | {0x5c65, 0x75}, | |
1121 | {0x5c66, 0x75}, | |
1122 | {0x5c67, 0x75}, | |
1123 | {0x5c68, 0x75}, | |
1124 | {0x5c69, 0x75}, | |
1125 | {0x5c6a, 0x75}, | |
1126 | {0x5c6b, 0x75}, | |
1127 | {0x5c6c, 0x75}, | |
1128 | {0x5c6d, 0x75}, | |
1129 | {0x5c6e, 0x75}, | |
1130 | {0x5c6f, 0x75}, | |
1131 | {0x5c70, 0x75}, | |
1132 | {0x5c71, 0x75}, | |
1133 | {0x5c72, 0x75}, | |
1134 | {0x5c73, 0x75}, | |
1135 | {0x5c74, 0x75}, | |
1136 | {0x5c75, 0x75}, | |
1137 | {0x5c76, 0x75}, | |
1138 | {0x5c77, 0x75}, | |
1139 | {0x5c78, 0x75}, | |
1140 | {0x5c79, 0x75}, | |
1141 | {0x5c7a, 0x75}, | |
1142 | {0x5c7b, 0x75}, | |
1143 | {0x5c7c, 0x75}, | |
1144 | {0x5c7d, 0x75}, | |
1145 | {0x5c7e, 0x75}, | |
1146 | {0x5c7f, 0x75}, | |
1147 | {0x5c80, 0x75}, | |
1148 | {0x5c81, 0x75}, | |
1149 | {0x5c82, 0x75}, | |
1150 | {0x5c83, 0x75}, | |
1151 | {0x5c84, 0x75}, | |
1152 | {0x5c85, 0x75}, | |
1153 | {0x5c86, 0x75}, | |
1154 | {0x5c87, 0x75}, | |
1155 | {0x5c88, 0x75}, | |
1156 | {0x5c89, 0x75}, | |
1157 | {0x5c8a, 0x75}, | |
1158 | {0x5c8b, 0x75}, | |
1159 | {0x5c8c, 0x75}, | |
1160 | {0x5c8d, 0x75}, | |
1161 | {0x5c8e, 0x75}, | |
1162 | {0x5c8f, 0x75}, | |
1163 | {0x5c90, 0x75}, | |
1164 | {0x5c91, 0x75}, | |
1165 | {0x5c92, 0x75}, | |
1166 | {0x5c93, 0x75}, | |
1167 | {0x5c94, 0x75}, | |
1168 | {0x5c95, 0x75}, | |
1169 | {0x5c96, 0x75}, | |
1170 | {0x5c97, 0x75}, | |
1171 | {0x5c98, 0x75}, | |
1172 | {0x5c99, 0x75}, | |
1173 | {0x5c9a, 0x75}, | |
1174 | {0x5c9b, 0x75}, | |
1175 | {0x5c9c, 0x75}, | |
1176 | {0x5c9d, 0x75}, | |
1177 | {0x5c9e, 0x75}, | |
1178 | {0x5c9f, 0x75}, | |
1179 | {0x5ca0, 0x75}, | |
1180 | {0x5ca1, 0x75}, | |
1181 | {0x5ca2, 0x75}, | |
1182 | {0x5ca3, 0x75}, | |
1183 | {0x5ca4, 0x75}, | |
1184 | {0x5ca5, 0x75}, | |
1185 | {0x5ca6, 0x75}, | |
1186 | {0x5ca7, 0x75}, | |
1187 | {0x5ca8, 0x75}, | |
1188 | {0x5ca9, 0x75}, | |
1189 | {0x5caa, 0x75}, | |
1190 | {0x5cab, 0x75}, | |
1191 | {0x5cac, 0x75}, | |
1192 | {0x5cad, 0x75}, | |
1193 | {0x5cae, 0x75}, | |
1194 | {0x5caf, 0x75}, | |
1195 | {0x5cb0, 0x75}, | |
1196 | {0x5cb1, 0x75}, | |
1197 | {0x5cb2, 0x75}, | |
1198 | {0x5cb3, 0x75}, | |
1199 | {0x5cb4, 0x75}, | |
1200 | {0x5cb5, 0x75}, | |
1201 | {0x5cb6, 0x75}, | |
1202 | {0x5cb7, 0x75}, | |
1203 | {0x5cb8, 0x75}, | |
1204 | {0x5cb9, 0x75}, | |
1205 | {0x5cba, 0x75}, | |
1206 | {0x5cbb, 0x75}, | |
1207 | {0x5cbc, 0x75}, | |
1208 | {0x5cbd, 0x75}, | |
1209 | {0x5cbe, 0x75}, | |
1210 | {0x5cbf, 0x75}, | |
1211 | {0x5cc0, 0x75}, | |
1212 | {0x5cc1, 0x75}, | |
1213 | {0x5cc2, 0x75}, | |
1214 | {0x5cc3, 0x75}, | |
1215 | {0x5cc4, 0x75}, | |
1216 | {0x5cc5, 0x75}, | |
1217 | {0x5cc6, 0x75}, | |
1218 | {0x5cc7, 0x75}, | |
1219 | {0x5cc8, 0x75}, | |
1220 | {0x5cc9, 0x75}, | |
1221 | {0x5cca, 0x75}, | |
1222 | {0x5ccb, 0x75}, | |
1223 | {0x5ccc, 0x75}, | |
1224 | {0x5ccd, 0x75}, | |
1225 | {0x5cce, 0x75}, | |
1226 | {0x5ccf, 0x75}, | |
1227 | {0x5cd0, 0x75}, | |
1228 | {0x5cd1, 0x75}, | |
1229 | {0x5cd2, 0x75}, | |
1230 | {0x5cd3, 0x75}, | |
1231 | {0x5cd4, 0x75}, | |
1232 | {0x5cd5, 0x75}, | |
1233 | {0x5cd6, 0x75}, | |
1234 | {0x5cd7, 0x75}, | |
1235 | {0x5cd8, 0x75}, | |
1236 | {0x5cd9, 0x75}, | |
1237 | {0x5cda, 0x75}, | |
1238 | {0x5cdb, 0x75}, | |
1239 | {0x5cdc, 0x75}, | |
1240 | {0x5cdd, 0x75}, | |
1241 | {0x5cde, 0x75}, | |
1242 | {0x5cdf, 0x75}, | |
1243 | {0x5ce0, 0x75}, | |
1244 | {0x5ce1, 0x75}, | |
1245 | {0x5ce2, 0x75}, | |
1246 | {0x5ce3, 0x75}, | |
1247 | {0x5ce4, 0x75}, | |
1248 | {0x5ce5, 0x75}, | |
1249 | {0x5ce6, 0x75}, | |
1250 | {0x5ce7, 0x75}, | |
1251 | {0x5ce8, 0x75}, | |
1252 | {0x5ce9, 0x75}, | |
1253 | {0x5cea, 0x75}, | |
1254 | {0x5ceb, 0x75}, | |
1255 | {0x5cec, 0x75}, | |
1256 | {0x5ced, 0x75}, | |
1257 | {0x5cee, 0x75}, | |
1258 | {0x5cef, 0x75}, | |
1259 | {0x5cf0, 0x75}, | |
1260 | {0x5cf1, 0x75}, | |
1261 | {0x5cf2, 0x75}, | |
1262 | {0x5cf3, 0x75}, | |
1263 | {0x5cf4, 0x75}, | |
1264 | {0x5cf5, 0x75}, | |
1265 | {0x5cf6, 0x75}, | |
1266 | {0x5cf7, 0x75}, | |
1267 | {0x5cf8, 0x75}, | |
1268 | {0x5cf9, 0x75}, | |
1269 | {0x5cfa, 0x75}, | |
1270 | {0x5cfb, 0x75}, | |
1271 | {0x5cfc, 0x75}, | |
1272 | {0x5cfd, 0x75}, | |
1273 | {0x5cfe, 0x75}, | |
1274 | {0x5cff, 0x75}, | |
1275 | {0x5d00, 0x75}, | |
1276 | {0x5d01, 0x75}, | |
1277 | {0x5d02, 0x75}, | |
1278 | {0x5d03, 0x75}, | |
1279 | {0x5d04, 0x75}, | |
1280 | {0x5d05, 0x75}, | |
1281 | {0x5d06, 0x75}, | |
1282 | {0x5d07, 0x75}, | |
1283 | {0x5d08, 0x75}, | |
1284 | {0x5d09, 0x75}, | |
1285 | {0x5d0a, 0x75}, | |
1286 | {0x5d0b, 0x75}, | |
1287 | {0x5d0c, 0x75}, | |
1288 | {0x5d0d, 0x75}, | |
1289 | {0x5d0e, 0x75}, | |
1290 | {0x5d0f, 0x75}, | |
1291 | {0x5d10, 0x75}, | |
1292 | {0x5d11, 0x75}, | |
1293 | {0x5d12, 0x75}, | |
1294 | {0x5d13, 0x75}, | |
1295 | {0x5d14, 0x75}, | |
1296 | {0x5d15, 0x75}, | |
1297 | {0x5d16, 0x75}, | |
1298 | {0x5d17, 0x75}, | |
1299 | {0x5d18, 0x75}, | |
1300 | {0x5d19, 0x75}, | |
1301 | {0x5d1a, 0x75}, | |
1302 | {0x5d1b, 0x75}, | |
1303 | {0x5d1c, 0x75}, | |
1304 | {0x5d1d, 0x75}, | |
1305 | {0x5d1e, 0x75}, | |
1306 | {0x5d1f, 0x75}, | |
1307 | {0x5d20, 0x75}, | |
1308 | {0x5d21, 0x75}, | |
1309 | {0x5d22, 0x75}, | |
1310 | {0x5d23, 0x75}, | |
1311 | {0x5d24, 0x75}, | |
1312 | {0x5d25, 0x75}, | |
1313 | {0x5d26, 0x75}, | |
1314 | {0x5d27, 0x75}, | |
1315 | {0x5d28, 0x75}, | |
1316 | {0x5d29, 0x75}, | |
1317 | {0x5d2a, 0x75}, | |
1318 | {0x5d2b, 0x75}, | |
1319 | {0x5d2c, 0x75}, | |
1320 | {0x5d2d, 0x75}, | |
1321 | {0x5d2e, 0x75}, | |
1322 | {0x5d2f, 0x75}, | |
1323 | {0x5d30, 0x75}, | |
1324 | {0x5d31, 0x75}, | |
1325 | {0x5d32, 0x75}, | |
1326 | {0x5d33, 0x75}, | |
1327 | {0x5d34, 0x75}, | |
1328 | {0x5d35, 0x75}, | |
1329 | {0x5d36, 0x75}, | |
1330 | {0x5d37, 0x75}, | |
1331 | {0x5d38, 0x75}, | |
1332 | {0x5d39, 0x75}, | |
1333 | {0x5d3a, 0x75}, | |
1334 | {0x5d3b, 0x75}, | |
1335 | {0x5d3c, 0x75}, | |
1336 | {0x5d3d, 0x75}, | |
1337 | {0x5d3e, 0x75}, | |
1338 | {0x5d3f, 0x75}, | |
1339 | {0x5d40, 0x75}, | |
1340 | {0x5d41, 0x75}, | |
1341 | {0x5d42, 0x75}, | |
1342 | {0x5d43, 0x75}, | |
1343 | {0x5d44, 0x75}, | |
1344 | {0x5d45, 0x75}, | |
1345 | {0x5d46, 0x75}, | |
1346 | {0x5d47, 0x75}, | |
1347 | {0x5d48, 0x75}, | |
1348 | {0x5d49, 0x75}, | |
1349 | {0x5d4a, 0x75}, | |
1350 | {0x5d4b, 0x75}, | |
1351 | {0x5d4c, 0x75}, | |
1352 | {0x5d4d, 0x75}, | |
1353 | {0x5d4e, 0x75}, | |
1354 | {0x5d4f, 0x75}, | |
1355 | {0x5d50, 0x75}, | |
1356 | {0x5d51, 0x75}, | |
1357 | {0x5d52, 0x75}, | |
1358 | {0x5d53, 0x75}, | |
1359 | {0x5d54, 0x75}, | |
1360 | {0x5d55, 0x75}, | |
1361 | {0x5d56, 0x75}, | |
1362 | {0x5d57, 0x75}, | |
1363 | {0x5d58, 0x75}, | |
1364 | {0x5d59, 0x75}, | |
1365 | {0x5d5a, 0x75}, | |
1366 | {0x5d5b, 0x75}, | |
1367 | {0x5d5c, 0x75}, | |
1368 | {0x5d5d, 0x75}, | |
1369 | {0x5d5e, 0x75}, | |
1370 | {0x5d5f, 0x75}, | |
1371 | {0x5d60, 0x75}, | |
1372 | {0x5d61, 0x75}, | |
1373 | {0x5d62, 0x75}, | |
1374 | {0x5d63, 0x75}, | |
1375 | {0x5d64, 0x75}, | |
1376 | {0x5d65, 0x75}, | |
1377 | {0x5d66, 0x75}, | |
1378 | {0x5d67, 0x75}, | |
1379 | {0x5d68, 0x75}, | |
1380 | {0x5d69, 0x75}, | |
1381 | {0x5d6a, 0x75}, | |
1382 | {0x5d6b, 0x75}, | |
1383 | {0x5d6c, 0x75}, | |
1384 | {0x5d6d, 0x75}, | |
1385 | {0x5d6e, 0x75}, | |
1386 | {0x5d6f, 0x75}, | |
1387 | {0x5d70, 0x75}, | |
1388 | {0x5d71, 0x75}, | |
1389 | {0x5d72, 0x75}, | |
1390 | {0x5d73, 0x75}, | |
1391 | {0x5d74, 0x75}, | |
1392 | {0x5d75, 0x75}, | |
1393 | {0x5d76, 0x75}, | |
1394 | {0x5d77, 0x75}, | |
1395 | {0x5d78, 0x75}, | |
1396 | {0x5d79, 0x75}, | |
1397 | {0x5d7a, 0x75}, | |
1398 | {0x5d7b, 0x75}, | |
1399 | {0x5d7c, 0x75}, | |
1400 | {0x5d7d, 0x75}, | |
1401 | {0x5d7e, 0x75}, | |
1402 | {0x5d7f, 0x75}, | |
1403 | {0x5d80, 0x75}, | |
1404 | {0x5d81, 0x75}, | |
1405 | {0x5d82, 0x75}, | |
1406 | {0x5d83, 0x75}, | |
1407 | {0x5d84, 0x75}, | |
1408 | {0x5d85, 0x75}, | |
1409 | {0x5d86, 0x75}, | |
1410 | {0x5d87, 0x75}, | |
1411 | {0x5d88, 0x75}, | |
1412 | {0x5d89, 0x75}, | |
1413 | {0x5d8a, 0x75}, | |
1414 | {0x5d8b, 0x75}, | |
1415 | {0x5d8c, 0x75}, | |
1416 | {0x5d8d, 0x75}, | |
1417 | {0x5d8e, 0x75}, | |
1418 | {0x5d8f, 0x75}, | |
1419 | {0x5d90, 0x75}, | |
1420 | {0x5d91, 0x75}, | |
1421 | {0x5d92, 0x75}, | |
1422 | {0x5d93, 0x75}, | |
1423 | {0x5d94, 0x75}, | |
1424 | {0x5d95, 0x75}, | |
1425 | {0x5d96, 0x75}, | |
1426 | {0x5d97, 0x75}, | |
1427 | {0x5d98, 0x75}, | |
1428 | {0x5d99, 0x75}, | |
1429 | {0x5d9a, 0x75}, | |
1430 | {0x5d9b, 0x75}, | |
1431 | {0x5d9c, 0x75}, | |
1432 | {0x5d9d, 0x75}, | |
1433 | {0x5d9e, 0x75}, | |
1434 | {0x5d9f, 0x75}, | |
1435 | {0x5da0, 0x75}, | |
1436 | {0x5da1, 0x75}, | |
1437 | {0x5da2, 0x75}, | |
1438 | {0x5da3, 0x75}, | |
1439 | {0x5da4, 0x75}, | |
1440 | {0x5da5, 0x75}, | |
1441 | {0x5da6, 0x75}, | |
1442 | {0x5da7, 0x75}, | |
1443 | {0x5da8, 0x75}, | |
1444 | {0x5da9, 0x75}, | |
1445 | {0x5daa, 0x75}, | |
1446 | {0x5dab, 0x75}, | |
1447 | {0x5dac, 0x75}, | |
1448 | {0x5dad, 0x75}, | |
1449 | {0x5dae, 0x75}, | |
1450 | {0x5daf, 0x75}, | |
1451 | {0x5db0, 0x75}, | |
1452 | {0x5db1, 0x75}, | |
1453 | {0x5db2, 0x75}, | |
1454 | {0x5db3, 0x75}, | |
1455 | {0x5db4, 0x75}, | |
1456 | {0x5db5, 0x75}, | |
1457 | {0x5db6, 0x75}, | |
1458 | {0x5db7, 0x75}, | |
1459 | {0x5db8, 0x75}, | |
1460 | {0x5db9, 0x75}, | |
1461 | {0x5dba, 0x75}, | |
1462 | {0x5dbb, 0x75}, | |
1463 | {0x5dbc, 0x75}, | |
1464 | {0x5dbd, 0x75}, | |
1465 | {0x5dbe, 0x75}, | |
1466 | {0x5dbf, 0x75}, | |
1467 | {0x5dc0, 0x75}, | |
1468 | {0x5dc1, 0x75}, | |
1469 | {0x5dc2, 0x75}, | |
1470 | {0x5dc3, 0x75}, | |
1471 | {0x5dc4, 0x75}, | |
1472 | {0x5dc5, 0x75}, | |
1473 | {0x5dc6, 0x75}, | |
1474 | {0x5dc7, 0x75}, | |
1475 | {0x5dc8, 0x75}, | |
1476 | {0x5dc9, 0x75}, | |
1477 | {0x5dca, 0x75}, | |
1478 | {0x5dcb, 0x75}, | |
1479 | {0x5dcc, 0x75}, | |
1480 | {0x5dcd, 0x75}, | |
1481 | {0x5dce, 0x75}, | |
1482 | {0x5dcf, 0x75}, | |
1483 | {0x5dd0, 0x75}, | |
1484 | {0x5dd1, 0x75}, | |
1485 | {0x5dd2, 0x75}, | |
1486 | {0x5dd3, 0x75}, | |
1487 | {0x5dd4, 0x75}, | |
1488 | {0x5dd5, 0x75}, | |
1489 | {0x5dd6, 0x75}, | |
1490 | {0x5dd7, 0x75}, | |
1491 | {0x5dd8, 0x75}, | |
1492 | {0x5dd9, 0x75}, | |
1493 | {0x5dda, 0x75}, | |
1494 | {0x5ddb, 0x75}, | |
1495 | {0x5ddc, 0x75}, | |
1496 | {0x5ddd, 0x75}, | |
1497 | {0x5dde, 0x75}, | |
1498 | {0x5ddf, 0x75}, | |
1499 | {0x5de0, 0x75}, | |
1500 | {0x5de1, 0x75}, | |
1501 | {0x5de2, 0x75}, | |
1502 | {0x5de3, 0x75}, | |
1503 | {0x5de4, 0x75}, | |
1504 | {0x5de5, 0x75}, | |
1505 | {0x5de6, 0x75}, | |
1506 | {0x5de7, 0x75}, | |
1507 | {0x5de8, 0x75}, | |
1508 | {0x5de9, 0x75}, | |
1509 | {0x5dea, 0x75}, | |
1510 | {0x5deb, 0x75}, | |
1511 | {0x5dec, 0x75}, | |
1512 | {0x5ded, 0x75}, | |
1513 | {0x5dee, 0x75}, | |
1514 | {0x5def, 0x75}, | |
1515 | {0x5df0, 0x75}, | |
1516 | {0x5df1, 0x75}, | |
1517 | {0x5df2, 0x75}, | |
1518 | {0x5df3, 0x75}, | |
1519 | {0x5df4, 0x75}, | |
1520 | {0x5df5, 0x75}, | |
1521 | {0x5df6, 0x75}, | |
1522 | {0x5df7, 0x75}, | |
1523 | {0x5df8, 0x75}, | |
1524 | {0x5df9, 0x75}, | |
1525 | {0x5dfa, 0x75}, | |
1526 | {0x5dfb, 0x75}, | |
1527 | {0x5dfc, 0x75}, | |
1528 | {0x5dfd, 0x75}, | |
1529 | {0x5dfe, 0x75}, | |
1530 | {0x5dff, 0x75}, | |
1531 | {0x5e00, 0x75}, | |
1532 | {0x5e01, 0x75}, | |
1533 | {0x5e02, 0x75}, | |
1534 | {0x5e03, 0x75}, | |
1535 | {0x5e04, 0x75}, | |
1536 | {0x5e05, 0x75}, | |
1537 | {0x5e06, 0x75}, | |
1538 | {0x5e07, 0x75}, | |
1539 | {0x5e08, 0x75}, | |
1540 | {0x5e09, 0x75}, | |
1541 | {0x5e0a, 0x75}, | |
1542 | {0x5e0b, 0x75}, | |
1543 | {0x5e0c, 0x75}, | |
1544 | {0x5e0d, 0x75}, | |
1545 | {0x5e0e, 0x75}, | |
1546 | {0x5e0f, 0x75}, | |
1547 | {0x5e10, 0x75}, | |
1548 | {0x5e11, 0x75}, | |
1549 | {0x5e12, 0x75}, | |
1550 | {0x5e13, 0x75}, | |
1551 | {0x5e14, 0x75}, | |
1552 | {0x5e15, 0x75}, | |
1553 | {0x5e16, 0x75}, | |
1554 | {0x5e17, 0x75}, | |
1555 | {0x5e18, 0x75}, | |
1556 | {0x5e19, 0x75}, | |
1557 | {0x5e1a, 0x75}, | |
1558 | {0x5e1b, 0x75}, | |
1559 | {0x5e1c, 0x75}, | |
1560 | {0x5e1d, 0x75}, | |
1561 | {0x5e1e, 0x75}, | |
1562 | {0x5e1f, 0x75}, | |
1563 | {0x5e20, 0x75}, | |
1564 | {0x5e21, 0x75}, | |
1565 | {0x5e22, 0x75}, | |
1566 | {0x5e23, 0x75}, | |
1567 | {0x5e24, 0x75}, | |
1568 | {0x5e25, 0x75}, | |
1569 | {0x5e26, 0x75}, | |
1570 | {0x5e27, 0x75}, | |
1571 | {0x5e28, 0x75}, | |
1572 | {0x5e29, 0x75}, | |
1573 | {0x5e2a, 0x75}, | |
1574 | {0x5e2b, 0x75}, | |
1575 | {0x5e2c, 0x75}, | |
1576 | {0x5e2d, 0x75}, | |
1577 | {0x5e2e, 0x75}, | |
1578 | {0x5e2f, 0x75}, | |
1579 | {0x5e30, 0x75}, | |
1580 | {0x5e31, 0x75}, | |
1581 | {0x5e32, 0x75}, | |
1582 | {0x5e33, 0x75}, | |
1583 | {0x5e34, 0x75}, | |
1584 | {0x5e35, 0x75}, | |
1585 | {0x5e36, 0x75}, | |
1586 | {0x5e37, 0x75}, | |
1587 | {0x5e38, 0x75}, | |
1588 | {0x5e39, 0x75}, | |
1589 | {0x5e3a, 0x75}, | |
1590 | {0x5e3b, 0x75}, | |
1591 | {0x5e3c, 0x75}, | |
1592 | {0x5e3d, 0x75}, | |
1593 | {0x5e3e, 0x75}, | |
1594 | {0x5e3f, 0x75}, | |
1595 | {0x5e40, 0x75}, | |
1596 | {0x5e41, 0x75}, | |
1597 | {0x5e42, 0x75}, | |
1598 | {0x5e43, 0x75}, | |
1599 | {0x5e44, 0x75}, | |
1600 | {0x5e45, 0x75}, | |
1601 | {0x5e46, 0x75}, | |
1602 | {0x5e47, 0x75}, | |
1603 | {0x5e48, 0x75}, | |
1604 | {0x5e49, 0x75}, | |
1605 | {0x5e4a, 0x75}, | |
1606 | {0x5e4b, 0x75}, | |
1607 | {0x5e4c, 0x75}, | |
1608 | {0x5e4d, 0x75}, | |
1609 | {0x5e4e, 0x75}, | |
1610 | {0x5e4f, 0x75}, | |
1611 | {0x5e50, 0x75}, | |
1612 | {0x5e51, 0x75}, | |
1613 | {0x5e52, 0x75}, | |
1614 | {0x5e53, 0x75}, | |
1615 | {0x5e54, 0x75}, | |
1616 | {0x5e55, 0x75}, | |
1617 | {0x5e56, 0x75}, | |
1618 | {0x5e57, 0x75}, | |
1619 | {0x5e58, 0x75}, | |
1620 | {0x5e59, 0x75}, | |
1621 | {0x5e5a, 0x75}, | |
1622 | {0x5e5b, 0x75}, | |
1623 | {0x5e5c, 0x75}, | |
1624 | {0x5e5d, 0x75}, | |
1625 | {0x5e5e, 0x75}, | |
1626 | {0x5e5f, 0x75}, | |
1627 | {0x5e60, 0x75}, | |
1628 | {0x5e61, 0x75}, | |
1629 | {0x5e62, 0x75}, | |
1630 | {0x5e63, 0x75}, | |
1631 | {0x5e64, 0x75}, | |
1632 | {0x5e65, 0x75}, | |
1633 | {0x5e66, 0x75}, | |
1634 | {0x5e67, 0x75}, | |
1635 | {0x5e68, 0x75}, | |
1636 | {0x5e69, 0x75}, | |
1637 | {0x5e6a, 0x75}, | |
1638 | {0x5e6b, 0x75}, | |
1639 | {0x5e6c, 0x75}, | |
1640 | {0x5e6d, 0x75}, | |
1641 | {0x5e6e, 0x75}, | |
1642 | {0x5e6f, 0x75}, | |
1643 | {0x5e70, 0x75}, | |
1644 | {0x5e71, 0x75}, | |
1645 | {0x5e72, 0x75}, | |
1646 | {0x5e73, 0x75}, | |
1647 | {0x5e74, 0x75}, | |
1648 | {0x5e75, 0x75}, | |
1649 | {0x5e76, 0x75}, | |
1650 | {0x5e77, 0x75}, | |
1651 | {0x5e78, 0x75}, | |
1652 | {0x5e79, 0x75}, | |
1653 | {0x5e7a, 0x75}, | |
1654 | {0x5e7b, 0x75}, | |
1655 | {0x5e7c, 0x75}, | |
1656 | {0x5e7d, 0x75}, | |
1657 | {0x5e7e, 0x75}, | |
1658 | {0x5e7f, 0x75}, | |
1659 | {0x5e80, 0x75}, | |
1660 | {0x5e81, 0x75}, | |
1661 | {0x5e82, 0x75}, | |
1662 | {0x5e83, 0x75}, | |
1663 | {0x5e84, 0x75}, | |
1664 | {0x5e85, 0x75}, | |
1665 | {0x5e86, 0x75}, | |
1666 | {0x5e87, 0x75}, | |
1667 | {0x5e88, 0x75}, | |
1668 | {0x5e89, 0x75}, | |
1669 | {0x5e8a, 0x75}, | |
1670 | {0x5e8b, 0x75}, | |
1671 | {0x5e8c, 0x75}, | |
1672 | {0x5e8d, 0x75}, | |
1673 | {0x5e8e, 0x75}, | |
1674 | {0x5e8f, 0x75}, | |
1675 | {0x5e90, 0x75}, | |
1676 | {0x5e91, 0x75}, | |
1677 | {0x5e92, 0x75}, | |
1678 | {0x5e93, 0x75}, | |
1679 | {0x5e94, 0x75}, | |
1680 | {0x5e95, 0x75}, | |
1681 | {0x5e96, 0x75}, | |
1682 | {0x5e97, 0x75}, | |
1683 | {0x5e98, 0x75}, | |
1684 | {0x5e99, 0x75}, | |
1685 | {0x5e9a, 0x75}, | |
1686 | {0x5e9b, 0x75}, | |
1687 | {0x5e9c, 0x75}, | |
1688 | {0x5e9d, 0x75}, | |
1689 | {0x5e9e, 0x75}, | |
1690 | {0x5e9f, 0x75}, | |
1691 | {0x5ea0, 0x75}, | |
1692 | {0x5ea1, 0x75}, | |
1693 | {0x5ea2, 0x75}, | |
1694 | {0x5ea3, 0x75}, | |
1695 | {0x5ea4, 0x75}, | |
1696 | {0x5ea5, 0x75}, | |
1697 | {0x5ea6, 0x75}, | |
1698 | {0x5ea7, 0x75}, | |
1699 | {0x5ea8, 0x75}, | |
1700 | {0x5ea9, 0x75}, | |
1701 | {0x5eaa, 0x75}, | |
1702 | {0x5eab, 0x75}, | |
1703 | {0x5eac, 0x75}, | |
1704 | {0x5ead, 0x75}, | |
1705 | {0x5eae, 0x75}, | |
1706 | {0x5eaf, 0x75}, | |
1707 | {0x5eb0, 0x75}, | |
1708 | {0x5eb1, 0x75}, | |
1709 | {0x5eb2, 0x75}, | |
1710 | {0x5eb3, 0x75}, | |
1711 | {0x5eb4, 0x75}, | |
1712 | {0x5eb5, 0x75}, | |
1713 | {0x5eb6, 0x75}, | |
1714 | {0x5eb7, 0x75}, | |
1715 | {0x5eb8, 0x75}, | |
1716 | {0x5eb9, 0x75}, | |
1717 | {0x5eba, 0x75}, | |
1718 | {0x5ebb, 0x75}, | |
1719 | {0x5ebc, 0x75}, | |
1720 | {0x5ebd, 0x75}, | |
1721 | {0x5ebe, 0x75}, | |
1722 | {0x5ebf, 0x75}, | |
1723 | {0x5ec0, 0x75}, | |
1724 | {0x5ec1, 0x75}, | |
1725 | {0x5ec2, 0x75}, | |
1726 | {0x5ec3, 0x75}, | |
1727 | {0x5ec4, 0x75}, | |
1728 | {0x5ec5, 0x75}, | |
1729 | {0x5ec6, 0x75}, | |
1730 | {0x5ec7, 0x75}, | |
1731 | {0x5ec8, 0x75}, | |
1732 | {0x5ec9, 0x75}, | |
1733 | {0x5eca, 0x75}, | |
1734 | {0x5ecb, 0x75}, | |
1735 | {0x5ecc, 0x75}, | |
1736 | {0x5ecd, 0x75}, | |
1737 | {0x5ece, 0x75}, | |
1738 | {0x5ecf, 0x75}, | |
1739 | {0x5ed0, 0x75}, | |
1740 | {0x5ed1, 0x75}, | |
1741 | {0x5ed2, 0x75}, | |
1742 | {0x5ed3, 0x75}, | |
1743 | {0x5ed4, 0x75}, | |
1744 | {0x5ed5, 0x75}, | |
1745 | {0x5ed6, 0x75}, | |
1746 | {0x5ed7, 0x75}, | |
1747 | {0x5ed8, 0x75}, | |
1748 | {0x5ed9, 0x75}, | |
1749 | {0x5eda, 0x75}, | |
1750 | {0x5edb, 0x75}, | |
1751 | {0x5edc, 0x75}, | |
1752 | {0x5edd, 0x75}, | |
1753 | {0x5ede, 0x75}, | |
1754 | {0x5edf, 0x75}, | |
1755 | {0x5ee0, 0x75}, | |
1756 | {0x5ee1, 0x75}, | |
1757 | {0x5ee2, 0x75}, | |
1758 | {0x5ee3, 0x75}, | |
1759 | {0x5ee4, 0x75}, | |
1760 | {0x5ee5, 0x75}, | |
1761 | {0x5ee6, 0x75}, | |
1762 | {0x5ee7, 0x75}, | |
1763 | {0x5ee8, 0x75}, | |
1764 | {0x5ee9, 0x75}, | |
1765 | {0x5eea, 0x75}, | |
1766 | {0x5eeb, 0x75}, | |
1767 | {0x5eec, 0x75}, | |
1768 | {0x5eed, 0x75}, | |
1769 | {0x5eee, 0x75}, | |
1770 | {0x5eef, 0x75}, | |
1771 | {0x5ef0, 0x75}, | |
1772 | {0x5ef1, 0x75}, | |
1773 | {0x5ef2, 0x75}, | |
1774 | {0x5ef3, 0x75}, | |
1775 | {0x5ef4, 0x75}, | |
1776 | {0x5ef5, 0x75}, | |
1777 | {0x5ef6, 0x75}, | |
1778 | {0x5ef7, 0x75}, | |
1779 | {0x5ef8, 0x75}, | |
1780 | {0x5ef9, 0x75}, | |
1781 | {0x5efa, 0x75}, | |
1782 | {0x5efb, 0x75}, | |
1783 | {0x5efc, 0x75}, | |
1784 | {0x5efd, 0x75}, | |
1785 | {0x5efe, 0x75}, | |
1786 | {0x5eff, 0x75}, | |
1787 | {0x5f00, 0x75}, | |
1788 | {0x5f01, 0x75}, | |
1789 | {0x5f02, 0x75}, | |
1790 | {0x5f03, 0x75}, | |
1791 | {0x5f04, 0x75}, | |
1792 | {0x5f05, 0x75}, | |
1793 | {0x5f06, 0x75}, | |
1794 | {0x5f07, 0x75}, | |
1795 | {0x5f08, 0x75}, | |
1796 | {0x5f09, 0x75}, | |
1797 | {0x5f0a, 0x75}, | |
1798 | {0x5f0b, 0x75}, | |
1799 | {0x5f0c, 0x75}, | |
1800 | {0x5f0d, 0x75}, | |
1801 | {0x5f0e, 0x75}, | |
1802 | {0x5f0f, 0x75}, | |
1803 | {0x5f10, 0x75}, | |
1804 | {0x5f11, 0x75}, | |
1805 | {0x5f12, 0x75}, | |
1806 | {0x5f13, 0x75}, | |
1807 | {0x5f14, 0x75}, | |
1808 | {0x5f15, 0x75}, | |
1809 | {0x5f16, 0x75}, | |
1810 | {0x5f17, 0x75}, | |
1811 | {0x5f18, 0x75}, | |
1812 | {0x5f19, 0x75}, | |
1813 | {0x5f1a, 0x75}, | |
1814 | {0x5f1b, 0x75}, | |
1815 | {0x5f1c, 0x75}, | |
1816 | {0x5f1d, 0x75}, | |
1817 | {0x5f1e, 0x75}, | |
1818 | {0x5f1f, 0x75}, | |
1819 | }; | |
1820 | ||
1821 | static const struct ov08x40_reg mode_1928x1208_regs[] = { | |
1822 | {0x5000, 0x55}, | |
1823 | {0x5001, 0x00}, | |
1824 | {0x5008, 0xb0}, | |
1825 | {0x50c1, 0x00}, | |
1826 | {0x53c1, 0x00}, | |
1827 | {0x5f40, 0x00}, | |
1828 | {0x5f41, 0x40}, | |
1829 | {0x0300, 0x3a}, | |
1830 | {0x0301, 0xc8}, | |
1831 | {0x0302, 0x31}, | |
1832 | {0x0303, 0x03}, | |
1833 | {0x0304, 0x01}, | |
1834 | {0x0305, 0xa1}, | |
1835 | {0x0306, 0x04}, | |
1836 | {0x0307, 0x01}, | |
1837 | {0x0308, 0x03}, | |
1838 | {0x0309, 0x03}, | |
1839 | {0x0310, 0x0a}, | |
1840 | {0x0311, 0x02}, | |
1841 | {0x0312, 0x01}, | |
1842 | {0x0313, 0x08}, | |
1843 | {0x0314, 0x66}, | |
1844 | {0x0315, 0x00}, | |
1845 | {0x0316, 0x34}, | |
1846 | {0x0320, 0x02}, | |
1847 | {0x0321, 0x03}, | |
1848 | {0x0323, 0x05}, | |
1849 | {0x0324, 0x01}, | |
1850 | {0x0325, 0xb8}, | |
1851 | {0x0326, 0x4a}, | |
1852 | {0x0327, 0x04}, | |
1853 | {0x0329, 0x00}, | |
1854 | {0x032a, 0x05}, | |
1855 | {0x032b, 0x00}, | |
1856 | {0x032c, 0x00}, | |
1857 | {0x032d, 0x00}, | |
1858 | {0x032e, 0x02}, | |
1859 | {0x032f, 0xa0}, | |
1860 | {0x0350, 0x00}, | |
1861 | {0x0360, 0x01}, | |
1862 | {0x1216, 0x60}, | |
1863 | {0x1217, 0x5b}, | |
1864 | {0x1218, 0x00}, | |
1865 | {0x1220, 0x24}, | |
1866 | {0x198a, 0x00}, | |
1867 | {0x198b, 0x01}, | |
1868 | {0x198e, 0x00}, | |
1869 | {0x198f, 0x01}, | |
1870 | {0x3009, 0x04}, | |
1871 | {0x3012, 0x41}, | |
1872 | {0x3015, 0x00}, | |
1873 | {0x3016, 0xb0}, | |
1874 | {0x3017, 0xf0}, | |
1875 | {0x3018, 0xf0}, | |
1876 | {0x3019, 0xd2}, | |
1877 | {0x301a, 0xb0}, | |
1878 | {0x301c, 0x81}, | |
1879 | {0x301d, 0x02}, | |
1880 | {0x301e, 0x80}, | |
1881 | {0x3022, 0xf0}, | |
1882 | {0x3025, 0x89}, | |
1883 | {0x3030, 0x03}, | |
1884 | {0x3044, 0xc2}, | |
1885 | {0x3050, 0x35}, | |
1886 | {0x3051, 0x60}, | |
1887 | {0x3052, 0x25}, | |
1888 | {0x3053, 0x00}, | |
1889 | {0x3054, 0x00}, | |
1890 | {0x3055, 0x02}, | |
1891 | {0x3056, 0x80}, | |
1892 | {0x3057, 0x80}, | |
1893 | {0x3058, 0x80}, | |
1894 | {0x3059, 0x00}, | |
1895 | {0x3107, 0x86}, | |
1896 | {0x3400, 0x1c}, | |
1897 | {0x3401, 0x80}, | |
1898 | {0x3402, 0x8c}, | |
1899 | {0x3419, 0x08}, | |
1900 | {0x341a, 0xaf}, | |
1901 | {0x341b, 0x30}, | |
1902 | {0x3420, 0x00}, | |
1903 | {0x3421, 0x00}, | |
1904 | {0x3422, 0x00}, | |
1905 | {0x3423, 0x00}, | |
1906 | {0x3424, 0x00}, | |
1907 | {0x3425, 0x00}, | |
1908 | {0x3426, 0x00}, | |
1909 | {0x3427, 0x00}, | |
1910 | {0x3428, 0x0f}, | |
1911 | {0x3429, 0x00}, | |
1912 | {0x342a, 0x00}, | |
1913 | {0x342b, 0x00}, | |
1914 | {0x342c, 0x00}, | |
1915 | {0x342d, 0x00}, | |
1916 | {0x342e, 0x00}, | |
1917 | {0x342f, 0x11}, | |
1918 | {0x3430, 0x11}, | |
1919 | {0x3431, 0x10}, | |
1920 | {0x3432, 0x00}, | |
1921 | {0x3433, 0x00}, | |
1922 | {0x3434, 0x00}, | |
1923 | {0x3435, 0x00}, | |
1924 | {0x3436, 0x00}, | |
1925 | {0x3437, 0x00}, | |
1926 | {0x3442, 0x02}, | |
1927 | {0x3443, 0x02}, | |
1928 | {0x3444, 0x07}, | |
1929 | {0x3450, 0x00}, | |
1930 | {0x3451, 0x00}, | |
1931 | {0x3452, 0x18}, | |
1932 | {0x3453, 0x18}, | |
1933 | {0x3454, 0x00}, | |
1934 | {0x3455, 0x80}, | |
1935 | {0x3456, 0x08}, | |
1936 | {0x3500, 0x00}, | |
1937 | {0x3501, 0x02}, | |
1938 | {0x3502, 0x00}, | |
1939 | {0x3504, 0x4c}, | |
1940 | {0x3506, 0x30}, | |
1941 | {0x3507, 0x00}, | |
1942 | {0x3508, 0x01}, | |
1943 | {0x3509, 0x00}, | |
1944 | {0x350a, 0x01}, | |
1945 | {0x350b, 0x00}, | |
1946 | {0x350c, 0x00}, | |
1947 | {0x3540, 0x00}, | |
1948 | {0x3541, 0x01}, | |
1949 | {0x3542, 0x00}, | |
1950 | {0x3544, 0x4c}, | |
1951 | {0x3546, 0x30}, | |
1952 | {0x3547, 0x00}, | |
1953 | {0x3548, 0x01}, | |
1954 | {0x3549, 0x00}, | |
1955 | {0x354a, 0x01}, | |
1956 | {0x354b, 0x00}, | |
1957 | {0x354c, 0x00}, | |
1958 | {0x3688, 0x02}, | |
1959 | {0x368a, 0x2e}, | |
1960 | {0x368e, 0x71}, | |
1961 | {0x3696, 0xd1}, | |
1962 | {0x3699, 0x00}, | |
1963 | {0x369a, 0x00}, | |
1964 | {0x36a4, 0x00}, | |
1965 | {0x36a6, 0x00}, | |
1966 | {0x3711, 0x00}, | |
1967 | {0x3712, 0x50}, | |
1968 | {0x3713, 0x00}, | |
1969 | {0x3714, 0x21}, | |
1970 | {0x3716, 0x00}, | |
1971 | {0x3718, 0x07}, | |
1972 | {0x371a, 0x1c}, | |
1973 | {0x371b, 0x00}, | |
1974 | {0x3720, 0x08}, | |
1975 | {0x3725, 0x32}, | |
1976 | {0x3727, 0x05}, | |
1977 | {0x3760, 0x02}, | |
1978 | {0x3761, 0x28}, | |
1979 | {0x3762, 0x02}, | |
1980 | {0x3763, 0x02}, | |
1981 | {0x3764, 0x02}, | |
1982 | {0x3765, 0x2c}, | |
1983 | {0x3766, 0x04}, | |
1984 | {0x3767, 0x2c}, | |
1985 | {0x3768, 0x02}, | |
1986 | {0x3769, 0x00}, | |
1987 | {0x376b, 0x20}, | |
1988 | {0x376e, 0x07}, | |
1989 | {0x37b0, 0x01}, | |
1990 | {0x37b1, 0x0f}, | |
1991 | {0x37b2, 0x01}, | |
1992 | {0x37b3, 0xd6}, | |
1993 | {0x37b4, 0x01}, | |
1994 | {0x37b5, 0x48}, | |
1995 | {0x37b6, 0x02}, | |
1996 | {0x37b7, 0x40}, | |
1997 | {0x3800, 0x00}, | |
1998 | {0x3801, 0x00}, | |
1999 | {0x3802, 0x00}, | |
2000 | {0x3803, 0x00}, | |
2001 | {0x3804, 0x0f}, | |
2002 | {0x3805, 0x1f}, | |
2003 | {0x3806, 0x09}, | |
2004 | {0x3807, 0x7f}, | |
2005 | {0x3808, 0x07}, | |
2006 | {0x3809, 0x88}, | |
2007 | {0x380a, 0x04}, | |
2008 | {0x380b, 0xb8}, | |
2009 | {0x380c, 0x02}, | |
2010 | {0x380d, 0xd0}, | |
2011 | {0x380e, 0x11}, | |
2012 | {0x380f, 0x5c}, | |
2013 | {0x3810, 0x00}, | |
2014 | {0x3811, 0x04}, | |
2015 | {0x3812, 0x00}, | |
2016 | {0x3813, 0x03}, | |
2017 | {0x3814, 0x11}, | |
2018 | {0x3815, 0x11}, | |
2019 | {0x3820, 0x02}, | |
2020 | {0x3821, 0x14}, | |
2021 | {0x3822, 0x00}, | |
2022 | {0x3823, 0x04}, | |
2023 | {0x3828, 0x0f}, | |
2024 | {0x382a, 0x80}, | |
2025 | {0x382e, 0x41}, | |
2026 | {0x3837, 0x08}, | |
2027 | {0x383a, 0x81}, | |
2028 | {0x383b, 0x81}, | |
2029 | {0x383c, 0x11}, | |
2030 | {0x383d, 0x11}, | |
2031 | {0x383e, 0x00}, | |
2032 | {0x383f, 0x38}, | |
2033 | {0x3840, 0x00}, | |
2034 | {0x3847, 0x00}, | |
2035 | {0x384a, 0x00}, | |
2036 | {0x384c, 0x02}, | |
2037 | {0x384d, 0xd0}, | |
2038 | {0x3856, 0x50}, | |
2039 | {0x3857, 0x30}, | |
2040 | {0x3858, 0x80}, | |
2041 | {0x3859, 0x40}, | |
2042 | {0x3860, 0x00}, | |
2043 | {0x3888, 0x00}, | |
2044 | {0x3889, 0x00}, | |
2045 | {0x388a, 0x00}, | |
2046 | {0x388b, 0x00}, | |
2047 | {0x388c, 0x00}, | |
2048 | {0x388d, 0x00}, | |
2049 | {0x388e, 0x00}, | |
2050 | {0x388f, 0x00}, | |
2051 | {0x3894, 0x00}, | |
2052 | {0x3895, 0x00}, | |
2053 | {0x3c84, 0x00}, | |
2054 | {0x3d85, 0x8b}, | |
2055 | {0x3daa, 0x80}, | |
2056 | {0x3dab, 0x14}, | |
2057 | {0x3dac, 0x80}, | |
2058 | {0x3dad, 0xc8}, | |
2059 | {0x3dae, 0x81}, | |
2060 | {0x3daf, 0x7b}, | |
2061 | {0x3f00, 0x10}, | |
2062 | {0x3f01, 0x11}, | |
2063 | {0x3f06, 0x0d}, | |
2064 | {0x3f07, 0x0b}, | |
2065 | {0x3f08, 0x0d}, | |
2066 | {0x3f09, 0x0b}, | |
2067 | {0x3f0a, 0x01}, | |
2068 | {0x3f0b, 0x11}, | |
2069 | {0x3f0c, 0x33}, | |
2070 | {0x4001, 0x07}, | |
2071 | {0x4007, 0x20}, | |
2072 | {0x4008, 0x00}, | |
2073 | {0x4009, 0x05}, | |
2074 | {0x400a, 0x00}, | |
2075 | {0x400b, 0x04}, | |
2076 | {0x400c, 0x00}, | |
2077 | {0x400d, 0x04}, | |
2078 | {0x400e, 0x14}, | |
2079 | {0x4010, 0xf4}, | |
2080 | {0x4011, 0x03}, | |
2081 | {0x4012, 0x55}, | |
2082 | {0x4015, 0x00}, | |
2083 | {0x4016, 0x27}, | |
2084 | {0x4017, 0x00}, | |
2085 | {0x4018, 0x0f}, | |
2086 | {0x401b, 0x08}, | |
2087 | {0x401c, 0x00}, | |
2088 | {0x401d, 0x10}, | |
2089 | {0x401e, 0x02}, | |
2090 | {0x401f, 0x00}, | |
2091 | {0x4050, 0x06}, | |
2092 | {0x4051, 0xff}, | |
2093 | {0x4052, 0xff}, | |
2094 | {0x4053, 0xff}, | |
2095 | {0x4054, 0xff}, | |
2096 | {0x4055, 0xff}, | |
2097 | {0x4056, 0xff}, | |
2098 | {0x4057, 0x7f}, | |
2099 | {0x4058, 0x00}, | |
2100 | {0x4059, 0x00}, | |
2101 | {0x405a, 0x00}, | |
2102 | {0x405b, 0x00}, | |
2103 | {0x405c, 0x07}, | |
2104 | {0x405d, 0xff}, | |
2105 | {0x405e, 0x07}, | |
2106 | {0x405f, 0xff}, | |
2107 | {0x4080, 0x78}, | |
2108 | {0x4081, 0x78}, | |
2109 | {0x4082, 0x78}, | |
2110 | {0x4083, 0x78}, | |
2111 | {0x4019, 0x00}, | |
2112 | {0x401a, 0x40}, | |
2113 | {0x4020, 0x04}, | |
2114 | {0x4021, 0x00}, | |
2115 | {0x4022, 0x04}, | |
2116 | {0x4023, 0x00}, | |
2117 | {0x4024, 0x04}, | |
2118 | {0x4025, 0x00}, | |
2119 | {0x4026, 0x04}, | |
2120 | {0x4027, 0x00}, | |
2121 | {0x4030, 0x00}, | |
2122 | {0x4031, 0x00}, | |
2123 | {0x4032, 0x00}, | |
2124 | {0x4033, 0x00}, | |
2125 | {0x4034, 0x00}, | |
2126 | {0x4035, 0x00}, | |
2127 | {0x4036, 0x00}, | |
2128 | {0x4037, 0x00}, | |
2129 | {0x4040, 0x00}, | |
2130 | {0x4041, 0x80}, | |
2131 | {0x4042, 0x00}, | |
2132 | {0x4043, 0x80}, | |
2133 | {0x4044, 0x00}, | |
2134 | {0x4045, 0x80}, | |
2135 | {0x4046, 0x00}, | |
2136 | {0x4047, 0x80}, | |
2137 | {0x4060, 0x00}, | |
2138 | {0x4061, 0x00}, | |
2139 | {0x4062, 0x00}, | |
2140 | {0x4063, 0x00}, | |
2141 | {0x4064, 0x00}, | |
2142 | {0x4065, 0x00}, | |
2143 | {0x4066, 0x00}, | |
2144 | {0x4067, 0x00}, | |
2145 | {0x4068, 0x00}, | |
2146 | {0x4069, 0x00}, | |
2147 | {0x406a, 0x00}, | |
2148 | {0x406b, 0x00}, | |
2149 | {0x406c, 0x00}, | |
2150 | {0x406d, 0x00}, | |
2151 | {0x406e, 0x00}, | |
2152 | {0x406f, 0x00}, | |
2153 | {0x4070, 0x00}, | |
2154 | {0x4071, 0x00}, | |
2155 | {0x4072, 0x00}, | |
2156 | {0x4073, 0x00}, | |
2157 | {0x4074, 0x00}, | |
2158 | {0x4075, 0x00}, | |
2159 | {0x4076, 0x00}, | |
2160 | {0x4077, 0x00}, | |
2161 | {0x4078, 0x00}, | |
2162 | {0x4079, 0x00}, | |
2163 | {0x407a, 0x00}, | |
2164 | {0x407b, 0x00}, | |
2165 | {0x407c, 0x00}, | |
2166 | {0x407d, 0x00}, | |
2167 | {0x407e, 0x00}, | |
2168 | {0x407f, 0x00}, | |
2169 | {0x40e0, 0x00}, | |
2170 | {0x40e1, 0x00}, | |
2171 | {0x40e2, 0x00}, | |
2172 | {0x40e3, 0x00}, | |
2173 | {0x40e4, 0x00}, | |
2174 | {0x40e5, 0x00}, | |
2175 | {0x40e6, 0x00}, | |
2176 | {0x40e7, 0x00}, | |
2177 | {0x40e8, 0x00}, | |
2178 | {0x40e9, 0x80}, | |
2179 | {0x40ea, 0x00}, | |
2180 | {0x40eb, 0x80}, | |
2181 | {0x40ec, 0x00}, | |
2182 | {0x40ed, 0x80}, | |
2183 | {0x40ee, 0x00}, | |
2184 | {0x40ef, 0x80}, | |
2185 | {0x40f0, 0x02}, | |
2186 | {0x40f1, 0x04}, | |
2187 | {0x4300, 0x00}, | |
2188 | {0x4301, 0x00}, | |
2189 | {0x4302, 0x00}, | |
2190 | {0x4303, 0x00}, | |
2191 | {0x4304, 0x00}, | |
2192 | {0x4305, 0x00}, | |
2193 | {0x4306, 0x00}, | |
2194 | {0x4307, 0x00}, | |
2195 | {0x4308, 0x00}, | |
2196 | {0x4309, 0x00}, | |
2197 | {0x430a, 0x00}, | |
2198 | {0x430b, 0xff}, | |
2199 | {0x430c, 0xff}, | |
2200 | {0x430d, 0x00}, | |
2201 | {0x430e, 0x00}, | |
2202 | {0x4315, 0x00}, | |
2203 | {0x4316, 0x00}, | |
2204 | {0x4317, 0x00}, | |
2205 | {0x4318, 0x00}, | |
2206 | {0x4319, 0x00}, | |
2207 | {0x431a, 0x00}, | |
2208 | {0x431b, 0x00}, | |
2209 | {0x431c, 0x00}, | |
2210 | {0x4500, 0x07}, | |
2211 | {0x4501, 0x10}, | |
2212 | {0x4502, 0x00}, | |
2213 | {0x4503, 0x0f}, | |
2214 | {0x4504, 0x80}, | |
2215 | {0x4506, 0x01}, | |
2216 | {0x4509, 0x05}, | |
2217 | {0x450c, 0x00}, | |
2218 | {0x450d, 0x20}, | |
2219 | {0x450e, 0x00}, | |
2220 | {0x450f, 0x00}, | |
2221 | {0x4510, 0x00}, | |
2222 | {0x4523, 0x00}, | |
2223 | {0x4526, 0x00}, | |
2224 | {0x4542, 0x00}, | |
2225 | {0x4543, 0x00}, | |
2226 | {0x4544, 0x00}, | |
2227 | {0x4545, 0x00}, | |
2228 | {0x4546, 0x00}, | |
2229 | {0x4547, 0x10}, | |
2230 | {0x4602, 0x00}, | |
2231 | {0x4603, 0x15}, | |
2232 | {0x460b, 0x07}, | |
2233 | {0x4680, 0x11}, | |
2234 | {0x4686, 0x00}, | |
2235 | {0x4687, 0x00}, | |
2236 | {0x4700, 0x00}, | |
2237 | {0x4800, 0x64}, | |
2238 | {0x4806, 0x40}, | |
2239 | {0x480b, 0x10}, | |
2240 | {0x480c, 0x80}, | |
2241 | {0x480f, 0x32}, | |
2242 | {0x4813, 0xe4}, | |
2243 | {0x4837, 0x14}, | |
2244 | {0x4850, 0x42}, | |
2245 | {0x4884, 0x04}, | |
2246 | {0x4c00, 0xf8}, | |
2247 | {0x4c01, 0x44}, | |
2248 | {0x4c03, 0x00}, | |
2249 | {0x4d00, 0x00}, | |
2250 | {0x4d01, 0x16}, | |
2251 | {0x4d04, 0x10}, | |
2252 | {0x4d05, 0x00}, | |
2253 | {0x4d06, 0x0c}, | |
2254 | {0x4d07, 0x00}, | |
2255 | {0x3d84, 0x04}, | |
2256 | {0x3680, 0xa4}, | |
2257 | {0x3682, 0x80}, | |
2258 | {0x3601, 0x40}, | |
2259 | {0x3602, 0x90}, | |
2260 | {0x3608, 0x0a}, | |
2261 | {0x3938, 0x09}, | |
2262 | {0x3a74, 0x84}, | |
2263 | {0x3a99, 0x84}, | |
2264 | {0x3ab9, 0xa6}, | |
2265 | {0x3aba, 0xba}, | |
2266 | {0x3b12, 0x84}, | |
2267 | {0x3b14, 0xbb}, | |
2268 | {0x3b15, 0xbf}, | |
2269 | {0x3a29, 0x26}, | |
2270 | {0x3a1f, 0x8a}, | |
2271 | {0x3a22, 0x91}, | |
2272 | {0x3a25, 0x96}, | |
2273 | {0x3a28, 0xb4}, | |
2274 | {0x3a2b, 0xba}, | |
2275 | {0x3a2e, 0xbf}, | |
2276 | {0x3a31, 0xc1}, | |
2277 | {0x3a20, 0x05}, | |
2278 | {0x3939, 0x6b}, | |
2279 | {0x3902, 0x10}, | |
2280 | {0x3903, 0x10}, | |
2281 | {0x3904, 0x10}, | |
2282 | {0x3905, 0x10}, | |
2283 | {0x3906, 0x01}, | |
2284 | {0x3907, 0x0b}, | |
2285 | {0x3908, 0x10}, | |
2286 | {0x3909, 0x13}, | |
2287 | {0x360f, 0x99}, | |
2288 | {0x390b, 0x11}, | |
2289 | {0x390c, 0x21}, | |
2290 | {0x390d, 0x32}, | |
2291 | {0x390e, 0x76}, | |
2292 | {0x3911, 0x90}, | |
2293 | {0x3913, 0x90}, | |
2294 | {0x3b3f, 0x9d}, | |
2295 | {0x3b45, 0x9d}, | |
2296 | {0x3b1b, 0xc9}, | |
2297 | {0x3b21, 0xc9}, | |
2298 | {0x3a1a, 0x1c}, | |
2299 | {0x3a23, 0x15}, | |
2300 | {0x3a26, 0x17}, | |
2301 | {0x3a2c, 0x50}, | |
2302 | {0x3a2f, 0x18}, | |
2303 | {0x3a32, 0x4f}, | |
2304 | {0x3ace, 0x01}, | |
2305 | {0x3ad2, 0x01}, | |
2306 | {0x3ad6, 0x01}, | |
2307 | {0x3ada, 0x01}, | |
2308 | {0x3ade, 0x01}, | |
2309 | {0x3ae2, 0x01}, | |
2310 | {0x3aee, 0x01}, | |
2311 | {0x3af2, 0x01}, | |
2312 | {0x3af6, 0x01}, | |
2313 | {0x3afa, 0x01}, | |
2314 | {0x3afe, 0x01}, | |
2315 | {0x3b02, 0x01}, | |
2316 | {0x3b06, 0x01}, | |
2317 | {0x3b0a, 0x01}, | |
2318 | {0x3b0b, 0x00}, | |
2319 | {0x3b0e, 0x01}, | |
2320 | {0x3b0f, 0x00}, | |
2321 | {0x392c, 0x02}, | |
2322 | {0x392d, 0x01}, | |
2323 | {0x392e, 0x04}, | |
2324 | {0x392f, 0x03}, | |
2325 | {0x3930, 0x09}, | |
2326 | {0x3931, 0x07}, | |
2327 | {0x3932, 0x10}, | |
2328 | {0x3933, 0x0d}, | |
2329 | {0x3609, 0x08}, | |
2330 | {0x3921, 0x0f}, | |
2331 | {0x3928, 0x15}, | |
2332 | {0x3929, 0x2a}, | |
2333 | {0x392a, 0x52}, | |
2334 | {0x392b, 0xa3}, | |
2335 | {0x340b, 0x1b}, | |
2336 | {0x3426, 0x10}, | |
2337 | {0x3407, 0x01}, | |
2338 | {0x3404, 0x01}, | |
2339 | {0x3500, 0x00}, | |
2340 | {0x3501, 0x08}, | |
2341 | {0x3502, 0x10}, | |
2342 | {0x3508, 0x04}, | |
2343 | {0x3509, 0x00}, | |
2344 | }; | |
2345 | ||
2346 | static const char * const ov08x40_test_pattern_menu[] = { | |
2347 | "Disabled", | |
2348 | "Vertical Color Bar Type 1", | |
2349 | "Vertical Color Bar Type 2", | |
2350 | "Vertical Color Bar Type 3", | |
2351 | "Vertical Color Bar Type 4" | |
2352 | }; | |
2353 | ||
2354 | /* Configurations for supported link frequencies */ | |
2355 | #define OV08X40_LINK_FREQ_400MHZ 400000000ULL | |
2356 | ||
2357 | #define OV08X40_EXT_CLK 19200000 | |
2358 | #define OV08X40_DATA_LANES 4 | |
2359 | ||
2360 | /* | |
2361 | * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample | |
2362 | * data rate => double data rate; number of lanes => 4; bits per pixel => 10 | |
2363 | */ | |
2364 | static u64 link_freq_to_pixel_rate(u64 f) | |
2365 | { | |
2366 | f *= 2 * OV08X40_DATA_LANES; | |
2367 | do_div(f, 10); | |
2368 | ||
2369 | return f; | |
2370 | } | |
2371 | ||
2372 | /* Menu items for LINK_FREQ V4L2 control */ | |
2373 | static const s64 link_freq_menu_items[] = { | |
2374 | OV08X40_LINK_FREQ_400MHZ, | |
2375 | }; | |
2376 | ||
2377 | /* Link frequency configs */ | |
2378 | static const struct ov08x40_link_freq_config link_freq_configs[] = { | |
2379 | [OV08X40_LINK_FREQ_400MHZ_INDEX] = { | |
2380 | .reg_list = { | |
2381 | .num_of_regs = ARRAY_SIZE(mipi_data_rate_800mbps), | |
2382 | .regs = mipi_data_rate_800mbps, | |
2383 | } | |
2384 | }, | |
2385 | }; | |
2386 | ||
2387 | /* Mode configs */ | |
2388 | static const struct ov08x40_mode supported_modes[] = { | |
2389 | { | |
2390 | .width = 3856, | |
2391 | .height = 2416, | |
2392 | .vts_def = OV08X40_VTS_30FPS, | |
2393 | .vts_min = OV08X40_VTS_30FPS, | |
2394 | .lanes = 4, | |
2395 | .reg_list = { | |
2396 | .num_of_regs = ARRAY_SIZE(mode_3856x2416_regs), | |
2397 | .regs = mode_3856x2416_regs, | |
2398 | }, | |
2399 | .link_freq_index = OV08X40_LINK_FREQ_400MHZ_INDEX, | |
2400 | }, | |
2401 | { | |
2402 | .width = 1928, | |
2403 | .height = 1208, | |
2404 | .vts_def = OV08X40_VTS_BIN_30FPS, | |
2405 | .vts_min = OV08X40_VTS_BIN_30FPS, | |
2406 | .lanes = 4, | |
2407 | .reg_list = { | |
2408 | .num_of_regs = ARRAY_SIZE(mode_1928x1208_regs), | |
2409 | .regs = mode_1928x1208_regs, | |
2410 | }, | |
2411 | .link_freq_index = OV08X40_LINK_FREQ_400MHZ_INDEX, | |
2412 | }, | |
2413 | }; | |
2414 | ||
2415 | struct ov08x40 { | |
2416 | struct v4l2_subdev sd; | |
2417 | struct media_pad pad; | |
2418 | ||
2419 | struct v4l2_ctrl_handler ctrl_handler; | |
2420 | /* V4L2 Controls */ | |
2421 | struct v4l2_ctrl *link_freq; | |
2422 | struct v4l2_ctrl *pixel_rate; | |
2423 | struct v4l2_ctrl *vblank; | |
2424 | struct v4l2_ctrl *hblank; | |
2425 | struct v4l2_ctrl *exposure; | |
2426 | ||
2427 | /* Current mode */ | |
2428 | const struct ov08x40_mode *cur_mode; | |
2429 | ||
2430 | /* Mutex for serialized access */ | |
2431 | struct mutex mutex; | |
2432 | ||
2433 | /* Streaming on/off */ | |
2434 | bool streaming; | |
2435 | }; | |
2436 | ||
2437 | #define to_ov08x40(_sd) container_of(_sd, struct ov08x40, sd) | |
2438 | ||
2439 | /* Read registers up to 4 at a time */ | |
2440 | static int ov08x40_read_reg(struct ov08x40 *ov08x, | |
2441 | u16 reg, u32 len, u32 *val) | |
2442 | { | |
2443 | struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd); | |
2444 | struct i2c_msg msgs[2]; | |
2445 | u8 *data_be_p; | |
2446 | int ret; | |
2447 | __be32 data_be = 0; | |
2448 | __be16 reg_addr_be = cpu_to_be16(reg); | |
2449 | ||
2450 | if (len > 4) | |
2451 | return -EINVAL; | |
2452 | ||
2453 | data_be_p = (u8 *)&data_be; | |
2454 | /* Write register address */ | |
2455 | msgs[0].addr = client->addr; | |
2456 | msgs[0].flags = 0; | |
2457 | msgs[0].len = 2; | |
2458 | msgs[0].buf = (u8 *)®_addr_be; | |
2459 | ||
2460 | /* Read data from register */ | |
2461 | msgs[1].addr = client->addr; | |
2462 | msgs[1].flags = I2C_M_RD; | |
2463 | msgs[1].len = len; | |
2464 | msgs[1].buf = &data_be_p[4 - len]; | |
2465 | ||
2466 | ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); | |
2467 | if (ret != ARRAY_SIZE(msgs)) | |
2468 | return -EIO; | |
2469 | ||
2470 | *val = be32_to_cpu(data_be); | |
2471 | ||
2472 | return 0; | |
2473 | } | |
2474 | ||
2475 | /* Write registers up to 4 at a time */ | |
2476 | static int ov08x40_write_reg(struct ov08x40 *ov08x, | |
2477 | u16 reg, u32 len, u32 __val) | |
2478 | { | |
2479 | struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd); | |
2480 | int buf_i, val_i; | |
2481 | u8 buf[6], *val_p; | |
2482 | __be32 val; | |
2483 | ||
2484 | if (len > 4) | |
2485 | return -EINVAL; | |
2486 | ||
2487 | buf[0] = reg >> 8; | |
2488 | buf[1] = reg & 0xff; | |
2489 | ||
2490 | val = cpu_to_be32(__val); | |
2491 | val_p = (u8 *)&val; | |
2492 | buf_i = 2; | |
2493 | val_i = 4 - len; | |
2494 | ||
2495 | while (val_i < 4) | |
2496 | buf[buf_i++] = val_p[val_i++]; | |
2497 | ||
2498 | if (i2c_master_send(client, buf, len + 2) != len + 2) | |
2499 | return -EIO; | |
2500 | ||
2501 | return 0; | |
2502 | } | |
2503 | ||
2504 | /* Write a list of registers */ | |
2505 | static int ov08x40_write_regs(struct ov08x40 *ov08x, | |
2506 | const struct ov08x40_reg *regs, u32 len) | |
2507 | { | |
2508 | struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd); | |
2509 | int ret; | |
2510 | u32 i; | |
2511 | ||
2512 | for (i = 0; i < len; i++) { | |
2513 | ret = ov08x40_write_reg(ov08x, regs[i].address, 1, | |
2514 | regs[i].val); | |
2515 | ||
2516 | if (ret) { | |
2517 | dev_err_ratelimited(&client->dev, | |
2518 | "Failed to write reg 0x%4.4x. error = %d\n", | |
2519 | regs[i].address, ret); | |
2520 | ||
2521 | return ret; | |
2522 | } | |
2523 | } | |
2524 | ||
2525 | return 0; | |
2526 | } | |
2527 | ||
2528 | static int ov08x40_write_reg_list(struct ov08x40 *ov08x, | |
2529 | const struct ov08x40_reg_list *r_list) | |
2530 | { | |
2531 | return ov08x40_write_regs(ov08x, r_list->regs, r_list->num_of_regs); | |
2532 | } | |
2533 | ||
2534 | static int ov08x40_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) | |
2535 | { | |
2536 | const struct ov08x40_mode *default_mode = &supported_modes[0]; | |
2537 | struct ov08x40 *ov08x = to_ov08x40(sd); | |
2538 | struct v4l2_mbus_framefmt *try_fmt = | |
2539 | v4l2_subdev_get_try_format(sd, fh->state, 0); | |
2540 | ||
2541 | mutex_lock(&ov08x->mutex); | |
2542 | ||
2543 | /* Initialize try_fmt */ | |
2544 | try_fmt->width = default_mode->width; | |
2545 | try_fmt->height = default_mode->height; | |
2546 | try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; | |
2547 | try_fmt->field = V4L2_FIELD_NONE; | |
2548 | ||
2549 | /* No crop or compose */ | |
2550 | mutex_unlock(&ov08x->mutex); | |
2551 | ||
2552 | return 0; | |
2553 | } | |
2554 | ||
2555 | static int ov08x40_update_digital_gain(struct ov08x40 *ov08x, u32 d_gain) | |
2556 | { | |
2557 | int ret; | |
2558 | u32 val; | |
2559 | ||
2560 | /* | |
2561 | * 0x350C[1:0], 0x350B[7:0], 0x350A[4:0] | |
2562 | */ | |
2563 | ||
2564 | val = (d_gain & OV08X40_DGTL_GAIN_L_MASK) << OV08X40_DGTL_GAIN_L_SHIFT; | |
2565 | ret = ov08x40_write_reg(ov08x, OV08X40_REG_DGTL_GAIN_L, | |
2566 | OV08X40_REG_VALUE_08BIT, val); | |
2567 | if (ret) | |
2568 | return ret; | |
2569 | ||
2570 | val = (d_gain >> OV08X40_DGTL_GAIN_M_SHIFT) & OV08X40_DGTL_GAIN_M_MASK; | |
2571 | ret = ov08x40_write_reg(ov08x, OV08X40_REG_DGTL_GAIN_M, | |
2572 | OV08X40_REG_VALUE_08BIT, val); | |
2573 | if (ret) | |
2574 | return ret; | |
2575 | ||
2576 | val = (d_gain >> OV08X40_DGTL_GAIN_H_SHIFT) & OV08X40_DGTL_GAIN_H_MASK; | |
2577 | ||
2578 | return ov08x40_write_reg(ov08x, OV08X40_REG_DGTL_GAIN_H, | |
2579 | OV08X40_REG_VALUE_08BIT, val); | |
2580 | } | |
2581 | ||
2582 | static int ov08x40_enable_test_pattern(struct ov08x40 *ov08x, u32 pattern) | |
2583 | { | |
2584 | int ret; | |
2585 | u32 val; | |
2586 | ||
2587 | ret = ov08x40_read_reg(ov08x, OV08X40_REG_TEST_PATTERN, | |
2588 | OV08X40_REG_VALUE_08BIT, &val); | |
2589 | if (ret) | |
2590 | return ret; | |
2591 | ||
2592 | if (pattern) { | |
2593 | ret = ov08x40_read_reg(ov08x, OV08X40_REG_ISP, | |
2594 | OV08X40_REG_VALUE_08BIT, &val); | |
2595 | if (ret) | |
2596 | return ret; | |
2597 | ||
2598 | ret = ov08x40_write_reg(ov08x, OV08X40_REG_ISP, | |
2599 | OV08X40_REG_VALUE_08BIT, | |
2600 | val | BIT(1)); | |
2601 | if (ret) | |
2602 | return ret; | |
2603 | ||
2604 | ret = ov08x40_read_reg(ov08x, OV08X40_REG_SHORT_TEST_PATTERN, | |
2605 | OV08X40_REG_VALUE_08BIT, &val); | |
2606 | if (ret) | |
2607 | return ret; | |
2608 | ||
2609 | ret = ov08x40_write_reg(ov08x, OV08X40_REG_SHORT_TEST_PATTERN, | |
2610 | OV08X40_REG_VALUE_08BIT, | |
2611 | val | BIT(0)); | |
2612 | if (ret) | |
2613 | return ret; | |
2614 | ||
2615 | ret = ov08x40_read_reg(ov08x, OV08X40_REG_TEST_PATTERN, | |
2616 | OV08X40_REG_VALUE_08BIT, &val); | |
2617 | if (ret) | |
2618 | return ret; | |
2619 | ||
2620 | val &= OV08X40_TEST_PATTERN_MASK; | |
2621 | val |= ((pattern - 1) << OV08X40_TEST_PATTERN_BAR_SHIFT) | | |
2622 | OV08X40_TEST_PATTERN_ENABLE; | |
2623 | } else { | |
2624 | val &= ~OV08X40_TEST_PATTERN_ENABLE; | |
2625 | } | |
2626 | ||
2627 | return ov08x40_write_reg(ov08x, OV08X40_REG_TEST_PATTERN, | |
2628 | OV08X40_REG_VALUE_08BIT, val); | |
2629 | } | |
2630 | ||
2631 | static int ov08x40_set_ctrl_hflip(struct ov08x40 *ov08x, u32 ctrl_val) | |
2632 | { | |
2633 | int ret; | |
2634 | u32 val; | |
2635 | ||
2636 | ret = ov08x40_read_reg(ov08x, OV08X40_REG_MIRROR, | |
2637 | OV08X40_REG_VALUE_08BIT, &val); | |
2638 | if (ret) | |
2639 | return ret; | |
2640 | ||
2641 | return ov08x40_write_reg(ov08x, OV08X40_REG_MIRROR, | |
2642 | OV08X40_REG_VALUE_08BIT, | |
2643 | ctrl_val ? val | BIT(2) : val & ~BIT(2)); | |
2644 | } | |
2645 | ||
2646 | static int ov08x40_set_ctrl_vflip(struct ov08x40 *ov08x, u32 ctrl_val) | |
2647 | { | |
2648 | int ret; | |
2649 | u32 val; | |
2650 | ||
2651 | ret = ov08x40_read_reg(ov08x, OV08X40_REG_VFLIP, | |
2652 | OV08X40_REG_VALUE_08BIT, &val); | |
2653 | if (ret) | |
2654 | return ret; | |
2655 | ||
2656 | return ov08x40_write_reg(ov08x, OV08X40_REG_VFLIP, | |
2657 | OV08X40_REG_VALUE_08BIT, | |
2658 | ctrl_val ? val | BIT(2) : val & ~BIT(2)); | |
2659 | } | |
2660 | ||
2661 | static int ov08x40_set_ctrl(struct v4l2_ctrl *ctrl) | |
2662 | { | |
2663 | struct ov08x40 *ov08x = container_of(ctrl->handler, | |
2664 | struct ov08x40, ctrl_handler); | |
2665 | struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd); | |
2666 | s64 max; | |
2667 | int ret = 0; | |
2668 | ||
2669 | /* Propagate change of current control to all related controls */ | |
2670 | switch (ctrl->id) { | |
2671 | case V4L2_CID_VBLANK: | |
2672 | /* Update max exposure while meeting expected vblanking */ | |
2673 | max = ov08x->cur_mode->height + ctrl->val - OV08X40_EXPOSURE_MAX_MARGIN; | |
2674 | __v4l2_ctrl_modify_range(ov08x->exposure, | |
2675 | ov08x->exposure->minimum, | |
2676 | max, ov08x->exposure->step, max); | |
2677 | break; | |
2678 | } | |
2679 | ||
2680 | /* | |
2681 | * Applying V4L2 control value only happens | |
2682 | * when power is up for streaming | |
2683 | */ | |
2684 | if (!pm_runtime_get_if_in_use(&client->dev)) | |
2685 | return 0; | |
2686 | ||
2687 | switch (ctrl->id) { | |
2688 | case V4L2_CID_ANALOGUE_GAIN: | |
2689 | ret = ov08x40_write_reg(ov08x, OV08X40_REG_ANALOG_GAIN, | |
2690 | OV08X40_REG_VALUE_16BIT, | |
2691 | ctrl->val << 1); | |
2692 | break; | |
2693 | case V4L2_CID_DIGITAL_GAIN: | |
2694 | ret = ov08x40_update_digital_gain(ov08x, ctrl->val); | |
2695 | break; | |
2696 | case V4L2_CID_EXPOSURE: | |
2697 | ret = ov08x40_write_reg(ov08x, OV08X40_REG_EXPOSURE, | |
2698 | OV08X40_REG_VALUE_24BIT, | |
2699 | ctrl->val); | |
2700 | break; | |
2701 | case V4L2_CID_VBLANK: | |
2702 | ret = ov08x40_write_reg(ov08x, OV08X40_REG_VTS, | |
2703 | OV08X40_REG_VALUE_16BIT, | |
2704 | ov08x->cur_mode->height | |
2705 | + ctrl->val); | |
2706 | break; | |
2707 | case V4L2_CID_TEST_PATTERN: | |
2708 | ret = ov08x40_enable_test_pattern(ov08x, ctrl->val); | |
2709 | break; | |
2710 | case V4L2_CID_HFLIP: | |
2711 | ov08x40_set_ctrl_hflip(ov08x, ctrl->val); | |
2712 | break; | |
2713 | case V4L2_CID_VFLIP: | |
2714 | ov08x40_set_ctrl_vflip(ov08x, ctrl->val); | |
2715 | break; | |
2716 | default: | |
2717 | dev_info(&client->dev, | |
2718 | "ctrl(id:0x%x,val:0x%x) is not handled\n", | |
2719 | ctrl->id, ctrl->val); | |
2720 | break; | |
2721 | } | |
2722 | ||
2723 | pm_runtime_put(&client->dev); | |
2724 | ||
2725 | return ret; | |
2726 | } | |
2727 | ||
2728 | static const struct v4l2_ctrl_ops ov08x40_ctrl_ops = { | |
2729 | .s_ctrl = ov08x40_set_ctrl, | |
2730 | }; | |
2731 | ||
2732 | static int ov08x40_enum_mbus_code(struct v4l2_subdev *sd, | |
2733 | struct v4l2_subdev_state *sd_state, | |
2734 | struct v4l2_subdev_mbus_code_enum *code) | |
2735 | { | |
2736 | /* Only one bayer order(GRBG) is supported */ | |
2737 | if (code->index > 0) | |
2738 | return -EINVAL; | |
2739 | ||
2740 | code->code = MEDIA_BUS_FMT_SGRBG10_1X10; | |
2741 | ||
2742 | return 0; | |
2743 | } | |
2744 | ||
2745 | static int ov08x40_enum_frame_size(struct v4l2_subdev *sd, | |
2746 | struct v4l2_subdev_state *sd_state, | |
2747 | struct v4l2_subdev_frame_size_enum *fse) | |
2748 | { | |
2749 | if (fse->index >= ARRAY_SIZE(supported_modes)) | |
2750 | return -EINVAL; | |
2751 | ||
2752 | if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) | |
2753 | return -EINVAL; | |
2754 | ||
2755 | fse->min_width = supported_modes[fse->index].width; | |
2756 | fse->max_width = fse->min_width; | |
2757 | fse->min_height = supported_modes[fse->index].height; | |
2758 | fse->max_height = fse->min_height; | |
2759 | ||
2760 | return 0; | |
2761 | } | |
2762 | ||
2763 | static void ov08x40_update_pad_format(const struct ov08x40_mode *mode, | |
2764 | struct v4l2_subdev_format *fmt) | |
2765 | { | |
2766 | fmt->format.width = mode->width; | |
2767 | fmt->format.height = mode->height; | |
2768 | fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10; | |
2769 | fmt->format.field = V4L2_FIELD_NONE; | |
2770 | } | |
2771 | ||
2772 | static int ov08x40_do_get_pad_format(struct ov08x40 *ov08x, | |
2773 | struct v4l2_subdev_state *sd_state, | |
2774 | struct v4l2_subdev_format *fmt) | |
2775 | { | |
2776 | struct v4l2_mbus_framefmt *framefmt; | |
2777 | struct v4l2_subdev *sd = &ov08x->sd; | |
2778 | ||
2779 | if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { | |
2780 | framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad); | |
2781 | fmt->format = *framefmt; | |
2782 | } else { | |
2783 | ov08x40_update_pad_format(ov08x->cur_mode, fmt); | |
2784 | } | |
2785 | ||
2786 | return 0; | |
2787 | } | |
2788 | ||
2789 | static int ov08x40_get_pad_format(struct v4l2_subdev *sd, | |
2790 | struct v4l2_subdev_state *sd_state, | |
2791 | struct v4l2_subdev_format *fmt) | |
2792 | { | |
2793 | struct ov08x40 *ov08x = to_ov08x40(sd); | |
2794 | int ret; | |
2795 | ||
2796 | mutex_lock(&ov08x->mutex); | |
2797 | ret = ov08x40_do_get_pad_format(ov08x, sd_state, fmt); | |
2798 | mutex_unlock(&ov08x->mutex); | |
2799 | ||
2800 | return ret; | |
2801 | } | |
2802 | ||
2803 | static int | |
2804 | ov08x40_set_pad_format(struct v4l2_subdev *sd, | |
2805 | struct v4l2_subdev_state *sd_state, | |
2806 | struct v4l2_subdev_format *fmt) | |
2807 | { | |
2808 | struct ov08x40 *ov08x = to_ov08x40(sd); | |
2809 | const struct ov08x40_mode *mode; | |
2810 | struct v4l2_mbus_framefmt *framefmt; | |
2811 | s32 vblank_def; | |
2812 | s32 vblank_min; | |
2813 | s64 h_blank; | |
2814 | s64 pixel_rate; | |
2815 | s64 link_freq; | |
2816 | ||
2817 | mutex_lock(&ov08x->mutex); | |
2818 | ||
2819 | /* Only one raw bayer(GRBG) order is supported */ | |
2820 | if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10) | |
2821 | fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10; | |
2822 | ||
2823 | mode = v4l2_find_nearest_size(supported_modes, | |
2824 | ARRAY_SIZE(supported_modes), | |
2825 | width, height, | |
2826 | fmt->format.width, fmt->format.height); | |
2827 | ov08x40_update_pad_format(mode, fmt); | |
2828 | if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { | |
2829 | framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad); | |
2830 | *framefmt = fmt->format; | |
2831 | } else { | |
2832 | ov08x->cur_mode = mode; | |
2833 | __v4l2_ctrl_s_ctrl(ov08x->link_freq, mode->link_freq_index); | |
2834 | link_freq = link_freq_menu_items[mode->link_freq_index]; | |
2835 | pixel_rate = link_freq_to_pixel_rate(link_freq); | |
2836 | __v4l2_ctrl_s_ctrl_int64(ov08x->pixel_rate, pixel_rate); | |
2837 | ||
2838 | /* Update limits and set FPS to default */ | |
2839 | vblank_def = ov08x->cur_mode->vts_def - | |
2840 | ov08x->cur_mode->height; | |
2841 | vblank_min = ov08x->cur_mode->vts_min - | |
2842 | ov08x->cur_mode->height; | |
2843 | __v4l2_ctrl_modify_range(ov08x->vblank, vblank_min, | |
2844 | OV08X40_VTS_MAX | |
2845 | - ov08x->cur_mode->height, | |
2846 | 1, | |
2847 | vblank_def); | |
2848 | __v4l2_ctrl_s_ctrl(ov08x->vblank, vblank_def); | |
2849 | h_blank = | |
2850 | link_freq_configs[mode->link_freq_index].pixels_per_line | |
2851 | - ov08x->cur_mode->width; | |
2852 | __v4l2_ctrl_modify_range(ov08x->hblank, h_blank, | |
2853 | h_blank, 1, h_blank); | |
2854 | } | |
2855 | ||
2856 | mutex_unlock(&ov08x->mutex); | |
2857 | ||
2858 | return 0; | |
2859 | } | |
2860 | ||
2861 | static int ov08x40_start_streaming(struct ov08x40 *ov08x) | |
2862 | { | |
2863 | struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd); | |
2864 | const struct ov08x40_reg_list *reg_list; | |
2865 | int ret, link_freq_index; | |
2866 | ||
2867 | /* Get out of from software reset */ | |
2868 | ret = ov08x40_write_reg(ov08x, OV08X40_REG_SOFTWARE_RST, | |
2869 | OV08X40_REG_VALUE_08BIT, OV08X40_SOFTWARE_RST); | |
2870 | if (ret) { | |
2871 | dev_err(&client->dev, "%s failed to set powerup registers\n", | |
2872 | __func__); | |
2873 | return ret; | |
2874 | } | |
2875 | ||
2876 | link_freq_index = ov08x->cur_mode->link_freq_index; | |
2877 | reg_list = &link_freq_configs[link_freq_index].reg_list; | |
2878 | ||
2879 | ret = ov08x40_write_reg_list(ov08x, reg_list); | |
2880 | if (ret) { | |
2881 | dev_err(&client->dev, "%s failed to set plls\n", __func__); | |
2882 | return ret; | |
2883 | } | |
2884 | ||
2885 | /* Apply default values of current mode */ | |
2886 | reg_list = &ov08x->cur_mode->reg_list; | |
2887 | ret = ov08x40_write_reg_list(ov08x, reg_list); | |
2888 | if (ret) { | |
2889 | dev_err(&client->dev, "%s failed to set mode\n", __func__); | |
2890 | return ret; | |
2891 | } | |
2892 | ||
2893 | /* Apply customized values from user */ | |
2894 | ret = __v4l2_ctrl_handler_setup(ov08x->sd.ctrl_handler); | |
2895 | if (ret) | |
2896 | return ret; | |
2897 | ||
2898 | return ov08x40_write_reg(ov08x, OV08X40_REG_MODE_SELECT, | |
2899 | OV08X40_REG_VALUE_08BIT, | |
2900 | OV08X40_MODE_STREAMING); | |
2901 | } | |
2902 | ||
2903 | /* Stop streaming */ | |
2904 | static int ov08x40_stop_streaming(struct ov08x40 *ov08x) | |
2905 | { | |
2906 | return ov08x40_write_reg(ov08x, OV08X40_REG_MODE_SELECT, | |
2907 | OV08X40_REG_VALUE_08BIT, OV08X40_MODE_STANDBY); | |
2908 | } | |
2909 | ||
2910 | static int ov08x40_set_stream(struct v4l2_subdev *sd, int enable) | |
2911 | { | |
2912 | struct ov08x40 *ov08x = to_ov08x40(sd); | |
2913 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
2914 | int ret = 0; | |
2915 | ||
2916 | mutex_lock(&ov08x->mutex); | |
2917 | if (ov08x->streaming == enable) { | |
2918 | mutex_unlock(&ov08x->mutex); | |
2919 | return 0; | |
2920 | } | |
2921 | ||
2922 | if (enable) { | |
2923 | ret = pm_runtime_resume_and_get(&client->dev); | |
2924 | if (ret < 0) | |
2925 | goto err_unlock; | |
2926 | ||
2927 | /* | |
2928 | * Apply default & customized values | |
2929 | * and then start streaming. | |
2930 | */ | |
2931 | ret = ov08x40_start_streaming(ov08x); | |
2932 | if (ret) | |
2933 | goto err_rpm_put; | |
2934 | } else { | |
2935 | ov08x40_stop_streaming(ov08x); | |
2936 | pm_runtime_put(&client->dev); | |
2937 | } | |
2938 | ||
2939 | ov08x->streaming = enable; | |
2940 | mutex_unlock(&ov08x->mutex); | |
2941 | ||
2942 | return ret; | |
2943 | ||
2944 | err_rpm_put: | |
2945 | pm_runtime_put(&client->dev); | |
2946 | err_unlock: | |
2947 | mutex_unlock(&ov08x->mutex); | |
2948 | ||
2949 | return ret; | |
2950 | } | |
2951 | ||
2952 | static int __maybe_unused ov08x40_suspend(struct device *dev) | |
2953 | { | |
2954 | struct v4l2_subdev *sd = dev_get_drvdata(dev); | |
2955 | struct ov08x40 *ov08x = to_ov08x40(sd); | |
2956 | ||
2957 | if (ov08x->streaming) | |
2958 | ov08x40_stop_streaming(ov08x); | |
2959 | ||
2960 | return 0; | |
2961 | } | |
2962 | ||
2963 | static int __maybe_unused ov08x40_resume(struct device *dev) | |
2964 | { | |
2965 | struct v4l2_subdev *sd = dev_get_drvdata(dev); | |
2966 | struct ov08x40 *ov08x = to_ov08x40(sd); | |
2967 | int ret; | |
2968 | ||
2969 | if (ov08x->streaming) { | |
2970 | ret = ov08x40_start_streaming(ov08x); | |
2971 | if (ret) | |
2972 | goto error; | |
2973 | } | |
2974 | ||
2975 | return 0; | |
2976 | ||
2977 | error: | |
2978 | ov08x40_stop_streaming(ov08x); | |
2979 | ov08x->streaming = false; | |
2980 | return ret; | |
2981 | } | |
2982 | ||
2983 | /* Verify chip ID */ | |
2984 | static int ov08x40_identify_module(struct ov08x40 *ov08x) | |
2985 | { | |
2986 | struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd); | |
2987 | int ret; | |
2988 | u32 val; | |
2989 | ||
2990 | ret = ov08x40_read_reg(ov08x, OV08X40_REG_CHIP_ID, | |
2991 | OV08X40_REG_VALUE_24BIT, &val); | |
2992 | if (ret) | |
2993 | return ret; | |
2994 | ||
2995 | if (val != OV08X40_CHIP_ID) { | |
2996 | dev_err(&client->dev, "chip id mismatch: %x!=%x\n", | |
2997 | OV08X40_CHIP_ID, val); | |
2998 | return -EIO; | |
2999 | } | |
3000 | ||
3001 | return 0; | |
3002 | } | |
3003 | ||
3004 | static const struct v4l2_subdev_video_ops ov08x40_video_ops = { | |
3005 | .s_stream = ov08x40_set_stream, | |
3006 | }; | |
3007 | ||
3008 | static const struct v4l2_subdev_pad_ops ov08x40_pad_ops = { | |
3009 | .enum_mbus_code = ov08x40_enum_mbus_code, | |
3010 | .get_fmt = ov08x40_get_pad_format, | |
3011 | .set_fmt = ov08x40_set_pad_format, | |
3012 | .enum_frame_size = ov08x40_enum_frame_size, | |
3013 | }; | |
3014 | ||
3015 | static const struct v4l2_subdev_ops ov08x40_subdev_ops = { | |
3016 | .video = &ov08x40_video_ops, | |
3017 | .pad = &ov08x40_pad_ops, | |
3018 | }; | |
3019 | ||
3020 | static const struct media_entity_operations ov08x40_subdev_entity_ops = { | |
3021 | .link_validate = v4l2_subdev_link_validate, | |
3022 | }; | |
3023 | ||
3024 | static const struct v4l2_subdev_internal_ops ov08x40_internal_ops = { | |
3025 | .open = ov08x40_open, | |
3026 | }; | |
3027 | ||
3028 | static int ov08x40_init_controls(struct ov08x40 *ov08x) | |
3029 | { | |
3030 | struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd); | |
3031 | struct v4l2_fwnode_device_properties props; | |
3032 | struct v4l2_ctrl_handler *ctrl_hdlr; | |
3033 | s64 exposure_max; | |
3034 | s64 vblank_def; | |
3035 | s64 vblank_min; | |
3036 | s64 hblank; | |
3037 | s64 pixel_rate_min; | |
3038 | s64 pixel_rate_max; | |
3039 | const struct ov08x40_mode *mode; | |
3040 | u32 max; | |
3041 | int ret; | |
3042 | ||
3043 | ctrl_hdlr = &ov08x->ctrl_handler; | |
3044 | ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10); | |
3045 | if (ret) | |
3046 | return ret; | |
3047 | ||
3048 | mutex_init(&ov08x->mutex); | |
3049 | ctrl_hdlr->lock = &ov08x->mutex; | |
3050 | max = ARRAY_SIZE(link_freq_menu_items) - 1; | |
3051 | ov08x->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, | |
3052 | &ov08x40_ctrl_ops, | |
3053 | V4L2_CID_LINK_FREQ, | |
3054 | max, | |
3055 | 0, | |
3056 | link_freq_menu_items); | |
3057 | if (ov08x->link_freq) | |
3058 | ov08x->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; | |
3059 | ||
3060 | pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0]); | |
3061 | pixel_rate_min = 0; | |
3062 | /* By default, PIXEL_RATE is read only */ | |
3063 | ov08x->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, | |
3064 | V4L2_CID_PIXEL_RATE, | |
3065 | pixel_rate_min, pixel_rate_max, | |
3066 | 1, pixel_rate_max); | |
3067 | ||
3068 | mode = ov08x->cur_mode; | |
3069 | vblank_def = mode->vts_def - mode->height; | |
3070 | vblank_min = mode->vts_min - mode->height; | |
3071 | ov08x->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, | |
3072 | V4L2_CID_VBLANK, | |
3073 | vblank_min, | |
3074 | OV08X40_VTS_MAX - mode->height, 1, | |
3075 | vblank_def); | |
3076 | ||
3077 | hblank = link_freq_configs[mode->link_freq_index].pixels_per_line - | |
3078 | mode->width; | |
3079 | ov08x->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, | |
3080 | V4L2_CID_HBLANK, | |
3081 | hblank, hblank, 1, hblank); | |
3082 | if (ov08x->hblank) | |
3083 | ov08x->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; | |
3084 | ||
3085 | exposure_max = mode->vts_def - OV08X40_EXPOSURE_MAX_MARGIN; | |
3086 | ov08x->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, | |
3087 | V4L2_CID_EXPOSURE, | |
3088 | OV08X40_EXPOSURE_MIN, | |
3089 | exposure_max, OV08X40_EXPOSURE_STEP, | |
3090 | exposure_max); | |
3091 | ||
3092 | v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, | |
3093 | OV08X40_ANA_GAIN_MIN, OV08X40_ANA_GAIN_MAX, | |
3094 | OV08X40_ANA_GAIN_STEP, OV08X40_ANA_GAIN_DEFAULT); | |
3095 | ||
3096 | /* Digital gain */ | |
3097 | v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, V4L2_CID_DIGITAL_GAIN, | |
3098 | OV08X40_DGTL_GAIN_MIN, OV08X40_DGTL_GAIN_MAX, | |
3099 | OV08X40_DGTL_GAIN_STEP, OV08X40_DGTL_GAIN_DEFAULT); | |
3100 | ||
3101 | v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov08x40_ctrl_ops, | |
3102 | V4L2_CID_TEST_PATTERN, | |
3103 | ARRAY_SIZE(ov08x40_test_pattern_menu) - 1, | |
3104 | 0, 0, ov08x40_test_pattern_menu); | |
3105 | ||
3106 | v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, | |
3107 | V4L2_CID_HFLIP, 0, 1, 1, 0); | |
3108 | v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, | |
3109 | V4L2_CID_VFLIP, 0, 1, 1, 0); | |
3110 | ||
3111 | if (ctrl_hdlr->error) { | |
3112 | ret = ctrl_hdlr->error; | |
3113 | dev_err(&client->dev, "%s control init failed (%d)\n", | |
3114 | __func__, ret); | |
3115 | goto error; | |
3116 | } | |
3117 | ||
3118 | ret = v4l2_fwnode_device_parse(&client->dev, &props); | |
3119 | if (ret) | |
3120 | goto error; | |
3121 | ||
3122 | ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov08x40_ctrl_ops, | |
3123 | &props); | |
3124 | if (ret) | |
3125 | goto error; | |
3126 | ||
3127 | ov08x->sd.ctrl_handler = ctrl_hdlr; | |
3128 | ||
3129 | return 0; | |
3130 | ||
3131 | error: | |
3132 | v4l2_ctrl_handler_free(ctrl_hdlr); | |
3133 | mutex_destroy(&ov08x->mutex); | |
3134 | ||
3135 | return ret; | |
3136 | } | |
3137 | ||
3138 | static void ov08x40_free_controls(struct ov08x40 *ov08x) | |
3139 | { | |
3140 | v4l2_ctrl_handler_free(ov08x->sd.ctrl_handler); | |
3141 | mutex_destroy(&ov08x->mutex); | |
3142 | } | |
3143 | ||
3144 | static int ov08x40_check_hwcfg(struct device *dev) | |
3145 | { | |
3146 | struct v4l2_fwnode_endpoint bus_cfg = { | |
3147 | .bus_type = V4L2_MBUS_CSI2_DPHY | |
3148 | }; | |
3149 | struct fwnode_handle *ep; | |
3150 | struct fwnode_handle *fwnode = dev_fwnode(dev); | |
3151 | unsigned int i, j; | |
3152 | int ret; | |
3153 | u32 ext_clk; | |
3154 | ||
3155 | if (!fwnode) | |
3156 | return -ENXIO; | |
3157 | ||
3158 | ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency", | |
3159 | &ext_clk); | |
3160 | if (ret) { | |
3161 | dev_err(dev, "can't get clock frequency"); | |
3162 | return ret; | |
3163 | } | |
3164 | ||
3165 | if (ext_clk != OV08X40_EXT_CLK) { | |
3166 | dev_err(dev, "external clock %d is not supported", | |
3167 | ext_clk); | |
3168 | return -EINVAL; | |
3169 | } | |
3170 | ||
3171 | ep = fwnode_graph_get_next_endpoint(fwnode, NULL); | |
3172 | if (!ep) | |
3173 | return -ENXIO; | |
3174 | ||
3175 | ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); | |
3176 | fwnode_handle_put(ep); | |
3177 | if (ret) | |
3178 | return ret; | |
3179 | ||
3180 | if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV08X40_DATA_LANES) { | |
3181 | dev_err(dev, "number of CSI2 data lanes %d is not supported", | |
3182 | bus_cfg.bus.mipi_csi2.num_data_lanes); | |
3183 | ret = -EINVAL; | |
3184 | goto out_err; | |
3185 | } | |
3186 | ||
3187 | if (!bus_cfg.nr_of_link_frequencies) { | |
3188 | dev_err(dev, "no link frequencies defined"); | |
3189 | ret = -EINVAL; | |
3190 | goto out_err; | |
3191 | } | |
3192 | ||
3193 | for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) { | |
3194 | for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) { | |
3195 | if (link_freq_menu_items[i] == | |
3196 | bus_cfg.link_frequencies[j]) | |
3197 | break; | |
3198 | } | |
3199 | ||
3200 | if (j == bus_cfg.nr_of_link_frequencies) { | |
3201 | dev_err(dev, "no link frequency %lld supported", | |
3202 | link_freq_menu_items[i]); | |
3203 | ret = -EINVAL; | |
3204 | goto out_err; | |
3205 | } | |
3206 | } | |
3207 | ||
3208 | out_err: | |
3209 | v4l2_fwnode_endpoint_free(&bus_cfg); | |
3210 | ||
3211 | return ret; | |
3212 | } | |
3213 | ||
3214 | static int ov08x40_probe(struct i2c_client *client) | |
3215 | { | |
3216 | struct ov08x40 *ov08x; | |
3217 | int ret; | |
3218 | ||
3219 | /* Check HW config */ | |
3220 | ret = ov08x40_check_hwcfg(&client->dev); | |
3221 | if (ret) { | |
3222 | dev_err(&client->dev, "failed to check hwcfg: %d", ret); | |
3223 | return ret; | |
3224 | } | |
3225 | ||
3226 | ov08x = devm_kzalloc(&client->dev, sizeof(*ov08x), GFP_KERNEL); | |
3227 | if (!ov08x) | |
3228 | return -ENOMEM; | |
3229 | ||
3230 | /* Initialize subdev */ | |
3231 | v4l2_i2c_subdev_init(&ov08x->sd, client, &ov08x40_subdev_ops); | |
3232 | ||
3233 | /* Check module identity */ | |
3234 | ret = ov08x40_identify_module(ov08x); | |
3235 | if (ret) { | |
3236 | dev_err(&client->dev, "failed to find sensor: %d\n", ret); | |
3237 | return ret; | |
3238 | } | |
3239 | ||
3240 | /* Set default mode to max resolution */ | |
3241 | ov08x->cur_mode = &supported_modes[0]; | |
3242 | ||
3243 | ret = ov08x40_init_controls(ov08x); | |
3244 | if (ret) | |
3245 | return ret; | |
3246 | ||
3247 | /* Initialize subdev */ | |
3248 | ov08x->sd.internal_ops = &ov08x40_internal_ops; | |
3249 | ov08x->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; | |
3250 | ov08x->sd.entity.ops = &ov08x40_subdev_entity_ops; | |
3251 | ov08x->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; | |
3252 | ||
3253 | /* Initialize source pad */ | |
3254 | ov08x->pad.flags = MEDIA_PAD_FL_SOURCE; | |
3255 | ret = media_entity_pads_init(&ov08x->sd.entity, 1, &ov08x->pad); | |
3256 | if (ret) { | |
3257 | dev_err(&client->dev, "%s failed:%d\n", __func__, ret); | |
3258 | goto error_handler_free; | |
3259 | } | |
3260 | ||
3261 | ret = v4l2_async_register_subdev_sensor(&ov08x->sd); | |
3262 | if (ret < 0) | |
3263 | goto error_media_entity; | |
3264 | ||
3265 | /* | |
3266 | * Device is already turned on by i2c-core with ACPI domain PM. | |
3267 | * Enable runtime PM and turn off the device. | |
3268 | */ | |
3269 | pm_runtime_set_active(&client->dev); | |
3270 | pm_runtime_enable(&client->dev); | |
3271 | pm_runtime_idle(&client->dev); | |
3272 | ||
3273 | return 0; | |
3274 | ||
3275 | error_media_entity: | |
3276 | media_entity_cleanup(&ov08x->sd.entity); | |
3277 | ||
3278 | error_handler_free: | |
3279 | ov08x40_free_controls(ov08x); | |
3280 | ||
3281 | return ret; | |
3282 | } | |
3283 | ||
f54f5fd0 | 3284 | static void ov08x40_remove(struct i2c_client *client) |
38fc5136 ST |
3285 | { |
3286 | struct v4l2_subdev *sd = i2c_get_clientdata(client); | |
3287 | struct ov08x40 *ov08x = to_ov08x40(sd); | |
3288 | ||
3289 | v4l2_async_unregister_subdev(sd); | |
3290 | media_entity_cleanup(&sd->entity); | |
3291 | ov08x40_free_controls(ov08x); | |
3292 | ||
3293 | pm_runtime_disable(&client->dev); | |
3294 | pm_runtime_set_suspended(&client->dev); | |
38fc5136 ST |
3295 | } |
3296 | ||
3297 | static const struct dev_pm_ops ov08x40_pm_ops = { | |
3298 | SET_SYSTEM_SLEEP_PM_OPS(ov08x40_suspend, ov08x40_resume) | |
3299 | }; | |
3300 | ||
3301 | #ifdef CONFIG_ACPI | |
3302 | static const struct acpi_device_id ov08x40_acpi_ids[] = { | |
3303 | {"OVTI08F4"}, | |
3304 | { /* sentinel */ } | |
3305 | }; | |
3306 | ||
3307 | MODULE_DEVICE_TABLE(acpi, ov08x40_acpi_ids); | |
3308 | #endif | |
3309 | ||
3310 | static struct i2c_driver ov08x40_i2c_driver = { | |
3311 | .driver = { | |
3312 | .name = "ov08x40", | |
3313 | .pm = &ov08x40_pm_ops, | |
3314 | .acpi_match_table = ACPI_PTR(ov08x40_acpi_ids), | |
3315 | }, | |
3316 | .probe_new = ov08x40_probe, | |
3317 | .remove = ov08x40_remove, | |
3318 | }; | |
3319 | ||
3320 | module_i2c_driver(ov08x40_i2c_driver); | |
3321 | ||
3322 | MODULE_AUTHOR("Jason Chen <jason.z.chen@intel.com>"); | |
3323 | MODULE_AUTHOR("Shawn Tu <shawnx.tu@intel.com>"); | |
3324 | MODULE_DESCRIPTION("OmniVision OV08X40 sensor driver"); | |
3325 | MODULE_LICENSE("GPL"); |