Commit | Line | Data |
---|---|---|
66d8c9d2 KB |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* | |
3 | * Maxim MAX9286 GMSL Deserializer Driver | |
4 | * | |
5 | * Copyright (C) 2017-2019 Jacopo Mondi | |
6 | * Copyright (C) 2017-2019 Kieran Bingham | |
7 | * Copyright (C) 2017-2019 Laurent Pinchart | |
8 | * Copyright (C) 2017-2019 Niklas Söderlund | |
9 | * Copyright (C) 2016 Renesas Electronics Corporation | |
10 | * Copyright (C) 2015 Cogent Embedded, Inc. | |
11 | */ | |
12 | ||
13 | #include <linux/delay.h> | |
14 | #include <linux/device.h> | |
15 | #include <linux/fwnode.h> | |
16 | #include <linux/gpio/consumer.h> | |
17 | #include <linux/gpio/driver.h> | |
c9352df7 | 18 | #include <linux/gpio/machine.h> |
66d8c9d2 KB |
19 | #include <linux/i2c.h> |
20 | #include <linux/i2c-mux.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/mutex.h> | |
23 | #include <linux/of_graph.h> | |
24 | #include <linux/regulator/consumer.h> | |
25 | #include <linux/slab.h> | |
26 | ||
27 | #include <media/v4l2-async.h> | |
28 | #include <media/v4l2-ctrls.h> | |
29 | #include <media/v4l2-device.h> | |
30 | #include <media/v4l2-fwnode.h> | |
31 | #include <media/v4l2-subdev.h> | |
32 | ||
33 | /* Register 0x00 */ | |
34 | #define MAX9286_MSTLINKSEL_AUTO (7 << 5) | |
35 | #define MAX9286_MSTLINKSEL(n) ((n) << 5) | |
36 | #define MAX9286_EN_VS_GEN BIT(4) | |
37 | #define MAX9286_LINKEN(n) (1 << (n)) | |
38 | /* Register 0x01 */ | |
39 | #define MAX9286_FSYNCMODE_ECU (3 << 6) | |
40 | #define MAX9286_FSYNCMODE_EXT (2 << 6) | |
41 | #define MAX9286_FSYNCMODE_INT_OUT (1 << 6) | |
42 | #define MAX9286_FSYNCMODE_INT_HIZ (0 << 6) | |
43 | #define MAX9286_GPIEN BIT(5) | |
44 | #define MAX9286_ENLMO_RSTFSYNC BIT(2) | |
45 | #define MAX9286_FSYNCMETH_AUTO (2 << 0) | |
46 | #define MAX9286_FSYNCMETH_SEMI_AUTO (1 << 0) | |
47 | #define MAX9286_FSYNCMETH_MANUAL (0 << 0) | |
48 | #define MAX9286_REG_FSYNC_PERIOD_L 0x06 | |
49 | #define MAX9286_REG_FSYNC_PERIOD_M 0x07 | |
50 | #define MAX9286_REG_FSYNC_PERIOD_H 0x08 | |
51 | /* Register 0x0a */ | |
52 | #define MAX9286_FWDCCEN(n) (1 << ((n) + 4)) | |
53 | #define MAX9286_REVCCEN(n) (1 << (n)) | |
54 | /* Register 0x0c */ | |
55 | #define MAX9286_HVEN BIT(7) | |
56 | #define MAX9286_EDC_6BIT_HAMMING (2 << 5) | |
57 | #define MAX9286_EDC_6BIT_CRC (1 << 5) | |
58 | #define MAX9286_EDC_1BIT_PARITY (0 << 5) | |
59 | #define MAX9286_DESEL BIT(4) | |
60 | #define MAX9286_INVVS BIT(3) | |
61 | #define MAX9286_INVHS BIT(2) | |
62 | #define MAX9286_HVSRC_D0 (2 << 0) | |
63 | #define MAX9286_HVSRC_D14 (1 << 0) | |
64 | #define MAX9286_HVSRC_D18 (0 << 0) | |
65 | /* Register 0x0f */ | |
66 | #define MAX9286_0X0F_RESERVED BIT(3) | |
67 | /* Register 0x12 */ | |
68 | #define MAX9286_CSILANECNT(n) (((n) - 1) << 6) | |
69 | #define MAX9286_CSIDBL BIT(5) | |
70 | #define MAX9286_DBL BIT(4) | |
71 | #define MAX9286_DATATYPE_USER_8BIT (11 << 0) | |
72 | #define MAX9286_DATATYPE_USER_YUV_12BIT (10 << 0) | |
73 | #define MAX9286_DATATYPE_USER_24BIT (9 << 0) | |
74 | #define MAX9286_DATATYPE_RAW14 (8 << 0) | |
b904512b | 75 | #define MAX9286_DATATYPE_RAW12 (7 << 0) |
66d8c9d2 KB |
76 | #define MAX9286_DATATYPE_RAW10 (6 << 0) |
77 | #define MAX9286_DATATYPE_RAW8 (5 << 0) | |
78 | #define MAX9286_DATATYPE_YUV422_10BIT (4 << 0) | |
79 | #define MAX9286_DATATYPE_YUV422_8BIT (3 << 0) | |
80 | #define MAX9286_DATATYPE_RGB555 (2 << 0) | |
81 | #define MAX9286_DATATYPE_RGB565 (1 << 0) | |
82 | #define MAX9286_DATATYPE_RGB888 (0 << 0) | |
83 | /* Register 0x15 */ | |
cdcb186e | 84 | #define MAX9286_CSI_IMAGE_TYP BIT(7) |
66d8c9d2 KB |
85 | #define MAX9286_VC(n) ((n) << 5) |
86 | #define MAX9286_VCTYPE BIT(4) | |
87 | #define MAX9286_CSIOUTEN BIT(3) | |
cdcb186e LP |
88 | #define MAX9286_SWP_ENDIAN BIT(2) |
89 | #define MAX9286_EN_CCBSYB_CLK_STR BIT(1) | |
90 | #define MAX9286_EN_GPI_CCBSYB BIT(0) | |
66d8c9d2 KB |
91 | /* Register 0x1b */ |
92 | #define MAX9286_SWITCHIN(n) (1 << ((n) + 4)) | |
93 | #define MAX9286_ENEQ(n) (1 << (n)) | |
3697f108 LP |
94 | /* Register 0x1c */ |
95 | #define MAX9286_HIGHIMM(n) BIT((n) + 4) | |
96 | #define MAX9286_I2CSEL BIT(2) | |
97 | #define MAX9286_HIBW BIT(1) | |
98 | #define MAX9286_BWS BIT(0) | |
66d8c9d2 KB |
99 | /* Register 0x27 */ |
100 | #define MAX9286_LOCKED BIT(7) | |
101 | /* Register 0x31 */ | |
102 | #define MAX9286_FSYNC_LOCKED BIT(6) | |
103 | /* Register 0x34 */ | |
104 | #define MAX9286_I2CLOCACK BIT(7) | |
105 | #define MAX9286_I2CSLVSH_1046NS_469NS (3 << 5) | |
106 | #define MAX9286_I2CSLVSH_938NS_352NS (2 << 5) | |
107 | #define MAX9286_I2CSLVSH_469NS_234NS (1 << 5) | |
108 | #define MAX9286_I2CSLVSH_352NS_117NS (0 << 5) | |
109 | #define MAX9286_I2CMSTBT_837KBPS (7 << 2) | |
110 | #define MAX9286_I2CMSTBT_533KBPS (6 << 2) | |
111 | #define MAX9286_I2CMSTBT_339KBPS (5 << 2) | |
112 | #define MAX9286_I2CMSTBT_173KBPS (4 << 2) | |
113 | #define MAX9286_I2CMSTBT_105KBPS (3 << 2) | |
114 | #define MAX9286_I2CMSTBT_84KBPS (2 << 2) | |
115 | #define MAX9286_I2CMSTBT_28KBPS (1 << 2) | |
116 | #define MAX9286_I2CMSTBT_8KBPS (0 << 2) | |
117 | #define MAX9286_I2CSLVTO_NONE (3 << 0) | |
118 | #define MAX9286_I2CSLVTO_1024US (2 << 0) | |
119 | #define MAX9286_I2CSLVTO_256US (1 << 0) | |
120 | #define MAX9286_I2CSLVTO_64US (0 << 0) | |
121 | /* Register 0x3b */ | |
122 | #define MAX9286_REV_TRF(n) ((n) << 4) | |
123 | #define MAX9286_REV_AMP(n) ((((n) - 30) / 10) << 1) /* in mV */ | |
124 | #define MAX9286_REV_AMP_X BIT(0) | |
731c24ff | 125 | #define MAX9286_REV_AMP_HIGH 170 |
66d8c9d2 KB |
126 | /* Register 0x3f */ |
127 | #define MAX9286_EN_REV_CFG BIT(6) | |
128 | #define MAX9286_REV_FLEN(n) ((n) - 20) | |
129 | /* Register 0x49 */ | |
130 | #define MAX9286_VIDEO_DETECT_MASK 0x0f | |
131 | /* Register 0x69 */ | |
132 | #define MAX9286_LFLTBMONMASKED BIT(7) | |
133 | #define MAX9286_LOCKMONMASKED BIT(6) | |
134 | #define MAX9286_AUTOCOMBACKEN BIT(5) | |
135 | #define MAX9286_AUTOMASKEN BIT(4) | |
136 | #define MAX9286_MASKLINK(n) ((n) << 0) | |
137 | ||
138 | /* | |
139 | * The sink and source pads are created to match the OF graph port numbers so | |
140 | * that their indexes can be used interchangeably. | |
141 | */ | |
142 | #define MAX9286_NUM_GMSL 4 | |
143 | #define MAX9286_N_SINKS 4 | |
144 | #define MAX9286_N_PADS 5 | |
145 | #define MAX9286_SRC_PAD 4 | |
146 | ||
f1403802 LP |
147 | struct max9286_format_info { |
148 | u32 code; | |
149 | u8 datatype; | |
150 | }; | |
151 | ||
e332061b LP |
152 | struct max9286_i2c_speed { |
153 | u32 rate; | |
154 | u8 mstbt; | |
155 | }; | |
156 | ||
66d8c9d2 | 157 | struct max9286_source { |
66d8c9d2 KB |
158 | struct v4l2_subdev *sd; |
159 | struct fwnode_handle *fwnode; | |
817660f4 | 160 | struct regulator *regulator; |
66d8c9d2 KB |
161 | }; |
162 | ||
86d37bf3 | 163 | struct max9286_asd { |
adb2dcd5 | 164 | struct v4l2_async_connection base; |
86d37bf3 LP |
165 | struct max9286_source *source; |
166 | }; | |
167 | ||
adb2dcd5 SA |
168 | static inline struct max9286_asd * |
169 | to_max9286_asd(struct v4l2_async_connection *asd) | |
86d37bf3 LP |
170 | { |
171 | return container_of(asd, struct max9286_asd, base); | |
172 | } | |
66d8c9d2 KB |
173 | |
174 | struct max9286_priv { | |
175 | struct i2c_client *client; | |
176 | struct gpio_desc *gpiod_pwdn; | |
177 | struct v4l2_subdev sd; | |
178 | struct media_pad pads[MAX9286_N_PADS]; | |
179 | struct regulator *regulator; | |
180 | ||
181 | struct gpio_chip gpio; | |
182 | u8 gpio_state; | |
183 | ||
184 | struct i2c_mux_core *mux; | |
185 | unsigned int mux_channel; | |
186 | bool mux_open; | |
187 | ||
f78723eb JM |
188 | /* The initial reverse control channel amplitude. */ |
189 | u32 init_rev_chan_mv; | |
902edc2a | 190 | u32 rev_chan_mv; |
e332061b | 191 | u8 i2c_mstbt; |
3697f108 | 192 | u32 bus_width; |
85cb767c | 193 | |
817660f4 | 194 | bool use_gpio_poc; |
c9352df7 JM |
195 | u32 gpio_poc[2]; |
196 | ||
66d8c9d2 | 197 | struct v4l2_ctrl_handler ctrls; |
cffc9fb1 LP |
198 | struct v4l2_ctrl *pixelrate_ctrl; |
199 | unsigned int pixelrate; | |
66d8c9d2 KB |
200 | |
201 | struct v4l2_mbus_framefmt fmt[MAX9286_N_SINKS]; | |
cffc9fb1 | 202 | struct v4l2_fract interval; |
66d8c9d2 KB |
203 | |
204 | /* Protects controls and fmt structures */ | |
205 | struct mutex mutex; | |
206 | ||
207 | unsigned int nsources; | |
208 | unsigned int source_mask; | |
209 | unsigned int route_mask; | |
210 | unsigned int bound_sources; | |
211 | unsigned int csi2_data_lanes; | |
212 | struct max9286_source sources[MAX9286_NUM_GMSL]; | |
213 | struct v4l2_async_notifier notifier; | |
214 | }; | |
215 | ||
216 | static struct max9286_source *next_source(struct max9286_priv *priv, | |
217 | struct max9286_source *source) | |
218 | { | |
219 | if (!source) | |
220 | source = &priv->sources[0]; | |
221 | else | |
222 | source++; | |
223 | ||
224 | for (; source < &priv->sources[MAX9286_NUM_GMSL]; source++) { | |
225 | if (source->fwnode) | |
226 | return source; | |
227 | } | |
228 | ||
229 | return NULL; | |
230 | } | |
231 | ||
232 | #define for_each_source(priv, source) \ | |
233 | for ((source) = NULL; ((source) = next_source((priv), (source))); ) | |
234 | ||
235 | #define to_index(priv, source) ((source) - &(priv)->sources[0]) | |
236 | ||
237 | static inline struct max9286_priv *sd_to_max9286(struct v4l2_subdev *sd) | |
238 | { | |
239 | return container_of(sd, struct max9286_priv, sd); | |
240 | } | |
241 | ||
f1403802 LP |
242 | static const struct max9286_format_info max9286_formats[] = { |
243 | { | |
244 | .code = MEDIA_BUS_FMT_UYVY8_1X16, | |
245 | .datatype = MAX9286_DATATYPE_YUV422_8BIT, | |
246 | }, { | |
247 | .code = MEDIA_BUS_FMT_VYUY8_1X16, | |
248 | .datatype = MAX9286_DATATYPE_YUV422_8BIT, | |
249 | }, { | |
250 | .code = MEDIA_BUS_FMT_YUYV8_1X16, | |
251 | .datatype = MAX9286_DATATYPE_YUV422_8BIT, | |
252 | }, { | |
253 | .code = MEDIA_BUS_FMT_YVYU8_1X16, | |
254 | .datatype = MAX9286_DATATYPE_YUV422_8BIT, | |
255 | }, { | |
256 | .code = MEDIA_BUS_FMT_SBGGR12_1X12, | |
257 | .datatype = MAX9286_DATATYPE_RAW12, | |
258 | }, { | |
259 | .code = MEDIA_BUS_FMT_SGBRG12_1X12, | |
260 | .datatype = MAX9286_DATATYPE_RAW12, | |
261 | }, { | |
262 | .code = MEDIA_BUS_FMT_SGRBG12_1X12, | |
263 | .datatype = MAX9286_DATATYPE_RAW12, | |
264 | }, { | |
265 | .code = MEDIA_BUS_FMT_SRGGB12_1X12, | |
266 | .datatype = MAX9286_DATATYPE_RAW12, | |
267 | }, | |
268 | }; | |
269 | ||
e332061b LP |
270 | static const struct max9286_i2c_speed max9286_i2c_speeds[] = { |
271 | { .rate = 8470, .mstbt = MAX9286_I2CMSTBT_8KBPS }, | |
272 | { .rate = 28300, .mstbt = MAX9286_I2CMSTBT_28KBPS }, | |
273 | { .rate = 84700, .mstbt = MAX9286_I2CMSTBT_84KBPS }, | |
274 | { .rate = 105000, .mstbt = MAX9286_I2CMSTBT_105KBPS }, | |
275 | { .rate = 173000, .mstbt = MAX9286_I2CMSTBT_173KBPS }, | |
276 | { .rate = 339000, .mstbt = MAX9286_I2CMSTBT_339KBPS }, | |
277 | { .rate = 533000, .mstbt = MAX9286_I2CMSTBT_533KBPS }, | |
278 | { .rate = 837000, .mstbt = MAX9286_I2CMSTBT_837KBPS }, | |
279 | }; | |
280 | ||
66d8c9d2 KB |
281 | /* ----------------------------------------------------------------------------- |
282 | * I2C IO | |
283 | */ | |
284 | ||
285 | static int max9286_read(struct max9286_priv *priv, u8 reg) | |
286 | { | |
287 | int ret; | |
288 | ||
289 | ret = i2c_smbus_read_byte_data(priv->client, reg); | |
290 | if (ret < 0) | |
291 | dev_err(&priv->client->dev, | |
292 | "%s: register 0x%02x read failed (%d)\n", | |
293 | __func__, reg, ret); | |
294 | ||
295 | return ret; | |
296 | } | |
297 | ||
298 | static int max9286_write(struct max9286_priv *priv, u8 reg, u8 val) | |
299 | { | |
300 | int ret; | |
301 | ||
302 | ret = i2c_smbus_write_byte_data(priv->client, reg, val); | |
303 | if (ret < 0) | |
304 | dev_err(&priv->client->dev, | |
305 | "%s: register 0x%02x write failed (%d)\n", | |
306 | __func__, reg, ret); | |
307 | ||
308 | return ret; | |
309 | } | |
310 | ||
311 | /* ----------------------------------------------------------------------------- | |
312 | * I2C Multiplexer | |
313 | */ | |
314 | ||
315 | static void max9286_i2c_mux_configure(struct max9286_priv *priv, u8 conf) | |
316 | { | |
317 | max9286_write(priv, 0x0a, conf); | |
318 | ||
319 | /* | |
320 | * We must sleep after any change to the forward or reverse channel | |
321 | * configuration. | |
322 | */ | |
323 | usleep_range(3000, 5000); | |
324 | } | |
325 | ||
326 | static void max9286_i2c_mux_open(struct max9286_priv *priv) | |
327 | { | |
328 | /* Open all channels on the MAX9286 */ | |
329 | max9286_i2c_mux_configure(priv, 0xff); | |
330 | ||
331 | priv->mux_open = true; | |
332 | } | |
333 | ||
334 | static void max9286_i2c_mux_close(struct max9286_priv *priv) | |
335 | { | |
336 | /* | |
337 | * Ensure that both the forward and reverse channel are disabled on the | |
338 | * mux, and that the channel ID is invalidated to ensure we reconfigure | |
339 | * on the next max9286_i2c_mux_select() call. | |
340 | */ | |
341 | max9286_i2c_mux_configure(priv, 0x00); | |
342 | ||
343 | priv->mux_open = false; | |
344 | priv->mux_channel = -1; | |
345 | } | |
346 | ||
347 | static int max9286_i2c_mux_select(struct i2c_mux_core *muxc, u32 chan) | |
348 | { | |
349 | struct max9286_priv *priv = i2c_mux_priv(muxc); | |
350 | ||
351 | /* Channel select is disabled when configured in the opened state. */ | |
352 | if (priv->mux_open) | |
353 | return 0; | |
354 | ||
355 | if (priv->mux_channel == chan) | |
356 | return 0; | |
357 | ||
358 | priv->mux_channel = chan; | |
359 | ||
3de09c7a JM |
360 | max9286_i2c_mux_configure(priv, MAX9286_FWDCCEN(chan) | |
361 | MAX9286_REVCCEN(chan)); | |
66d8c9d2 KB |
362 | |
363 | return 0; | |
364 | } | |
365 | ||
366 | static int max9286_i2c_mux_init(struct max9286_priv *priv) | |
367 | { | |
368 | struct max9286_source *source; | |
369 | int ret; | |
370 | ||
371 | if (!i2c_check_functionality(priv->client->adapter, | |
372 | I2C_FUNC_SMBUS_WRITE_BYTE_DATA)) | |
373 | return -ENODEV; | |
374 | ||
375 | priv->mux = i2c_mux_alloc(priv->client->adapter, &priv->client->dev, | |
376 | priv->nsources, 0, I2C_MUX_LOCKED, | |
377 | max9286_i2c_mux_select, NULL); | |
378 | if (!priv->mux) | |
379 | return -ENOMEM; | |
380 | ||
381 | priv->mux->priv = priv; | |
382 | ||
383 | for_each_source(priv, source) { | |
384 | unsigned int index = to_index(priv, source); | |
385 | ||
fec1982d | 386 | ret = i2c_mux_add_adapter(priv->mux, 0, index); |
66d8c9d2 KB |
387 | if (ret < 0) |
388 | goto error; | |
389 | } | |
390 | ||
391 | return 0; | |
392 | ||
393 | error: | |
394 | i2c_mux_del_adapters(priv->mux); | |
395 | return ret; | |
396 | } | |
397 | ||
398 | static void max9286_configure_i2c(struct max9286_priv *priv, bool localack) | |
399 | { | |
400 | u8 config = MAX9286_I2CSLVSH_469NS_234NS | MAX9286_I2CSLVTO_1024US | | |
e332061b | 401 | priv->i2c_mstbt; |
66d8c9d2 KB |
402 | |
403 | if (localack) | |
404 | config |= MAX9286_I2CLOCACK; | |
405 | ||
406 | max9286_write(priv, 0x34, config); | |
407 | usleep_range(3000, 5000); | |
408 | } | |
409 | ||
5a386b1f JM |
410 | static void max9286_reverse_channel_setup(struct max9286_priv *priv, |
411 | unsigned int chan_amplitude) | |
02b57eb3 | 412 | { |
902edc2a JM |
413 | u8 chan_config; |
414 | ||
415 | if (priv->rev_chan_mv == chan_amplitude) | |
416 | return; | |
417 | ||
418 | priv->rev_chan_mv = chan_amplitude; | |
419 | ||
5a386b1f | 420 | /* Reverse channel transmission time: default to 1. */ |
902edc2a | 421 | chan_config = MAX9286_REV_TRF(1); |
5a386b1f | 422 | |
02b57eb3 JM |
423 | /* |
424 | * Reverse channel setup. | |
425 | * | |
426 | * - Enable custom reverse channel configuration (through register 0x3f) | |
427 | * and set the first pulse length to 35 clock cycles. | |
5a386b1f JM |
428 | * - Adjust reverse channel amplitude: values > 130 are programmed |
429 | * using the additional +100mV REV_AMP_X boost flag | |
02b57eb3 JM |
430 | */ |
431 | max9286_write(priv, 0x3f, MAX9286_EN_REV_CFG | MAX9286_REV_FLEN(35)); | |
5a386b1f JM |
432 | |
433 | if (chan_amplitude > 100) { | |
434 | /* It is not possible to express values (100 < x < 130) */ | |
435 | chan_amplitude = max(30U, chan_amplitude - 100); | |
436 | chan_config |= MAX9286_REV_AMP_X; | |
437 | } | |
438 | max9286_write(priv, 0x3b, chan_config | MAX9286_REV_AMP(chan_amplitude)); | |
02b57eb3 JM |
439 | usleep_range(2000, 2500); |
440 | } | |
441 | ||
66d8c9d2 KB |
442 | /* |
443 | * max9286_check_video_links() - Make sure video links are detected and locked | |
444 | * | |
445 | * Performs safety checks on video link status. Make sure they are detected | |
446 | * and all enabled links are locked. | |
447 | * | |
448 | * Returns 0 for success, -EIO for errors. | |
449 | */ | |
450 | static int max9286_check_video_links(struct max9286_priv *priv) | |
451 | { | |
452 | unsigned int i; | |
453 | int ret; | |
454 | ||
455 | /* | |
456 | * Make sure valid video links are detected. | |
457 | * The delay is not characterized in de-serializer manual, wait up | |
458 | * to 5 ms. | |
459 | */ | |
460 | for (i = 0; i < 10; i++) { | |
461 | ret = max9286_read(priv, 0x49); | |
462 | if (ret < 0) | |
463 | return -EIO; | |
464 | ||
465 | if ((ret & MAX9286_VIDEO_DETECT_MASK) == priv->source_mask) | |
466 | break; | |
467 | ||
468 | usleep_range(350, 500); | |
469 | } | |
470 | ||
471 | if (i == 10) { | |
472 | dev_err(&priv->client->dev, | |
473 | "Unable to detect video links: 0x%02x\n", ret); | |
474 | return -EIO; | |
475 | } | |
476 | ||
477 | /* Make sure all enabled links are locked (4ms max). */ | |
478 | for (i = 0; i < 10; i++) { | |
479 | ret = max9286_read(priv, 0x27); | |
480 | if (ret < 0) | |
481 | return -EIO; | |
482 | ||
483 | if (ret & MAX9286_LOCKED) | |
484 | break; | |
485 | ||
486 | usleep_range(350, 450); | |
487 | } | |
488 | ||
489 | if (i == 10) { | |
490 | dev_err(&priv->client->dev, "Not all enabled links locked\n"); | |
491 | return -EIO; | |
492 | } | |
493 | ||
494 | return 0; | |
495 | } | |
496 | ||
497 | /* | |
498 | * max9286_check_config_link() - Detect and wait for configuration links | |
499 | * | |
500 | * Determine if the configuration channel is up and settled for a link. | |
501 | * | |
502 | * Returns 0 for success, -EIO for errors. | |
503 | */ | |
504 | static int max9286_check_config_link(struct max9286_priv *priv, | |
505 | unsigned int source_mask) | |
506 | { | |
507 | unsigned int conflink_mask = (source_mask & 0x0f) << 4; | |
508 | unsigned int i; | |
509 | int ret; | |
510 | ||
511 | /* | |
512 | * Make sure requested configuration links are detected. | |
513 | * The delay is not characterized in the chip manual: wait up | |
514 | * to 5 milliseconds. | |
515 | */ | |
516 | for (i = 0; i < 10; i++) { | |
e5b95c8f | 517 | ret = max9286_read(priv, 0x49); |
66d8c9d2 KB |
518 | if (ret < 0) |
519 | return -EIO; | |
520 | ||
e5b95c8f | 521 | ret &= 0xf0; |
66d8c9d2 KB |
522 | if (ret == conflink_mask) |
523 | break; | |
524 | ||
525 | usleep_range(350, 500); | |
526 | } | |
527 | ||
528 | if (ret != conflink_mask) { | |
529 | dev_err(&priv->client->dev, | |
530 | "Unable to detect configuration links: 0x%02x expected 0x%02x\n", | |
531 | ret, conflink_mask); | |
532 | return -EIO; | |
533 | } | |
534 | ||
535 | dev_info(&priv->client->dev, | |
536 | "Successfully detected configuration links after %u loops: 0x%02x\n", | |
537 | i, conflink_mask); | |
538 | ||
539 | return 0; | |
540 | } | |
541 | ||
f1403802 LP |
542 | static void max9286_set_video_format(struct max9286_priv *priv, |
543 | const struct v4l2_mbus_framefmt *format) | |
544 | { | |
545 | const struct max9286_format_info *info = NULL; | |
546 | unsigned int i; | |
547 | ||
548 | for (i = 0; i < ARRAY_SIZE(max9286_formats); ++i) { | |
549 | if (max9286_formats[i].code == format->code) { | |
550 | info = &max9286_formats[i]; | |
551 | break; | |
552 | } | |
553 | } | |
554 | ||
555 | if (WARN_ON(!info)) | |
556 | return; | |
557 | ||
558 | /* | |
cdcb186e LP |
559 | * Video format setup: disable CSI output, set VC according to Link |
560 | * number, enable I2C clock stretching when CCBSY is low, enable CCBSY | |
561 | * in external GPI-to-GPO mode. | |
f1403802 | 562 | */ |
cdcb186e LP |
563 | max9286_write(priv, 0x15, MAX9286_VCTYPE | MAX9286_EN_CCBSYB_CLK_STR | |
564 | MAX9286_EN_GPI_CCBSYB); | |
f1403802 LP |
565 | |
566 | /* Enable CSI-2 Lane D0-D3 only, DBL mode. */ | |
567 | max9286_write(priv, 0x12, MAX9286_CSIDBL | MAX9286_DBL | | |
568 | MAX9286_CSILANECNT(priv->csi2_data_lanes) | | |
569 | info->datatype); | |
570 | ||
40f75457 LP |
571 | /* |
572 | * Enable HS/VS encoding, use HS as line valid source, use D14/15 for | |
573 | * HS/VS, invert VS. | |
574 | */ | |
575 | max9286_write(priv, 0x0c, MAX9286_HVEN | MAX9286_DESEL | | |
576 | MAX9286_INVVS | MAX9286_HVSRC_D14); | |
f1403802 LP |
577 | } |
578 | ||
cffc9fb1 LP |
579 | static void max9286_set_fsync_period(struct max9286_priv *priv) |
580 | { | |
581 | u32 fsync; | |
582 | ||
583 | if (!priv->interval.numerator || !priv->interval.denominator) { | |
584 | /* | |
585 | * Special case, a null interval enables automatic FRAMESYNC | |
586 | * mode. FRAMESYNC is taken from the slowest link. | |
587 | */ | |
588 | max9286_write(priv, 0x01, MAX9286_FSYNCMODE_INT_HIZ | | |
589 | MAX9286_FSYNCMETH_AUTO); | |
590 | return; | |
591 | } | |
592 | ||
593 | /* | |
594 | * Manual FRAMESYNC | |
595 | * | |
596 | * The FRAMESYNC generator is configured with a period expressed as a | |
597 | * number of PCLK periods. | |
598 | */ | |
599 | fsync = div_u64((u64)priv->pixelrate * priv->interval.numerator, | |
600 | priv->interval.denominator); | |
601 | ||
602 | dev_dbg(&priv->client->dev, "fsync period %u (pclk %u)\n", fsync, | |
603 | priv->pixelrate); | |
604 | ||
605 | max9286_write(priv, 0x01, MAX9286_FSYNCMODE_INT_OUT | | |
606 | MAX9286_FSYNCMETH_MANUAL); | |
607 | ||
608 | max9286_write(priv, 0x06, (fsync >> 0) & 0xff); | |
609 | max9286_write(priv, 0x07, (fsync >> 8) & 0xff); | |
610 | max9286_write(priv, 0x08, (fsync >> 16) & 0xff); | |
611 | } | |
612 | ||
66d8c9d2 KB |
613 | /* ----------------------------------------------------------------------------- |
614 | * V4L2 Subdev | |
615 | */ | |
616 | ||
617 | static int max9286_set_pixelrate(struct max9286_priv *priv) | |
618 | { | |
619 | struct max9286_source *source = NULL; | |
620 | u64 pixelrate = 0; | |
621 | ||
622 | for_each_source(priv, source) { | |
623 | struct v4l2_ctrl *ctrl; | |
624 | u64 source_rate = 0; | |
625 | ||
626 | /* Pixel rate is mandatory to be reported by sources. */ | |
627 | ctrl = v4l2_ctrl_find(source->sd->ctrl_handler, | |
628 | V4L2_CID_PIXEL_RATE); | |
629 | if (!ctrl) { | |
630 | pixelrate = 0; | |
631 | break; | |
632 | } | |
633 | ||
634 | /* All source must report the same pixel rate. */ | |
635 | source_rate = v4l2_ctrl_g_ctrl_int64(ctrl); | |
636 | if (!pixelrate) { | |
637 | pixelrate = source_rate; | |
638 | } else if (pixelrate != source_rate) { | |
639 | dev_err(&priv->client->dev, | |
640 | "Unable to calculate pixel rate\n"); | |
641 | return -EINVAL; | |
642 | } | |
643 | } | |
644 | ||
645 | if (!pixelrate) { | |
646 | dev_err(&priv->client->dev, | |
647 | "No pixel rate control available in sources\n"); | |
648 | return -EINVAL; | |
649 | } | |
650 | ||
cffc9fb1 LP |
651 | priv->pixelrate = pixelrate; |
652 | ||
66d8c9d2 KB |
653 | /* |
654 | * The CSI-2 transmitter pixel rate is the single source rate multiplied | |
655 | * by the number of available sources. | |
656 | */ | |
cffc9fb1 | 657 | return v4l2_ctrl_s_ctrl_int64(priv->pixelrate_ctrl, |
66d8c9d2 KB |
658 | pixelrate * priv->nsources); |
659 | } | |
660 | ||
661 | static int max9286_notify_bound(struct v4l2_async_notifier *notifier, | |
662 | struct v4l2_subdev *subdev, | |
adb2dcd5 | 663 | struct v4l2_async_connection *asd) |
66d8c9d2 KB |
664 | { |
665 | struct max9286_priv *priv = sd_to_max9286(notifier->sd); | |
86d37bf3 | 666 | struct max9286_source *source = to_max9286_asd(asd)->source; |
66d8c9d2 KB |
667 | unsigned int index = to_index(priv, source); |
668 | unsigned int src_pad; | |
669 | int ret; | |
670 | ||
671 | ret = media_entity_get_fwnode_pad(&subdev->entity, | |
672 | source->fwnode, | |
673 | MEDIA_PAD_FL_SOURCE); | |
674 | if (ret < 0) { | |
675 | dev_err(&priv->client->dev, | |
676 | "Failed to find pad for %s\n", subdev->name); | |
677 | return ret; | |
678 | } | |
679 | ||
680 | priv->bound_sources |= BIT(index); | |
681 | source->sd = subdev; | |
682 | src_pad = ret; | |
683 | ||
684 | ret = media_create_pad_link(&source->sd->entity, src_pad, | |
685 | &priv->sd.entity, index, | |
686 | MEDIA_LNK_FL_ENABLED | | |
687 | MEDIA_LNK_FL_IMMUTABLE); | |
688 | if (ret) { | |
689 | dev_err(&priv->client->dev, | |
690 | "Unable to link %s:%u -> %s:%u\n", | |
691 | source->sd->name, src_pad, priv->sd.name, index); | |
692 | return ret; | |
693 | } | |
694 | ||
695 | dev_dbg(&priv->client->dev, "Bound %s pad: %u on index %u\n", | |
696 | subdev->name, src_pad, index); | |
697 | ||
698 | /* | |
4ff5278d JM |
699 | * As we register a subdev notifiers we won't get a .complete() callback |
700 | * here, so we have to use bound_sources to identify when all remote | |
701 | * serializers have probed. | |
66d8c9d2 KB |
702 | */ |
703 | if (priv->bound_sources != priv->source_mask) | |
704 | return 0; | |
705 | ||
706 | /* | |
707 | * All enabled sources have probed and enabled their reverse control | |
708 | * channels: | |
709 | * | |
85cb767c | 710 | * - Increase the reverse channel amplitude to compensate for the |
731c24ff | 711 | * remote ends high threshold |
66d8c9d2 KB |
712 | * - Verify all configuration links are properly detected |
713 | * - Disable auto-ack as communication on the control channel are now | |
714 | * stable. | |
715 | */ | |
731c24ff | 716 | max9286_reverse_channel_setup(priv, MAX9286_REV_AMP_HIGH); |
66d8c9d2 | 717 | max9286_check_config_link(priv, priv->source_mask); |
66d8c9d2 KB |
718 | max9286_configure_i2c(priv, false); |
719 | ||
720 | return max9286_set_pixelrate(priv); | |
721 | } | |
722 | ||
723 | static void max9286_notify_unbind(struct v4l2_async_notifier *notifier, | |
724 | struct v4l2_subdev *subdev, | |
adb2dcd5 | 725 | struct v4l2_async_connection *asd) |
66d8c9d2 KB |
726 | { |
727 | struct max9286_priv *priv = sd_to_max9286(notifier->sd); | |
86d37bf3 | 728 | struct max9286_source *source = to_max9286_asd(asd)->source; |
66d8c9d2 KB |
729 | unsigned int index = to_index(priv, source); |
730 | ||
731 | source->sd = NULL; | |
732 | priv->bound_sources &= ~BIT(index); | |
733 | } | |
734 | ||
735 | static const struct v4l2_async_notifier_operations max9286_notify_ops = { | |
736 | .bound = max9286_notify_bound, | |
737 | .unbind = max9286_notify_unbind, | |
738 | }; | |
739 | ||
740 | static int max9286_v4l2_notifier_register(struct max9286_priv *priv) | |
741 | { | |
742 | struct device *dev = &priv->client->dev; | |
743 | struct max9286_source *source = NULL; | |
744 | int ret; | |
745 | ||
746 | if (!priv->nsources) | |
747 | return 0; | |
748 | ||
b8ec754a | 749 | v4l2_async_subdev_nf_init(&priv->notifier, &priv->sd); |
66d8c9d2 KB |
750 | |
751 | for_each_source(priv, source) { | |
752 | unsigned int i = to_index(priv, source); | |
b01edcbd | 753 | struct max9286_asd *mas; |
86d37bf3 | 754 | |
3c8c1539 SA |
755 | mas = v4l2_async_nf_add_fwnode(&priv->notifier, source->fwnode, |
756 | struct max9286_asd); | |
b01edcbd | 757 | if (IS_ERR(mas)) { |
86d37bf3 | 758 | dev_err(dev, "Failed to add subdev for source %u: %ld", |
b01edcbd | 759 | i, PTR_ERR(mas)); |
3c8c1539 | 760 | v4l2_async_nf_cleanup(&priv->notifier); |
b01edcbd | 761 | return PTR_ERR(mas); |
66d8c9d2 KB |
762 | } |
763 | ||
b01edcbd | 764 | mas->source = source; |
66d8c9d2 KB |
765 | } |
766 | ||
767 | priv->notifier.ops = &max9286_notify_ops; | |
768 | ||
b8ec754a | 769 | ret = v4l2_async_nf_register(&priv->notifier); |
66d8c9d2 KB |
770 | if (ret) { |
771 | dev_err(dev, "Failed to register subdev_notifier"); | |
3c8c1539 | 772 | v4l2_async_nf_cleanup(&priv->notifier); |
66d8c9d2 KB |
773 | return ret; |
774 | } | |
775 | ||
776 | return 0; | |
777 | } | |
778 | ||
779 | static void max9286_v4l2_notifier_unregister(struct max9286_priv *priv) | |
780 | { | |
781 | if (!priv->nsources) | |
782 | return; | |
783 | ||
3c8c1539 SA |
784 | v4l2_async_nf_unregister(&priv->notifier); |
785 | v4l2_async_nf_cleanup(&priv->notifier); | |
66d8c9d2 KB |
786 | } |
787 | ||
788 | static int max9286_s_stream(struct v4l2_subdev *sd, int enable) | |
789 | { | |
790 | struct max9286_priv *priv = sd_to_max9286(sd); | |
791 | struct max9286_source *source; | |
792 | unsigned int i; | |
793 | bool sync = false; | |
794 | int ret; | |
795 | ||
796 | if (enable) { | |
f1403802 LP |
797 | const struct v4l2_mbus_framefmt *format; |
798 | ||
799 | /* | |
800 | * Get the format from the first used sink pad, as all sink | |
801 | * formats must be identical. | |
802 | */ | |
803 | format = &priv->fmt[__ffs(priv->bound_sources)]; | |
804 | ||
805 | max9286_set_video_format(priv, format); | |
cffc9fb1 LP |
806 | max9286_set_fsync_period(priv); |
807 | ||
66d8c9d2 KB |
808 | /* |
809 | * The frame sync between cameras is transmitted across the | |
810 | * reverse channel as GPIO. We must open all channels while | |
811 | * streaming to allow this synchronisation signal to be shared. | |
812 | */ | |
813 | max9286_i2c_mux_open(priv); | |
814 | ||
815 | /* Start all cameras. */ | |
816 | for_each_source(priv, source) { | |
817 | ret = v4l2_subdev_call(source->sd, video, s_stream, 1); | |
818 | if (ret) | |
819 | return ret; | |
820 | } | |
821 | ||
822 | ret = max9286_check_video_links(priv); | |
823 | if (ret) | |
824 | return ret; | |
825 | ||
826 | /* | |
827 | * Wait until frame synchronization is locked. | |
828 | * | |
829 | * Manual says frame sync locking should take ~6 VTS. | |
830 | * From practical experience at least 8 are required. Give | |
831 | * 12 complete frames time (~400ms at 30 fps) to achieve frame | |
832 | * locking before returning error. | |
833 | */ | |
834 | for (i = 0; i < 40; i++) { | |
835 | if (max9286_read(priv, 0x31) & MAX9286_FSYNC_LOCKED) { | |
836 | sync = true; | |
837 | break; | |
838 | } | |
839 | usleep_range(9000, 11000); | |
840 | } | |
841 | ||
842 | if (!sync) { | |
843 | dev_err(&priv->client->dev, | |
844 | "Failed to get frame synchronization\n"); | |
845 | return -EXDEV; /* Invalid cross-device link */ | |
846 | } | |
847 | ||
848 | /* | |
cdcb186e LP |
849 | * Configure the CSI-2 output to line interleaved mode (W x (N |
850 | * x H), as opposed to the (N x W) x H mode that outputs the | |
851 | * images stitched side-by-side) and enable it. | |
66d8c9d2 | 852 | */ |
cdcb186e LP |
853 | max9286_write(priv, 0x15, MAX9286_CSI_IMAGE_TYP | MAX9286_VCTYPE | |
854 | MAX9286_CSIOUTEN | MAX9286_EN_CCBSYB_CLK_STR | | |
855 | MAX9286_EN_GPI_CCBSYB); | |
66d8c9d2 | 856 | } else { |
cdcb186e LP |
857 | max9286_write(priv, 0x15, MAX9286_VCTYPE | |
858 | MAX9286_EN_CCBSYB_CLK_STR | | |
859 | MAX9286_EN_GPI_CCBSYB); | |
66d8c9d2 KB |
860 | |
861 | /* Stop all cameras. */ | |
862 | for_each_source(priv, source) | |
863 | v4l2_subdev_call(source->sd, video, s_stream, 0); | |
864 | ||
865 | max9286_i2c_mux_close(priv); | |
866 | } | |
867 | ||
868 | return 0; | |
869 | } | |
870 | ||
287fe160 LP |
871 | static int max9286_get_frame_interval(struct v4l2_subdev *sd, |
872 | struct v4l2_subdev_state *sd_state, | |
873 | struct v4l2_subdev_frame_interval *interval) | |
cffc9fb1 LP |
874 | { |
875 | struct max9286_priv *priv = sd_to_max9286(sd); | |
876 | ||
805d4311 LP |
877 | /* |
878 | * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2 | |
879 | * subdev active state API. | |
880 | */ | |
881 | if (interval->which != V4L2_SUBDEV_FORMAT_ACTIVE) | |
882 | return -EINVAL; | |
883 | ||
cffc9fb1 LP |
884 | if (interval->pad != MAX9286_SRC_PAD) |
885 | return -EINVAL; | |
886 | ||
887 | interval->interval = priv->interval; | |
888 | ||
889 | return 0; | |
890 | } | |
891 | ||
287fe160 LP |
892 | static int max9286_set_frame_interval(struct v4l2_subdev *sd, |
893 | struct v4l2_subdev_state *sd_state, | |
894 | struct v4l2_subdev_frame_interval *interval) | |
cffc9fb1 LP |
895 | { |
896 | struct max9286_priv *priv = sd_to_max9286(sd); | |
897 | ||
805d4311 LP |
898 | /* |
899 | * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2 | |
900 | * subdev active state API. | |
901 | */ | |
902 | if (interval->which != V4L2_SUBDEV_FORMAT_ACTIVE) | |
903 | return -EINVAL; | |
904 | ||
cffc9fb1 LP |
905 | if (interval->pad != MAX9286_SRC_PAD) |
906 | return -EINVAL; | |
907 | ||
908 | priv->interval = interval->interval; | |
909 | ||
910 | return 0; | |
911 | } | |
912 | ||
66d8c9d2 | 913 | static int max9286_enum_mbus_code(struct v4l2_subdev *sd, |
0d346d2a | 914 | struct v4l2_subdev_state *sd_state, |
66d8c9d2 KB |
915 | struct v4l2_subdev_mbus_code_enum *code) |
916 | { | |
917 | if (code->pad || code->index > 0) | |
918 | return -EINVAL; | |
919 | ||
920 | code->code = MEDIA_BUS_FMT_UYVY8_1X16; | |
921 | ||
922 | return 0; | |
923 | } | |
924 | ||
925 | static struct v4l2_mbus_framefmt * | |
926 | max9286_get_pad_format(struct max9286_priv *priv, | |
0d346d2a | 927 | struct v4l2_subdev_state *sd_state, |
66d8c9d2 KB |
928 | unsigned int pad, u32 which) |
929 | { | |
930 | switch (which) { | |
931 | case V4L2_SUBDEV_FORMAT_TRY: | |
bc0e8d91 | 932 | return v4l2_subdev_state_get_format(sd_state, pad); |
66d8c9d2 KB |
933 | case V4L2_SUBDEV_FORMAT_ACTIVE: |
934 | return &priv->fmt[pad]; | |
935 | default: | |
936 | return NULL; | |
937 | } | |
938 | } | |
939 | ||
940 | static int max9286_set_fmt(struct v4l2_subdev *sd, | |
0d346d2a | 941 | struct v4l2_subdev_state *sd_state, |
66d8c9d2 KB |
942 | struct v4l2_subdev_format *format) |
943 | { | |
944 | struct max9286_priv *priv = sd_to_max9286(sd); | |
945 | struct v4l2_mbus_framefmt *cfg_fmt; | |
f1403802 | 946 | unsigned int i; |
66d8c9d2 KB |
947 | |
948 | if (format->pad == MAX9286_SRC_PAD) | |
949 | return -EINVAL; | |
950 | ||
f1403802 LP |
951 | /* Validate the format. */ |
952 | for (i = 0; i < ARRAY_SIZE(max9286_formats); ++i) { | |
953 | if (max9286_formats[i].code == format->format.code) | |
954 | break; | |
66d8c9d2 KB |
955 | } |
956 | ||
f1403802 LP |
957 | if (i == ARRAY_SIZE(max9286_formats)) |
958 | format->format.code = max9286_formats[0].code; | |
959 | ||
0d346d2a TV |
960 | cfg_fmt = max9286_get_pad_format(priv, sd_state, format->pad, |
961 | format->which); | |
66d8c9d2 KB |
962 | if (!cfg_fmt) |
963 | return -EINVAL; | |
964 | ||
965 | mutex_lock(&priv->mutex); | |
966 | *cfg_fmt = format->format; | |
967 | mutex_unlock(&priv->mutex); | |
968 | ||
969 | return 0; | |
970 | } | |
971 | ||
972 | static int max9286_get_fmt(struct v4l2_subdev *sd, | |
0d346d2a | 973 | struct v4l2_subdev_state *sd_state, |
66d8c9d2 KB |
974 | struct v4l2_subdev_format *format) |
975 | { | |
976 | struct max9286_priv *priv = sd_to_max9286(sd); | |
977 | struct v4l2_mbus_framefmt *cfg_fmt; | |
978 | unsigned int pad = format->pad; | |
979 | ||
980 | /* | |
981 | * Multiplexed Stream Support: Support link validation by returning the | |
982 | * format of the first bound link. All links must have the same format, | |
983 | * as we do not support mixing and matching of cameras connected to the | |
984 | * max9286. | |
985 | */ | |
986 | if (pad == MAX9286_SRC_PAD) | |
987 | pad = __ffs(priv->bound_sources); | |
988 | ||
0d346d2a | 989 | cfg_fmt = max9286_get_pad_format(priv, sd_state, pad, format->which); |
66d8c9d2 KB |
990 | if (!cfg_fmt) |
991 | return -EINVAL; | |
992 | ||
993 | mutex_lock(&priv->mutex); | |
994 | format->format = *cfg_fmt; | |
995 | mutex_unlock(&priv->mutex); | |
996 | ||
997 | return 0; | |
998 | } | |
999 | ||
1000 | static const struct v4l2_subdev_video_ops max9286_video_ops = { | |
1001 | .s_stream = max9286_s_stream, | |
1002 | }; | |
1003 | ||
1004 | static const struct v4l2_subdev_pad_ops max9286_pad_ops = { | |
1005 | .enum_mbus_code = max9286_enum_mbus_code, | |
1006 | .get_fmt = max9286_get_fmt, | |
1007 | .set_fmt = max9286_set_fmt, | |
287fe160 LP |
1008 | .get_frame_interval = max9286_get_frame_interval, |
1009 | .set_frame_interval = max9286_set_frame_interval, | |
66d8c9d2 KB |
1010 | }; |
1011 | ||
1012 | static const struct v4l2_subdev_ops max9286_subdev_ops = { | |
1013 | .video = &max9286_video_ops, | |
1014 | .pad = &max9286_pad_ops, | |
1015 | }; | |
1016 | ||
f1403802 LP |
1017 | static const struct v4l2_mbus_framefmt max9286_default_format = { |
1018 | .width = 1280, | |
1019 | .height = 800, | |
1020 | .code = MEDIA_BUS_FMT_UYVY8_1X16, | |
1021 | .colorspace = V4L2_COLORSPACE_SRGB, | |
1022 | .field = V4L2_FIELD_NONE, | |
1023 | .ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT, | |
1024 | .quantization = V4L2_QUANTIZATION_DEFAULT, | |
1025 | .xfer_func = V4L2_XFER_FUNC_DEFAULT, | |
1026 | }; | |
1027 | ||
66d8c9d2 KB |
1028 | static void max9286_init_format(struct v4l2_mbus_framefmt *fmt) |
1029 | { | |
f1403802 | 1030 | *fmt = max9286_default_format; |
66d8c9d2 KB |
1031 | } |
1032 | ||
1033 | static int max9286_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh) | |
1034 | { | |
1035 | struct v4l2_mbus_framefmt *format; | |
1036 | unsigned int i; | |
1037 | ||
1038 | for (i = 0; i < MAX9286_N_SINKS; i++) { | |
bc0e8d91 | 1039 | format = v4l2_subdev_state_get_format(fh->state, i); |
66d8c9d2 KB |
1040 | max9286_init_format(format); |
1041 | } | |
1042 | ||
1043 | return 0; | |
1044 | } | |
1045 | ||
1046 | static const struct v4l2_subdev_internal_ops max9286_subdev_internal_ops = { | |
1047 | .open = max9286_open, | |
1048 | }; | |
1049 | ||
1fe6ae4e LP |
1050 | static const struct media_entity_operations max9286_media_ops = { |
1051 | .link_validate = v4l2_subdev_link_validate | |
1052 | }; | |
1053 | ||
66d8c9d2 KB |
1054 | static int max9286_s_ctrl(struct v4l2_ctrl *ctrl) |
1055 | { | |
1056 | switch (ctrl->id) { | |
1057 | case V4L2_CID_PIXEL_RATE: | |
1058 | return 0; | |
1059 | default: | |
1060 | return -EINVAL; | |
1061 | } | |
1062 | } | |
1063 | ||
1064 | static const struct v4l2_ctrl_ops max9286_ctrl_ops = { | |
1065 | .s_ctrl = max9286_s_ctrl, | |
1066 | }; | |
1067 | ||
1068 | static int max9286_v4l2_register(struct max9286_priv *priv) | |
1069 | { | |
1070 | struct device *dev = &priv->client->dev; | |
66d8c9d2 KB |
1071 | int ret; |
1072 | int i; | |
1073 | ||
1074 | /* Register v4l2 async notifiers for connected Camera subdevices */ | |
1075 | ret = max9286_v4l2_notifier_register(priv); | |
1076 | if (ret) { | |
1077 | dev_err(dev, "Unable to register V4L2 async notifiers\n"); | |
1078 | return ret; | |
1079 | } | |
1080 | ||
1081 | /* Configure V4L2 for the MAX9286 itself */ | |
1082 | ||
1083 | for (i = 0; i < MAX9286_N_SINKS; i++) | |
1084 | max9286_init_format(&priv->fmt[i]); | |
1085 | ||
1086 | v4l2_i2c_subdev_init(&priv->sd, priv->client, &max9286_subdev_ops); | |
1087 | priv->sd.internal_ops = &max9286_subdev_internal_ops; | |
1088 | priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; | |
1089 | ||
1090 | v4l2_ctrl_handler_init(&priv->ctrls, 1); | |
cffc9fb1 LP |
1091 | priv->pixelrate_ctrl = v4l2_ctrl_new_std(&priv->ctrls, |
1092 | &max9286_ctrl_ops, | |
1093 | V4L2_CID_PIXEL_RATE, | |
1094 | 1, INT_MAX, 1, 50000000); | |
66d8c9d2 KB |
1095 | |
1096 | priv->sd.ctrl_handler = &priv->ctrls; | |
1097 | ret = priv->ctrls.error; | |
1098 | if (ret) | |
1099 | goto err_async; | |
1100 | ||
1101 | priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; | |
1fe6ae4e | 1102 | priv->sd.entity.ops = &max9286_media_ops; |
66d8c9d2 KB |
1103 | |
1104 | priv->pads[MAX9286_SRC_PAD].flags = MEDIA_PAD_FL_SOURCE; | |
1105 | for (i = 0; i < MAX9286_SRC_PAD; i++) | |
1106 | priv->pads[i].flags = MEDIA_PAD_FL_SINK; | |
1107 | ret = media_entity_pads_init(&priv->sd.entity, MAX9286_N_PADS, | |
1108 | priv->pads); | |
1109 | if (ret) | |
1110 | goto err_async; | |
1111 | ||
66d8c9d2 KB |
1112 | ret = v4l2_async_register_subdev(&priv->sd); |
1113 | if (ret < 0) { | |
1114 | dev_err(dev, "Unable to register subdevice\n"); | |
1029939b | 1115 | goto err_async; |
66d8c9d2 KB |
1116 | } |
1117 | ||
1118 | return 0; | |
1119 | ||
66d8c9d2 | 1120 | err_async: |
8636c5fc | 1121 | v4l2_ctrl_handler_free(&priv->ctrls); |
66d8c9d2 KB |
1122 | max9286_v4l2_notifier_unregister(priv); |
1123 | ||
1124 | return ret; | |
1125 | } | |
1126 | ||
1127 | static void max9286_v4l2_unregister(struct max9286_priv *priv) | |
1128 | { | |
bfce6a12 | 1129 | v4l2_ctrl_handler_free(&priv->ctrls); |
66d8c9d2 KB |
1130 | v4l2_async_unregister_subdev(&priv->sd); |
1131 | max9286_v4l2_notifier_unregister(priv); | |
1132 | } | |
1133 | ||
1134 | /* ----------------------------------------------------------------------------- | |
1135 | * Probe/Remove | |
1136 | */ | |
1137 | ||
1138 | static int max9286_setup(struct max9286_priv *priv) | |
1139 | { | |
1140 | /* | |
1141 | * Link ordering values for all enabled links combinations. Orders must | |
1142 | * be assigned sequentially from 0 to the number of enabled links | |
1143 | * without leaving any hole for disabled links. We thus assign orders to | |
1144 | * enabled links first, and use the remaining order values for disabled | |
1145 | * links are all links must have a different order value; | |
1146 | */ | |
1147 | static const u8 link_order[] = { | |
1148 | (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xxxx */ | |
1149 | (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xxx0 */ | |
1150 | (3 << 6) | (2 << 4) | (0 << 2) | (1 << 0), /* xx0x */ | |
1151 | (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xx10 */ | |
1152 | (3 << 6) | (0 << 4) | (2 << 2) | (1 << 0), /* x0xx */ | |
1153 | (3 << 6) | (1 << 4) | (2 << 2) | (0 << 0), /* x1x0 */ | |
1154 | (3 << 6) | (1 << 4) | (0 << 2) | (2 << 0), /* x10x */ | |
1155 | (3 << 6) | (1 << 4) | (1 << 2) | (0 << 0), /* x210 */ | |
1156 | (0 << 6) | (3 << 4) | (2 << 2) | (1 << 0), /* 0xxx */ | |
1157 | (1 << 6) | (3 << 4) | (2 << 2) | (0 << 0), /* 1xx0 */ | |
1158 | (1 << 6) | (3 << 4) | (0 << 2) | (2 << 0), /* 1x0x */ | |
1159 | (2 << 6) | (3 << 4) | (1 << 2) | (0 << 0), /* 2x10 */ | |
1160 | (1 << 6) | (0 << 4) | (3 << 2) | (2 << 0), /* 10xx */ | |
1161 | (2 << 6) | (1 << 4) | (3 << 2) | (0 << 0), /* 21x0 */ | |
1162 | (2 << 6) | (1 << 4) | (0 << 2) | (3 << 0), /* 210x */ | |
1163 | (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* 3210 */ | |
1164 | }; | |
defcedfb | 1165 | int cfg; |
66d8c9d2 KB |
1166 | |
1167 | /* | |
1168 | * Set the I2C bus speed. | |
1169 | * | |
1170 | * Enable I2C Local Acknowledge during the probe sequences of the camera | |
1171 | * only. This should be disabled after the mux is initialised. | |
1172 | */ | |
1173 | max9286_configure_i2c(priv, true); | |
f78723eb | 1174 | max9286_reverse_channel_setup(priv, priv->init_rev_chan_mv); |
66d8c9d2 KB |
1175 | |
1176 | /* | |
1177 | * Enable GMSL links, mask unused ones and autodetect link | |
1178 | * used as CSI clock source. | |
1179 | */ | |
1180 | max9286_write(priv, 0x00, MAX9286_MSTLINKSEL_AUTO | priv->route_mask); | |
1181 | max9286_write(priv, 0x0b, link_order[priv->route_mask]); | |
1182 | max9286_write(priv, 0x69, (0xf & ~priv->route_mask)); | |
1183 | ||
f1403802 | 1184 | max9286_set_video_format(priv, &max9286_default_format); |
cffc9fb1 | 1185 | max9286_set_fsync_period(priv); |
66d8c9d2 | 1186 | |
defcedfb LP |
1187 | cfg = max9286_read(priv, 0x1c); |
1188 | if (cfg < 0) | |
1189 | return cfg; | |
3697f108 | 1190 | |
defcedfb LP |
1191 | dev_dbg(&priv->client->dev, "power-up config: %s immunity, %u-bit bus\n", |
1192 | cfg & MAX9286_HIGHIMM(0) ? "high" : "legacy", | |
1193 | cfg & MAX9286_BWS ? 32 : cfg & MAX9286_HIBW ? 27 : 24); | |
3697f108 | 1194 | |
defcedfb LP |
1195 | if (priv->bus_width) { |
1196 | cfg &= ~(MAX9286_HIBW | MAX9286_BWS); | |
3697f108 LP |
1197 | |
1198 | if (priv->bus_width == 27) | |
defcedfb | 1199 | cfg |= MAX9286_HIBW; |
3697f108 | 1200 | else if (priv->bus_width == 32) |
defcedfb | 1201 | cfg |= MAX9286_BWS; |
3697f108 | 1202 | |
defcedfb | 1203 | max9286_write(priv, 0x1c, cfg); |
3697f108 LP |
1204 | } |
1205 | ||
66d8c9d2 KB |
1206 | /* |
1207 | * The overlap window seems to provide additional validation by tracking | |
1208 | * the delay between vsync and frame sync, generating an error if the | |
1209 | * delay is bigger than the programmed window, though it's not yet clear | |
1210 | * what value should be set. | |
1211 | * | |
1212 | * As it's an optional value and can be disabled, we do so by setting | |
1213 | * a 0 overlap value. | |
1214 | */ | |
1215 | max9286_write(priv, 0x63, 0); | |
1216 | max9286_write(priv, 0x64, 0); | |
1217 | ||
1218 | /* | |
1219 | * Wait for 2ms to allow the link to resynchronize after the | |
1220 | * configuration change. | |
1221 | */ | |
1222 | usleep_range(2000, 5000); | |
1223 | ||
1224 | return 0; | |
1225 | } | |
1226 | ||
c9352df7 JM |
1227 | static int max9286_gpio_set(struct max9286_priv *priv, unsigned int offset, |
1228 | int value) | |
66d8c9d2 | 1229 | { |
66d8c9d2 KB |
1230 | if (value) |
1231 | priv->gpio_state |= BIT(offset); | |
1232 | else | |
1233 | priv->gpio_state &= ~BIT(offset); | |
1234 | ||
c9352df7 JM |
1235 | return max9286_write(priv, 0x0f, |
1236 | MAX9286_0X0F_RESERVED | priv->gpio_state); | |
66d8c9d2 KB |
1237 | } |
1238 | ||
c9352df7 JM |
1239 | static void max9286_gpiochip_set(struct gpio_chip *chip, |
1240 | unsigned int offset, int value) | |
1241 | { | |
1242 | struct max9286_priv *priv = gpiochip_get_data(chip); | |
1243 | ||
1244 | max9286_gpio_set(priv, offset, value); | |
1245 | } | |
1246 | ||
1247 | static int max9286_gpiochip_get(struct gpio_chip *chip, unsigned int offset) | |
66d8c9d2 KB |
1248 | { |
1249 | struct max9286_priv *priv = gpiochip_get_data(chip); | |
1250 | ||
1251 | return priv->gpio_state & BIT(offset); | |
1252 | } | |
1253 | ||
1254 | static int max9286_register_gpio(struct max9286_priv *priv) | |
1255 | { | |
1256 | struct device *dev = &priv->client->dev; | |
1257 | struct gpio_chip *gpio = &priv->gpio; | |
1258 | int ret; | |
1259 | ||
1260 | /* Configure the GPIO */ | |
1261 | gpio->label = dev_name(dev); | |
1262 | gpio->parent = dev; | |
1263 | gpio->owner = THIS_MODULE; | |
66d8c9d2 KB |
1264 | gpio->ngpio = 2; |
1265 | gpio->base = -1; | |
c9352df7 JM |
1266 | gpio->set = max9286_gpiochip_set; |
1267 | gpio->get = max9286_gpiochip_get; | |
66d8c9d2 KB |
1268 | gpio->can_sleep = true; |
1269 | ||
66d8c9d2 KB |
1270 | ret = devm_gpiochip_add_data(dev, gpio, priv); |
1271 | if (ret) | |
1272 | dev_err(dev, "Unable to create gpio_chip\n"); | |
1273 | ||
1274 | return ret; | |
1275 | } | |
1276 | ||
c9352df7 JM |
1277 | static int max9286_parse_gpios(struct max9286_priv *priv) |
1278 | { | |
1279 | struct device *dev = &priv->client->dev; | |
1280 | int ret; | |
1281 | ||
c9352df7 JM |
1282 | /* |
1283 | * Parse the "gpio-poc" vendor property. If the property is not | |
1284 | * specified the camera power is controlled by a regulator. | |
1285 | */ | |
1286 | ret = of_property_read_u32_array(dev->of_node, "maxim,gpio-poc", | |
1287 | priv->gpio_poc, 2); | |
1288 | if (ret == -EINVAL) { | |
1289 | /* | |
1290 | * If gpio lines are not used for the camera power, register | |
1291 | * a gpio controller for consumers. | |
1292 | */ | |
817660f4 | 1293 | return max9286_register_gpio(priv); |
c9352df7 JM |
1294 | } |
1295 | ||
1296 | /* If the property is specified make sure it is well formed. */ | |
1297 | if (ret || priv->gpio_poc[0] > 1 || | |
1298 | (priv->gpio_poc[1] != GPIO_ACTIVE_HIGH && | |
1299 | priv->gpio_poc[1] != GPIO_ACTIVE_LOW)) { | |
1300 | dev_err(dev, "Invalid 'gpio-poc' property\n"); | |
1301 | return -EINVAL; | |
1302 | } | |
1303 | ||
817660f4 | 1304 | priv->use_gpio_poc = true; |
c9352df7 JM |
1305 | return 0; |
1306 | } | |
1307 | ||
817660f4 TN |
1308 | static int max9286_poc_power_on(struct max9286_priv *priv) |
1309 | { | |
1310 | struct max9286_source *source; | |
1311 | unsigned int enabled = 0; | |
1312 | int ret; | |
1313 | ||
1314 | /* Enable the global regulator if available. */ | |
1315 | if (priv->regulator) | |
1316 | return regulator_enable(priv->regulator); | |
1317 | ||
1318 | if (priv->use_gpio_poc) | |
1319 | return max9286_gpio_set(priv, priv->gpio_poc[0], | |
1320 | !priv->gpio_poc[1]); | |
1321 | ||
1322 | /* Otherwise use the per-port regulators. */ | |
1323 | for_each_source(priv, source) { | |
1324 | ret = regulator_enable(source->regulator); | |
1325 | if (ret < 0) | |
1326 | goto error; | |
1327 | ||
1328 | enabled |= BIT(to_index(priv, source)); | |
1329 | } | |
1330 | ||
1331 | return 0; | |
1332 | ||
1333 | error: | |
1334 | for_each_source(priv, source) { | |
1335 | if (enabled & BIT(to_index(priv, source))) | |
1336 | regulator_disable(source->regulator); | |
1337 | } | |
1338 | ||
1339 | return ret; | |
1340 | } | |
1341 | ||
1342 | static int max9286_poc_power_off(struct max9286_priv *priv) | |
1343 | { | |
1344 | struct max9286_source *source; | |
1345 | int ret = 0; | |
1346 | ||
1347 | if (priv->regulator) | |
1348 | return regulator_disable(priv->regulator); | |
1349 | ||
1350 | if (priv->use_gpio_poc) | |
1351 | return max9286_gpio_set(priv, priv->gpio_poc[0], | |
1352 | priv->gpio_poc[1]); | |
1353 | ||
1354 | for_each_source(priv, source) { | |
1355 | int err; | |
1356 | ||
1357 | err = regulator_disable(source->regulator); | |
1358 | if (!ret) | |
1359 | ret = err; | |
1360 | } | |
1361 | ||
1362 | return ret; | |
1363 | } | |
1364 | ||
c9352df7 JM |
1365 | static int max9286_poc_enable(struct max9286_priv *priv, bool enable) |
1366 | { | |
1367 | int ret; | |
1368 | ||
817660f4 TN |
1369 | if (enable) |
1370 | ret = max9286_poc_power_on(priv); | |
c9352df7 | 1371 | else |
817660f4 | 1372 | ret = max9286_poc_power_off(priv); |
c9352df7 JM |
1373 | |
1374 | if (ret < 0) | |
1375 | dev_err(&priv->client->dev, "Unable to turn power %s\n", | |
1376 | enable ? "on" : "off"); | |
1377 | ||
1378 | return ret; | |
1379 | } | |
1380 | ||
365ab7eb | 1381 | static int max9286_init(struct max9286_priv *priv) |
66d8c9d2 | 1382 | { |
365ab7eb | 1383 | struct i2c_client *client = priv->client; |
66d8c9d2 KB |
1384 | int ret; |
1385 | ||
c9352df7 JM |
1386 | ret = max9286_poc_enable(priv, true); |
1387 | if (ret) | |
66d8c9d2 | 1388 | return ret; |
66d8c9d2 KB |
1389 | |
1390 | ret = max9286_setup(priv); | |
1391 | if (ret) { | |
365ab7eb | 1392 | dev_err(&client->dev, "Unable to setup max9286\n"); |
c9352df7 | 1393 | goto err_poc_disable; |
66d8c9d2 KB |
1394 | } |
1395 | ||
1396 | /* | |
1397 | * Register all V4L2 interactions for the MAX9286 and notifiers for | |
1398 | * any subdevices connected. | |
1399 | */ | |
1400 | ret = max9286_v4l2_register(priv); | |
1401 | if (ret) { | |
365ab7eb | 1402 | dev_err(&client->dev, "Failed to register with V4L2\n"); |
c9352df7 | 1403 | goto err_poc_disable; |
66d8c9d2 KB |
1404 | } |
1405 | ||
1406 | ret = max9286_i2c_mux_init(priv); | |
1407 | if (ret) { | |
365ab7eb | 1408 | dev_err(&client->dev, "Unable to initialize I2C multiplexer\n"); |
66d8c9d2 KB |
1409 | goto err_v4l2_register; |
1410 | } | |
1411 | ||
1412 | /* Leave the mux channels disabled until they are selected. */ | |
1413 | max9286_i2c_mux_close(priv); | |
1414 | ||
1415 | return 0; | |
1416 | ||
1417 | err_v4l2_register: | |
1418 | max9286_v4l2_unregister(priv); | |
c9352df7 JM |
1419 | err_poc_disable: |
1420 | max9286_poc_enable(priv, false); | |
66d8c9d2 KB |
1421 | |
1422 | return ret; | |
1423 | } | |
1424 | ||
1425 | static void max9286_cleanup_dt(struct max9286_priv *priv) | |
1426 | { | |
1427 | struct max9286_source *source; | |
1428 | ||
1429 | for_each_source(priv, source) { | |
1430 | fwnode_handle_put(source->fwnode); | |
1431 | source->fwnode = NULL; | |
1432 | } | |
1433 | } | |
1434 | ||
1435 | static int max9286_parse_dt(struct max9286_priv *priv) | |
1436 | { | |
1437 | struct device *dev = &priv->client->dev; | |
1438 | struct device_node *i2c_mux; | |
1439 | struct device_node *node = NULL; | |
1440 | unsigned int i2c_mux_mask = 0; | |
85cb767c | 1441 | u32 reverse_channel_microvolt; |
e332061b LP |
1442 | u32 i2c_clk_freq = 105000; |
1443 | unsigned int i; | |
66d8c9d2 KB |
1444 | |
1445 | /* Balance the of_node_put() performed by of_find_node_by_name(). */ | |
1446 | of_node_get(dev->of_node); | |
1447 | i2c_mux = of_find_node_by_name(dev->of_node, "i2c-mux"); | |
1448 | if (!i2c_mux) { | |
1449 | dev_err(dev, "Failed to find i2c-mux node\n"); | |
1450 | return -EINVAL; | |
1451 | } | |
1452 | ||
1453 | /* Identify which i2c-mux channels are enabled */ | |
1454 | for_each_child_of_node(i2c_mux, node) { | |
1455 | u32 id = 0; | |
1456 | ||
1457 | of_property_read_u32(node, "reg", &id); | |
1458 | if (id >= MAX9286_NUM_GMSL) | |
1459 | continue; | |
1460 | ||
1461 | if (!of_device_is_available(node)) { | |
1462 | dev_dbg(dev, "Skipping disabled I2C bus port %u\n", id); | |
1463 | continue; | |
1464 | } | |
1465 | ||
1466 | i2c_mux_mask |= BIT(id); | |
1467 | } | |
66d8c9d2 KB |
1468 | of_node_put(i2c_mux); |
1469 | ||
1470 | /* Parse the endpoints */ | |
1471 | for_each_endpoint_of_node(dev->of_node, node) { | |
1472 | struct max9286_source *source; | |
1473 | struct of_endpoint ep; | |
1474 | ||
1475 | of_graph_parse_endpoint(node, &ep); | |
1476 | dev_dbg(dev, "Endpoint %pOF on port %d", | |
1477 | ep.local_node, ep.port); | |
1478 | ||
1479 | if (ep.port > MAX9286_NUM_GMSL) { | |
1480 | dev_err(dev, "Invalid endpoint %s on port %d", | |
1481 | of_node_full_name(ep.local_node), ep.port); | |
1482 | continue; | |
1483 | } | |
1484 | ||
1485 | /* For the source endpoint just parse the bus configuration. */ | |
1486 | if (ep.port == MAX9286_SRC_PAD) { | |
1487 | struct v4l2_fwnode_endpoint vep = { | |
1488 | .bus_type = V4L2_MBUS_CSI2_DPHY | |
1489 | }; | |
1490 | int ret; | |
1491 | ||
1492 | ret = v4l2_fwnode_endpoint_parse( | |
1493 | of_fwnode_handle(node), &vep); | |
1494 | if (ret) { | |
1495 | of_node_put(node); | |
1496 | return ret; | |
1497 | } | |
1498 | ||
1499 | priv->csi2_data_lanes = | |
1500 | vep.bus.mipi_csi2.num_data_lanes; | |
1501 | ||
1502 | continue; | |
1503 | } | |
1504 | ||
1505 | /* Skip if the corresponding GMSL link is unavailable. */ | |
1506 | if (!(i2c_mux_mask & BIT(ep.port))) | |
1507 | continue; | |
1508 | ||
1509 | if (priv->sources[ep.port].fwnode) { | |
1510 | dev_err(dev, | |
1511 | "Multiple port endpoints are not supported: %d", | |
1512 | ep.port); | |
1513 | ||
1514 | continue; | |
1515 | } | |
1516 | ||
1517 | source = &priv->sources[ep.port]; | |
1518 | source->fwnode = fwnode_graph_get_remote_endpoint( | |
1519 | of_fwnode_handle(node)); | |
1520 | if (!source->fwnode) { | |
1521 | dev_err(dev, | |
1522 | "Endpoint %pOF has no remote endpoint connection\n", | |
1523 | ep.local_node); | |
1524 | ||
1525 | continue; | |
1526 | } | |
1527 | ||
1528 | priv->source_mask |= BIT(ep.port); | |
1529 | priv->nsources++; | |
1530 | } | |
66d8c9d2 | 1531 | |
3697f108 LP |
1532 | of_property_read_u32(dev->of_node, "maxim,bus-width", &priv->bus_width); |
1533 | switch (priv->bus_width) { | |
1534 | case 0: | |
1535 | /* | |
1536 | * The property isn't specified in the device tree, the driver | |
1537 | * will keep the default value selected by the BWS pin. | |
1538 | */ | |
1539 | case 24: | |
1540 | case 27: | |
1541 | case 32: | |
1542 | break; | |
1543 | default: | |
1544 | dev_err(dev, "Invalid %s value %u\n", "maxim,bus-width", | |
1545 | priv->bus_width); | |
1546 | return -EINVAL; | |
1547 | } | |
1548 | ||
e332061b LP |
1549 | of_property_read_u32(dev->of_node, "maxim,i2c-remote-bus-hz", |
1550 | &i2c_clk_freq); | |
1551 | for (i = 0; i < ARRAY_SIZE(max9286_i2c_speeds); ++i) { | |
1552 | const struct max9286_i2c_speed *speed = &max9286_i2c_speeds[i]; | |
1553 | ||
1554 | if (speed->rate == i2c_clk_freq) { | |
1555 | priv->i2c_mstbt = speed->mstbt; | |
1556 | break; | |
1557 | } | |
1558 | } | |
1559 | ||
1560 | if (i == ARRAY_SIZE(max9286_i2c_speeds)) { | |
1561 | dev_err(dev, "Invalid %s value %u\n", "maxim,i2c-remote-bus-hz", | |
1562 | i2c_clk_freq); | |
1563 | return -EINVAL; | |
1564 | } | |
1565 | ||
85cb767c JM |
1566 | /* |
1567 | * Parse the initial value of the reverse channel amplitude from | |
1568 | * the firmware interface and convert it to millivolts. | |
1569 | * | |
1570 | * Default it to 170mV for backward compatibility with DTBs that do not | |
1571 | * provide the property. | |
1572 | */ | |
1573 | if (of_property_read_u32(dev->of_node, | |
1574 | "maxim,reverse-channel-microvolt", | |
1575 | &reverse_channel_microvolt)) | |
f78723eb | 1576 | priv->init_rev_chan_mv = 170; |
85cb767c | 1577 | else |
f78723eb | 1578 | priv->init_rev_chan_mv = reverse_channel_microvolt / 1000U; |
85cb767c | 1579 | |
66d8c9d2 KB |
1580 | priv->route_mask = priv->source_mask; |
1581 | ||
1582 | return 0; | |
1583 | } | |
1584 | ||
817660f4 TN |
1585 | static int max9286_get_poc_supplies(struct max9286_priv *priv) |
1586 | { | |
1587 | struct device *dev = &priv->client->dev; | |
1588 | struct max9286_source *source; | |
1589 | int ret; | |
1590 | ||
1591 | /* Start by getting the global regulator. */ | |
1592 | priv->regulator = devm_regulator_get_optional(dev, "poc"); | |
1593 | if (!IS_ERR(priv->regulator)) | |
1594 | return 0; | |
1595 | ||
1596 | if (PTR_ERR(priv->regulator) != -ENODEV) | |
1597 | return dev_err_probe(dev, PTR_ERR(priv->regulator), | |
1598 | "Unable to get PoC regulator\n"); | |
1599 | ||
1600 | /* If there's no global regulator, get per-port regulators. */ | |
1601 | dev_dbg(dev, | |
1602 | "No global PoC regulator, looking for per-port regulators\n"); | |
1603 | priv->regulator = NULL; | |
1604 | ||
1605 | for_each_source(priv, source) { | |
1606 | unsigned int index = to_index(priv, source); | |
1607 | char name[10]; | |
1608 | ||
1609 | snprintf(name, sizeof(name), "port%u-poc", index); | |
1610 | source->regulator = devm_regulator_get(dev, name); | |
1611 | if (IS_ERR(source->regulator)) { | |
1612 | ret = PTR_ERR(source->regulator); | |
1613 | dev_err_probe(dev, ret, | |
1614 | "Unable to get port %u PoC regulator\n", | |
1615 | index); | |
1616 | return ret; | |
1617 | } | |
1618 | } | |
1619 | ||
1620 | return 0; | |
1621 | } | |
1622 | ||
66d8c9d2 KB |
1623 | static int max9286_probe(struct i2c_client *client) |
1624 | { | |
1625 | struct max9286_priv *priv; | |
1626 | int ret; | |
1627 | ||
1628 | priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); | |
1629 | if (!priv) | |
1630 | return -ENOMEM; | |
1631 | ||
1632 | mutex_init(&priv->mutex); | |
1633 | ||
1634 | priv->client = client; | |
66d8c9d2 | 1635 | |
817660f4 TN |
1636 | /* GPIO values default to high */ |
1637 | priv->gpio_state = BIT(0) | BIT(1); | |
1638 | ||
e332061b LP |
1639 | ret = max9286_parse_dt(priv); |
1640 | if (ret) | |
1641 | goto err_cleanup_dt; | |
1642 | ||
66d8c9d2 KB |
1643 | priv->gpiod_pwdn = devm_gpiod_get_optional(&client->dev, "enable", |
1644 | GPIOD_OUT_HIGH); | |
e332061b LP |
1645 | if (IS_ERR(priv->gpiod_pwdn)) { |
1646 | ret = PTR_ERR(priv->gpiod_pwdn); | |
1647 | goto err_cleanup_dt; | |
1648 | } | |
66d8c9d2 KB |
1649 | |
1650 | gpiod_set_consumer_name(priv->gpiod_pwdn, "max9286-pwdn"); | |
1651 | gpiod_set_value_cansleep(priv->gpiod_pwdn, 1); | |
1652 | ||
1653 | /* Wait at least 4ms before the I2C lines latch to the address */ | |
1654 | if (priv->gpiod_pwdn) | |
1655 | usleep_range(4000, 5000); | |
1656 | ||
1657 | /* | |
1658 | * The MAX9286 starts by default with all ports enabled, we disable all | |
1659 | * ports early to ensure that all channels are disabled if we error out | |
1660 | * and keep the bus consistent. | |
1661 | */ | |
1662 | max9286_i2c_mux_close(priv); | |
1663 | ||
1664 | /* | |
1665 | * The MAX9286 initialises with auto-acknowledge enabled by default. | |
1666 | * This can be invasive to other transactions on the same bus, so | |
1667 | * disable it early. It will be enabled only as and when needed. | |
1668 | */ | |
1669 | max9286_configure_i2c(priv, false); | |
1670 | ||
c9352df7 | 1671 | ret = max9286_parse_gpios(priv); |
66d8c9d2 KB |
1672 | if (ret) |
1673 | goto err_powerdown; | |
1674 | ||
817660f4 TN |
1675 | if (!priv->use_gpio_poc) { |
1676 | ret = max9286_get_poc_supplies(priv); | |
1677 | if (ret) | |
1678 | goto err_cleanup_dt; | |
1679 | } | |
66d8c9d2 | 1680 | |
365ab7eb | 1681 | ret = max9286_init(priv); |
66d8c9d2 KB |
1682 | if (ret < 0) |
1683 | goto err_cleanup_dt; | |
1684 | ||
1685 | return 0; | |
1686 | ||
66d8c9d2 KB |
1687 | err_powerdown: |
1688 | gpiod_set_value_cansleep(priv->gpiod_pwdn, 0); | |
e332061b LP |
1689 | err_cleanup_dt: |
1690 | max9286_cleanup_dt(priv); | |
66d8c9d2 KB |
1691 | |
1692 | return ret; | |
1693 | } | |
1694 | ||
ed5c2f5f | 1695 | static void max9286_remove(struct i2c_client *client) |
66d8c9d2 | 1696 | { |
365ab7eb | 1697 | struct max9286_priv *priv = sd_to_max9286(i2c_get_clientdata(client)); |
66d8c9d2 KB |
1698 | |
1699 | i2c_mux_del_adapters(priv->mux); | |
1700 | ||
1701 | max9286_v4l2_unregister(priv); | |
1702 | ||
c9352df7 | 1703 | max9286_poc_enable(priv, false); |
66d8c9d2 KB |
1704 | |
1705 | gpiod_set_value_cansleep(priv->gpiod_pwdn, 0); | |
1706 | ||
1707 | max9286_cleanup_dt(priv); | |
66d8c9d2 KB |
1708 | } |
1709 | ||
1710 | static const struct of_device_id max9286_dt_ids[] = { | |
1711 | { .compatible = "maxim,max9286" }, | |
1712 | {}, | |
1713 | }; | |
1714 | MODULE_DEVICE_TABLE(of, max9286_dt_ids); | |
1715 | ||
1716 | static struct i2c_driver max9286_i2c_driver = { | |
1717 | .driver = { | |
1718 | .name = "max9286", | |
db657dfb | 1719 | .of_match_table = max9286_dt_ids, |
66d8c9d2 | 1720 | }, |
aaeb31c0 | 1721 | .probe = max9286_probe, |
66d8c9d2 KB |
1722 | .remove = max9286_remove, |
1723 | }; | |
1724 | ||
1725 | module_i2c_driver(max9286_i2c_driver); | |
1726 | ||
1727 | MODULE_DESCRIPTION("Maxim MAX9286 GMSL Deserializer Driver"); | |
1728 | MODULE_AUTHOR("Jacopo Mondi, Kieran Bingham, Laurent Pinchart, Niklas Söderlund, Vladimir Barinov"); | |
1729 | MODULE_LICENSE("GPL"); |