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Merge tag 'powerpc-5.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc...
[linux-2.6-block.git] / drivers / media / i2c / max9286.c
CommitLineData
66d8c9d2
KB		 1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Maxim MAX9286 GMSL Deserializer Driver
4 *
5 * Copyright (C) 2017-2019 Jacopo Mondi
6 * Copyright (C) 2017-2019 Kieran Bingham
7 * Copyright (C) 2017-2019 Laurent Pinchart
8 * Copyright (C) 2017-2019 Niklas Söderlund
9 * Copyright (C) 2016 Renesas Electronics Corporation
10 * Copyright (C) 2015 Cogent Embedded, Inc.
11 */
12
13#include <linux/delay.h>
14#include <linux/device.h>
15#include <linux/fwnode.h>
16#include <linux/gpio/consumer.h>
17#include <linux/gpio/driver.h>
18#include <linux/i2c.h>
19#include <linux/i2c-mux.h>
20#include <linux/module.h>
21#include <linux/mutex.h>
22#include <linux/of_graph.h>
23#include <linux/regulator/consumer.h>
24#include <linux/slab.h>
25
26#include <media/v4l2-async.h>
27#include <media/v4l2-ctrls.h>
28#include <media/v4l2-device.h>
29#include <media/v4l2-fwnode.h>
30#include <media/v4l2-subdev.h>
31
32/* Register 0x00 */
33#define MAX9286_MSTLINKSEL_AUTO (7 << 5)
34#define MAX9286_MSTLINKSEL(n) ((n) << 5)
35#define MAX9286_EN_VS_GEN BIT(4)
36#define MAX9286_LINKEN(n) (1 << (n))
37/* Register 0x01 */
38#define MAX9286_FSYNCMODE_ECU (3 << 6)
39#define MAX9286_FSYNCMODE_EXT (2 << 6)
40#define MAX9286_FSYNCMODE_INT_OUT (1 << 6)
41#define MAX9286_FSYNCMODE_INT_HIZ (0 << 6)
42#define MAX9286_GPIEN BIT(5)
43#define MAX9286_ENLMO_RSTFSYNC BIT(2)
44#define MAX9286_FSYNCMETH_AUTO (2 << 0)
45#define MAX9286_FSYNCMETH_SEMI_AUTO (1 << 0)
46#define MAX9286_FSYNCMETH_MANUAL (0 << 0)
47#define MAX9286_REG_FSYNC_PERIOD_L 0x06
48#define MAX9286_REG_FSYNC_PERIOD_M 0x07
49#define MAX9286_REG_FSYNC_PERIOD_H 0x08
50/* Register 0x0a */
51#define MAX9286_FWDCCEN(n) (1 << ((n) + 4))
52#define MAX9286_REVCCEN(n) (1 << (n))
53/* Register 0x0c */
54#define MAX9286_HVEN BIT(7)
55#define MAX9286_EDC_6BIT_HAMMING (2 << 5)
56#define MAX9286_EDC_6BIT_CRC (1 << 5)
57#define MAX9286_EDC_1BIT_PARITY (0 << 5)
58#define MAX9286_DESEL BIT(4)
59#define MAX9286_INVVS BIT(3)
60#define MAX9286_INVHS BIT(2)
61#define MAX9286_HVSRC_D0 (2 << 0)
62#define MAX9286_HVSRC_D14 (1 << 0)
63#define MAX9286_HVSRC_D18 (0 << 0)
64/* Register 0x0f */
65#define MAX9286_0X0F_RESERVED BIT(3)
66/* Register 0x12 */
67#define MAX9286_CSILANECNT(n) (((n) - 1) << 6)
68#define MAX9286_CSIDBL BIT(5)
69#define MAX9286_DBL BIT(4)
70#define MAX9286_DATATYPE_USER_8BIT (11 << 0)
71#define MAX9286_DATATYPE_USER_YUV_12BIT (10 << 0)
72#define MAX9286_DATATYPE_USER_24BIT (9 << 0)
73#define MAX9286_DATATYPE_RAW14 (8 << 0)
74#define MAX9286_DATATYPE_RAW11 (7 << 0)
75#define MAX9286_DATATYPE_RAW10 (6 << 0)
76#define MAX9286_DATATYPE_RAW8 (5 << 0)
77#define MAX9286_DATATYPE_YUV422_10BIT (4 << 0)
78#define MAX9286_DATATYPE_YUV422_8BIT (3 << 0)
79#define MAX9286_DATATYPE_RGB555 (2 << 0)
80#define MAX9286_DATATYPE_RGB565 (1 << 0)
81#define MAX9286_DATATYPE_RGB888 (0 << 0)
82/* Register 0x15 */
83#define MAX9286_VC(n) ((n) << 5)
84#define MAX9286_VCTYPE BIT(4)
85#define MAX9286_CSIOUTEN BIT(3)
86#define MAX9286_0X15_RESV (3 << 0)
87/* Register 0x1b */
88#define MAX9286_SWITCHIN(n) (1 << ((n) + 4))
89#define MAX9286_ENEQ(n) (1 << (n))
90/* Register 0x27 */
91#define MAX9286_LOCKED BIT(7)
92/* Register 0x31 */
93#define MAX9286_FSYNC_LOCKED BIT(6)
94/* Register 0x34 */
95#define MAX9286_I2CLOCACK BIT(7)
96#define MAX9286_I2CSLVSH_1046NS_469NS (3 << 5)
97#define MAX9286_I2CSLVSH_938NS_352NS (2 << 5)
98#define MAX9286_I2CSLVSH_469NS_234NS (1 << 5)
99#define MAX9286_I2CSLVSH_352NS_117NS (0 << 5)
100#define MAX9286_I2CMSTBT_837KBPS (7 << 2)
101#define MAX9286_I2CMSTBT_533KBPS (6 << 2)
102#define MAX9286_I2CMSTBT_339KBPS (5 << 2)
103#define MAX9286_I2CMSTBT_173KBPS (4 << 2)
104#define MAX9286_I2CMSTBT_105KBPS (3 << 2)
105#define MAX9286_I2CMSTBT_84KBPS (2 << 2)
106#define MAX9286_I2CMSTBT_28KBPS (1 << 2)
107#define MAX9286_I2CMSTBT_8KBPS (0 << 2)
108#define MAX9286_I2CSLVTO_NONE (3 << 0)
109#define MAX9286_I2CSLVTO_1024US (2 << 0)
110#define MAX9286_I2CSLVTO_256US (1 << 0)
111#define MAX9286_I2CSLVTO_64US (0 << 0)
112/* Register 0x3b */
113#define MAX9286_REV_TRF(n) ((n) << 4)
114#define MAX9286_REV_AMP(n) ((((n) - 30) / 10) << 1) /* in mV */
115#define MAX9286_REV_AMP_X BIT(0)
116/* Register 0x3f */
117#define MAX9286_EN_REV_CFG BIT(6)
118#define MAX9286_REV_FLEN(n) ((n) - 20)
119/* Register 0x49 */
120#define MAX9286_VIDEO_DETECT_MASK 0x0f
121/* Register 0x69 */
122#define MAX9286_LFLTBMONMASKED BIT(7)
123#define MAX9286_LOCKMONMASKED BIT(6)
124#define MAX9286_AUTOCOMBACKEN BIT(5)
125#define MAX9286_AUTOMASKEN BIT(4)
126#define MAX9286_MASKLINK(n) ((n) << 0)
127
128/*
129 * The sink and source pads are created to match the OF graph port numbers so
130 * that their indexes can be used interchangeably.
131 */
132#define MAX9286_NUM_GMSL 4
133#define MAX9286_N_SINKS 4
134#define MAX9286_N_PADS 5
135#define MAX9286_SRC_PAD 4
136
137struct max9286_source {
66d8c9d2
KB		 138 struct v4l2_subdev *sd;
139 struct fwnode_handle *fwnode;
140};
141
86d37bf3
LP		 142struct max9286_asd {
143 struct v4l2_async_subdev base;
144 struct max9286_source *source;
145};
146
147static inline struct max9286_asd *to_max9286_asd(struct v4l2_async_subdev *asd)
148{
149 return container_of(asd, struct max9286_asd, base);
150}
66d8c9d2
KB		 151
152struct max9286_priv {
153 struct i2c_client *client;
154 struct gpio_desc *gpiod_pwdn;
155 struct v4l2_subdev sd;
156 struct media_pad pads[MAX9286_N_PADS];
157 struct regulator *regulator;
158
159 struct gpio_chip gpio;
160 u8 gpio_state;
161
162 struct i2c_mux_core *mux;
163 unsigned int mux_channel;
164 bool mux_open;
165
166 struct v4l2_ctrl_handler ctrls;
167 struct v4l2_ctrl *pixelrate;
168
169 struct v4l2_mbus_framefmt fmt[MAX9286_N_SINKS];
170
171 /* Protects controls and fmt structures */
172 struct mutex mutex;
173
174 unsigned int nsources;
175 unsigned int source_mask;
176 unsigned int route_mask;
177 unsigned int bound_sources;
178 unsigned int csi2_data_lanes;
179 struct max9286_source sources[MAX9286_NUM_GMSL];
180 struct v4l2_async_notifier notifier;
181};
182
183static struct max9286_source *next_source(struct max9286_priv *priv,
184 struct max9286_source *source)
185{
186 if (!source)
187 source = &priv->sources[0];
188 else
189 source++;
190
191 for (; source < &priv->sources[MAX9286_NUM_GMSL]; source++) {
192 if (source->fwnode)
193 return source;
194 }
195
196 return NULL;
197}
198
199#define for_each_source(priv, source) \
200 for ((source) = NULL; ((source) = next_source((priv), (source))); )
201
202#define to_index(priv, source) ((source) - &(priv)->sources[0])
203
204static inline struct max9286_priv *sd_to_max9286(struct v4l2_subdev *sd)
205{
206 return container_of(sd, struct max9286_priv, sd);
207}
208
209/* -----------------------------------------------------------------------------
210 * I2C IO
211 */
212
213static int max9286_read(struct max9286_priv *priv, u8 reg)
214{
215 int ret;
216
217 ret = i2c_smbus_read_byte_data(priv->client, reg);
218 if (ret < 0)
219 dev_err(&priv->client->dev,
220 "%s: register 0x%02x read failed (%d)\n",
221 __func__, reg, ret);
222
223 return ret;
224}
225
226static int max9286_write(struct max9286_priv *priv, u8 reg, u8 val)
227{
228 int ret;
229
230 ret = i2c_smbus_write_byte_data(priv->client, reg, val);
231 if (ret < 0)
232 dev_err(&priv->client->dev,
233 "%s: register 0x%02x write failed (%d)\n",
234 __func__, reg, ret);
235
236 return ret;
237}
238
239/* -----------------------------------------------------------------------------
240 * I2C Multiplexer
241 */
242
243static void max9286_i2c_mux_configure(struct max9286_priv *priv, u8 conf)
244{
245 max9286_write(priv, 0x0a, conf);
246
247 /*
248 * We must sleep after any change to the forward or reverse channel
249 * configuration.
250 */
251 usleep_range(3000, 5000);
252}
253
254static void max9286_i2c_mux_open(struct max9286_priv *priv)
255{
256 /* Open all channels on the MAX9286 */
257 max9286_i2c_mux_configure(priv, 0xff);
258
259 priv->mux_open = true;
260}
261
262static void max9286_i2c_mux_close(struct max9286_priv *priv)
263{
264 /*
265 * Ensure that both the forward and reverse channel are disabled on the
266 * mux, and that the channel ID is invalidated to ensure we reconfigure
267 * on the next max9286_i2c_mux_select() call.
268 */
269 max9286_i2c_mux_configure(priv, 0x00);
270
271 priv->mux_open = false;
272 priv->mux_channel = -1;
273}
274
275static int max9286_i2c_mux_select(struct i2c_mux_core *muxc, u32 chan)
276{
277 struct max9286_priv *priv = i2c_mux_priv(muxc);
278
279 /* Channel select is disabled when configured in the opened state. */
280 if (priv->mux_open)
281 return 0;
282
283 if (priv->mux_channel == chan)
284 return 0;
285
286 priv->mux_channel = chan;
287
288 max9286_i2c_mux_configure(priv,
289 MAX9286_FWDCCEN(chan) |
290 MAX9286_REVCCEN(chan));
291
292 return 0;
293}
294
295static int max9286_i2c_mux_init(struct max9286_priv *priv)
296{
297 struct max9286_source *source;
298 int ret;
299
300 if (!i2c_check_functionality(priv->client->adapter,
301 I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
302 return -ENODEV;
303
304 priv->mux = i2c_mux_alloc(priv->client->adapter, &priv->client->dev,
305 priv->nsources, 0, I2C_MUX_LOCKED,
306 max9286_i2c_mux_select, NULL);
307 if (!priv->mux)
308 return -ENOMEM;
309
310 priv->mux->priv = priv;
311
312 for_each_source(priv, source) {
313 unsigned int index = to_index(priv, source);
314
315 ret = i2c_mux_add_adapter(priv->mux, 0, index, 0);
316 if (ret < 0)
317 goto error;
318 }
319
320 return 0;
321
322error:
323 i2c_mux_del_adapters(priv->mux);
324 return ret;
325}
326
327static void max9286_configure_i2c(struct max9286_priv *priv, bool localack)
328{
329 u8 config = MAX9286_I2CSLVSH_469NS_234NS | MAX9286_I2CSLVTO_1024US |
330 MAX9286_I2CMSTBT_105KBPS;
331
332 if (localack)
333 config |= MAX9286_I2CLOCACK;
334
335 max9286_write(priv, 0x34, config);
336 usleep_range(3000, 5000);
337}
338
339/*
340 * max9286_check_video_links() - Make sure video links are detected and locked
341 *
342 * Performs safety checks on video link status. Make sure they are detected
343 * and all enabled links are locked.
344 *
345 * Returns 0 for success, -EIO for errors.
346 */
347static int max9286_check_video_links(struct max9286_priv *priv)
348{
349 unsigned int i;
350 int ret;
351
352 /*
353 * Make sure valid video links are detected.
354 * The delay is not characterized in de-serializer manual, wait up
355 * to 5 ms.
356 */
357 for (i = 0; i < 10; i++) {
358 ret = max9286_read(priv, 0x49);
359 if (ret < 0)
360 return -EIO;
361
362 if ((ret & MAX9286_VIDEO_DETECT_MASK) == priv->source_mask)
363 break;
364
365 usleep_range(350, 500);
366 }
367
368 if (i == 10) {
369 dev_err(&priv->client->dev,
370 "Unable to detect video links: 0x%02x\n", ret);
371 return -EIO;
372 }
373
374 /* Make sure all enabled links are locked (4ms max). */
375 for (i = 0; i < 10; i++) {
376 ret = max9286_read(priv, 0x27);
377 if (ret < 0)
378 return -EIO;
379
380 if (ret & MAX9286_LOCKED)
381 break;
382
383 usleep_range(350, 450);
384 }
385
386 if (i == 10) {
387 dev_err(&priv->client->dev, "Not all enabled links locked\n");
388 return -EIO;
389 }
390
391 return 0;
392}
393
394/*
395 * max9286_check_config_link() - Detect and wait for configuration links
396 *
397 * Determine if the configuration channel is up and settled for a link.
398 *
399 * Returns 0 for success, -EIO for errors.
400 */
401static int max9286_check_config_link(struct max9286_priv *priv,
402 unsigned int source_mask)
403{
404 unsigned int conflink_mask = (source_mask & 0x0f) << 4;
405 unsigned int i;
406 int ret;
407
408 /*
409 * Make sure requested configuration links are detected.
410 * The delay is not characterized in the chip manual: wait up
411 * to 5 milliseconds.
412 */
413 for (i = 0; i < 10; i++) {
e5b95c8f 414 ret = max9286_read(priv, 0x49);
66d8c9d2
KB		 415 if (ret < 0)
416 return -EIO;
417
e5b95c8f 418 ret &= 0xf0;
66d8c9d2
KB		 419 if (ret == conflink_mask)
420 break;
421
422 usleep_range(350, 500);
423 }
424
425 if (ret != conflink_mask) {
426 dev_err(&priv->client->dev,
427 "Unable to detect configuration links: 0x%02x expected 0x%02x\n",
428 ret, conflink_mask);
429 return -EIO;
430 }
431
432 dev_info(&priv->client->dev,
433 "Successfully detected configuration links after %u loops: 0x%02x\n",
434 i, conflink_mask);
435
436 return 0;
437}
438
439/* -----------------------------------------------------------------------------
440 * V4L2 Subdev
441 */
442
443static int max9286_set_pixelrate(struct max9286_priv *priv)
444{
445 struct max9286_source *source = NULL;
446 u64 pixelrate = 0;
447
448 for_each_source(priv, source) {
449 struct v4l2_ctrl *ctrl;
450 u64 source_rate = 0;
451
452 /* Pixel rate is mandatory to be reported by sources. */
453 ctrl = v4l2_ctrl_find(source->sd->ctrl_handler,
454 V4L2_CID_PIXEL_RATE);
455 if (!ctrl) {
456 pixelrate = 0;
457 break;
458 }
459
460 /* All source must report the same pixel rate. */
461 source_rate = v4l2_ctrl_g_ctrl_int64(ctrl);
462 if (!pixelrate) {
463 pixelrate = source_rate;
464 } else if (pixelrate != source_rate) {
465 dev_err(&priv->client->dev,
466 "Unable to calculate pixel rate\n");
467 return -EINVAL;
468 }
469 }
470
471 if (!pixelrate) {
472 dev_err(&priv->client->dev,
473 "No pixel rate control available in sources\n");
474 return -EINVAL;
475 }
476
477 /*
478 * The CSI-2 transmitter pixel rate is the single source rate multiplied
479 * by the number of available sources.
480 */
481 return v4l2_ctrl_s_ctrl_int64(priv->pixelrate,
482 pixelrate * priv->nsources);
483}
484
485static int max9286_notify_bound(struct v4l2_async_notifier *notifier,
486 struct v4l2_subdev *subdev,
487 struct v4l2_async_subdev *asd)
488{
489 struct max9286_priv *priv = sd_to_max9286(notifier->sd);
86d37bf3 490 struct max9286_source *source = to_max9286_asd(asd)->source;
66d8c9d2
KB		 491 unsigned int index = to_index(priv, source);
492 unsigned int src_pad;
493 int ret;
494
495 ret = media_entity_get_fwnode_pad(&subdev->entity,
496 source->fwnode,
497 MEDIA_PAD_FL_SOURCE);
498 if (ret < 0) {
499 dev_err(&priv->client->dev,
500 "Failed to find pad for %s\n", subdev->name);
501 return ret;
502 }
503
504 priv->bound_sources |= BIT(index);
505 source->sd = subdev;
506 src_pad = ret;
507
508 ret = media_create_pad_link(&source->sd->entity, src_pad,
509 &priv->sd.entity, index,
510 MEDIA_LNK_FL_ENABLED |
511 MEDIA_LNK_FL_IMMUTABLE);
512 if (ret) {
513 dev_err(&priv->client->dev,
514 "Unable to link %s:%u -> %s:%u\n",
515 source->sd->name, src_pad, priv->sd.name, index);
516 return ret;
517 }
518
519 dev_dbg(&priv->client->dev, "Bound %s pad: %u on index %u\n",
520 subdev->name, src_pad, index);
521
522 /*
523 * We can only register v4l2_async_notifiers, which do not provide a
524 * means to register a complete callback. bound_sources allows us to
525 * identify when all remote serializers have completed their probe.
526 */
527 if (priv->bound_sources != priv->source_mask)
528 return 0;
529
530 /*
531 * All enabled sources have probed and enabled their reverse control
532 * channels:
533 *
534 * - Verify all configuration links are properly detected
535 * - Disable auto-ack as communication on the control channel are now
536 * stable.
537 */
538 max9286_check_config_link(priv, priv->source_mask);
539
540 /*
541 * Re-configure I2C with local acknowledge disabled after cameras have
542 * probed.
543 */
544 max9286_configure_i2c(priv, false);
545
546 return max9286_set_pixelrate(priv);
547}
548
549static void max9286_notify_unbind(struct v4l2_async_notifier *notifier,
550 struct v4l2_subdev *subdev,
551 struct v4l2_async_subdev *asd)
552{
553 struct max9286_priv *priv = sd_to_max9286(notifier->sd);
86d37bf3 554 struct max9286_source *source = to_max9286_asd(asd)->source;
66d8c9d2
KB		 555 unsigned int index = to_index(priv, source);
556
557 source->sd = NULL;
558 priv->bound_sources &= ~BIT(index);
559}
560
561static const struct v4l2_async_notifier_operations max9286_notify_ops = {
562 .bound = max9286_notify_bound,
563 .unbind = max9286_notify_unbind,
564};
565
566static int max9286_v4l2_notifier_register(struct max9286_priv *priv)
567{
568 struct device *dev = &priv->client->dev;
569 struct max9286_source *source = NULL;
570 int ret;
571
572 if (!priv->nsources)
573 return 0;
574
575 v4l2_async_notifier_init(&priv->notifier);
576
577 for_each_source(priv, source) {
578 unsigned int i = to_index(priv, source);
86d37bf3
LP		 579 struct v4l2_async_subdev *asd;
580
581 asd = v4l2_async_notifier_add_fwnode_subdev(&priv->notifier,
582 source->fwnode,
583 sizeof(*asd));
584 if (IS_ERR(asd)) {
585 dev_err(dev, "Failed to add subdev for source %u: %ld",
586 i, PTR_ERR(asd));
66d8c9d2 587 v4l2_async_notifier_cleanup(&priv->notifier);
86d37bf3 588 return PTR_ERR(asd);
66d8c9d2
KB		 589 }
590
86d37bf3 591 to_max9286_asd(asd)->source = source;
66d8c9d2
KB		 592 }
593
594 priv->notifier.ops = &max9286_notify_ops;
595
596 ret = v4l2_async_subdev_notifier_register(&priv->sd, &priv->notifier);
597 if (ret) {
598 dev_err(dev, "Failed to register subdev_notifier");
599 v4l2_async_notifier_cleanup(&priv->notifier);
600 return ret;
601 }
602
603 return 0;
604}
605
606static void max9286_v4l2_notifier_unregister(struct max9286_priv *priv)
607{
608 if (!priv->nsources)
609 return;
610
611 v4l2_async_notifier_unregister(&priv->notifier);
612 v4l2_async_notifier_cleanup(&priv->notifier);
613}
614
615static int max9286_s_stream(struct v4l2_subdev *sd, int enable)
616{
617 struct max9286_priv *priv = sd_to_max9286(sd);
618 struct max9286_source *source;
619 unsigned int i;
620 bool sync = false;
621 int ret;
622
623 if (enable) {
624 /*
625 * The frame sync between cameras is transmitted across the
626 * reverse channel as GPIO. We must open all channels while
627 * streaming to allow this synchronisation signal to be shared.
628 */
629 max9286_i2c_mux_open(priv);
630
631 /* Start all cameras. */
632 for_each_source(priv, source) {
633 ret = v4l2_subdev_call(source->sd, video, s_stream, 1);
634 if (ret)
635 return ret;
636 }
637
638 ret = max9286_check_video_links(priv);
639 if (ret)
640 return ret;
641
642 /*
643 * Wait until frame synchronization is locked.
644 *
645 * Manual says frame sync locking should take ~6 VTS.
646 * From practical experience at least 8 are required. Give
647 * 12 complete frames time (~400ms at 30 fps) to achieve frame
648 * locking before returning error.
649 */
650 for (i = 0; i < 40; i++) {
651 if (max9286_read(priv, 0x31) & MAX9286_FSYNC_LOCKED) {
652 sync = true;
653 break;
654 }
655 usleep_range(9000, 11000);
656 }
657
658 if (!sync) {
659 dev_err(&priv->client->dev,
660 "Failed to get frame synchronization\n");
661 return -EXDEV; /* Invalid cross-device link */
662 }
663
664 /*
665 * Enable CSI output, VC set according to link number.
666 * Bit 7 must be set (chip manual says it's 0 and reserved).
667 */
668 max9286_write(priv, 0x15, 0x80 | MAX9286_VCTYPE |
669 MAX9286_CSIOUTEN | MAX9286_0X15_RESV);
670 } else {
671 max9286_write(priv, 0x15, MAX9286_VCTYPE | MAX9286_0X15_RESV);
672
673 /* Stop all cameras. */
674 for_each_source(priv, source)
675 v4l2_subdev_call(source->sd, video, s_stream, 0);
676
677 max9286_i2c_mux_close(priv);
678 }
679
680 return 0;
681}
682
683static int max9286_enum_mbus_code(struct v4l2_subdev *sd,
684 struct v4l2_subdev_pad_config *cfg,
685 struct v4l2_subdev_mbus_code_enum *code)
686{
687 if (code->pad || code->index > 0)
688 return -EINVAL;
689
690 code->code = MEDIA_BUS_FMT_UYVY8_1X16;
691
692 return 0;
693}
694
695static struct v4l2_mbus_framefmt *
696max9286_get_pad_format(struct max9286_priv *priv,
697 struct v4l2_subdev_pad_config *cfg,
698 unsigned int pad, u32 which)
699{
700 switch (which) {
701 case V4L2_SUBDEV_FORMAT_TRY:
702 return v4l2_subdev_get_try_format(&priv->sd, cfg, pad);
703 case V4L2_SUBDEV_FORMAT_ACTIVE:
704 return &priv->fmt[pad];
705 default:
706 return NULL;
707 }
708}
709
710static int max9286_set_fmt(struct v4l2_subdev *sd,
711 struct v4l2_subdev_pad_config *cfg,
712 struct v4l2_subdev_format *format)
713{
714 struct max9286_priv *priv = sd_to_max9286(sd);
715 struct v4l2_mbus_framefmt *cfg_fmt;
716
717 if (format->pad == MAX9286_SRC_PAD)
718 return -EINVAL;
719
720 /* Refuse non YUV422 formats as we hardcode DT to 8 bit YUV422 */
721 switch (format->format.code) {
722 case MEDIA_BUS_FMT_UYVY8_1X16:
723 case MEDIA_BUS_FMT_VYUY8_1X16:
724 case MEDIA_BUS_FMT_YUYV8_1X16:
725 case MEDIA_BUS_FMT_YVYU8_1X16:
726 break;
727 default:
728 format->format.code = MEDIA_BUS_FMT_UYVY8_1X16;
729 break;
730 }
731
732 cfg_fmt = max9286_get_pad_format(priv, cfg, format->pad, format->which);
733 if (!cfg_fmt)
734 return -EINVAL;
735
736 mutex_lock(&priv->mutex);
737 *cfg_fmt = format->format;
738 mutex_unlock(&priv->mutex);
739
740 return 0;
741}
742
743static int max9286_get_fmt(struct v4l2_subdev *sd,
744 struct v4l2_subdev_pad_config *cfg,
745 struct v4l2_subdev_format *format)
746{
747 struct max9286_priv *priv = sd_to_max9286(sd);
748 struct v4l2_mbus_framefmt *cfg_fmt;
749 unsigned int pad = format->pad;
750
751 /*
752 * Multiplexed Stream Support: Support link validation by returning the
753 * format of the first bound link. All links must have the same format,
754 * as we do not support mixing and matching of cameras connected to the
755 * max9286.
756 */
757 if (pad == MAX9286_SRC_PAD)
758 pad = __ffs(priv->bound_sources);
759
760 cfg_fmt = max9286_get_pad_format(priv, cfg, pad, format->which);
761 if (!cfg_fmt)
762 return -EINVAL;
763
764 mutex_lock(&priv->mutex);
765 format->format = *cfg_fmt;
766 mutex_unlock(&priv->mutex);
767
768 return 0;
769}
770
771static const struct v4l2_subdev_video_ops max9286_video_ops = {
772 .s_stream = max9286_s_stream,
773};
774
775static const struct v4l2_subdev_pad_ops max9286_pad_ops = {
776 .enum_mbus_code = max9286_enum_mbus_code,
777 .get_fmt = max9286_get_fmt,
778 .set_fmt = max9286_set_fmt,
779};
780
781static const struct v4l2_subdev_ops max9286_subdev_ops = {
782 .video = &max9286_video_ops,
783 .pad = &max9286_pad_ops,
784};
785
786static void max9286_init_format(struct v4l2_mbus_framefmt *fmt)
787{
788 fmt->width = 1280;
789 fmt->height = 800;
790 fmt->code = MEDIA_BUS_FMT_UYVY8_1X16;
791 fmt->colorspace = V4L2_COLORSPACE_SRGB;
792 fmt->field = V4L2_FIELD_NONE;
793 fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
794 fmt->quantization = V4L2_QUANTIZATION_DEFAULT;
795 fmt->xfer_func = V4L2_XFER_FUNC_DEFAULT;
796}
797
798static int max9286_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
799{
800 struct v4l2_mbus_framefmt *format;
801 unsigned int i;
802
803 for (i = 0; i < MAX9286_N_SINKS; i++) {
804 format = v4l2_subdev_get_try_format(subdev, fh->pad, i);
805 max9286_init_format(format);
806 }
807
808 return 0;
809}
810
811static const struct v4l2_subdev_internal_ops max9286_subdev_internal_ops = {
812 .open = max9286_open,
813};
814
815static int max9286_s_ctrl(struct v4l2_ctrl *ctrl)
816{
817 switch (ctrl->id) {
818 case V4L2_CID_PIXEL_RATE:
819 return 0;
820 default:
821 return -EINVAL;
822 }
823}
824
825static const struct v4l2_ctrl_ops max9286_ctrl_ops = {
826 .s_ctrl = max9286_s_ctrl,
827};
828
829static int max9286_v4l2_register(struct max9286_priv *priv)
830{
831 struct device *dev = &priv->client->dev;
832 struct fwnode_handle *ep;
833 int ret;
834 int i;
835
836 /* Register v4l2 async notifiers for connected Camera subdevices */
837 ret = max9286_v4l2_notifier_register(priv);
838 if (ret) {
839 dev_err(dev, "Unable to register V4L2 async notifiers\n");
840 return ret;
841 }
842
843 /* Configure V4L2 for the MAX9286 itself */
844
845 for (i = 0; i < MAX9286_N_SINKS; i++)
846 max9286_init_format(&priv->fmt[i]);
847
848 v4l2_i2c_subdev_init(&priv->sd, priv->client, &max9286_subdev_ops);
849 priv->sd.internal_ops = &max9286_subdev_internal_ops;
850 priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
851
852 v4l2_ctrl_handler_init(&priv->ctrls, 1);
853 priv->pixelrate = v4l2_ctrl_new_std(&priv->ctrls,
854 &max9286_ctrl_ops,
855 V4L2_CID_PIXEL_RATE,
856 1, INT_MAX, 1, 50000000);
857
858 priv->sd.ctrl_handler = &priv->ctrls;
859 ret = priv->ctrls.error;
860 if (ret)
861 goto err_async;
862
863 priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
864
865 priv->pads[MAX9286_SRC_PAD].flags = MEDIA_PAD_FL_SOURCE;
866 for (i = 0; i < MAX9286_SRC_PAD; i++)
867 priv->pads[i].flags = MEDIA_PAD_FL_SINK;
868 ret = media_entity_pads_init(&priv->sd.entity, MAX9286_N_PADS,
869 priv->pads);
870 if (ret)
871 goto err_async;
872
873 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), MAX9286_SRC_PAD,
874 0, 0);
875 if (!ep) {
876 dev_err(dev, "Unable to retrieve endpoint on \"port@4\"\n");
877 ret = -ENOENT;
878 goto err_async;
879 }
880 priv->sd.fwnode = ep;
881
882 ret = v4l2_async_register_subdev(&priv->sd);
883 if (ret < 0) {
884 dev_err(dev, "Unable to register subdevice\n");
885 goto err_put_node;
886 }
887
888 return 0;
889
890err_put_node:
891 fwnode_handle_put(ep);
892err_async:
893 max9286_v4l2_notifier_unregister(priv);
894
895 return ret;
896}
897
898static void max9286_v4l2_unregister(struct max9286_priv *priv)
899{
900 fwnode_handle_put(priv->sd.fwnode);
901 v4l2_async_unregister_subdev(&priv->sd);
902 max9286_v4l2_notifier_unregister(priv);
903}
904
905/* -----------------------------------------------------------------------------
906 * Probe/Remove
907 */
908
909static int max9286_setup(struct max9286_priv *priv)
910{
911 /*
912 * Link ordering values for all enabled links combinations. Orders must
913 * be assigned sequentially from 0 to the number of enabled links
914 * without leaving any hole for disabled links. We thus assign orders to
915 * enabled links first, and use the remaining order values for disabled
916 * links are all links must have a different order value;
917 */
918 static const u8 link_order[] = {
919 (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xxxx */
920 (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xxx0 */
921 (3 << 6) | (2 << 4) | (0 << 2) | (1 << 0), /* xx0x */
922 (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xx10 */
923 (3 << 6) | (0 << 4) | (2 << 2) | (1 << 0), /* x0xx */
924 (3 << 6) | (1 << 4) | (2 << 2) | (0 << 0), /* x1x0 */
925 (3 << 6) | (1 << 4) | (0 << 2) | (2 << 0), /* x10x */
926 (3 << 6) | (1 << 4) | (1 << 2) | (0 << 0), /* x210 */
927 (0 << 6) | (3 << 4) | (2 << 2) | (1 << 0), /* 0xxx */
928 (1 << 6) | (3 << 4) | (2 << 2) | (0 << 0), /* 1xx0 */
929 (1 << 6) | (3 << 4) | (0 << 2) | (2 << 0), /* 1x0x */
930 (2 << 6) | (3 << 4) | (1 << 2) | (0 << 0), /* 2x10 */
931 (1 << 6) | (0 << 4) | (3 << 2) | (2 << 0), /* 10xx */
932 (2 << 6) | (1 << 4) | (3 << 2) | (0 << 0), /* 21x0 */
933 (2 << 6) | (1 << 4) | (0 << 2) | (3 << 0), /* 210x */
934 (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* 3210 */
935 };
936
937 /*
938 * Set the I2C bus speed.
939 *
940 * Enable I2C Local Acknowledge during the probe sequences of the camera
941 * only. This should be disabled after the mux is initialised.
942 */
943 max9286_configure_i2c(priv, true);
944
945 /*
946 * Reverse channel setup.
947 *
948 * - Enable custom reverse channel configuration (through register 0x3f)
949 * and set the first pulse length to 35 clock cycles.
950 * - Increase the reverse channel amplitude to 170mV to accommodate the
951 * high threshold enabled by the serializer driver.
952 */
953 max9286_write(priv, 0x3f, MAX9286_EN_REV_CFG | MAX9286_REV_FLEN(35));
954 max9286_write(priv, 0x3b, MAX9286_REV_TRF(1) | MAX9286_REV_AMP(70) |
955 MAX9286_REV_AMP_X);
956 usleep_range(2000, 2500);
957
958 /*
959 * Enable GMSL links, mask unused ones and autodetect link
960 * used as CSI clock source.
961 */
962 max9286_write(priv, 0x00, MAX9286_MSTLINKSEL_AUTO | priv->route_mask);
963 max9286_write(priv, 0x0b, link_order[priv->route_mask]);
964 max9286_write(priv, 0x69, (0xf & ~priv->route_mask));
965
966 /*
967 * Video format setup:
968 * Disable CSI output, VC is set according to Link number.
969 */
970 max9286_write(priv, 0x15, MAX9286_VCTYPE | MAX9286_0X15_RESV);
971
972 /* Enable CSI-2 Lane D0-D3 only, DBL mode, YUV422 8-bit. */
973 max9286_write(priv, 0x12, MAX9286_CSIDBL | MAX9286_DBL |
974 MAX9286_CSILANECNT(priv->csi2_data_lanes) |
975 MAX9286_DATATYPE_YUV422_8BIT);
976
977 /* Automatic: FRAMESYNC taken from the slowest Link. */
978 max9286_write(priv, 0x01, MAX9286_FSYNCMODE_INT_HIZ |
979 MAX9286_FSYNCMETH_AUTO);
980
981 /* Enable HS/VS encoding, use D14/15 for HS/VS, invert VS. */
982 max9286_write(priv, 0x0c, MAX9286_HVEN | MAX9286_INVVS |
983 MAX9286_HVSRC_D14);
984
985 /*
986 * The overlap window seems to provide additional validation by tracking
987 * the delay between vsync and frame sync, generating an error if the
988 * delay is bigger than the programmed window, though it's not yet clear
989 * what value should be set.
990 *
991 * As it's an optional value and can be disabled, we do so by setting
992 * a 0 overlap value.
993 */
994 max9286_write(priv, 0x63, 0);
995 max9286_write(priv, 0x64, 0);
996
997 /*
998 * Wait for 2ms to allow the link to resynchronize after the
999 * configuration change.
1000 */
1001 usleep_range(2000, 5000);
1002
1003 return 0;
1004}
1005
1006static void max9286_gpio_set(struct gpio_chip *chip,
1007 unsigned int offset, int value)
1008{
1009 struct max9286_priv *priv = gpiochip_get_data(chip);
1010
1011 if (value)
1012 priv->gpio_state |= BIT(offset);
1013 else
1014 priv->gpio_state &= ~BIT(offset);
1015
1016 max9286_write(priv, 0x0f, MAX9286_0X0F_RESERVED | priv->gpio_state);
1017}
1018
1019static int max9286_gpio_get(struct gpio_chip *chip, unsigned int offset)
1020{
1021 struct max9286_priv *priv = gpiochip_get_data(chip);
1022
1023 return priv->gpio_state & BIT(offset);
1024}
1025
1026static int max9286_register_gpio(struct max9286_priv *priv)
1027{
1028 struct device *dev = &priv->client->dev;
1029 struct gpio_chip *gpio = &priv->gpio;
1030 int ret;
1031
1032 /* Configure the GPIO */
1033 gpio->label = dev_name(dev);
1034 gpio->parent = dev;
1035 gpio->owner = THIS_MODULE;
1036 gpio->of_node = dev->of_node;
1037 gpio->ngpio = 2;
1038 gpio->base = -1;
1039 gpio->set = max9286_gpio_set;
1040 gpio->get = max9286_gpio_get;
1041 gpio->can_sleep = true;
1042
1043 /* GPIO values default to high */
1044 priv->gpio_state = BIT(0) | BIT(1);
1045
1046 ret = devm_gpiochip_add_data(dev, gpio, priv);
1047 if (ret)
1048 dev_err(dev, "Unable to create gpio_chip\n");
1049
1050 return ret;
1051}
1052
1053static int max9286_init(struct device *dev)
1054{
1055 struct max9286_priv *priv;
1056 struct i2c_client *client;
1057 int ret;
1058
1059 client = to_i2c_client(dev);
1060 priv = i2c_get_clientdata(client);
1061
1062 /* Enable the bus power. */
1063 ret = regulator_enable(priv->regulator);
1064 if (ret < 0) {
1065 dev_err(&client->dev, "Unable to turn PoC on\n");
1066 return ret;
1067 }
1068
1069 ret = max9286_setup(priv);
1070 if (ret) {
1071 dev_err(dev, "Unable to setup max9286\n");
1072 goto err_regulator;
1073 }
1074
1075 /*
1076 * Register all V4L2 interactions for the MAX9286 and notifiers for
1077 * any subdevices connected.
1078 */
1079 ret = max9286_v4l2_register(priv);
1080 if (ret) {
1081 dev_err(dev, "Failed to register with V4L2\n");
1082 goto err_regulator;
1083 }
1084
1085 ret = max9286_i2c_mux_init(priv);
1086 if (ret) {
1087 dev_err(dev, "Unable to initialize I2C multiplexer\n");
1088 goto err_v4l2_register;
1089 }
1090
1091 /* Leave the mux channels disabled until they are selected. */
1092 max9286_i2c_mux_close(priv);
1093
1094 return 0;
1095
1096err_v4l2_register:
1097 max9286_v4l2_unregister(priv);
1098err_regulator:
1099 regulator_disable(priv->regulator);
1100
1101 return ret;
1102}
1103
1104static void max9286_cleanup_dt(struct max9286_priv *priv)
1105{
1106 struct max9286_source *source;
1107
1108 for_each_source(priv, source) {
1109 fwnode_handle_put(source->fwnode);
1110 source->fwnode = NULL;
1111 }
1112}
1113
1114static int max9286_parse_dt(struct max9286_priv *priv)
1115{
1116 struct device *dev = &priv->client->dev;
1117 struct device_node *i2c_mux;
1118 struct device_node *node = NULL;
1119 unsigned int i2c_mux_mask = 0;
1120
1121 /* Balance the of_node_put() performed by of_find_node_by_name(). */
1122 of_node_get(dev->of_node);
1123 i2c_mux = of_find_node_by_name(dev->of_node, "i2c-mux");
1124 if (!i2c_mux) {
1125 dev_err(dev, "Failed to find i2c-mux node\n");
1126 return -EINVAL;
1127 }
1128
1129 /* Identify which i2c-mux channels are enabled */
1130 for_each_child_of_node(i2c_mux, node) {
1131 u32 id = 0;
1132
1133 of_property_read_u32(node, "reg", &id);
1134 if (id >= MAX9286_NUM_GMSL)
1135 continue;
1136
1137 if (!of_device_is_available(node)) {
1138 dev_dbg(dev, "Skipping disabled I2C bus port %u\n", id);
1139 continue;
1140 }
1141
1142 i2c_mux_mask |= BIT(id);
1143 }
1144 of_node_put(node);
1145 of_node_put(i2c_mux);
1146
1147 /* Parse the endpoints */
1148 for_each_endpoint_of_node(dev->of_node, node) {
1149 struct max9286_source *source;
1150 struct of_endpoint ep;
1151
1152 of_graph_parse_endpoint(node, &ep);
1153 dev_dbg(dev, "Endpoint %pOF on port %d",
1154 ep.local_node, ep.port);
1155
1156 if (ep.port > MAX9286_NUM_GMSL) {
1157 dev_err(dev, "Invalid endpoint %s on port %d",
1158 of_node_full_name(ep.local_node), ep.port);
1159 continue;
1160 }
1161
1162 /* For the source endpoint just parse the bus configuration. */
1163 if (ep.port == MAX9286_SRC_PAD) {
1164 struct v4l2_fwnode_endpoint vep = {
1165 .bus_type = V4L2_MBUS_CSI2_DPHY
1166 };
1167 int ret;
1168
1169 ret = v4l2_fwnode_endpoint_parse(
1170 of_fwnode_handle(node), &vep);
1171 if (ret) {
1172 of_node_put(node);
1173 return ret;
1174 }
1175
1176 priv->csi2_data_lanes =
1177 vep.bus.mipi_csi2.num_data_lanes;
1178
1179 continue;
1180 }
1181
1182 /* Skip if the corresponding GMSL link is unavailable. */
1183 if (!(i2c_mux_mask & BIT(ep.port)))
1184 continue;
1185
1186 if (priv->sources[ep.port].fwnode) {
1187 dev_err(dev,
1188 "Multiple port endpoints are not supported: %d",
1189 ep.port);
1190
1191 continue;
1192 }
1193
1194 source = &priv->sources[ep.port];
1195 source->fwnode = fwnode_graph_get_remote_endpoint(
1196 of_fwnode_handle(node));
1197 if (!source->fwnode) {
1198 dev_err(dev,
1199 "Endpoint %pOF has no remote endpoint connection\n",
1200 ep.local_node);
1201
1202 continue;
1203 }
1204
1205 priv->source_mask |= BIT(ep.port);
1206 priv->nsources++;
1207 }
1208 of_node_put(node);
1209
1210 priv->route_mask = priv->source_mask;
1211
1212 return 0;
1213}
1214
1215static int max9286_probe(struct i2c_client *client)
1216{
1217 struct max9286_priv *priv;
1218 int ret;
1219
1220 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
1221 if (!priv)
1222 return -ENOMEM;
1223
1224 mutex_init(&priv->mutex);
1225
1226 priv->client = client;
1227 i2c_set_clientdata(client, priv);
1228
1229 priv->gpiod_pwdn = devm_gpiod_get_optional(&client->dev, "enable",
1230 GPIOD_OUT_HIGH);
1231 if (IS_ERR(priv->gpiod_pwdn))
1232 return PTR_ERR(priv->gpiod_pwdn);
1233
1234 gpiod_set_consumer_name(priv->gpiod_pwdn, "max9286-pwdn");
1235 gpiod_set_value_cansleep(priv->gpiod_pwdn, 1);
1236
1237 /* Wait at least 4ms before the I2C lines latch to the address */
1238 if (priv->gpiod_pwdn)
1239 usleep_range(4000, 5000);
1240
1241 /*
1242 * The MAX9286 starts by default with all ports enabled, we disable all
1243 * ports early to ensure that all channels are disabled if we error out
1244 * and keep the bus consistent.
1245 */
1246 max9286_i2c_mux_close(priv);
1247
1248 /*
1249 * The MAX9286 initialises with auto-acknowledge enabled by default.
1250 * This can be invasive to other transactions on the same bus, so
1251 * disable it early. It will be enabled only as and when needed.
1252 */
1253 max9286_configure_i2c(priv, false);
1254
1255 ret = max9286_register_gpio(priv);
1256 if (ret)
1257 goto err_powerdown;
1258
1259 priv->regulator = devm_regulator_get(&client->dev, "poc");
1260 if (IS_ERR(priv->regulator)) {
1261 if (PTR_ERR(priv->regulator) != -EPROBE_DEFER)
1262 dev_err(&client->dev,
1263 "Unable to get PoC regulator (%ld)\n",
1264 PTR_ERR(priv->regulator));
1265 ret = PTR_ERR(priv->regulator);
1266 goto err_powerdown;
1267 }
1268
1269 ret = max9286_parse_dt(priv);
1270 if (ret)
1271 goto err_powerdown;
1272
1273 ret = max9286_init(&client->dev);
1274 if (ret < 0)
1275 goto err_cleanup_dt;
1276
1277 return 0;
1278
1279err_cleanup_dt:
1280 max9286_cleanup_dt(priv);
1281err_powerdown:
1282 gpiod_set_value_cansleep(priv->gpiod_pwdn, 0);
1283
1284 return ret;
1285}
1286
1287static int max9286_remove(struct i2c_client *client)
1288{
1289 struct max9286_priv *priv = i2c_get_clientdata(client);
1290
1291 i2c_mux_del_adapters(priv->mux);
1292
1293 max9286_v4l2_unregister(priv);
1294
1295 regulator_disable(priv->regulator);
1296
1297 gpiod_set_value_cansleep(priv->gpiod_pwdn, 0);
1298
1299 max9286_cleanup_dt(priv);
1300
1301 return 0;
1302}
1303
1304static const struct of_device_id max9286_dt_ids[] = {
1305 { .compatible = "maxim,max9286" },
1306 {},
1307};
1308MODULE_DEVICE_TABLE(of, max9286_dt_ids);
1309
1310static struct i2c_driver max9286_i2c_driver = {
1311 .driver = {
1312 .name = "max9286",
1313 .of_match_table = of_match_ptr(max9286_dt_ids),
1314 },
1315 .probe_new = max9286_probe,
1316 .remove = max9286_remove,
1317};
1318
1319module_i2c_driver(max9286_i2c_driver);
1320
1321MODULE_DESCRIPTION("Maxim MAX9286 GMSL Deserializer Driver");
1322MODULE_AUTHOR("Jacopo Mondi, Kieran Bingham, Laurent Pinchart, Niklas Söderlund, Vladimir Barinov");
1323MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)