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media: ar0521: Rework PLL computation
[linux-block.git] / drivers / media / i2c / ar0521.c
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852b50ae
KH		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Sieć Badawcza Łukasiewicz
4 * - Przemysłowy Instytut Automatyki i Pomiarów PIAP
5 * Written by Krzysztof Hałasa
6 */
7
8#include <linux/clk.h>
9#include <linux/delay.h>
10#include <linux/pm_runtime.h>
11
12#include <media/v4l2-ctrls.h>
13#include <media/v4l2-fwnode.h>
14#include <media/v4l2-subdev.h>
15
16/* External clock (extclk) frequencies */
17#define AR0521_EXTCLK_MIN (10 * 1000 * 1000)
18#define AR0521_EXTCLK_MAX (48 * 1000 * 1000)
19
20/* PLL and PLL2 */
21#define AR0521_PLL_MIN (320 * 1000 * 1000)
22#define AR0521_PLL_MAX (1280 * 1000 * 1000)
23
3a51fd71 24/* Effective pixel sample rate on the pixel array. */
852b50ae
KH		 25#define AR0521_PIXEL_CLOCK_RATE (184 * 1000 * 1000)
26#define AR0521_PIXEL_CLOCK_MIN (168 * 1000 * 1000)
27#define AR0521_PIXEL_CLOCK_MAX (414 * 1000 * 1000)
28
e4bdc249
JM		 29#define AR0521_NATIVE_WIDTH 2604u
30#define AR0521_NATIVE_HEIGHT 1964u
31#define AR0521_MIN_X_ADDR_START 0u
32#define AR0521_MIN_Y_ADDR_START 0u
33#define AR0521_MAX_X_ADDR_END 2603u
34#define AR0521_MAX_Y_ADDR_END 1955u
35
852b50ae 36#define AR0521_WIDTH_MIN 8u
e4bdc249 37#define AR0521_WIDTH_MAX 2592u
852b50ae 38#define AR0521_HEIGHT_MIN 8u
e4bdc249 39#define AR0521_HEIGHT_MAX 1944u
852b50ae
KH		 40
41#define AR0521_WIDTH_BLANKING_MIN 572u
42#define AR0521_HEIGHT_BLANKING_MIN 38u /* must be even */
43#define AR0521_TOTAL_WIDTH_MIN 2968u
44
114df304
JM		 45#define AR0521_ANA_GAIN_MIN 0x00
46#define AR0521_ANA_GAIN_MAX 0x3f
47#define AR0521_ANA_GAIN_STEP 0x01
48#define AR0521_ANA_GAIN_DEFAULT 0x00
49
852b50ae
KH		 50/* AR0521 registers */
51#define AR0521_REG_VT_PIX_CLK_DIV 0x0300
52#define AR0521_REG_FRAME_LENGTH_LINES 0x0340
53
54#define AR0521_REG_CHIP_ID 0x3000
55#define AR0521_REG_COARSE_INTEGRATION_TIME 0x3012
56#define AR0521_REG_ROW_SPEED 0x3016
57#define AR0521_REG_EXTRA_DELAY 0x3018
58#define AR0521_REG_RESET 0x301A
59#define AR0521_REG_RESET_DEFAULTS 0x0238
60#define AR0521_REG_RESET_GROUP_PARAM_HOLD 0x8000
61#define AR0521_REG_RESET_STREAM BIT(2)
62#define AR0521_REG_RESET_RESTART BIT(1)
63#define AR0521_REG_RESET_INIT BIT(0)
64
114df304
JM		 65#define AR0521_REG_ANA_GAIN_CODE_GLOBAL 0x3028
66
852b50ae
KH		 67#define AR0521_REG_GREEN1_GAIN 0x3056
68#define AR0521_REG_BLUE_GAIN 0x3058
69#define AR0521_REG_RED_GAIN 0x305A
70#define AR0521_REG_GREEN2_GAIN 0x305C
71#define AR0521_REG_GLOBAL_GAIN 0x305E
72
73#define AR0521_REG_HISPI_TEST_MODE 0x3066
74#define AR0521_REG_HISPI_TEST_MODE_LP11 0x0004
75
76#define AR0521_REG_TEST_PATTERN_MODE 0x3070
77
78#define AR0521_REG_SERIAL_FORMAT 0x31AE
79#define AR0521_REG_SERIAL_FORMAT_MIPI 0x0200
80
81#define AR0521_REG_HISPI_CONTROL_STATUS 0x31C6
82#define AR0521_REG_HISPI_CONTROL_STATUS_FRAMER_TEST_MODE_ENABLE 0x80
83
84#define be cpu_to_be16
85
86static const char * const ar0521_supply_names[] = {
87 "vdd_io", /* I/O (1.8V) supply */
88 "vdd", /* Core, PLL and MIPI (1.2V) supply */
89 "vaa", /* Analog (2.7V) supply */
90};
91
92struct ar0521_ctrls {
93 struct v4l2_ctrl_handler handler;
94 struct {
95 struct v4l2_ctrl *gain;
96 struct v4l2_ctrl *red_balance;
97 struct v4l2_ctrl *blue_balance;
98 };
99 struct {
100 struct v4l2_ctrl *hblank;
101 struct v4l2_ctrl *vblank;
102 };
103 struct v4l2_ctrl *pixrate;
104 struct v4l2_ctrl *exposure;
105 struct v4l2_ctrl *test_pattern;
106};
107
108struct ar0521_dev {
109 struct i2c_client *i2c_client;
110 struct v4l2_subdev sd;
111 struct media_pad pad;
112 struct clk *extclk;
113 u32 extclk_freq;
114
115 struct regulator *supplies[ARRAY_SIZE(ar0521_supply_names)];
116 struct gpio_desc *reset_gpio;
117
118 /* lock to protect all members below */
119 struct mutex lock;
120
121 struct v4l2_mbus_framefmt fmt;
122 struct ar0521_ctrls ctrls;
123 unsigned int lane_count;
124 u16 total_width;
125 u16 total_height;
3a51fd71
JM		 126 struct {
127 u16 pre;
128 u16 mult;
129 u16 pre2;
130 u16 mult2;
131 u16 vt_pix;
132 } pll;
133
852b50ae
KH		 134 bool streaming;
135};
136
137static inline struct ar0521_dev *to_ar0521_dev(struct v4l2_subdev *sd)
138{
139 return container_of(sd, struct ar0521_dev, sd);
140}
141
142static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
143{
144 return &container_of(ctrl->handler, struct ar0521_dev,
145 ctrls.handler)->sd;
146}
147
148static u32 div64_round(u64 v, u32 d)
149{
150 return div_u64(v + (d >> 1), d);
151}
152
153static u32 div64_round_up(u64 v, u32 d)
154{
155 return div_u64(v + d - 1, d);
156}
157
3a51fd71
JM		 158static int ar0521_code_to_bpp(struct ar0521_dev *sensor)
159{
160 switch (sensor->fmt.code) {
161 case MEDIA_BUS_FMT_SGRBG8_1X8:
162 return 8;
163 }
164
165 return -EINVAL;
166}
167
852b50ae
KH		 168/* Data must be BE16, the first value is the register address */
169static int ar0521_write_regs(struct ar0521_dev *sensor, const __be16 *data,
170 unsigned int count)
171{
172 struct i2c_client *client = sensor->i2c_client;
173 struct i2c_msg msg;
174 int ret;
175
176 msg.addr = client->addr;
177 msg.flags = client->flags;
178 msg.buf = (u8 *)data;
179 msg.len = count * sizeof(*data);
180
181 ret = i2c_transfer(client->adapter, &msg, 1);
182
183 if (ret < 0) {
184 v4l2_err(&sensor->sd, "%s: I2C write error\n", __func__);
185 return ret;
186 }
187
188 return 0;
189}
190
191static int ar0521_write_reg(struct ar0521_dev *sensor, u16 reg, u16 val)
192{
193 __be16 buf[2] = {be(reg), be(val)};
194
195 return ar0521_write_regs(sensor, buf, 2);
196}
197
198static int ar0521_set_geometry(struct ar0521_dev *sensor)
199{
e4bdc249
JM		 200 /* Center the image in the visible output window. */
201 u16 x = clamp((AR0521_WIDTH_MAX - sensor->fmt.width) / 2,
202 AR0521_MIN_X_ADDR_START, AR0521_MAX_X_ADDR_END);
203 u16 y = clamp(((AR0521_HEIGHT_MAX - sensor->fmt.height) / 2) & ~1,
204 AR0521_MIN_Y_ADDR_START, AR0521_MAX_Y_ADDR_END);
205
852b50ae 206 /* All dimensions are unsigned 12-bit integers */
852b50ae
KH		 207 __be16 regs[] = {
208 be(AR0521_REG_FRAME_LENGTH_LINES),
e4bdc249
JM		 209 be(sensor->fmt.height + sensor->ctrls.vblank->val),
210 be(sensor->fmt.width + sensor->ctrls.hblank->val),
852b50ae
KH		 211 be(x),
212 be(y),
213 be(x + sensor->fmt.width - 1),
214 be(y + sensor->fmt.height - 1),
215 be(sensor->fmt.width),
216 be(sensor->fmt.height)
217 };
218
219 return ar0521_write_regs(sensor, regs, ARRAY_SIZE(regs));
220}
221
222static int ar0521_set_gains(struct ar0521_dev *sensor)
223{
224 int green = sensor->ctrls.gain->val;
225 int red = max(green + sensor->ctrls.red_balance->val, 0);
226 int blue = max(green + sensor->ctrls.blue_balance->val, 0);
227 unsigned int gain = min(red, min(green, blue));
228 unsigned int analog = min(gain, 64u); /* range is 0 - 127 */
229 __be16 regs[5];
230
231 red = min(red - analog + 64, 511u);
232 green = min(green - analog + 64, 511u);
233 blue = min(blue - analog + 64, 511u);
234 regs[0] = be(AR0521_REG_GREEN1_GAIN);
235 regs[1] = be(green << 7 | analog);
236 regs[2] = be(blue << 7 | analog);
237 regs[3] = be(red << 7 | analog);
238 regs[4] = be(green << 7 | analog);
239
240 return ar0521_write_regs(sensor, regs, ARRAY_SIZE(regs));
241}
242
3a51fd71 243static u32 calc_pll(struct ar0521_dev *sensor, u32 freq, u16 *pre_ptr, u16 *mult_ptr)
852b50ae
KH		 244{
245 u16 pre = 1, mult = 1, new_pre;
246 u32 pll = AR0521_PLL_MAX + 1;
247
248 for (new_pre = 1; new_pre < 64; new_pre++) {
249 u32 new_pll;
250 u32 new_mult = div64_round_up((u64)freq * new_pre,
251 sensor->extclk_freq);
252
253 if (new_mult < 32)
254 continue; /* Minimum value */
255 if (new_mult > 254)
256 break; /* Maximum, larger pre won't work either */
257 if (sensor->extclk_freq * (u64)new_mult < AR0521_PLL_MIN *
258 new_pre)
259 continue;
260 if (sensor->extclk_freq * (u64)new_mult > AR0521_PLL_MAX *
261 new_pre)
262 break; /* Larger pre won't work either */
263 new_pll = div64_round_up(sensor->extclk_freq * (u64)new_mult,
264 new_pre);
265 if (new_pll < pll) {
266 pll = new_pll;
267 pre = new_pre;
268 mult = new_mult;
269 }
270 }
271
272 pll = div64_round(sensor->extclk_freq * (u64)mult, pre);
273 *pre_ptr = pre;
274 *mult_ptr = mult;
275 return pll;
276}
277
852b50ae
KH		 278static void ar0521_calc_mode(struct ar0521_dev *sensor)
279{
3a51fd71
JM		 280 unsigned int pixel_clock;
281 u16 pre, mult;
282 u32 vco;
283 int bpp;
284
285 /*
286 * PLL1 and PLL2 are computed equally even if the application note
287 * suggests a slower PLL1 clock. Maintain pll1 and pll2 divider and
288 * multiplier separated to later specialize the calculation procedure.
289 *
290 * PLL1:
291 * - mclk -> / pre_div1 * pre_mul1 = VCO1 = COUNTER_CLOCK
292 *
293 * PLL2:
294 * - mclk -> / pre_div * pre_mul = VCO
295 *
296 * VCO -> / vt_pix = PIXEL_CLOCK
297 * VCO -> / vt_pix / 2 = WORD_CLOCK
298 * VCO -> / op_sys = SERIAL_CLOCK
299 *
300 * With:
301 * - vt_pix = bpp / 2
302 * - WORD_CLOCK = PIXEL_CLOCK / 2
303 * - SERIAL_CLOCK = MIPI data rate (Mbps / lane) = WORD_CLOCK * bpp
304 * NOTE: this implies the MIPI clock is divided internally by 2
305 * to account for DDR.
306 *
307 * As op_sys_div is fixed to 1:
308 *
309 * SERIAL_CLOCK = VCO
310 * VCO = 2 * MIPI_CLK
311 * VCO = PIXEL_CLOCK * bpp / 2
312 *
313 * In the clock tree:
314 * MIPI_CLK = PIXEL_CLOCK * bpp / 2 / 2
315 *
316 * Generic pixel_rate to bus clock frequencey equation:
317 * MIPI_CLK = V4L2_CID_PIXEL_RATE * bpp / lanes / 2
318 *
319 * From which we derive the PIXEL_CLOCK to use in the clock tree:
320 * PIXEL_CLOCK = V4L2_CID_PIXEL_RATE * 2 / lanes
321 *
322 * Documented clock ranges:
323 * WORD_CLOCK = (35MHz - 120 MHz)
324 * PIXEL_CLOCK = (84MHz - 207MHz)
325 * VCO = (320MHz - 1280MHz)
326 *
327 * TODO: in case we have less data lanes we have to reduce the desired
328 * VCO not to exceed the limits specified by the datasheet and
329 * consequentially reduce the obtained pixel clock.
330 */
331 pixel_clock = AR0521_PIXEL_CLOCK_RATE * 2 / sensor->lane_count;
332 bpp = ar0521_code_to_bpp(sensor);
333 sensor->pll.vt_pix = bpp / 2;
334 vco = pixel_clock * sensor->pll.vt_pix;
335
336 calc_pll(sensor, vco, &pre, &mult);
337
338 sensor->pll.pre = sensor->pll.pre2 = pre;
339 sensor->pll.mult = sensor->pll.mult2 = mult;
852b50ae
KH		 340}
341
342static int ar0521_write_mode(struct ar0521_dev *sensor)
343{
344 __be16 pll_regs[] = {
345 be(AR0521_REG_VT_PIX_CLK_DIV),
3a51fd71 346 /* 0x300 */ be(sensor->pll.vt_pix), /* vt_pix_clk_div = bpp / 2 */
852b50ae 347 /* 0x302 */ be(1), /* vt_sys_clk_div */
3a51fd71
JM		 348 /* 0x304 */ be((sensor->pll.pre2 << 8) | sensor->pll.pre),
349 /* 0x306 */ be((sensor->pll.mult2 << 8) | sensor->pll.mult),
350 /* 0x308 */ be(sensor->pll.vt_pix * 2), /* op_pix_clk_div = 2 * vt_pix_clk_div */
852b50ae
KH		 351 /* 0x30A */ be(1) /* op_sys_clk_div */
352 };
353 int ret;
354
355 /* Stop streaming for just a moment */
356 ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
357 AR0521_REG_RESET_DEFAULTS);
358 if (ret)
359 return ret;
360
361 ret = ar0521_set_geometry(sensor);
362 if (ret)
363 return ret;
364
365 ret = ar0521_write_regs(sensor, pll_regs, ARRAY_SIZE(pll_regs));
366 if (ret)
367 return ret;
368
369 ret = ar0521_write_reg(sensor, AR0521_REG_COARSE_INTEGRATION_TIME,
370 sensor->ctrls.exposure->val);
371 if (ret)
372 return ret;
373
374 ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
375 AR0521_REG_RESET_DEFAULTS |
376 AR0521_REG_RESET_STREAM);
377 if (ret)
378 return ret;
379
380 ret = ar0521_write_reg(sensor, AR0521_REG_TEST_PATTERN_MODE,
381 sensor->ctrls.test_pattern->val);
382 return ret;
383}
384
385static int ar0521_set_stream(struct ar0521_dev *sensor, bool on)
386{
387 int ret;
388
389 if (on) {
390 ret = pm_runtime_resume_and_get(&sensor->i2c_client->dev);
391 if (ret < 0)
392 return ret;
393
394 ar0521_calc_mode(sensor);
395 ret = ar0521_write_mode(sensor);
396 if (ret)
397 goto err;
398
399 ret = ar0521_set_gains(sensor);
400 if (ret)
401 goto err;
402
403 /* Exit LP-11 mode on clock and data lanes */
404 ret = ar0521_write_reg(sensor, AR0521_REG_HISPI_CONTROL_STATUS,
405 0);
406 if (ret)
407 goto err;
408
409 /* Start streaming */
410 ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
411 AR0521_REG_RESET_DEFAULTS |
412 AR0521_REG_RESET_STREAM);
413 if (ret)
414 goto err;
415
416 return 0;
417
418err:
419 pm_runtime_put(&sensor->i2c_client->dev);
420 return ret;
421
422 } else {
423 /*
424 * Reset gain, the sensor may produce all white pixels without
425 * this
426 */
427 ret = ar0521_write_reg(sensor, AR0521_REG_GLOBAL_GAIN, 0x2000);
428 if (ret)
429 return ret;
430
431 /* Stop streaming */
432 ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
433 AR0521_REG_RESET_DEFAULTS);
434 if (ret)
435 return ret;
436
437 pm_runtime_put(&sensor->i2c_client->dev);
438 return 0;
439 }
440}
441
442static void ar0521_adj_fmt(struct v4l2_mbus_framefmt *fmt)
443{
444 fmt->width = clamp(ALIGN(fmt->width, 4), AR0521_WIDTH_MIN,
445 AR0521_WIDTH_MAX);
446 fmt->height = clamp(ALIGN(fmt->height, 4), AR0521_HEIGHT_MIN,
447 AR0521_HEIGHT_MAX);
448 fmt->code = MEDIA_BUS_FMT_SGRBG8_1X8;
449 fmt->field = V4L2_FIELD_NONE;
450 fmt->colorspace = V4L2_COLORSPACE_SRGB;
451 fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
452 fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
453 fmt->xfer_func = V4L2_XFER_FUNC_DEFAULT;
454}
455
456static int ar0521_get_fmt(struct v4l2_subdev *sd,
457 struct v4l2_subdev_state *sd_state,
458 struct v4l2_subdev_format *format)
459{
460 struct ar0521_dev *sensor = to_ar0521_dev(sd);
461 struct v4l2_mbus_framefmt *fmt;
462
463 mutex_lock(&sensor->lock);
464
465 if (format->which == V4L2_SUBDEV_FORMAT_TRY)
466 fmt = v4l2_subdev_get_try_format(&sensor->sd, sd_state, 0
467 /* pad */);
468 else
469 fmt = &sensor->fmt;
470
471 format->format = *fmt;
472
473 mutex_unlock(&sensor->lock);
474 return 0;
475}
476
477static int ar0521_set_fmt(struct v4l2_subdev *sd,
478 struct v4l2_subdev_state *sd_state,
479 struct v4l2_subdev_format *format)
480{
481 struct ar0521_dev *sensor = to_ar0521_dev(sd);
852b50ae
KH		 482
483 ar0521_adj_fmt(&format->format);
484
485 mutex_lock(&sensor->lock);
486
487 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
488 struct v4l2_mbus_framefmt *fmt;
489
490 fmt = v4l2_subdev_get_try_format(sd, sd_state, 0 /* pad */);
491 *fmt = format->format;
492 } else {
493 sensor->fmt = format->format;
494 ar0521_calc_mode(sensor);
495 }
496
497 mutex_unlock(&sensor->lock);
8fcccd2f 498 return 0;
852b50ae
KH		 499}
500
501static int ar0521_s_ctrl(struct v4l2_ctrl *ctrl)
502{
503 struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
504 struct ar0521_dev *sensor = to_ar0521_dev(sd);
505 int ret;
506
507 /* v4l2_ctrl_lock() locks our own mutex */
508
509 switch (ctrl->id) {
510 case V4L2_CID_HBLANK:
511 case V4L2_CID_VBLANK:
512 sensor->total_width = sensor->fmt.width +
513 sensor->ctrls.hblank->val;
514 sensor->total_height = sensor->fmt.width +
515 sensor->ctrls.vblank->val;
516 break;
517 default:
518 ret = -EINVAL;
519 break;
520 }
521
522 /* access the sensor only if it's powered up */
523 if (!pm_runtime_get_if_in_use(&sensor->i2c_client->dev))
524 return 0;
525
526 switch (ctrl->id) {
527 case V4L2_CID_HBLANK:
528 case V4L2_CID_VBLANK:
529 ret = ar0521_set_geometry(sensor);
530 break;
114df304
JM		 531 case V4L2_CID_ANALOGUE_GAIN:
532 ret = ar0521_write_reg(sensor, AR0521_REG_ANA_GAIN_CODE_GLOBAL,
533 ctrl->val);
534 break;
852b50ae
KH		 535 case V4L2_CID_GAIN:
536 case V4L2_CID_RED_BALANCE:
537 case V4L2_CID_BLUE_BALANCE:
538 ret = ar0521_set_gains(sensor);
539 break;
540 case V4L2_CID_EXPOSURE:
541 ret = ar0521_write_reg(sensor,
542 AR0521_REG_COARSE_INTEGRATION_TIME,
543 ctrl->val);
544 break;
545 case V4L2_CID_TEST_PATTERN:
546 ret = ar0521_write_reg(sensor, AR0521_REG_TEST_PATTERN_MODE,
547 ctrl->val);
548 break;
549 }
550
551 pm_runtime_put(&sensor->i2c_client->dev);
552 return ret;
553}
554
555static const struct v4l2_ctrl_ops ar0521_ctrl_ops = {
556 .s_ctrl = ar0521_s_ctrl,
557};
558
559static const char * const test_pattern_menu[] = {
560 "Disabled",
561 "Solid color",
562 "Color bars",
563 "Faded color bars"
564};
565
566static int ar0521_init_controls(struct ar0521_dev *sensor)
567{
568 const struct v4l2_ctrl_ops *ops = &ar0521_ctrl_ops;
569 struct ar0521_ctrls *ctrls = &sensor->ctrls;
570 struct v4l2_ctrl_handler *hdl = &ctrls->handler;
571 int ret;
572
573 v4l2_ctrl_handler_init(hdl, 32);
574
575 /* We can use our own mutex for the ctrl lock */
576 hdl->lock = &sensor->lock;
577
114df304
JM		 578 /* Analog gain */
579 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_ANALOGUE_GAIN,
580 AR0521_ANA_GAIN_MIN, AR0521_ANA_GAIN_MAX,
581 AR0521_ANA_GAIN_STEP, AR0521_ANA_GAIN_DEFAULT);
582
852b50ae
KH		 583 /* Manual gain */
584 ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN, 0, 511, 1, 0);
585 ctrls->red_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_RED_BALANCE,
586 -512, 511, 1, 0);
587 ctrls->blue_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BLUE_BALANCE,
588 -512, 511, 1, 0);
589 v4l2_ctrl_cluster(3, &ctrls->gain);
590
591 ctrls->hblank = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HBLANK,
592 AR0521_WIDTH_BLANKING_MIN, 4094, 1,
593 AR0521_WIDTH_BLANKING_MIN);
594 ctrls->vblank = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VBLANK,
595 AR0521_HEIGHT_BLANKING_MIN, 4094, 2,
596 AR0521_HEIGHT_BLANKING_MIN);
597 v4l2_ctrl_cluster(2, &ctrls->hblank);
598
599 /* Read-only */
600 ctrls->pixrate = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_PIXEL_RATE,
601 AR0521_PIXEL_CLOCK_MIN,
602 AR0521_PIXEL_CLOCK_MAX, 1,
603 AR0521_PIXEL_CLOCK_RATE);
604
605 /* Manual exposure time */
606 ctrls->exposure = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE, 0,
607 65535, 1, 360);
608
609 ctrls->test_pattern = v4l2_ctrl_new_std_menu_items(hdl, ops,
610 V4L2_CID_TEST_PATTERN,
611 ARRAY_SIZE(test_pattern_menu) - 1,
612 0, 0, test_pattern_menu);
613
614 if (hdl->error) {
615 ret = hdl->error;
616 goto free_ctrls;
617 }
618
619 sensor->sd.ctrl_handler = hdl;
620 return 0;
621
622free_ctrls:
623 v4l2_ctrl_handler_free(hdl);
624 return ret;
625}
626
627#define REGS_ENTRY(a) {(a), ARRAY_SIZE(a)}
628#define REGS(...) REGS_ENTRY(((const __be16[]){__VA_ARGS__}))
629
630static const struct initial_reg {
631 const __be16 *data; /* data[0] is register address */
632 unsigned int count;
633} initial_regs[] = {
634 REGS(be(0x0112), be(0x0808)), /* 8-bit/8-bit mode */
635
636 /* PEDESTAL+2 :+2 is a workaround for 10bit mode +0.5 rounding */
637 REGS(be(0x301E), be(0x00AA)),
638
639 /* corrections_recommended_bayer */
640 REGS(be(0x3042),
641 be(0x0004), /* 3042: RNC: enable b/w rnc mode */
642 be(0x4580)), /* 3044: RNC: enable row noise correction */
643
644 REGS(be(0x30D2),
645 be(0x0000), /* 30D2: CRM/CC: enable crm on Visible and CC rows */
646 be(0x0000), /* 30D4: CC: CC enabled with 16 samples per column */
647 /* 30D6: CC: bw mode enabled/12 bit data resolution/bw mode */
648 be(0x2FFF)),
649
650 REGS(be(0x30DA),
651 be(0x0FFF), /* 30DA: CC: column correction clip level 2 is 0 */
652 be(0x0FFF), /* 30DC: CC: column correction clip level 3 is 0 */
653 be(0x0000)), /* 30DE: CC: Group FPN correction */
654
655 /* RNC: rnc scaling factor = * 54 / 64 (32 / 38 * 64 = 53.9) */
656 REGS(be(0x30EE), be(0x1136)),
657 REGS(be(0x30FA), be(0xFD00)), /* GPIO0 = flash, GPIO1 = shutter */
658 REGS(be(0x3120), be(0x0005)), /* p1 dither enabled for 10bit mode */
659 REGS(be(0x3172), be(0x0206)), /* txlo clk divider options */
660 /* FDOC:fdoc settings with fdoc every frame turned of */
661 REGS(be(0x3180), be(0x9434)),
662
663 REGS(be(0x31B0),
664 be(0x008B), /* 31B0: frame_preamble - FIXME check WRT lanes# */
665 be(0x0050)), /* 31B2: line_preamble - FIXME check WRT lanes# */
666
667 /* don't use continuous clock mode while shut down */
668 REGS(be(0x31BC), be(0x068C)),
669 REGS(be(0x31E0), be(0x0781)), /* Fuse/2DDC: enable 2ddc */
670
671 /* analog_setup_recommended_10bit */
672 REGS(be(0x341A), be(0x4735)), /* Samp&Hold pulse in ADC */
673 REGS(be(0x3420), be(0x4735)), /* Samp&Hold pulse in ADC */
674 REGS(be(0x3426), be(0x8A1A)), /* ADC offset distribution pulse */
675 REGS(be(0x342A), be(0x0018)), /* pulse_config */
676
677 /* pixel_timing_recommended */
678 REGS(be(0x3D00),
679 /* 3D00 */ be(0x043E), be(0x4760), be(0xFFFF), be(0xFFFF),
680 /* 3D08 */ be(0x8000), be(0x0510), be(0xAF08), be(0x0252),
681 /* 3D10 */ be(0x486F), be(0x5D5D), be(0x8056), be(0x8313),
682 /* 3D18 */ be(0x0087), be(0x6A48), be(0x6982), be(0x0280),
683 /* 3D20 */ be(0x8359), be(0x8D02), be(0x8020), be(0x4882),
684 /* 3D28 */ be(0x4269), be(0x6A95), be(0x5988), be(0x5A83),
685 /* 3D30 */ be(0x5885), be(0x6280), be(0x6289), be(0x6097),
686 /* 3D38 */ be(0x5782), be(0x605C), be(0xBF18), be(0x0961),
687 /* 3D40 */ be(0x5080), be(0x2090), be(0x4390), be(0x4382),
688 /* 3D48 */ be(0x5F8A), be(0x5D5D), be(0x9C63), be(0x8063),
689 /* 3D50 */ be(0xA960), be(0x9757), be(0x8260), be(0x5CFF),
690 /* 3D58 */ be(0xBF10), be(0x1681), be(0x0802), be(0x8000),
691 /* 3D60 */ be(0x141C), be(0x6000), be(0x6022), be(0x4D80),
692 /* 3D68 */ be(0x5C97), be(0x6A69), be(0xAC6F), be(0x4645),
693 /* 3D70 */ be(0x4400), be(0x0513), be(0x8069), be(0x6AC6),
694 /* 3D78 */ be(0x5F95), be(0x5F70), be(0x8040), be(0x4A81),
695 /* 3D80 */ be(0x0300), be(0xE703), be(0x0088), be(0x4A83),
696 /* 3D88 */ be(0x40FF), be(0xFFFF), be(0xFD70), be(0x8040),
697 /* 3D90 */ be(0x4A85), be(0x4FA8), be(0x4F8C), be(0x0070),
698 /* 3D98 */ be(0xBE47), be(0x8847), be(0xBC78), be(0x6B89),
699 /* 3DA0 */ be(0x6A80), be(0x6986), be(0x6B8E), be(0x6B80),
700 /* 3DA8 */ be(0x6980), be(0x6A88), be(0x7C9F), be(0x866B),
701 /* 3DB0 */ be(0x8765), be(0x46FF), be(0xE365), be(0xA679),
702 /* 3DB8 */ be(0x4A40), be(0x4580), be(0x44BC), be(0x7000),
703 /* 3DC0 */ be(0x8040), be(0x0802), be(0x10EF), be(0x0104),
704 /* 3DC8 */ be(0x3860), be(0x5D5D), be(0x5682), be(0x1300),
705 /* 3DD0 */ be(0x8648), be(0x8202), be(0x8082), be(0x598A),
706 /* 3DD8 */ be(0x0280), be(0x2048), be(0x3060), be(0x8042),
707 /* 3DE0 */ be(0x9259), be(0x865A), be(0x8258), be(0x8562),
708 /* 3DE8 */ be(0x8062), be(0x8560), be(0x9257), be(0x8221),
709 /* 3DF0 */ be(0x10FF), be(0xB757), be(0x9361), be(0x1019),
710 /* 3DF8 */ be(0x8020), be(0x9043), be(0x8E43), be(0x845F),
711 /* 3E00 */ be(0x835D), be(0x805D), be(0x8163), be(0x8063),
712 /* 3E08 */ be(0xA060), be(0x9157), be(0x8260), be(0x5CFF),
713 /* 3E10 */ be(0xFFFF), be(0xFFE5), be(0x1016), be(0x2048),
714 /* 3E18 */ be(0x0802), be(0x1C60), be(0x0014), be(0x0060),
715 /* 3E20 */ be(0x2205), be(0x8120), be(0x908F), be(0x6A80),
716 /* 3E28 */ be(0x6982), be(0x5F9F), be(0x6F46), be(0x4544),
717 /* 3E30 */ be(0x0005), be(0x8013), be(0x8069), be(0x6A80),
718 /* 3E38 */ be(0x7000), be(0x0000), be(0x0000), be(0x0000),
719 /* 3E40 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
720 /* 3E48 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
721 /* 3E50 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
722 /* 3E58 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
723 /* 3E60 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
724 /* 3E68 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
725 /* 3E70 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
726 /* 3E78 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
727 /* 3E80 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
728 /* 3E88 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
729 /* 3E90 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
730 /* 3E98 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
731 /* 3EA0 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
732 /* 3EA8 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
733 /* 3EB0 */ be(0x0000), be(0x0000), be(0x0000)),
734
735 REGS(be(0x3EB6), be(0x004C)), /* ECL */
736
737 REGS(be(0x3EBA),
738 be(0xAAAD), /* 3EBA */
739 be(0x0086)), /* 3EBC: Bias currents for FSC/ECL */
740
741 REGS(be(0x3EC0),
742 be(0x1E00), /* 3EC0: SFbin/SH mode settings */
743 be(0x100A), /* 3EC2: CLK divider for ramp for 10 bit 400MH */
744 /* 3EC4: FSC clamps for HDR mode and adc comp power down co */
745 be(0x3300),
746 be(0xEA44), /* 3EC6: VLN and clk gating controls */
747 be(0x6F6F), /* 3EC8: Txl0 and Txlo1 settings for normal mode */
748 be(0x2F4A), /* 3ECA: CDAC/Txlo2/RSTGHI/RSTGLO settings */
749 be(0x0506), /* 3ECC: RSTDHI/RSTDLO/CDAC/TXHI settings */
750 /* 3ECE: Ramp buffer settings and Booster enable (bits 0-5) */
751 be(0x203B),
752 be(0x13F0), /* 3ED0: TXLO from atest/sf bin settings */
753 be(0xA53D), /* 3ED2: Ramp offset */
754 be(0x862F), /* 3ED4: TXLO open loop/row driver settings */
755 be(0x4081), /* 3ED6: Txlatch fr cfpn rows/vln bias */
756 be(0x8003), /* 3ED8: Ramp step setting for 10 bit 400 Mhz */
757 be(0xA580), /* 3EDA: Ramp Offset */
758 be(0xC000), /* 3EDC: over range for rst and under range for sig */
759 be(0xC103)), /* 3EDE: over range for sig and col dec clk settings */
760
761 /* corrections_recommended_bayer */
762 REGS(be(0x3F00),
763 be(0x0017), /* 3F00: BM_T0 */
764 be(0x02DD), /* 3F02: BM_T1 */
765 /* 3F04: if Ana_gain less than 2, use noise_floor0, multipl */
766 be(0x0020),
767 /* 3F06: if Ana_gain between 4 and 7, use noise_floor2 and */
768 be(0x0040),
769 /* 3F08: if Ana_gain between 4 and 7, use noise_floor2 and */
770 be(0x0070),
771 /* 3F0A: Define noise_floor0(low address) and noise_floor1 */
772 be(0x0101),
773 be(0x0302)), /* 3F0C: Define noise_floor2 and noise_floor3 */
774
775 REGS(be(0x3F10),
776 be(0x0505), /* 3F10: single k factor 0 */
777 be(0x0505), /* 3F12: single k factor 1 */
778 be(0x0505), /* 3F14: single k factor 2 */
779 be(0x01FF), /* 3F16: cross factor 0 */
780 be(0x01FF), /* 3F18: cross factor 1 */
781 be(0x01FF), /* 3F1A: cross factor 2 */
782 be(0x0022)), /* 3F1E */
783
784 /* GTH_THRES_RTN: 4max,4min filtered out of every 46 samples and */
785 REGS(be(0x3F2C), be(0x442E)),
786
787 REGS(be(0x3F3E),
788 be(0x0000), /* 3F3E: Switch ADC from 12 bit to 10 bit mode */
789 be(0x1511), /* 3F40: couple k factor 0 */
790 be(0x1511), /* 3F42: couple k factor 1 */
791 be(0x0707)), /* 3F44: couple k factor 2 */
792};
793
794static int ar0521_power_off(struct device *dev)
795{
796 struct v4l2_subdev *sd = dev_get_drvdata(dev);
797 struct ar0521_dev *sensor = to_ar0521_dev(sd);
798 int i;
799
800 clk_disable_unprepare(sensor->extclk);
801
802 if (sensor->reset_gpio)
803 gpiod_set_value(sensor->reset_gpio, 1); /* assert RESET signal */
804
805 for (i = ARRAY_SIZE(ar0521_supply_names) - 1; i >= 0; i--) {
806 if (sensor->supplies[i])
807 regulator_disable(sensor->supplies[i]);
808 }
809 return 0;
810}
811
812static int ar0521_power_on(struct device *dev)
813{
814 struct v4l2_subdev *sd = dev_get_drvdata(dev);
815 struct ar0521_dev *sensor = to_ar0521_dev(sd);
816 unsigned int cnt;
817 int ret;
818
819 for (cnt = 0; cnt < ARRAY_SIZE(ar0521_supply_names); cnt++)
820 if (sensor->supplies[cnt]) {
821 ret = regulator_enable(sensor->supplies[cnt]);
822 if (ret < 0)
823 goto off;
824
825 usleep_range(1000, 1500); /* min 1 ms */
826 }
827
828 ret = clk_prepare_enable(sensor->extclk);
829 if (ret < 0) {
830 v4l2_err(&sensor->sd, "error enabling sensor clock\n");
831 goto off;
832 }
833 usleep_range(1000, 1500); /* min 1 ms */
834
835 if (sensor->reset_gpio)
836 /* deassert RESET signal */
837 gpiod_set_value(sensor->reset_gpio, 0);
838 usleep_range(4500, 5000); /* min 45000 clocks */
839
54bb7671 840 for (cnt = 0; cnt < ARRAY_SIZE(initial_regs); cnt++) {
b5f8fa87
YY		 841 ret = ar0521_write_regs(sensor, initial_regs[cnt].data,
842 initial_regs[cnt].count);
843 if (ret)
852b50ae 844 goto off;
54bb7671 845 }
852b50ae
KH		 846
847 ret = ar0521_write_reg(sensor, AR0521_REG_SERIAL_FORMAT,
848 AR0521_REG_SERIAL_FORMAT_MIPI |
849 sensor->lane_count);
850 if (ret)
851 goto off;
852
853 /* set MIPI test mode - disabled for now */
854 ret = ar0521_write_reg(sensor, AR0521_REG_HISPI_TEST_MODE,
855 ((0x40 << sensor->lane_count) - 0x40) |
856 AR0521_REG_HISPI_TEST_MODE_LP11);
857 if (ret)
858 goto off;
859
860 ret = ar0521_write_reg(sensor, AR0521_REG_ROW_SPEED, 0x110 |
861 4 / sensor->lane_count);
862 if (ret)
863 goto off;
864
865 return 0;
866off:
867 ar0521_power_off(dev);
868 return ret;
869}
870
871static int ar0521_enum_mbus_code(struct v4l2_subdev *sd,
872 struct v4l2_subdev_state *sd_state,
873 struct v4l2_subdev_mbus_code_enum *code)
874{
875 struct ar0521_dev *sensor = to_ar0521_dev(sd);
876
877 if (code->index)
878 return -EINVAL;
879
880 code->code = sensor->fmt.code;
881 return 0;
882}
883
f7910135
JM		 884static int ar0521_enum_frame_size(struct v4l2_subdev *sd,
885 struct v4l2_subdev_state *sd_state,
886 struct v4l2_subdev_frame_size_enum *fse)
887{
888 if (fse->index)
889 return -EINVAL;
890
891 if (fse->code != MEDIA_BUS_FMT_SGRBG8_1X8)
892 return -EINVAL;
893
894 fse->min_width = AR0521_WIDTH_MIN;
895 fse->max_width = AR0521_WIDTH_MAX;
896 fse->min_height = AR0521_HEIGHT_MIN;
897 fse->max_height = AR0521_HEIGHT_MAX;
898
899 return 0;
900}
901
852b50ae
KH		 902static int ar0521_pre_streamon(struct v4l2_subdev *sd, u32 flags)
903{
904 struct ar0521_dev *sensor = to_ar0521_dev(sd);
905 int ret;
906
907 if (!(flags & V4L2_SUBDEV_PRE_STREAMON_FL_MANUAL_LP))
908 return -EACCES;
909
910 ret = pm_runtime_resume_and_get(&sensor->i2c_client->dev);
911 if (ret < 0)
912 return ret;
913
914 /* Set LP-11 on clock and data lanes */
915 ret = ar0521_write_reg(sensor, AR0521_REG_HISPI_CONTROL_STATUS,
916 AR0521_REG_HISPI_CONTROL_STATUS_FRAMER_TEST_MODE_ENABLE);
917 if (ret)
918 goto err;
919
920 /* Start streaming LP-11 */
921 ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
922 AR0521_REG_RESET_DEFAULTS |
923 AR0521_REG_RESET_STREAM);
924 if (ret)
925 goto err;
926 return 0;
927
928err:
929 pm_runtime_put(&sensor->i2c_client->dev);
930 return ret;
931}
932
933static int ar0521_post_streamoff(struct v4l2_subdev *sd)
934{
935 struct ar0521_dev *sensor = to_ar0521_dev(sd);
936
937 pm_runtime_put(&sensor->i2c_client->dev);
938 return 0;
939}
940
941static int ar0521_s_stream(struct v4l2_subdev *sd, int enable)
942{
943 struct ar0521_dev *sensor = to_ar0521_dev(sd);
944 int ret;
945
946 mutex_lock(&sensor->lock);
947
948 ret = ar0521_set_stream(sensor, enable);
949 if (!ret)
950 sensor->streaming = enable;
951
952 mutex_unlock(&sensor->lock);
953 return ret;
954}
955
956static const struct v4l2_subdev_core_ops ar0521_core_ops = {
957 .log_status = v4l2_ctrl_subdev_log_status,
958};
959
960static const struct v4l2_subdev_video_ops ar0521_video_ops = {
961 .s_stream = ar0521_s_stream,
962 .pre_streamon = ar0521_pre_streamon,
963 .post_streamoff = ar0521_post_streamoff,
964};
965
966static const struct v4l2_subdev_pad_ops ar0521_pad_ops = {
967 .enum_mbus_code = ar0521_enum_mbus_code,
f7910135 968 .enum_frame_size = ar0521_enum_frame_size,
852b50ae
KH		 969 .get_fmt = ar0521_get_fmt,
970 .set_fmt = ar0521_set_fmt,
971};
972
973static const struct v4l2_subdev_ops ar0521_subdev_ops = {
974 .core = &ar0521_core_ops,
975 .video = &ar0521_video_ops,
976 .pad = &ar0521_pad_ops,
977};
978
979static int __maybe_unused ar0521_suspend(struct device *dev)
980{
981 struct v4l2_subdev *sd = dev_get_drvdata(dev);
982 struct ar0521_dev *sensor = to_ar0521_dev(sd);
983
984 if (sensor->streaming)
985 ar0521_set_stream(sensor, 0);
986
987 return 0;
988}
989
990static int __maybe_unused ar0521_resume(struct device *dev)
991{
992 struct v4l2_subdev *sd = dev_get_drvdata(dev);
993 struct ar0521_dev *sensor = to_ar0521_dev(sd);
994
995 if (sensor->streaming)
996 return ar0521_set_stream(sensor, 1);
997
998 return 0;
999}
1000
1001static int ar0521_probe(struct i2c_client *client)
1002{
1003 struct v4l2_fwnode_endpoint ep = {
1004 .bus_type = V4L2_MBUS_CSI2_DPHY
1005 };
1006 struct device *dev = &client->dev;
1007 struct fwnode_handle *endpoint;
1008 struct ar0521_dev *sensor;
1009 unsigned int cnt;
1010 int ret;
1011
1012 sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);
1013 if (!sensor)
1014 return -ENOMEM;
1015
1016 sensor->i2c_client = client;
1017 sensor->fmt.width = AR0521_WIDTH_MAX;
1018 sensor->fmt.height = AR0521_HEIGHT_MAX;
1019
1020 endpoint = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 0, 0,
1021 FWNODE_GRAPH_ENDPOINT_NEXT);
1022 if (!endpoint) {
1023 dev_err(dev, "endpoint node not found\n");
1024 return -EINVAL;
1025 }
1026
1027 ret = v4l2_fwnode_endpoint_parse(endpoint, &ep);
1028 fwnode_handle_put(endpoint);
1029 if (ret) {
1030 dev_err(dev, "could not parse endpoint\n");
1031 return ret;
1032 }
1033
1034 if (ep.bus_type != V4L2_MBUS_CSI2_DPHY) {
1035 dev_err(dev, "invalid bus type, must be MIPI CSI2\n");
1036 return -EINVAL;
1037 }
1038
1039 sensor->lane_count = ep.bus.mipi_csi2.num_data_lanes;
1040 switch (sensor->lane_count) {
1041 case 1:
1042 case 2:
1043 case 4:
1044 break;
1045 default:
1046 dev_err(dev, "invalid number of MIPI data lanes\n");
1047 return -EINVAL;
1048 }
1049
1050 /* Get master clock (extclk) */
1051 sensor->extclk = devm_clk_get(dev, "extclk");
1052 if (IS_ERR(sensor->extclk)) {
1053 dev_err(dev, "failed to get extclk\n");
1054 return PTR_ERR(sensor->extclk);
1055 }
1056
1057 sensor->extclk_freq = clk_get_rate(sensor->extclk);
1058
1059 if (sensor->extclk_freq < AR0521_EXTCLK_MIN ||
1060 sensor->extclk_freq > AR0521_EXTCLK_MAX) {
1061 dev_err(dev, "extclk frequency out of range: %u Hz\n",
1062 sensor->extclk_freq);
1063 return -EINVAL;
1064 }
1065
1066 /* Request optional reset pin (usually active low) and assert it */
1067 sensor->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1068 GPIOD_OUT_HIGH);
1069
1070 v4l2_i2c_subdev_init(&sensor->sd, client, &ar0521_subdev_ops);
1071
1072 sensor->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
1073 sensor->pad.flags = MEDIA_PAD_FL_SOURCE;
1074 sensor->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1075 ret = media_entity_pads_init(&sensor->sd.entity, 1, &sensor->pad);
1076 if (ret)
1077 return ret;
1078
1079 for (cnt = 0; cnt < ARRAY_SIZE(ar0521_supply_names); cnt++) {
1080 struct regulator *supply = devm_regulator_get(dev,
1081 ar0521_supply_names[cnt]);
1082
1083 if (IS_ERR(supply)) {
1084 dev_info(dev, "no %s regulator found: %li\n",
1085 ar0521_supply_names[cnt], PTR_ERR(supply));
1086 return PTR_ERR(supply);
1087 }
1088 sensor->supplies[cnt] = supply;
1089 }
1090
1091 mutex_init(&sensor->lock);
1092
1093 ret = ar0521_init_controls(sensor);
1094 if (ret)
1095 goto entity_cleanup;
1096
1097 ar0521_adj_fmt(&sensor->fmt);
1098
1099 ret = v4l2_async_register_subdev(&sensor->sd);
1100 if (ret)
1101 goto free_ctrls;
1102
1103 /* Turn on the device and enable runtime PM */
1104 ret = ar0521_power_on(&client->dev);
1105 if (ret)
1106 goto disable;
1107 pm_runtime_set_active(&client->dev);
1108 pm_runtime_enable(&client->dev);
1109 pm_runtime_idle(&client->dev);
1110 return 0;
1111
1112disable:
1113 v4l2_async_unregister_subdev(&sensor->sd);
1114 media_entity_cleanup(&sensor->sd.entity);
1115free_ctrls:
1116 v4l2_ctrl_handler_free(&sensor->ctrls.handler);
1117entity_cleanup:
1118 media_entity_cleanup(&sensor->sd.entity);
1119 mutex_destroy(&sensor->lock);
1120 return ret;
1121}
1122
ed5c2f5f 1123static void ar0521_remove(struct i2c_client *client)
852b50ae
KH		 1124{
1125 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1126 struct ar0521_dev *sensor = to_ar0521_dev(sd);
1127
1128 v4l2_async_unregister_subdev(&sensor->sd);
1129 media_entity_cleanup(&sensor->sd.entity);
1130 v4l2_ctrl_handler_free(&sensor->ctrls.handler);
1131 pm_runtime_disable(&client->dev);
1132 if (!pm_runtime_status_suspended(&client->dev))
1133 ar0521_power_off(&client->dev);
1134 pm_runtime_set_suspended(&client->dev);
1135 mutex_destroy(&sensor->lock);
852b50ae
KH		 1136}
1137
1138static const struct dev_pm_ops ar0521_pm_ops = {
1139 SET_SYSTEM_SLEEP_PM_OPS(ar0521_suspend, ar0521_resume)
1140 SET_RUNTIME_PM_OPS(ar0521_power_off, ar0521_power_on, NULL)
1141};
1142static const struct of_device_id ar0521_dt_ids[] = {
1143 {.compatible = "onnn,ar0521"},
1144 {}
1145};
1146MODULE_DEVICE_TABLE(of, ar0521_dt_ids);
1147
1148static struct i2c_driver ar0521_i2c_driver = {
1149 .driver = {
1150 .name = "ar0521",
1151 .pm = &ar0521_pm_ops,
1152 .of_match_table = ar0521_dt_ids,
1153 },
1154 .probe_new = ar0521_probe,
1155 .remove = ar0521_remove,
1156};
1157
1158module_i2c_driver(ar0521_i2c_driver);
1159
1160MODULE_DESCRIPTION("AR0521 MIPI Camera subdev driver");
1161MODULE_AUTHOR("Krzysztof Hałasa <khalasa@piap.pl>");
1162MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)