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[media] adv7604: use presets where possible
[linux-2.6-block.git] / drivers / media / i2c / adv7604.c
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54450f59
HV		 1/*
2 * adv7604 - Analog Devices ADV7604 video decoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21/*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
28 */
29
30
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/slab.h>
34#include <linux/i2c.h>
35#include <linux/delay.h>
36#include <linux/videodev2.h>
37#include <linux/workqueue.h>
38#include <linux/v4l2-dv-timings.h>
39#include <media/v4l2-device.h>
40#include <media/v4l2-ctrls.h>
41#include <media/v4l2-chip-ident.h>
42#include <media/adv7604.h>
43
44static int debug;
45module_param(debug, int, 0644);
46MODULE_PARM_DESC(debug, "debug level (0-2)");
47
48MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
49MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
50MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
51MODULE_LICENSE("GPL");
52
53/* ADV7604 system clock frequency */
54#define ADV7604_fsc (28636360)
55
6b0d5d34 56#define DIGITAL_INPUT (state->mode == ADV7604_MODE_HDMI)
54450f59
HV		 57
58/*
59 **********************************************************************
60 *
61 * Arrays with configuration parameters for the ADV7604
62 *
63 **********************************************************************
64 */
65struct adv7604_state {
66 struct adv7604_platform_data pdata;
67 struct v4l2_subdev sd;
68 struct media_pad pad;
69 struct v4l2_ctrl_handler hdl;
6b0d5d34 70 enum adv7604_mode mode;
54450f59
HV		 71 struct v4l2_dv_timings timings;
72 u8 edid[256];
73 unsigned edid_blocks;
74 struct v4l2_fract aspect_ratio;
75 u32 rgb_quantization_range;
76 struct workqueue_struct *work_queues;
77 struct delayed_work delayed_work_enable_hotplug;
78 bool connector_hdmi;
79
80 /* i2c clients */
81 struct i2c_client *i2c_avlink;
82 struct i2c_client *i2c_cec;
83 struct i2c_client *i2c_infoframe;
84 struct i2c_client *i2c_esdp;
85 struct i2c_client *i2c_dpp;
86 struct i2c_client *i2c_afe;
87 struct i2c_client *i2c_repeater;
88 struct i2c_client *i2c_edid;
89 struct i2c_client *i2c_hdmi;
90 struct i2c_client *i2c_test;
91 struct i2c_client *i2c_cp;
92 struct i2c_client *i2c_vdp;
93
94 /* controls */
95 struct v4l2_ctrl *detect_tx_5v_ctrl;
96 struct v4l2_ctrl *analog_sampling_phase_ctrl;
97 struct v4l2_ctrl *free_run_color_manual_ctrl;
98 struct v4l2_ctrl *free_run_color_ctrl;
99 struct v4l2_ctrl *rgb_quantization_range_ctrl;
100};
101
102/* Supported CEA and DMT timings */
103static const struct v4l2_dv_timings adv7604_timings[] = {
104 V4L2_DV_BT_CEA_720X480P59_94,
105 V4L2_DV_BT_CEA_720X576P50,
106 V4L2_DV_BT_CEA_1280X720P24,
107 V4L2_DV_BT_CEA_1280X720P25,
54450f59
HV		 108 V4L2_DV_BT_CEA_1280X720P50,
109 V4L2_DV_BT_CEA_1280X720P60,
110 V4L2_DV_BT_CEA_1920X1080P24,
111 V4L2_DV_BT_CEA_1920X1080P25,
112 V4L2_DV_BT_CEA_1920X1080P30,
113 V4L2_DV_BT_CEA_1920X1080P50,
114 V4L2_DV_BT_CEA_1920X1080P60,
115
ccbd5bc4 116 /* sorted by DMT ID */
54450f59
HV		 117 V4L2_DV_BT_DMT_640X350P85,
118 V4L2_DV_BT_DMT_640X400P85,
119 V4L2_DV_BT_DMT_720X400P85,
120 V4L2_DV_BT_DMT_640X480P60,
121 V4L2_DV_BT_DMT_640X480P72,
122 V4L2_DV_BT_DMT_640X480P75,
123 V4L2_DV_BT_DMT_640X480P85,
124 V4L2_DV_BT_DMT_800X600P56,
125 V4L2_DV_BT_DMT_800X600P60,
126 V4L2_DV_BT_DMT_800X600P72,
127 V4L2_DV_BT_DMT_800X600P75,
128 V4L2_DV_BT_DMT_800X600P85,
129 V4L2_DV_BT_DMT_848X480P60,
130 V4L2_DV_BT_DMT_1024X768P60,
131 V4L2_DV_BT_DMT_1024X768P70,
132 V4L2_DV_BT_DMT_1024X768P75,
133 V4L2_DV_BT_DMT_1024X768P85,
134 V4L2_DV_BT_DMT_1152X864P75,
135 V4L2_DV_BT_DMT_1280X768P60_RB,
136 V4L2_DV_BT_DMT_1280X768P60,
137 V4L2_DV_BT_DMT_1280X768P75,
138 V4L2_DV_BT_DMT_1280X768P85,
139 V4L2_DV_BT_DMT_1280X800P60_RB,
140 V4L2_DV_BT_DMT_1280X800P60,
141 V4L2_DV_BT_DMT_1280X800P75,
142 V4L2_DV_BT_DMT_1280X800P85,
143 V4L2_DV_BT_DMT_1280X960P60,
144 V4L2_DV_BT_DMT_1280X960P85,
145 V4L2_DV_BT_DMT_1280X1024P60,
146 V4L2_DV_BT_DMT_1280X1024P75,
147 V4L2_DV_BT_DMT_1280X1024P85,
148 V4L2_DV_BT_DMT_1360X768P60,
149 V4L2_DV_BT_DMT_1400X1050P60_RB,
150 V4L2_DV_BT_DMT_1400X1050P60,
151 V4L2_DV_BT_DMT_1400X1050P75,
152 V4L2_DV_BT_DMT_1400X1050P85,
153 V4L2_DV_BT_DMT_1440X900P60_RB,
154 V4L2_DV_BT_DMT_1440X900P60,
155 V4L2_DV_BT_DMT_1600X1200P60,
156 V4L2_DV_BT_DMT_1680X1050P60_RB,
157 V4L2_DV_BT_DMT_1680X1050P60,
158 V4L2_DV_BT_DMT_1792X1344P60,
159 V4L2_DV_BT_DMT_1856X1392P60,
160 V4L2_DV_BT_DMT_1920X1200P60_RB,
161 V4L2_DV_BT_DMT_1366X768P60,
162 V4L2_DV_BT_DMT_1920X1080P60,
163 { },
164};
165
ccbd5bc4
HV		 166struct adv7604_video_standards {
167 struct v4l2_dv_timings timings;
168 u8 vid_std;
169 u8 v_freq;
170};
171
172/* sorted by number of lines */
173static const struct adv7604_video_standards adv7604_prim_mode_comp[] = {
174 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
175 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
176 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
177 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
178 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
179 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
180 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
181 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
182 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
183 /* TODO add 1920x1080P60_RB (CVT timing) */
184 { },
185};
186
187/* sorted by number of lines */
188static const struct adv7604_video_standards adv7604_prim_mode_gr[] = {
189 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
190 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
191 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
192 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
193 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
194 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
195 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
196 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
197 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
198 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
199 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
200 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
201 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
202 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
203 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
204 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
205 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
206 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
207 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
208 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
209 /* TODO add 1600X1200P60_RB (not a DMT timing) */
210 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
211 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
212 { },
213};
214
215/* sorted by number of lines */
216static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = {
217 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
218 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
219 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
220 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
221 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
222 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
223 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
224 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
225 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
226 { },
227};
228
229/* sorted by number of lines */
230static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = {
231 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
232 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
233 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
234 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
235 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
236 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
237 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
238 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
239 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
240 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
241 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
242 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
243 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
244 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
245 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
246 { },
247};
248
54450f59
HV		 249/* ----------------------------------------------------------------------- */
250
251static inline struct adv7604_state *to_state(struct v4l2_subdev *sd)
252{
253 return container_of(sd, struct adv7604_state, sd);
254}
255
256static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
257{
258 return &container_of(ctrl->handler, struct adv7604_state, hdl)->sd;
259}
260
261static inline unsigned hblanking(const struct v4l2_bt_timings *t)
262{
263 return t->hfrontporch + t->hsync + t->hbackporch;
264}
265
266static inline unsigned htotal(const struct v4l2_bt_timings *t)
267{
268 return t->width + t->hfrontporch + t->hsync + t->hbackporch;
269}
270
271static inline unsigned vblanking(const struct v4l2_bt_timings *t)
272{
273 return t->vfrontporch + t->vsync + t->vbackporch;
274}
275
276static inline unsigned vtotal(const struct v4l2_bt_timings *t)
277{
278 return t->height + t->vfrontporch + t->vsync + t->vbackporch;
279}
280
281/* ----------------------------------------------------------------------- */
282
283static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
284 u8 command, bool check)
285{
286 union i2c_smbus_data data;
287
288 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
289 I2C_SMBUS_READ, command,
290 I2C_SMBUS_BYTE_DATA, &data))
291 return data.byte;
292 if (check)
293 v4l_err(client, "error reading %02x, %02x\n",
294 client->addr, command);
295 return -EIO;
296}
297
298static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
299{
300 return adv_smbus_read_byte_data_check(client, command, true);
301}
302
303static s32 adv_smbus_write_byte_data(struct i2c_client *client,
304 u8 command, u8 value)
305{
306 union i2c_smbus_data data;
307 int err;
308 int i;
309
310 data.byte = value;
311 for (i = 0; i < 3; i++) {
312 err = i2c_smbus_xfer(client->adapter, client->addr,
313 client->flags,
314 I2C_SMBUS_WRITE, command,
315 I2C_SMBUS_BYTE_DATA, &data);
316 if (!err)
317 break;
318 }
319 if (err < 0)
320 v4l_err(client, "error writing %02x, %02x, %02x\n",
321 client->addr, command, value);
322 return err;
323}
324
325static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
326 u8 command, unsigned length, const u8 *values)
327{
328 union i2c_smbus_data data;
329
330 if (length > I2C_SMBUS_BLOCK_MAX)
331 length = I2C_SMBUS_BLOCK_MAX;
332 data.block[0] = length;
333 memcpy(data.block + 1, values, length);
334 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
335 I2C_SMBUS_WRITE, command,
336 I2C_SMBUS_I2C_BLOCK_DATA, &data);
337}
338
339/* ----------------------------------------------------------------------- */
340
341static inline int io_read(struct v4l2_subdev *sd, u8 reg)
342{
343 struct i2c_client *client = v4l2_get_subdevdata(sd);
344
345 return adv_smbus_read_byte_data(client, reg);
346}
347
348static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
349{
350 struct i2c_client *client = v4l2_get_subdevdata(sd);
351
352 return adv_smbus_write_byte_data(client, reg, val);
353}
354
355static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
356{
357 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
358}
359
360static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
361{
362 struct adv7604_state *state = to_state(sd);
363
364 return adv_smbus_read_byte_data(state->i2c_avlink, reg);
365}
366
367static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
368{
369 struct adv7604_state *state = to_state(sd);
370
371 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
372}
373
374static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
375{
376 struct adv7604_state *state = to_state(sd);
377
378 return adv_smbus_read_byte_data(state->i2c_cec, reg);
379}
380
381static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
382{
383 struct adv7604_state *state = to_state(sd);
384
385 return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
386}
387
388static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
389{
390 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
391}
392
393static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
394{
395 struct adv7604_state *state = to_state(sd);
396
397 return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
398}
399
400static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
401{
402 struct adv7604_state *state = to_state(sd);
403
404 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
405}
406
407static inline int esdp_read(struct v4l2_subdev *sd, u8 reg)
408{
409 struct adv7604_state *state = to_state(sd);
410
411 return adv_smbus_read_byte_data(state->i2c_esdp, reg);
412}
413
414static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
415{
416 struct adv7604_state *state = to_state(sd);
417
418 return adv_smbus_write_byte_data(state->i2c_esdp, reg, val);
419}
420
421static inline int dpp_read(struct v4l2_subdev *sd, u8 reg)
422{
423 struct adv7604_state *state = to_state(sd);
424
425 return adv_smbus_read_byte_data(state->i2c_dpp, reg);
426}
427
428static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
429{
430 struct adv7604_state *state = to_state(sd);
431
432 return adv_smbus_write_byte_data(state->i2c_dpp, reg, val);
433}
434
435static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
436{
437 struct adv7604_state *state = to_state(sd);
438
439 return adv_smbus_read_byte_data(state->i2c_afe, reg);
440}
441
442static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
443{
444 struct adv7604_state *state = to_state(sd);
445
446 return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
447}
448
449static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
450{
451 struct adv7604_state *state = to_state(sd);
452
453 return adv_smbus_read_byte_data(state->i2c_repeater, reg);
454}
455
456static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
457{
458 struct adv7604_state *state = to_state(sd);
459
460 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
461}
462
463static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
464{
465 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
466}
467
468static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
469{
470 struct adv7604_state *state = to_state(sd);
471
472 return adv_smbus_read_byte_data(state->i2c_edid, reg);
473}
474
475static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
476{
477 struct adv7604_state *state = to_state(sd);
478
479 return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
480}
481
482static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val)
483{
484 struct adv7604_state *state = to_state(sd);
485 struct i2c_client *client = state->i2c_edid;
486 u8 msgbuf0[1] = { 0 };
487 u8 msgbuf1[256];
488 struct i2c_msg msg[2] = { { client->addr, 0, 1, msgbuf0 },
489 { client->addr, 0 | I2C_M_RD, len, msgbuf1 }
490 };
491
492 if (i2c_transfer(client->adapter, msg, 2) < 0)
493 return -EIO;
494 memcpy(val, msgbuf1, len);
495 return 0;
496}
497
498static void adv7604_delayed_work_enable_hotplug(struct work_struct *work)
499{
500 struct delayed_work *dwork = to_delayed_work(work);
501 struct adv7604_state *state = container_of(dwork, struct adv7604_state,
502 delayed_work_enable_hotplug);
503 struct v4l2_subdev *sd = &state->sd;
504
505 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
506
507 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)1);
508}
509
510static inline int edid_write_block(struct v4l2_subdev *sd,
511 unsigned len, const u8 *val)
512{
513 struct i2c_client *client = v4l2_get_subdevdata(sd);
514 struct adv7604_state *state = to_state(sd);
515 int err = 0;
516 int i;
517
518 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
519
520 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)0);
521
522 /* Disables I2C access to internal EDID ram from DDC port */
523 rep_write_and_or(sd, 0x77, 0xf0, 0x0);
524
525 for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
526 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
527 I2C_SMBUS_BLOCK_MAX, val + i);
528 if (err)
529 return err;
530
531 /* adv7604 calculates the checksums and enables I2C access to internal
532 EDID ram from DDC port. */
533 rep_write_and_or(sd, 0x77, 0xf0, 0x1);
534
535 for (i = 0; i < 1000; i++) {
536 if (rep_read(sd, 0x7d) & 1)
537 break;
538 mdelay(1);
539 }
540 if (i == 1000) {
541 v4l_err(client, "error enabling edid\n");
542 return -EIO;
543 }
544
545 /* enable hotplug after 100 ms */
546 queue_delayed_work(state->work_queues,
547 &state->delayed_work_enable_hotplug, HZ / 10);
548 return 0;
549}
550
551static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
552{
553 struct adv7604_state *state = to_state(sd);
554
555 return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
556}
557
558static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
559{
560 struct adv7604_state *state = to_state(sd);
561
562 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
563}
564
565static inline int test_read(struct v4l2_subdev *sd, u8 reg)
566{
567 struct adv7604_state *state = to_state(sd);
568
569 return adv_smbus_read_byte_data(state->i2c_test, reg);
570}
571
572static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
573{
574 struct adv7604_state *state = to_state(sd);
575
576 return adv_smbus_write_byte_data(state->i2c_test, reg, val);
577}
578
579static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
580{
581 struct adv7604_state *state = to_state(sd);
582
583 return adv_smbus_read_byte_data(state->i2c_cp, reg);
584}
585
586static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
587{
588 struct adv7604_state *state = to_state(sd);
589
590 return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
591}
592
593static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
594{
595 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
596}
597
598static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
599{
600 struct adv7604_state *state = to_state(sd);
601
602 return adv_smbus_read_byte_data(state->i2c_vdp, reg);
603}
604
605static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
606{
607 struct adv7604_state *state = to_state(sd);
608
609 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
610}
611
612/* ----------------------------------------------------------------------- */
613
614#ifdef CONFIG_VIDEO_ADV_DEBUG
615static void adv7604_inv_register(struct v4l2_subdev *sd)
616{
617 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
618 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
619 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
620 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
621 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
622 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
623 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
624 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
625 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
626 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
627 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
628 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
629 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
630}
631
632static int adv7604_g_register(struct v4l2_subdev *sd,
633 struct v4l2_dbg_register *reg)
634{
635 struct i2c_client *client = v4l2_get_subdevdata(sd);
636
637 if (!v4l2_chip_match_i2c_client(client, &reg->match))
638 return -EINVAL;
639 if (!capable(CAP_SYS_ADMIN))
640 return -EPERM;
641 reg->size = 1;
642 switch (reg->reg >> 8) {
643 case 0:
644 reg->val = io_read(sd, reg->reg & 0xff);
645 break;
646 case 1:
647 reg->val = avlink_read(sd, reg->reg & 0xff);
648 break;
649 case 2:
650 reg->val = cec_read(sd, reg->reg & 0xff);
651 break;
652 case 3:
653 reg->val = infoframe_read(sd, reg->reg & 0xff);
654 break;
655 case 4:
656 reg->val = esdp_read(sd, reg->reg & 0xff);
657 break;
658 case 5:
659 reg->val = dpp_read(sd, reg->reg & 0xff);
660 break;
661 case 6:
662 reg->val = afe_read(sd, reg->reg & 0xff);
663 break;
664 case 7:
665 reg->val = rep_read(sd, reg->reg & 0xff);
666 break;
667 case 8:
668 reg->val = edid_read(sd, reg->reg & 0xff);
669 break;
670 case 9:
671 reg->val = hdmi_read(sd, reg->reg & 0xff);
672 break;
673 case 0xa:
674 reg->val = test_read(sd, reg->reg & 0xff);
675 break;
676 case 0xb:
677 reg->val = cp_read(sd, reg->reg & 0xff);
678 break;
679 case 0xc:
680 reg->val = vdp_read(sd, reg->reg & 0xff);
681 break;
682 default:
683 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
684 adv7604_inv_register(sd);
685 break;
686 }
687 return 0;
688}
689
690static int adv7604_s_register(struct v4l2_subdev *sd,
691 struct v4l2_dbg_register *reg)
692{
693 struct i2c_client *client = v4l2_get_subdevdata(sd);
694
695 if (!v4l2_chip_match_i2c_client(client, &reg->match))
696 return -EINVAL;
697 if (!capable(CAP_SYS_ADMIN))
698 return -EPERM;
699 switch (reg->reg >> 8) {
700 case 0:
701 io_write(sd, reg->reg & 0xff, reg->val & 0xff);
702 break;
703 case 1:
704 avlink_write(sd, reg->reg & 0xff, reg->val & 0xff);
705 break;
706 case 2:
707 cec_write(sd, reg->reg & 0xff, reg->val & 0xff);
708 break;
709 case 3:
710 infoframe_write(sd, reg->reg & 0xff, reg->val & 0xff);
711 break;
712 case 4:
713 esdp_write(sd, reg->reg & 0xff, reg->val & 0xff);
714 break;
715 case 5:
716 dpp_write(sd, reg->reg & 0xff, reg->val & 0xff);
717 break;
718 case 6:
719 afe_write(sd, reg->reg & 0xff, reg->val & 0xff);
720 break;
721 case 7:
722 rep_write(sd, reg->reg & 0xff, reg->val & 0xff);
723 break;
724 case 8:
725 edid_write(sd, reg->reg & 0xff, reg->val & 0xff);
726 break;
727 case 9:
728 hdmi_write(sd, reg->reg & 0xff, reg->val & 0xff);
729 break;
730 case 0xa:
731 test_write(sd, reg->reg & 0xff, reg->val & 0xff);
732 break;
733 case 0xb:
734 cp_write(sd, reg->reg & 0xff, reg->val & 0xff);
735 break;
736 case 0xc:
737 vdp_write(sd, reg->reg & 0xff, reg->val & 0xff);
738 break;
739 default:
740 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
741 adv7604_inv_register(sd);
742 break;
743 }
744 return 0;
745}
746#endif
747
748static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
749{
750 struct adv7604_state *state = to_state(sd);
751
752 /* port A only */
753 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
754 ((io_read(sd, 0x6f) & 0x10) >> 4));
755}
756
ccbd5bc4
HV		 757static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
758 u8 prim_mode,
759 const struct adv7604_video_standards *predef_vid_timings,
760 const struct v4l2_dv_timings *timings)
761{
762 struct adv7604_state *state = to_state(sd);
763 int i;
764
765 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
766 if (!v4l_match_dv_timings(timings, &predef_vid_timings[i].timings,
767 DIGITAL_INPUT ? 250000 : 1000000))
768 continue;
769 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
770 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
771 prim_mode); /* v_freq and prim mode */
772 return 0;
773 }
774
775 return -1;
776}
777
778static int configure_predefined_video_timings(struct v4l2_subdev *sd,
779 struct v4l2_dv_timings *timings)
54450f59 780{
ccbd5bc4
HV		 781 struct adv7604_state *state = to_state(sd);
782 int err;
783
784 v4l2_dbg(1, debug, sd, "%s", __func__);
785
786 /* reset to default values */
787 io_write(sd, 0x16, 0x43);
788 io_write(sd, 0x17, 0x5a);
789 /* disable embedded syncs for auto graphics mode */
790 cp_write_and_or(sd, 0x81, 0xef, 0x00);
791 cp_write(sd, 0x8f, 0x00);
792 cp_write(sd, 0x90, 0x00);
793 cp_write(sd, 0xa2, 0x00);
794 cp_write(sd, 0xa3, 0x00);
795 cp_write(sd, 0xa4, 0x00);
796 cp_write(sd, 0xa5, 0x00);
797 cp_write(sd, 0xa6, 0x00);
798 cp_write(sd, 0xa7, 0x00);
799 cp_write(sd, 0xab, 0x00);
800 cp_write(sd, 0xac, 0x00);
801
802 switch (state->mode) {
803 case ADV7604_MODE_COMP:
804 case ADV7604_MODE_GR:
805 err = find_and_set_predefined_video_timings(sd,
806 0x01, adv7604_prim_mode_comp, timings);
807 if (err)
808 err = find_and_set_predefined_video_timings(sd,
809 0x02, adv7604_prim_mode_gr, timings);
810 break;
811 case ADV7604_MODE_HDMI:
812 err = find_and_set_predefined_video_timings(sd,
813 0x05, adv7604_prim_mode_hdmi_comp, timings);
814 if (err)
815 err = find_and_set_predefined_video_timings(sd,
816 0x06, adv7604_prim_mode_hdmi_gr, timings);
817 break;
818 default:
819 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
820 __func__, state->mode);
821 err = -1;
822 break;
823 }
824
825
826 return err;
827}
828
829static void configure_custom_video_timings(struct v4l2_subdev *sd,
830 const struct v4l2_bt_timings *bt)
831{
832 struct adv7604_state *state = to_state(sd);
54450f59 833 struct i2c_client *client = v4l2_get_subdevdata(sd);
ccbd5bc4
HV		 834 u32 width = htotal(bt);
835 u32 height = vtotal(bt);
836 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
837 u16 cp_start_eav = width - bt->hfrontporch;
838 u16 cp_start_vbi = height - bt->vfrontporch;
839 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
840 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
841 ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
842 const u8 pll[2] = {
843 0xc0 | ((width >> 8) & 0x1f),
844 width & 0xff
845 };
54450f59
HV		 846
847 v4l2_dbg(2, debug, sd, "%s\n", __func__);
848
ccbd5bc4
HV		 849 switch (state->mode) {
850 case ADV7604_MODE_COMP:
851 case ADV7604_MODE_GR:
852 /* auto graphics */
853 io_write(sd, 0x00, 0x07); /* video std */
854 io_write(sd, 0x01, 0x02); /* prim mode */
855 /* enable embedded syncs for auto graphics mode */
856 cp_write_and_or(sd, 0x81, 0xef, 0x10);
54450f59 857
ccbd5bc4 858 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
54450f59
HV		 859 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
860 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
861 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
862 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
ccbd5bc4 863 break;
54450f59
HV		 864 }
865
866 /* active video - horizontal timing */
54450f59 867 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
ccbd5bc4
HV		 868 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
869 ((cp_start_eav >> 8) & 0x0f));
54450f59
HV		 870 cp_write(sd, 0xa4, cp_start_eav & 0xff);
871
872 /* active video - vertical timing */
54450f59 873 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
ccbd5bc4
HV		 874 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
875 ((cp_end_vbi >> 8) & 0xf));
54450f59 876 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
ccbd5bc4
HV		 877 break;
878 case ADV7604_MODE_HDMI:
879 /* set default prim_mode/vid_std for HDMI
880 accoring to [REF_03, c. 4.2] */
881 io_write(sd, 0x00, 0x02); /* video std */
882 io_write(sd, 0x01, 0x06); /* prim mode */
883 break;
884 default:
885 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
886 __func__, state->mode);
887 break;
54450f59 888 }
54450f59 889
ccbd5bc4
HV		 890 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
891 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
892 cp_write(sd, 0xab, (height >> 4) & 0xff);
893 cp_write(sd, 0xac, (height & 0x0f) << 4);
894}
54450f59
HV		 895
896static void set_rgb_quantization_range(struct v4l2_subdev *sd)
897{
898 struct adv7604_state *state = to_state(sd);
899
900 switch (state->rgb_quantization_range) {
901 case V4L2_DV_RGB_RANGE_AUTO:
902 /* automatic */
6b0d5d34 903 if (DIGITAL_INPUT && !(hdmi_read(sd, 0x05) & 0x80)) {
54450f59
HV		 904 /* receiving DVI-D signal */
905
906 /* ADV7604 selects RGB limited range regardless of
907 input format (CE/IT) in automatic mode */
908 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
909 /* RGB limited range (16-235) */
910 io_write_and_or(sd, 0x02, 0x0f, 0x00);
911
912 } else {
913 /* RGB full range (0-255) */
914 io_write_and_or(sd, 0x02, 0x0f, 0x10);
915 }
6b0d5d34
HV		 916 } else {
917 /* receiving HDMI or analog signal, set automode */
918 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
54450f59
HV		 919 }
920 break;
921 case V4L2_DV_RGB_RANGE_LIMITED:
922 /* RGB limited range (16-235) */
923 io_write_and_or(sd, 0x02, 0x0f, 0x00);
924 break;
925 case V4L2_DV_RGB_RANGE_FULL:
926 /* RGB full range (0-255) */
927 io_write_and_or(sd, 0x02, 0x0f, 0x10);
928 break;
929 }
930}
931
932
933static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl)
934{
935 struct v4l2_subdev *sd = to_sd(ctrl);
936 struct adv7604_state *state = to_state(sd);
937
938 switch (ctrl->id) {
939 case V4L2_CID_BRIGHTNESS:
940 cp_write(sd, 0x3c, ctrl->val);
941 return 0;
942 case V4L2_CID_CONTRAST:
943 cp_write(sd, 0x3a, ctrl->val);
944 return 0;
945 case V4L2_CID_SATURATION:
946 cp_write(sd, 0x3b, ctrl->val);
947 return 0;
948 case V4L2_CID_HUE:
949 cp_write(sd, 0x3d, ctrl->val);
950 return 0;
951 case V4L2_CID_DV_RX_RGB_RANGE:
952 state->rgb_quantization_range = ctrl->val;
953 set_rgb_quantization_range(sd);
954 return 0;
955 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
956 /* Set the analog sampling phase. This is needed to find the
957 best sampling phase for analog video: an application or
958 driver has to try a number of phases and analyze the picture
959 quality before settling on the best performing phase. */
960 afe_write(sd, 0xc8, ctrl->val);
961 return 0;
962 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
963 /* Use the default blue color for free running mode,
964 or supply your own. */
965 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
966 return 0;
967 case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
968 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
969 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
970 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
971 return 0;
972 }
973 return -EINVAL;
974}
975
976static int adv7604_g_chip_ident(struct v4l2_subdev *sd,
977 struct v4l2_dbg_chip_ident *chip)
978{
979 struct i2c_client *client = v4l2_get_subdevdata(sd);
980
981 return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_ADV7604, 0);
982}
983
984/* ----------------------------------------------------------------------- */
985
986static inline bool no_power(struct v4l2_subdev *sd)
987{
988 /* Entire chip or CP powered off */
989 return io_read(sd, 0x0c) & 0x24;
990}
991
992static inline bool no_signal_tmds(struct v4l2_subdev *sd)
993{
994 /* TODO port B, C and D */
995 return !(io_read(sd, 0x6a) & 0x10);
996}
997
998static inline bool no_lock_tmds(struct v4l2_subdev *sd)
999{
1000 return (io_read(sd, 0x6a) & 0xe0) != 0xe0;
1001}
1002
1003static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1004{
1005 /* TODO channel 2 */
1006 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1007}
1008
1009static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1010{
1011 /* TODO channel 2 */
1012 return !(cp_read(sd, 0xb1) & 0x80);
1013}
1014
1015static inline bool no_signal(struct v4l2_subdev *sd)
1016{
1017 struct adv7604_state *state = to_state(sd);
1018 bool ret;
1019
1020 ret = no_power(sd);
1021
1022 ret |= no_lock_stdi(sd);
1023 ret |= no_lock_sspd(sd);
1024
1025 if (DIGITAL_INPUT) {
1026 ret |= no_lock_tmds(sd);
1027 ret |= no_signal_tmds(sd);
1028 }
1029
1030 return ret;
1031}
1032
1033static inline bool no_lock_cp(struct v4l2_subdev *sd)
1034{
1035 /* CP has detected a non standard number of lines on the incoming
1036 video compared to what it is configured to receive by s_dv_timings */
1037 return io_read(sd, 0x12) & 0x01;
1038}
1039
1040static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status)
1041{
1042 struct adv7604_state *state = to_state(sd);
1043
1044 *status = 0;
1045 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1046 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1047 if (no_lock_cp(sd))
1048 *status |= DIGITAL_INPUT ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1049
1050 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1051
1052 return 0;
1053}
1054
1055/* ----------------------------------------------------------------------- */
1056
1057static void adv7604_print_timings(struct v4l2_subdev *sd,
1058 struct v4l2_dv_timings *timings, const char *txt, bool detailed)
1059{
1060 struct v4l2_bt_timings *bt = &timings->bt;
1061 u32 htot, vtot;
1062
1063 if (timings->type != V4L2_DV_BT_656_1120)
1064 return;
1065
1066 htot = htotal(bt);
1067 vtot = vtotal(bt);
1068
1069 v4l2_info(sd, "%s %dx%d%s%d (%dx%d)",
1070 txt, bt->width, bt->height, bt->interlaced ? "i" : "p",
1071 (htot * vtot) > 0 ? ((u32)bt->pixelclock /
1072 (htot * vtot)) : 0,
1073 htot, vtot);
1074
1075 if (detailed) {
1076 v4l2_info(sd, " horizontal: fp = %d, %ssync = %d, bp = %d\n",
1077 bt->hfrontporch,
1078 (bt->polarities & V4L2_DV_HSYNC_POS_POL) ? "+" : "-",
1079 bt->hsync, bt->hbackporch);
1080 v4l2_info(sd, " vertical: fp = %d, %ssync = %d, bp = %d\n",
1081 bt->vfrontporch,
1082 (bt->polarities & V4L2_DV_VSYNC_POS_POL) ? "+" : "-",
1083 bt->vsync, bt->vbackporch);
1084 v4l2_info(sd, " pixelclock: %lld, flags: 0x%x, standards: 0x%x\n",
1085 bt->pixelclock, bt->flags, bt->standards);
1086 }
1087}
1088
1089struct stdi_readback {
1090 u16 bl, lcf, lcvs;
1091 u8 hs_pol, vs_pol;
1092 bool interlaced;
1093};
1094
1095static int stdi2dv_timings(struct v4l2_subdev *sd,
1096 struct stdi_readback *stdi,
1097 struct v4l2_dv_timings *timings)
1098{
1099 struct adv7604_state *state = to_state(sd);
1100 u32 hfreq = (ADV7604_fsc * 8) / stdi->bl;
1101 u32 pix_clk;
1102 int i;
1103
1104 for (i = 0; adv7604_timings[i].bt.height; i++) {
1105 if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1)
1106 continue;
1107 if (adv7604_timings[i].bt.vsync != stdi->lcvs)
1108 continue;
1109
1110 pix_clk = hfreq * htotal(&adv7604_timings[i].bt);
1111
1112 if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) &&
1113 (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) {
1114 *timings = adv7604_timings[i];
1115 return 0;
1116 }
1117 }
1118
1119 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1120 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1121 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1122 timings))
1123 return 0;
1124 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1125 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1126 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1127 state->aspect_ratio, timings))
1128 return 0;
1129
ccbd5bc4
HV		 1130 v4l2_dbg(2, debug, sd,
1131 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1132 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1133 stdi->hs_pol, stdi->vs_pol);
54450f59
HV		 1134 return -1;
1135}
1136
1137static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1138{
1139 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1140 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1141 return -1;
1142 }
1143
1144 /* read STDI */
1145 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1146 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1147 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1148 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1149
1150 /* read SSPD */
1151 if ((cp_read(sd, 0xb5) & 0x03) == 0x01) {
1152 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1153 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1154 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1155 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1156 } else {
1157 stdi->hs_pol = 'x';
1158 stdi->vs_pol = 'x';
1159 }
1160
1161 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1162 v4l2_dbg(2, debug, sd,
1163 "%s: signal lost during readout of STDI/SSPD\n", __func__);
1164 return -1;
1165 }
1166
1167 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1168 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1169 memset(stdi, 0, sizeof(struct stdi_readback));
1170 return -1;
1171 }
1172
1173 v4l2_dbg(2, debug, sd,
1174 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1175 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1176 stdi->hs_pol, stdi->vs_pol,
1177 stdi->interlaced ? "interlaced" : "progressive");
1178
1179 return 0;
1180}
1181
1182static int adv7604_enum_dv_timings(struct v4l2_subdev *sd,
1183 struct v4l2_enum_dv_timings *timings)
1184{
1185 if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1)
1186 return -EINVAL;
1187 memset(timings->reserved, 0, sizeof(timings->reserved));
1188 timings->timings = adv7604_timings[timings->index];
1189 return 0;
1190}
1191
1192static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
1193 struct v4l2_dv_timings_cap *cap)
1194{
1195 struct adv7604_state *state = to_state(sd);
1196
1197 cap->type = V4L2_DV_BT_656_1120;
1198 cap->bt.max_width = 1920;
1199 cap->bt.max_height = 1200;
1200 cap->bt.min_pixelclock = 27000000;
1201 if (DIGITAL_INPUT)
1202 cap->bt.max_pixelclock = 225000000;
1203 else
1204 cap->bt.max_pixelclock = 170000000;
1205 cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1206 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1207 cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1208 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1209 return 0;
1210}
1211
1212/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1213 if the format is listed in adv7604_timings[] */
1214static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1215 struct v4l2_dv_timings *timings)
1216{
1217 struct adv7604_state *state = to_state(sd);
1218 int i;
1219
1220 for (i = 0; adv7604_timings[i].bt.width; i++) {
1221 if (v4l_match_dv_timings(timings, &adv7604_timings[i],
1222 DIGITAL_INPUT ? 250000 : 1000000)) {
1223 *timings = adv7604_timings[i];
1224 break;
1225 }
1226 }
1227}
1228
1229static int adv7604_query_dv_timings(struct v4l2_subdev *sd,
1230 struct v4l2_dv_timings *timings)
1231{
1232 struct adv7604_state *state = to_state(sd);
1233 struct v4l2_bt_timings *bt = &timings->bt;
1234 struct stdi_readback stdi;
1235
1236 if (!timings)
1237 return -EINVAL;
1238
1239 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1240
1241 if (no_signal(sd)) {
1242 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1243 return -ENOLINK;
1244 }
1245
1246 /* read STDI */
1247 if (read_stdi(sd, &stdi)) {
1248 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1249 return -ENOLINK;
1250 }
1251 bt->interlaced = stdi.interlaced ?
1252 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1253
1254 if (DIGITAL_INPUT) {
1255 timings->type = V4L2_DV_BT_656_1120;
1256
1257 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1258 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1259 bt->pixelclock = (hdmi_read(sd, 0x06) * 1000000) +
1260 ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000;
1261 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1262 hdmi_read(sd, 0x21);
1263 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1264 hdmi_read(sd, 0x23);
1265 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1266 hdmi_read(sd, 0x25);
1267 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1268 hdmi_read(sd, 0x2b)) / 2;
1269 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1270 hdmi_read(sd, 0x2f)) / 2;
1271 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1272 hdmi_read(sd, 0x33)) / 2;
1273 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1274 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1275 if (bt->interlaced == V4L2_DV_INTERLACED) {
1276 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1277 hdmi_read(sd, 0x0c);
1278 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1279 hdmi_read(sd, 0x2d)) / 2;
1280 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1281 hdmi_read(sd, 0x31)) / 2;
1282 bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1283 hdmi_read(sd, 0x35)) / 2;
1284 }
1285 adv7604_fill_optional_dv_timings_fields(sd, timings);
1286 } else {
1287 /* find format
80939647 1288 * Since LCVS values are inaccurate [REF_03, p. 275-276],
54450f59
HV		 1289 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1290 */
1291 if (!stdi2dv_timings(sd, &stdi, timings))
1292 goto found;
1293 stdi.lcvs += 1;
1294 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1295 if (!stdi2dv_timings(sd, &stdi, timings))
1296 goto found;
1297 stdi.lcvs -= 2;
1298 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1299 if (stdi2dv_timings(sd, &stdi, timings)) {
1300 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1301 return -ERANGE;
1302 }
1303 }
1304found:
1305
1306 if (no_signal(sd)) {
1307 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1308 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1309 return -ENOLINK;
1310 }
1311
1312 if ((!DIGITAL_INPUT && bt->pixelclock > 170000000) ||
1313 (DIGITAL_INPUT && bt->pixelclock > 225000000)) {
1314 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1315 __func__, (u32)bt->pixelclock);
1316 return -ERANGE;
1317 }
1318
1319 if (debug > 1)
1320 adv7604_print_timings(sd, timings,
1321 "adv7604_query_dv_timings:", true);
1322
1323 return 0;
1324}
1325
1326static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
1327 struct v4l2_dv_timings *timings)
1328{
1329 struct adv7604_state *state = to_state(sd);
1330 struct v4l2_bt_timings *bt;
ccbd5bc4 1331 int err;
54450f59
HV		 1332
1333 if (!timings)
1334 return -EINVAL;
1335
1336 bt = &timings->bt;
1337
1338 if ((!DIGITAL_INPUT && bt->pixelclock > 170000000) ||
1339 (DIGITAL_INPUT && bt->pixelclock > 225000000)) {
1340 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1341 __func__, (u32)bt->pixelclock);
1342 return -ERANGE;
1343 }
ccbd5bc4 1344
54450f59
HV		 1345 adv7604_fill_optional_dv_timings_fields(sd, timings);
1346
1347 state->timings = *timings;
1348
ccbd5bc4
HV		 1349 cp_write(sd, 0x91, bt->interlaced ? 0x50 : 0x10);
1350
1351 /* Use prim_mode and vid_std when available */
1352 err = configure_predefined_video_timings(sd, timings);
1353 if (err) {
1354 /* custom settings when the video format
1355 does not have prim_mode/vid_std */
1356 configure_custom_video_timings(sd, bt);
1357 }
54450f59
HV		 1358
1359 set_rgb_quantization_range(sd);
1360
1361
1362 if (debug > 1)
1363 adv7604_print_timings(sd, timings,
1364 "adv7604_s_dv_timings:", true);
1365 return 0;
1366}
1367
1368static int adv7604_g_dv_timings(struct v4l2_subdev *sd,
1369 struct v4l2_dv_timings *timings)
1370{
1371 struct adv7604_state *state = to_state(sd);
1372
1373 *timings = state->timings;
1374 return 0;
1375}
1376
6b0d5d34 1377static void enable_input(struct v4l2_subdev *sd)
54450f59 1378{
6b0d5d34
HV		 1379 struct adv7604_state *state = to_state(sd);
1380
1381 switch (state->mode) {
1382 case ADV7604_MODE_COMP:
1383 case ADV7604_MODE_GR:
54450f59
HV		 1384 /* enable */
1385 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1386 break;
6b0d5d34 1387 case ADV7604_MODE_HDMI:
54450f59
HV		 1388 /* enable */
1389 hdmi_write(sd, 0x1a, 0x0a); /* Unmute audio */
1390 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1391 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
1392 break;
1393 default:
6b0d5d34
HV		 1394 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1395 __func__, state->mode);
54450f59
HV		 1396 break;
1397 }
1398}
1399
1400static void disable_input(struct v4l2_subdev *sd)
1401{
1402 /* disable */
1403 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
1404 hdmi_write(sd, 0x1a, 0x1a); /* Mute audio */
1405 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1406}
1407
6b0d5d34 1408static void select_input(struct v4l2_subdev *sd)
54450f59 1409{
6b0d5d34
HV		 1410 struct adv7604_state *state = to_state(sd);
1411
1412 switch (state->mode) {
1413 case ADV7604_MODE_COMP:
1414 case ADV7604_MODE_GR:
54450f59
HV		 1415 /* reset ADI recommended settings for HDMI: */
1416 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1417 hdmi_write(sd, 0x0d, 0x04); /* HDMI filter optimization */
1418 hdmi_write(sd, 0x3d, 0x00); /* DDC bus active pull-up control */
1419 hdmi_write(sd, 0x3e, 0x74); /* TMDS PLL optimization */
1420 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1421 hdmi_write(sd, 0x57, 0x74); /* TMDS PLL optimization */
1422 hdmi_write(sd, 0x58, 0x63); /* TMDS PLL optimization */
1423 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1424 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1425 hdmi_write(sd, 0x93, 0x88); /* equaliser */
1426 hdmi_write(sd, 0x94, 0x2e); /* equaliser */
1427 hdmi_write(sd, 0x96, 0x00); /* enable automatic EQ changing */
1428
1429 afe_write(sd, 0x00, 0x08); /* power up ADC */
1430 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1431 afe_write(sd, 0xc8, 0x00); /* phase control */
1432
1433 /* set ADI recommended settings for digitizer */
1434 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1435 afe_write(sd, 0x12, 0x7b); /* ADC noise shaping filter controls */
1436 afe_write(sd, 0x0c, 0x1f); /* CP core gain controls */
1437 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1438 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1439 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1440 break;
1441
6b0d5d34 1442 case ADV7604_MODE_HDMI:
54450f59
HV		 1443 /* set ADI recommended settings for HDMI: */
1444 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1445 hdmi_write(sd, 0x0d, 0x84); /* HDMI filter optimization */
1446 hdmi_write(sd, 0x3d, 0x10); /* DDC bus active pull-up control */
1447 hdmi_write(sd, 0x3e, 0x39); /* TMDS PLL optimization */
1448 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1449 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1450 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1451 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1452 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1453 hdmi_write(sd, 0x93, 0x8b); /* equaliser */
1454 hdmi_write(sd, 0x94, 0x2d); /* equaliser */
1455 hdmi_write(sd, 0x96, 0x01); /* enable automatic EQ changing */
1456
1457 afe_write(sd, 0x00, 0xff); /* power down ADC */
1458 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1459 afe_write(sd, 0xc8, 0x40); /* phase control */
1460
1461 /* reset ADI recommended settings for digitizer */
1462 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1463 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1464 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1465 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1466 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1467 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1468
1469 break;
1470 default:
6b0d5d34
HV		 1471 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1472 __func__, state->mode);
54450f59
HV		 1473 break;
1474 }
1475}
1476
1477static int adv7604_s_routing(struct v4l2_subdev *sd,
1478 u32 input, u32 output, u32 config)
1479{
1480 struct adv7604_state *state = to_state(sd);
1481
1482 v4l2_dbg(2, debug, sd, "%s: input %d", __func__, input);
1483
6b0d5d34 1484 state->mode = input;
54450f59
HV		 1485
1486 disable_input(sd);
1487
6b0d5d34 1488 select_input(sd);
54450f59 1489
6b0d5d34 1490 enable_input(sd);
54450f59
HV		 1491
1492 return 0;
1493}
1494
1495static int adv7604_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1496 enum v4l2_mbus_pixelcode *code)
1497{
1498 if (index)
1499 return -EINVAL;
1500 /* Good enough for now */
1501 *code = V4L2_MBUS_FMT_FIXED;
1502 return 0;
1503}
1504
1505static int adv7604_g_mbus_fmt(struct v4l2_subdev *sd,
1506 struct v4l2_mbus_framefmt *fmt)
1507{
1508 struct adv7604_state *state = to_state(sd);
1509
1510 fmt->width = state->timings.bt.width;
1511 fmt->height = state->timings.bt.height;
1512 fmt->code = V4L2_MBUS_FMT_FIXED;
1513 fmt->field = V4L2_FIELD_NONE;
1514 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1515 fmt->colorspace = (state->timings.bt.height <= 576) ?
1516 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1517 }
1518 return 0;
1519}
1520
1521static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1522{
1523 struct adv7604_state *state = to_state(sd);
1524 u8 fmt_change, fmt_change_digital, tx_5v;
1525
1526 /* format change */
1527 fmt_change = io_read(sd, 0x43) & 0x98;
1528 if (fmt_change)
1529 io_write(sd, 0x44, fmt_change);
1530 fmt_change_digital = DIGITAL_INPUT ? (io_read(sd, 0x6b) & 0xc0) : 0;
1531 if (fmt_change_digital)
1532 io_write(sd, 0x6c, fmt_change_digital);
1533 if (fmt_change || fmt_change_digital) {
1534 v4l2_dbg(1, debug, sd,
1535 "%s: ADV7604_FMT_CHANGE, fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
1536 __func__, fmt_change, fmt_change_digital);
1537 v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL);
1538 if (handled)
1539 *handled = true;
1540 }
1541 /* tx 5v detect */
1542 tx_5v = io_read(sd, 0x70) & 0x10;
1543 if (tx_5v) {
1544 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1545 io_write(sd, 0x71, tx_5v);
1546 adv7604_s_detect_tx_5v_ctrl(sd);
1547 if (handled)
1548 *handled = true;
1549 }
1550 return 0;
1551}
1552
1553static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1554{
1555 struct adv7604_state *state = to_state(sd);
1556
1557 if (edid->pad != 0)
1558 return -EINVAL;
1559 if (edid->blocks == 0)
1560 return -EINVAL;
1561 if (edid->start_block >= state->edid_blocks)
1562 return -EINVAL;
1563 if (edid->start_block + edid->blocks > state->edid_blocks)
1564 edid->blocks = state->edid_blocks - edid->start_block;
1565 if (!edid->edid)
1566 return -EINVAL;
1567 memcpy(edid->edid + edid->start_block * 128,
1568 state->edid + edid->start_block * 128,
1569 edid->blocks * 128);
1570 return 0;
1571}
1572
1573static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1574{
1575 struct adv7604_state *state = to_state(sd);
1576 int err;
1577
1578 if (edid->pad != 0)
1579 return -EINVAL;
1580 if (edid->start_block != 0)
1581 return -EINVAL;
1582 if (edid->blocks == 0) {
1583 /* Pull down the hotplug pin */
1584 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)0);
1585 /* Disables I2C access to internal EDID ram from DDC port */
1586 rep_write_and_or(sd, 0x77, 0xf0, 0x0);
1587 state->edid_blocks = 0;
1588 /* Fall back to a 16:9 aspect ratio */
1589 state->aspect_ratio.numerator = 16;
1590 state->aspect_ratio.denominator = 9;
1591 return 0;
1592 }
1593 if (edid->blocks > 2)
1594 return -E2BIG;
1595 if (!edid->edid)
1596 return -EINVAL;
1597 memcpy(state->edid, edid->edid, 128 * edid->blocks);
1598 state->edid_blocks = edid->blocks;
1599 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
1600 edid->edid[0x16]);
1601 err = edid_write_block(sd, 128 * edid->blocks, state->edid);
1602 if (err < 0)
1603 v4l2_err(sd, "error %d writing edid\n", err);
1604 return err;
1605}
1606
1607/*********** avi info frame CEA-861-E **************/
1608
1609static void print_avi_infoframe(struct v4l2_subdev *sd)
1610{
1611 int i;
1612 u8 buf[14];
1613 u8 avi_len;
1614 u8 avi_ver;
1615
1616 if (!(hdmi_read(sd, 0x05) & 0x80)) {
1617 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
1618 return;
1619 }
1620 if (!(io_read(sd, 0x60) & 0x01)) {
1621 v4l2_info(sd, "AVI infoframe not received\n");
1622 return;
1623 }
1624
1625 if (io_read(sd, 0x83) & 0x01) {
1626 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
1627 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1628 if (io_read(sd, 0x83) & 0x01) {
1629 v4l2_info(sd, "AVI infoframe checksum error still present\n");
1630 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1631 }
1632 }
1633
1634 avi_len = infoframe_read(sd, 0xe2);
1635 avi_ver = infoframe_read(sd, 0xe1);
1636 v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
1637 avi_ver, avi_len);
1638
1639 if (avi_ver != 0x02)
1640 return;
1641
1642 for (i = 0; i < 14; i++)
1643 buf[i] = infoframe_read(sd, i);
1644
1645 v4l2_info(sd,
1646 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
1647 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
1648 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
1649}
1650
1651static int adv7604_log_status(struct v4l2_subdev *sd)
1652{
1653 struct adv7604_state *state = to_state(sd);
1654 struct v4l2_dv_timings timings;
1655 struct stdi_readback stdi;
1656 u8 reg_io_0x02 = io_read(sd, 0x02);
1657
1658 char *csc_coeff_sel_rb[16] = {
1659 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
1660 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
1661 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
1662 "reserved", "reserved", "reserved", "reserved", "manual"
1663 };
1664 char *input_color_space_txt[16] = {
1665 "RGB limited range (16-235)", "RGB full range (0-255)",
1666 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
1667 "XvYCC Bt.601", "XvYCC Bt.709",
1668 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
1669 "invalid", "invalid", "invalid", "invalid", "invalid",
1670 "invalid", "invalid", "automatic"
1671 };
1672 char *rgb_quantization_range_txt[] = {
1673 "Automatic",
1674 "RGB limited range (16-235)",
1675 "RGB full range (0-255)",
1676 };
1677
1678 v4l2_info(sd, "-----Chip status-----\n");
1679 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
1680 v4l2_info(sd, "Connector type: %s\n", state->connector_hdmi ?
1681 "HDMI" : (DIGITAL_INPUT ? "DVI-D" : "DVI-A"));
1682 v4l2_info(sd, "EDID: %s\n", ((rep_read(sd, 0x7d) & 0x01) &&
1683 (rep_read(sd, 0x77) & 0x01)) ? "enabled" : "disabled ");
1684 v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
1685 "enabled" : "disabled");
1686
1687 v4l2_info(sd, "-----Signal status-----\n");
1688 v4l2_info(sd, "Cable detected (+5V power): %s\n",
1689 (io_read(sd, 0x6f) & 0x10) ? "true" : "false");
1690 v4l2_info(sd, "TMDS signal detected: %s\n",
1691 no_signal_tmds(sd) ? "false" : "true");
1692 v4l2_info(sd, "TMDS signal locked: %s\n",
1693 no_lock_tmds(sd) ? "false" : "true");
1694 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
1695 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
1696 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
1697 v4l2_info(sd, "CP free run: %s\n",
1698 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
ccbd5bc4
HV		 1699 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
1700 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
1701 (io_read(sd, 0x01) & 0x70) >> 4);
54450f59
HV		 1702
1703 v4l2_info(sd, "-----Video Timings-----\n");
1704 if (read_stdi(sd, &stdi))
1705 v4l2_info(sd, "STDI: not locked\n");
1706 else
1707 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
1708 stdi.lcf, stdi.bl, stdi.lcvs,
1709 stdi.interlaced ? "interlaced" : "progressive",
1710 stdi.hs_pol, stdi.vs_pol);
1711 if (adv7604_query_dv_timings(sd, &timings))
1712 v4l2_info(sd, "No video detected\n");
1713 else
1714 adv7604_print_timings(sd, &timings, "Detected format:", true);
1715 adv7604_print_timings(sd, &state->timings, "Configured format:", true);
1716
1717 v4l2_info(sd, "-----Color space-----\n");
1718 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
1719 rgb_quantization_range_txt[state->rgb_quantization_range]);
1720 v4l2_info(sd, "Input color space: %s\n",
1721 input_color_space_txt[reg_io_0x02 >> 4]);
1722 v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
1723 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
1724 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
1725 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
1726 "enabled" : "disabled");
1727 v4l2_info(sd, "Color space conversion: %s\n",
1728 csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]);
1729
1730 /* Digital video */
1731 if (DIGITAL_INPUT) {
1732 v4l2_info(sd, "-----HDMI status-----\n");
1733 v4l2_info(sd, "HDCP encrypted content: %s\n",
1734 hdmi_read(sd, 0x05) & 0x40 ? "true" : "false");
1735
1736 print_avi_infoframe(sd);
1737 }
1738
1739 return 0;
1740}
1741
1742/* ----------------------------------------------------------------------- */
1743
1744static const struct v4l2_ctrl_ops adv7604_ctrl_ops = {
1745 .s_ctrl = adv7604_s_ctrl,
1746};
1747
1748static const struct v4l2_subdev_core_ops adv7604_core_ops = {
1749 .log_status = adv7604_log_status,
1750 .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
1751 .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
1752 .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
1753 .g_ctrl = v4l2_subdev_g_ctrl,
1754 .s_ctrl = v4l2_subdev_s_ctrl,
1755 .queryctrl = v4l2_subdev_queryctrl,
1756 .querymenu = v4l2_subdev_querymenu,
1757 .g_chip_ident = adv7604_g_chip_ident,
1758 .interrupt_service_routine = adv7604_isr,
1759#ifdef CONFIG_VIDEO_ADV_DEBUG
1760 .g_register = adv7604_g_register,
1761 .s_register = adv7604_s_register,
1762#endif
1763};
1764
1765static const struct v4l2_subdev_video_ops adv7604_video_ops = {
1766 .s_routing = adv7604_s_routing,
1767 .g_input_status = adv7604_g_input_status,
1768 .s_dv_timings = adv7604_s_dv_timings,
1769 .g_dv_timings = adv7604_g_dv_timings,
1770 .query_dv_timings = adv7604_query_dv_timings,
1771 .enum_dv_timings = adv7604_enum_dv_timings,
1772 .dv_timings_cap = adv7604_dv_timings_cap,
1773 .enum_mbus_fmt = adv7604_enum_mbus_fmt,
1774 .g_mbus_fmt = adv7604_g_mbus_fmt,
1775 .try_mbus_fmt = adv7604_g_mbus_fmt,
1776 .s_mbus_fmt = adv7604_g_mbus_fmt,
1777};
1778
1779static const struct v4l2_subdev_pad_ops adv7604_pad_ops = {
1780 .get_edid = adv7604_get_edid,
1781 .set_edid = adv7604_set_edid,
1782};
1783
1784static const struct v4l2_subdev_ops adv7604_ops = {
1785 .core = &adv7604_core_ops,
1786 .video = &adv7604_video_ops,
1787 .pad = &adv7604_pad_ops,
1788};
1789
1790/* -------------------------- custom ctrls ---------------------------------- */
1791
1792static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
1793 .ops = &adv7604_ctrl_ops,
1794 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
1795 .name = "Analog Sampling Phase",
1796 .type = V4L2_CTRL_TYPE_INTEGER,
1797 .min = 0,
1798 .max = 0x1f,
1799 .step = 1,
1800 .def = 0,
1801};
1802
1803static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = {
1804 .ops = &adv7604_ctrl_ops,
1805 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
1806 .name = "Free Running Color, Manual",
1807 .type = V4L2_CTRL_TYPE_BOOLEAN,
1808 .min = false,
1809 .max = true,
1810 .step = 1,
1811 .def = false,
1812};
1813
1814static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = {
1815 .ops = &adv7604_ctrl_ops,
1816 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
1817 .name = "Free Running Color",
1818 .type = V4L2_CTRL_TYPE_INTEGER,
1819 .min = 0x0,
1820 .max = 0xffffff,
1821 .step = 0x1,
1822 .def = 0x0,
1823};
1824
1825/* ----------------------------------------------------------------------- */
1826
1827static int adv7604_core_init(struct v4l2_subdev *sd)
1828{
1829 struct adv7604_state *state = to_state(sd);
1830 struct adv7604_platform_data *pdata = &state->pdata;
1831
1832 hdmi_write(sd, 0x48,
1833 (pdata->disable_pwrdnb ? 0x80 : 0) |
1834 (pdata->disable_cable_det_rst ? 0x40 : 0));
1835
1836 disable_input(sd);
1837
1838 /* power */
1839 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
1840 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
1841 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
1842
1843 /* video format */
1844 io_write_and_or(sd, 0x02, 0xf0,
1845 pdata->alt_gamma << 3 |
1846 pdata->op_656_range << 2 |
1847 pdata->rgb_out << 1 |
1848 pdata->alt_data_sat << 0);
1849 io_write(sd, 0x03, pdata->op_format_sel);
1850 io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
1851 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
1852 pdata->insert_av_codes << 2 |
1853 pdata->replicate_av_codes << 1 |
1854 pdata->invert_cbcr << 0);
1855
1856 /* TODO from platform data */
1857 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
1858 io_write(sd, 0x06, 0xa6); /* positive VS and HS */
1859 io_write(sd, 0x14, 0x7f); /* Drive strength adjusted to max */
1860 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
1861 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
1862 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
80939647 1863 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59 1864 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
80939647 1865 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59
HV		 1866 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
1867 for digital formats */
1868
1869 /* TODO from platform data */
1870 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
1871
1872 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
1873 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
1874
54450f59
HV		 1875 /* interrupts */
1876 io_write(sd, 0x40, 0xc2); /* Configure INT1 */
1877 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
1878 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
1879 io_write(sd, 0x6e, 0xc0); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
1880 io_write(sd, 0x73, 0x10); /* Enable CABLE_DET_A_ST (+5v) interrupt */
1881
1882 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
1883}
1884
1885static void adv7604_unregister_clients(struct adv7604_state *state)
1886{
1887 if (state->i2c_avlink)
1888 i2c_unregister_device(state->i2c_avlink);
1889 if (state->i2c_cec)
1890 i2c_unregister_device(state->i2c_cec);
1891 if (state->i2c_infoframe)
1892 i2c_unregister_device(state->i2c_infoframe);
1893 if (state->i2c_esdp)
1894 i2c_unregister_device(state->i2c_esdp);
1895 if (state->i2c_dpp)
1896 i2c_unregister_device(state->i2c_dpp);
1897 if (state->i2c_afe)
1898 i2c_unregister_device(state->i2c_afe);
1899 if (state->i2c_repeater)
1900 i2c_unregister_device(state->i2c_repeater);
1901 if (state->i2c_edid)
1902 i2c_unregister_device(state->i2c_edid);
1903 if (state->i2c_hdmi)
1904 i2c_unregister_device(state->i2c_hdmi);
1905 if (state->i2c_test)
1906 i2c_unregister_device(state->i2c_test);
1907 if (state->i2c_cp)
1908 i2c_unregister_device(state->i2c_cp);
1909 if (state->i2c_vdp)
1910 i2c_unregister_device(state->i2c_vdp);
1911}
1912
1913static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd,
1914 u8 addr, u8 io_reg)
1915{
1916 struct i2c_client *client = v4l2_get_subdevdata(sd);
1917
1918 if (addr)
1919 io_write(sd, io_reg, addr << 1);
1920 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
1921}
1922
1923static int adv7604_probe(struct i2c_client *client,
1924 const struct i2c_device_id *id)
1925{
1926 struct adv7604_state *state;
1927 struct adv7604_platform_data *pdata = client->dev.platform_data;
1928 struct v4l2_ctrl_handler *hdl;
1929 struct v4l2_subdev *sd;
1930 int err;
1931
1932 /* Check if the adapter supports the needed features */
1933 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1934 return -EIO;
1935 v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n",
1936 client->addr << 1);
1937
1938 state = kzalloc(sizeof(struct adv7604_state), GFP_KERNEL);
1939 if (!state) {
1940 v4l_err(client, "Could not allocate adv7604_state memory!\n");
1941 return -ENOMEM;
1942 }
1943
1944 /* platform data */
1945 if (!pdata) {
1946 v4l_err(client, "No platform data!\n");
1947 err = -ENODEV;
1948 goto err_state;
1949 }
1950 memcpy(&state->pdata, pdata, sizeof(state->pdata));
1951
1952 sd = &state->sd;
1953 v4l2_i2c_subdev_init(sd, client, &adv7604_ops);
1954 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1955 state->connector_hdmi = pdata->connector_hdmi;
1956
1957 /* i2c access to adv7604? */
1958 if (adv_smbus_read_byte_data_check(client, 0xfb, false) != 0x68) {
1959 v4l2_info(sd, "not an adv7604 on address 0x%x\n",
1960 client->addr << 1);
1961 err = -ENODEV;
1962 goto err_state;
1963 }
1964
1965 /* control handlers */
1966 hdl = &state->hdl;
1967 v4l2_ctrl_handler_init(hdl, 9);
1968
1969 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
1970 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
1971 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
1972 V4L2_CID_CONTRAST, 0, 255, 1, 128);
1973 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
1974 V4L2_CID_SATURATION, 0, 255, 1, 128);
1975 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
1976 V4L2_CID_HUE, 0, 128, 1, 0);
1977
1978 /* private controls */
1979 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1980 V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);
1981 state->detect_tx_5v_ctrl->is_private = true;
1982 state->rgb_quantization_range_ctrl =
1983 v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops,
1984 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
1985 0, V4L2_DV_RGB_RANGE_AUTO);
1986 state->rgb_quantization_range_ctrl->is_private = true;
1987
1988 /* custom controls */
1989 state->analog_sampling_phase_ctrl =
1990 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
1991 state->analog_sampling_phase_ctrl->is_private = true;
1992 state->free_run_color_manual_ctrl =
1993 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL);
1994 state->free_run_color_manual_ctrl->is_private = true;
1995 state->free_run_color_ctrl =
1996 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL);
1997 state->free_run_color_ctrl->is_private = true;
1998
1999 sd->ctrl_handler = hdl;
2000 if (hdl->error) {
2001 err = hdl->error;
2002 goto err_hdl;
2003 }
2004 if (adv7604_s_detect_tx_5v_ctrl(sd)) {
2005 err = -ENODEV;
2006 goto err_hdl;
2007 }
2008
2009 state->i2c_avlink = adv7604_dummy_client(sd, pdata->i2c_avlink, 0xf3);
2010 state->i2c_cec = adv7604_dummy_client(sd, pdata->i2c_cec, 0xf4);
2011 state->i2c_infoframe = adv7604_dummy_client(sd, pdata->i2c_infoframe, 0xf5);
2012 state->i2c_esdp = adv7604_dummy_client(sd, pdata->i2c_esdp, 0xf6);
2013 state->i2c_dpp = adv7604_dummy_client(sd, pdata->i2c_dpp, 0xf7);
2014 state->i2c_afe = adv7604_dummy_client(sd, pdata->i2c_afe, 0xf8);
2015 state->i2c_repeater = adv7604_dummy_client(sd, pdata->i2c_repeater, 0xf9);
2016 state->i2c_edid = adv7604_dummy_client(sd, pdata->i2c_edid, 0xfa);
2017 state->i2c_hdmi = adv7604_dummy_client(sd, pdata->i2c_hdmi, 0xfb);
2018 state->i2c_test = adv7604_dummy_client(sd, pdata->i2c_test, 0xfc);
2019 state->i2c_cp = adv7604_dummy_client(sd, pdata->i2c_cp, 0xfd);
2020 state->i2c_vdp = adv7604_dummy_client(sd, pdata->i2c_vdp, 0xfe);
2021 if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe ||
2022 !state->i2c_esdp || !state->i2c_dpp || !state->i2c_afe ||
2023 !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi ||
2024 !state->i2c_test || !state->i2c_cp || !state->i2c_vdp) {
2025 err = -ENOMEM;
2026 v4l2_err(sd, "failed to create all i2c clients\n");
2027 goto err_i2c;
2028 }
2029
2030 /* work queues */
2031 state->work_queues = create_singlethread_workqueue(client->name);
2032 if (!state->work_queues) {
2033 v4l2_err(sd, "Could not create work queue\n");
2034 err = -ENOMEM;
2035 goto err_i2c;
2036 }
2037
2038 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2039 adv7604_delayed_work_enable_hotplug);
2040
2041 state->pad.flags = MEDIA_PAD_FL_SOURCE;
2042 err = media_entity_init(&sd->entity, 1, &state->pad, 0);
2043 if (err)
2044 goto err_work_queues;
2045
2046 err = adv7604_core_init(sd);
2047 if (err)
2048 goto err_entity;
2049 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2050 client->addr << 1, client->adapter->name);
2051 return 0;
2052
2053err_entity:
2054 media_entity_cleanup(&sd->entity);
2055err_work_queues:
2056 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2057 destroy_workqueue(state->work_queues);
2058err_i2c:
2059 adv7604_unregister_clients(state);
2060err_hdl:
2061 v4l2_ctrl_handler_free(hdl);
2062err_state:
2063 kfree(state);
2064 return err;
2065}
2066
2067/* ----------------------------------------------------------------------- */
2068
2069static int adv7604_remove(struct i2c_client *client)
2070{
2071 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2072 struct adv7604_state *state = to_state(sd);
2073
2074 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2075 destroy_workqueue(state->work_queues);
2076 v4l2_device_unregister_subdev(sd);
2077 media_entity_cleanup(&sd->entity);
2078 adv7604_unregister_clients(to_state(sd));
2079 v4l2_ctrl_handler_free(sd->ctrl_handler);
2080 kfree(to_state(sd));
2081 return 0;
2082}
2083
2084/* ----------------------------------------------------------------------- */
2085
2086static struct i2c_device_id adv7604_id[] = {
2087 { "adv7604", 0 },
2088 { }
2089};
2090MODULE_DEVICE_TABLE(i2c, adv7604_id);
2091
2092static struct i2c_driver adv7604_driver = {
2093 .driver = {
2094 .owner = THIS_MODULE,
2095 .name = "adv7604",
2096 },
2097 .probe = adv7604_probe,
2098 .remove = adv7604_remove,
2099 .id_table = adv7604_id,
2100};
2101
2102module_i2c_driver(adv7604_driver);
Linux 6.x block layer and io_uring tree(s)