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Merge remote-tracking branches 'spi/topic/fsl-espi', 'spi/topic/gpio', 'spi/topic...
[linux-2.6-block.git] / drivers / media / i2c / adv7604.c
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54450f59
HV		 1/*
2 * adv7604 - Analog Devices ADV7604 video decoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21/*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
28 */
29
30
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/slab.h>
34#include <linux/i2c.h>
35#include <linux/delay.h>
36#include <linux/videodev2.h>
37#include <linux/workqueue.h>
38#include <linux/v4l2-dv-timings.h>
39#include <media/v4l2-device.h>
40#include <media/v4l2-ctrls.h>
25764158 41#include <media/v4l2-dv-timings.h>
54450f59
HV		 42#include <media/adv7604.h>
43
44static int debug;
45module_param(debug, int, 0644);
46MODULE_PARM_DESC(debug, "debug level (0-2)");
47
48MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
49MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
50MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
51MODULE_LICENSE("GPL");
52
53/* ADV7604 system clock frequency */
54#define ADV7604_fsc (28636360)
55
6b0d5d34 56#define DIGITAL_INPUT (state->mode == ADV7604_MODE_HDMI)
54450f59
HV		 57
58/*
59 **********************************************************************
60 *
61 * Arrays with configuration parameters for the ADV7604
62 *
63 **********************************************************************
64 */
65struct adv7604_state {
66 struct adv7604_platform_data pdata;
67 struct v4l2_subdev sd;
68 struct media_pad pad;
69 struct v4l2_ctrl_handler hdl;
6b0d5d34 70 enum adv7604_mode mode;
54450f59
HV		 71 struct v4l2_dv_timings timings;
72 u8 edid[256];
73 unsigned edid_blocks;
74 struct v4l2_fract aspect_ratio;
75 u32 rgb_quantization_range;
76 struct workqueue_struct *work_queues;
77 struct delayed_work delayed_work_enable_hotplug;
78 bool connector_hdmi;
cf9afb1d 79 bool restart_stdi_once;
25a64ac9 80 u32 prev_input_status;
54450f59
HV		 81
82 /* i2c clients */
83 struct i2c_client *i2c_avlink;
84 struct i2c_client *i2c_cec;
85 struct i2c_client *i2c_infoframe;
86 struct i2c_client *i2c_esdp;
87 struct i2c_client *i2c_dpp;
88 struct i2c_client *i2c_afe;
89 struct i2c_client *i2c_repeater;
90 struct i2c_client *i2c_edid;
91 struct i2c_client *i2c_hdmi;
92 struct i2c_client *i2c_test;
93 struct i2c_client *i2c_cp;
94 struct i2c_client *i2c_vdp;
95
96 /* controls */
97 struct v4l2_ctrl *detect_tx_5v_ctrl;
98 struct v4l2_ctrl *analog_sampling_phase_ctrl;
99 struct v4l2_ctrl *free_run_color_manual_ctrl;
100 struct v4l2_ctrl *free_run_color_ctrl;
101 struct v4l2_ctrl *rgb_quantization_range_ctrl;
102};
103
104/* Supported CEA and DMT timings */
105static const struct v4l2_dv_timings adv7604_timings[] = {
106 V4L2_DV_BT_CEA_720X480P59_94,
107 V4L2_DV_BT_CEA_720X576P50,
108 V4L2_DV_BT_CEA_1280X720P24,
109 V4L2_DV_BT_CEA_1280X720P25,
54450f59
HV		 110 V4L2_DV_BT_CEA_1280X720P50,
111 V4L2_DV_BT_CEA_1280X720P60,
112 V4L2_DV_BT_CEA_1920X1080P24,
113 V4L2_DV_BT_CEA_1920X1080P25,
114 V4L2_DV_BT_CEA_1920X1080P30,
115 V4L2_DV_BT_CEA_1920X1080P50,
116 V4L2_DV_BT_CEA_1920X1080P60,
117
ccbd5bc4 118 /* sorted by DMT ID */
54450f59
HV		 119 V4L2_DV_BT_DMT_640X350P85,
120 V4L2_DV_BT_DMT_640X400P85,
121 V4L2_DV_BT_DMT_720X400P85,
122 V4L2_DV_BT_DMT_640X480P60,
123 V4L2_DV_BT_DMT_640X480P72,
124 V4L2_DV_BT_DMT_640X480P75,
125 V4L2_DV_BT_DMT_640X480P85,
126 V4L2_DV_BT_DMT_800X600P56,
127 V4L2_DV_BT_DMT_800X600P60,
128 V4L2_DV_BT_DMT_800X600P72,
129 V4L2_DV_BT_DMT_800X600P75,
130 V4L2_DV_BT_DMT_800X600P85,
131 V4L2_DV_BT_DMT_848X480P60,
132 V4L2_DV_BT_DMT_1024X768P60,
133 V4L2_DV_BT_DMT_1024X768P70,
134 V4L2_DV_BT_DMT_1024X768P75,
135 V4L2_DV_BT_DMT_1024X768P85,
136 V4L2_DV_BT_DMT_1152X864P75,
137 V4L2_DV_BT_DMT_1280X768P60_RB,
138 V4L2_DV_BT_DMT_1280X768P60,
139 V4L2_DV_BT_DMT_1280X768P75,
140 V4L2_DV_BT_DMT_1280X768P85,
141 V4L2_DV_BT_DMT_1280X800P60_RB,
142 V4L2_DV_BT_DMT_1280X800P60,
143 V4L2_DV_BT_DMT_1280X800P75,
144 V4L2_DV_BT_DMT_1280X800P85,
145 V4L2_DV_BT_DMT_1280X960P60,
146 V4L2_DV_BT_DMT_1280X960P85,
147 V4L2_DV_BT_DMT_1280X1024P60,
148 V4L2_DV_BT_DMT_1280X1024P75,
149 V4L2_DV_BT_DMT_1280X1024P85,
150 V4L2_DV_BT_DMT_1360X768P60,
151 V4L2_DV_BT_DMT_1400X1050P60_RB,
152 V4L2_DV_BT_DMT_1400X1050P60,
153 V4L2_DV_BT_DMT_1400X1050P75,
154 V4L2_DV_BT_DMT_1400X1050P85,
155 V4L2_DV_BT_DMT_1440X900P60_RB,
156 V4L2_DV_BT_DMT_1440X900P60,
157 V4L2_DV_BT_DMT_1600X1200P60,
158 V4L2_DV_BT_DMT_1680X1050P60_RB,
159 V4L2_DV_BT_DMT_1680X1050P60,
160 V4L2_DV_BT_DMT_1792X1344P60,
161 V4L2_DV_BT_DMT_1856X1392P60,
162 V4L2_DV_BT_DMT_1920X1200P60_RB,
163 V4L2_DV_BT_DMT_1366X768P60,
164 V4L2_DV_BT_DMT_1920X1080P60,
165 { },
166};
167
ccbd5bc4
HV		 168struct adv7604_video_standards {
169 struct v4l2_dv_timings timings;
170 u8 vid_std;
171 u8 v_freq;
172};
173
174/* sorted by number of lines */
175static const struct adv7604_video_standards adv7604_prim_mode_comp[] = {
176 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
177 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
178 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
179 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
180 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
181 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
182 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
183 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
184 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
185 /* TODO add 1920x1080P60_RB (CVT timing) */
186 { },
187};
188
189/* sorted by number of lines */
190static const struct adv7604_video_standards adv7604_prim_mode_gr[] = {
191 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
192 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
193 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
194 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
195 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
196 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
197 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
198 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
199 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
200 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
201 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
202 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
203 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
204 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
205 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
206 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
207 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
208 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
209 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
210 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
211 /* TODO add 1600X1200P60_RB (not a DMT timing) */
212 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
213 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
214 { },
215};
216
217/* sorted by number of lines */
218static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = {
219 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
220 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
221 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
222 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
223 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
224 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
225 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
226 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
227 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
228 { },
229};
230
231/* sorted by number of lines */
232static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = {
233 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
234 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
235 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
236 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
237 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
238 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
239 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
240 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
241 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
242 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
243 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
244 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
245 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
246 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
247 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
248 { },
249};
250
54450f59
HV		 251/* ----------------------------------------------------------------------- */
252
253static inline struct adv7604_state *to_state(struct v4l2_subdev *sd)
254{
255 return container_of(sd, struct adv7604_state, sd);
256}
257
258static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
259{
260 return &container_of(ctrl->handler, struct adv7604_state, hdl)->sd;
261}
262
263static inline unsigned hblanking(const struct v4l2_bt_timings *t)
264{
eacf8f9a 265 return V4L2_DV_BT_BLANKING_WIDTH(t);
54450f59
HV		 266}
267
268static inline unsigned htotal(const struct v4l2_bt_timings *t)
269{
eacf8f9a 270 return V4L2_DV_BT_FRAME_WIDTH(t);
54450f59
HV		 271}
272
273static inline unsigned vblanking(const struct v4l2_bt_timings *t)
274{
eacf8f9a 275 return V4L2_DV_BT_BLANKING_HEIGHT(t);
54450f59
HV		 276}
277
278static inline unsigned vtotal(const struct v4l2_bt_timings *t)
279{
eacf8f9a 280 return V4L2_DV_BT_FRAME_HEIGHT(t);
54450f59
HV		 281}
282
283/* ----------------------------------------------------------------------- */
284
285static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
286 u8 command, bool check)
287{
288 union i2c_smbus_data data;
289
290 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
291 I2C_SMBUS_READ, command,
292 I2C_SMBUS_BYTE_DATA, &data))
293 return data.byte;
294 if (check)
295 v4l_err(client, "error reading %02x, %02x\n",
296 client->addr, command);
297 return -EIO;
298}
299
300static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
301{
302 return adv_smbus_read_byte_data_check(client, command, true);
303}
304
305static s32 adv_smbus_write_byte_data(struct i2c_client *client,
306 u8 command, u8 value)
307{
308 union i2c_smbus_data data;
309 int err;
310 int i;
311
312 data.byte = value;
313 for (i = 0; i < 3; i++) {
314 err = i2c_smbus_xfer(client->adapter, client->addr,
315 client->flags,
316 I2C_SMBUS_WRITE, command,
317 I2C_SMBUS_BYTE_DATA, &data);
318 if (!err)
319 break;
320 }
321 if (err < 0)
322 v4l_err(client, "error writing %02x, %02x, %02x\n",
323 client->addr, command, value);
324 return err;
325}
326
327static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
328 u8 command, unsigned length, const u8 *values)
329{
330 union i2c_smbus_data data;
331
332 if (length > I2C_SMBUS_BLOCK_MAX)
333 length = I2C_SMBUS_BLOCK_MAX;
334 data.block[0] = length;
335 memcpy(data.block + 1, values, length);
336 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
337 I2C_SMBUS_WRITE, command,
338 I2C_SMBUS_I2C_BLOCK_DATA, &data);
339}
340
341/* ----------------------------------------------------------------------- */
342
343static inline int io_read(struct v4l2_subdev *sd, u8 reg)
344{
345 struct i2c_client *client = v4l2_get_subdevdata(sd);
346
347 return adv_smbus_read_byte_data(client, reg);
348}
349
350static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
351{
352 struct i2c_client *client = v4l2_get_subdevdata(sd);
353
354 return adv_smbus_write_byte_data(client, reg, val);
355}
356
357static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
358{
359 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
360}
361
362static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
363{
364 struct adv7604_state *state = to_state(sd);
365
366 return adv_smbus_read_byte_data(state->i2c_avlink, reg);
367}
368
369static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
370{
371 struct adv7604_state *state = to_state(sd);
372
373 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
374}
375
376static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
377{
378 struct adv7604_state *state = to_state(sd);
379
380 return adv_smbus_read_byte_data(state->i2c_cec, reg);
381}
382
383static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
384{
385 struct adv7604_state *state = to_state(sd);
386
387 return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
388}
389
390static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
391{
392 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
393}
394
395static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
396{
397 struct adv7604_state *state = to_state(sd);
398
399 return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
400}
401
402static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
403{
404 struct adv7604_state *state = to_state(sd);
405
406 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
407}
408
409static inline int esdp_read(struct v4l2_subdev *sd, u8 reg)
410{
411 struct adv7604_state *state = to_state(sd);
412
413 return adv_smbus_read_byte_data(state->i2c_esdp, reg);
414}
415
416static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
417{
418 struct adv7604_state *state = to_state(sd);
419
420 return adv_smbus_write_byte_data(state->i2c_esdp, reg, val);
421}
422
423static inline int dpp_read(struct v4l2_subdev *sd, u8 reg)
424{
425 struct adv7604_state *state = to_state(sd);
426
427 return adv_smbus_read_byte_data(state->i2c_dpp, reg);
428}
429
430static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
431{
432 struct adv7604_state *state = to_state(sd);
433
434 return adv_smbus_write_byte_data(state->i2c_dpp, reg, val);
435}
436
437static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
438{
439 struct adv7604_state *state = to_state(sd);
440
441 return adv_smbus_read_byte_data(state->i2c_afe, reg);
442}
443
444static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
445{
446 struct adv7604_state *state = to_state(sd);
447
448 return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
449}
450
451static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
452{
453 struct adv7604_state *state = to_state(sd);
454
455 return adv_smbus_read_byte_data(state->i2c_repeater, reg);
456}
457
458static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
459{
460 struct adv7604_state *state = to_state(sd);
461
462 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
463}
464
465static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
466{
467 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
468}
469
470static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
471{
472 struct adv7604_state *state = to_state(sd);
473
474 return adv_smbus_read_byte_data(state->i2c_edid, reg);
475}
476
477static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
478{
479 struct adv7604_state *state = to_state(sd);
480
481 return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
482}
483
484static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val)
485{
486 struct adv7604_state *state = to_state(sd);
487 struct i2c_client *client = state->i2c_edid;
488 u8 msgbuf0[1] = { 0 };
489 u8 msgbuf1[256];
09f29673
S		 490 struct i2c_msg msg[2] = {
491 {
492 .addr = client->addr,
493 .len = 1,
494 .buf = msgbuf0
495 },
496 {
497 .addr = client->addr,
498 .flags = I2C_M_RD,
499 .len = len,
500 .buf = msgbuf1
501 },
502 };
54450f59
HV		 503
504 if (i2c_transfer(client->adapter, msg, 2) < 0)
505 return -EIO;
506 memcpy(val, msgbuf1, len);
507 return 0;
508}
509
510static void adv7604_delayed_work_enable_hotplug(struct work_struct *work)
511{
512 struct delayed_work *dwork = to_delayed_work(work);
513 struct adv7604_state *state = container_of(dwork, struct adv7604_state,
514 delayed_work_enable_hotplug);
515 struct v4l2_subdev *sd = &state->sd;
516
517 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
518
519 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)1);
520}
521
522static inline int edid_write_block(struct v4l2_subdev *sd,
523 unsigned len, const u8 *val)
524{
525 struct i2c_client *client = v4l2_get_subdevdata(sd);
526 struct adv7604_state *state = to_state(sd);
527 int err = 0;
528 int i;
529
530 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
531
532 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)0);
533
534 /* Disables I2C access to internal EDID ram from DDC port */
535 rep_write_and_or(sd, 0x77, 0xf0, 0x0);
536
537 for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
538 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
539 I2C_SMBUS_BLOCK_MAX, val + i);
540 if (err)
541 return err;
542
543 /* adv7604 calculates the checksums and enables I2C access to internal
544 EDID ram from DDC port. */
545 rep_write_and_or(sd, 0x77, 0xf0, 0x1);
546
547 for (i = 0; i < 1000; i++) {
548 if (rep_read(sd, 0x7d) & 1)
549 break;
550 mdelay(1);
551 }
552 if (i == 1000) {
553 v4l_err(client, "error enabling edid\n");
554 return -EIO;
555 }
556
557 /* enable hotplug after 100 ms */
558 queue_delayed_work(state->work_queues,
559 &state->delayed_work_enable_hotplug, HZ / 10);
560 return 0;
561}
562
563static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
564{
565 struct adv7604_state *state = to_state(sd);
566
567 return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
568}
569
570static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
571{
572 struct adv7604_state *state = to_state(sd);
573
574 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
575}
576
577static inline int test_read(struct v4l2_subdev *sd, u8 reg)
578{
579 struct adv7604_state *state = to_state(sd);
580
581 return adv_smbus_read_byte_data(state->i2c_test, reg);
582}
583
584static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
585{
586 struct adv7604_state *state = to_state(sd);
587
588 return adv_smbus_write_byte_data(state->i2c_test, reg, val);
589}
590
591static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
592{
593 struct adv7604_state *state = to_state(sd);
594
595 return adv_smbus_read_byte_data(state->i2c_cp, reg);
596}
597
598static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
599{
600 struct adv7604_state *state = to_state(sd);
601
602 return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
603}
604
605static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
606{
607 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
608}
609
610static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
611{
612 struct adv7604_state *state = to_state(sd);
613
614 return adv_smbus_read_byte_data(state->i2c_vdp, reg);
615}
616
617static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
618{
619 struct adv7604_state *state = to_state(sd);
620
621 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
622}
623
624/* ----------------------------------------------------------------------- */
625
626#ifdef CONFIG_VIDEO_ADV_DEBUG
627static void adv7604_inv_register(struct v4l2_subdev *sd)
628{
629 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
630 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
631 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
632 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
633 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
634 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
635 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
636 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
637 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
638 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
639 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
640 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
641 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
642}
643
644static int adv7604_g_register(struct v4l2_subdev *sd,
645 struct v4l2_dbg_register *reg)
646{
54450f59
HV		 647 reg->size = 1;
648 switch (reg->reg >> 8) {
649 case 0:
650 reg->val = io_read(sd, reg->reg & 0xff);
651 break;
652 case 1:
653 reg->val = avlink_read(sd, reg->reg & 0xff);
654 break;
655 case 2:
656 reg->val = cec_read(sd, reg->reg & 0xff);
657 break;
658 case 3:
659 reg->val = infoframe_read(sd, reg->reg & 0xff);
660 break;
661 case 4:
662 reg->val = esdp_read(sd, reg->reg & 0xff);
663 break;
664 case 5:
665 reg->val = dpp_read(sd, reg->reg & 0xff);
666 break;
667 case 6:
668 reg->val = afe_read(sd, reg->reg & 0xff);
669 break;
670 case 7:
671 reg->val = rep_read(sd, reg->reg & 0xff);
672 break;
673 case 8:
674 reg->val = edid_read(sd, reg->reg & 0xff);
675 break;
676 case 9:
677 reg->val = hdmi_read(sd, reg->reg & 0xff);
678 break;
679 case 0xa:
680 reg->val = test_read(sd, reg->reg & 0xff);
681 break;
682 case 0xb:
683 reg->val = cp_read(sd, reg->reg & 0xff);
684 break;
685 case 0xc:
686 reg->val = vdp_read(sd, reg->reg & 0xff);
687 break;
688 default:
689 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
690 adv7604_inv_register(sd);
691 break;
692 }
693 return 0;
694}
695
696static int adv7604_s_register(struct v4l2_subdev *sd,
977ba3b1 697 const struct v4l2_dbg_register *reg)
54450f59 698{
54450f59
HV		 699 switch (reg->reg >> 8) {
700 case 0:
701 io_write(sd, reg->reg & 0xff, reg->val & 0xff);
702 break;
703 case 1:
704 avlink_write(sd, reg->reg & 0xff, reg->val & 0xff);
705 break;
706 case 2:
707 cec_write(sd, reg->reg & 0xff, reg->val & 0xff);
708 break;
709 case 3:
710 infoframe_write(sd, reg->reg & 0xff, reg->val & 0xff);
711 break;
712 case 4:
713 esdp_write(sd, reg->reg & 0xff, reg->val & 0xff);
714 break;
715 case 5:
716 dpp_write(sd, reg->reg & 0xff, reg->val & 0xff);
717 break;
718 case 6:
719 afe_write(sd, reg->reg & 0xff, reg->val & 0xff);
720 break;
721 case 7:
722 rep_write(sd, reg->reg & 0xff, reg->val & 0xff);
723 break;
724 case 8:
725 edid_write(sd, reg->reg & 0xff, reg->val & 0xff);
726 break;
727 case 9:
728 hdmi_write(sd, reg->reg & 0xff, reg->val & 0xff);
729 break;
730 case 0xa:
731 test_write(sd, reg->reg & 0xff, reg->val & 0xff);
732 break;
733 case 0xb:
734 cp_write(sd, reg->reg & 0xff, reg->val & 0xff);
735 break;
736 case 0xc:
737 vdp_write(sd, reg->reg & 0xff, reg->val & 0xff);
738 break;
739 default:
740 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
741 adv7604_inv_register(sd);
742 break;
743 }
744 return 0;
745}
746#endif
747
748static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
749{
750 struct adv7604_state *state = to_state(sd);
751
752 /* port A only */
753 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
754 ((io_read(sd, 0x6f) & 0x10) >> 4));
755}
756
ccbd5bc4
HV		 757static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
758 u8 prim_mode,
759 const struct adv7604_video_standards *predef_vid_timings,
760 const struct v4l2_dv_timings *timings)
761{
762 struct adv7604_state *state = to_state(sd);
763 int i;
764
765 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
ef1ed8f5 766 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
ccbd5bc4
HV		 767 DIGITAL_INPUT ? 250000 : 1000000))
768 continue;
769 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
770 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
771 prim_mode); /* v_freq and prim mode */
772 return 0;
773 }
774
775 return -1;
776}
777
778static int configure_predefined_video_timings(struct v4l2_subdev *sd,
779 struct v4l2_dv_timings *timings)
54450f59 780{
ccbd5bc4
HV		 781 struct adv7604_state *state = to_state(sd);
782 int err;
783
784 v4l2_dbg(1, debug, sd, "%s", __func__);
785
786 /* reset to default values */
787 io_write(sd, 0x16, 0x43);
788 io_write(sd, 0x17, 0x5a);
789 /* disable embedded syncs for auto graphics mode */
790 cp_write_and_or(sd, 0x81, 0xef, 0x00);
791 cp_write(sd, 0x8f, 0x00);
792 cp_write(sd, 0x90, 0x00);
793 cp_write(sd, 0xa2, 0x00);
794 cp_write(sd, 0xa3, 0x00);
795 cp_write(sd, 0xa4, 0x00);
796 cp_write(sd, 0xa5, 0x00);
797 cp_write(sd, 0xa6, 0x00);
798 cp_write(sd, 0xa7, 0x00);
799 cp_write(sd, 0xab, 0x00);
800 cp_write(sd, 0xac, 0x00);
801
802 switch (state->mode) {
803 case ADV7604_MODE_COMP:
804 case ADV7604_MODE_GR:
805 err = find_and_set_predefined_video_timings(sd,
806 0x01, adv7604_prim_mode_comp, timings);
807 if (err)
808 err = find_and_set_predefined_video_timings(sd,
809 0x02, adv7604_prim_mode_gr, timings);
810 break;
811 case ADV7604_MODE_HDMI:
812 err = find_and_set_predefined_video_timings(sd,
813 0x05, adv7604_prim_mode_hdmi_comp, timings);
814 if (err)
815 err = find_and_set_predefined_video_timings(sd,
816 0x06, adv7604_prim_mode_hdmi_gr, timings);
817 break;
818 default:
819 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
820 __func__, state->mode);
821 err = -1;
822 break;
823 }
824
825
826 return err;
827}
828
829static void configure_custom_video_timings(struct v4l2_subdev *sd,
830 const struct v4l2_bt_timings *bt)
831{
832 struct adv7604_state *state = to_state(sd);
54450f59 833 struct i2c_client *client = v4l2_get_subdevdata(sd);
ccbd5bc4
HV		 834 u32 width = htotal(bt);
835 u32 height = vtotal(bt);
836 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
837 u16 cp_start_eav = width - bt->hfrontporch;
838 u16 cp_start_vbi = height - bt->vfrontporch;
839 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
840 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
841 ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
842 const u8 pll[2] = {
843 0xc0 | ((width >> 8) & 0x1f),
844 width & 0xff
845 };
54450f59
HV		 846
847 v4l2_dbg(2, debug, sd, "%s\n", __func__);
848
ccbd5bc4
HV		 849 switch (state->mode) {
850 case ADV7604_MODE_COMP:
851 case ADV7604_MODE_GR:
852 /* auto graphics */
853 io_write(sd, 0x00, 0x07); /* video std */
854 io_write(sd, 0x01, 0x02); /* prim mode */
855 /* enable embedded syncs for auto graphics mode */
856 cp_write_and_or(sd, 0x81, 0xef, 0x10);
54450f59 857
ccbd5bc4 858 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
54450f59
HV		 859 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
860 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
861 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
862 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
ccbd5bc4 863 break;
54450f59
HV		 864 }
865
866 /* active video - horizontal timing */
54450f59 867 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
ccbd5bc4
HV		 868 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
869 ((cp_start_eav >> 8) & 0x0f));
54450f59
HV		 870 cp_write(sd, 0xa4, cp_start_eav & 0xff);
871
872 /* active video - vertical timing */
54450f59 873 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
ccbd5bc4
HV		 874 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
875 ((cp_end_vbi >> 8) & 0xf));
54450f59 876 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
ccbd5bc4
HV		 877 break;
878 case ADV7604_MODE_HDMI:
879 /* set default prim_mode/vid_std for HDMI
f58c91ce 880 according to [REF_03, c. 4.2] */
ccbd5bc4
HV		 881 io_write(sd, 0x00, 0x02); /* video std */
882 io_write(sd, 0x01, 0x06); /* prim mode */
883 break;
884 default:
885 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
886 __func__, state->mode);
887 break;
54450f59 888 }
54450f59 889
ccbd5bc4
HV		 890 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
891 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
892 cp_write(sd, 0xab, (height >> 4) & 0xff);
893 cp_write(sd, 0xac, (height & 0x0f) << 4);
894}
54450f59
HV		 895
896static void set_rgb_quantization_range(struct v4l2_subdev *sd)
897{
898 struct adv7604_state *state = to_state(sd);
899
900 switch (state->rgb_quantization_range) {
901 case V4L2_DV_RGB_RANGE_AUTO:
902 /* automatic */
6b0d5d34 903 if (DIGITAL_INPUT && !(hdmi_read(sd, 0x05) & 0x80)) {
54450f59
HV		 904 /* receiving DVI-D signal */
905
906 /* ADV7604 selects RGB limited range regardless of
907 input format (CE/IT) in automatic mode */
908 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
909 /* RGB limited range (16-235) */
910 io_write_and_or(sd, 0x02, 0x0f, 0x00);
911
912 } else {
913 /* RGB full range (0-255) */
914 io_write_and_or(sd, 0x02, 0x0f, 0x10);
915 }
6b0d5d34
HV		 916 } else {
917 /* receiving HDMI or analog signal, set automode */
918 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
54450f59
HV		 919 }
920 break;
921 case V4L2_DV_RGB_RANGE_LIMITED:
922 /* RGB limited range (16-235) */
923 io_write_and_or(sd, 0x02, 0x0f, 0x00);
924 break;
925 case V4L2_DV_RGB_RANGE_FULL:
926 /* RGB full range (0-255) */
927 io_write_and_or(sd, 0x02, 0x0f, 0x10);
928 break;
929 }
930}
931
932
933static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl)
934{
935 struct v4l2_subdev *sd = to_sd(ctrl);
936 struct adv7604_state *state = to_state(sd);
937
938 switch (ctrl->id) {
939 case V4L2_CID_BRIGHTNESS:
940 cp_write(sd, 0x3c, ctrl->val);
941 return 0;
942 case V4L2_CID_CONTRAST:
943 cp_write(sd, 0x3a, ctrl->val);
944 return 0;
945 case V4L2_CID_SATURATION:
946 cp_write(sd, 0x3b, ctrl->val);
947 return 0;
948 case V4L2_CID_HUE:
949 cp_write(sd, 0x3d, ctrl->val);
950 return 0;
951 case V4L2_CID_DV_RX_RGB_RANGE:
952 state->rgb_quantization_range = ctrl->val;
953 set_rgb_quantization_range(sd);
954 return 0;
955 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
956 /* Set the analog sampling phase. This is needed to find the
957 best sampling phase for analog video: an application or
958 driver has to try a number of phases and analyze the picture
959 quality before settling on the best performing phase. */
960 afe_write(sd, 0xc8, ctrl->val);
961 return 0;
962 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
963 /* Use the default blue color for free running mode,
964 or supply your own. */
965 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
966 return 0;
967 case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
968 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
969 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
970 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
971 return 0;
972 }
973 return -EINVAL;
974}
975
54450f59
HV		 976/* ----------------------------------------------------------------------- */
977
978static inline bool no_power(struct v4l2_subdev *sd)
979{
980 /* Entire chip or CP powered off */
981 return io_read(sd, 0x0c) & 0x24;
982}
983
984static inline bool no_signal_tmds(struct v4l2_subdev *sd)
985{
986 /* TODO port B, C and D */
987 return !(io_read(sd, 0x6a) & 0x10);
988}
989
990static inline bool no_lock_tmds(struct v4l2_subdev *sd)
991{
992 return (io_read(sd, 0x6a) & 0xe0) != 0xe0;
993}
994
bb88f325
MB		 995static inline bool is_hdmi(struct v4l2_subdev *sd)
996{
997 return hdmi_read(sd, 0x05) & 0x80;
998}
999
54450f59
HV		 1000static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1001{
1002 /* TODO channel 2 */
1003 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1004}
1005
1006static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1007{
1008 /* TODO channel 2 */
1009 return !(cp_read(sd, 0xb1) & 0x80);
1010}
1011
1012static inline bool no_signal(struct v4l2_subdev *sd)
1013{
1014 struct adv7604_state *state = to_state(sd);
1015 bool ret;
1016
1017 ret = no_power(sd);
1018
1019 ret |= no_lock_stdi(sd);
1020 ret |= no_lock_sspd(sd);
1021
1022 if (DIGITAL_INPUT) {
1023 ret |= no_lock_tmds(sd);
1024 ret |= no_signal_tmds(sd);
1025 }
1026
1027 return ret;
1028}
1029
1030static inline bool no_lock_cp(struct v4l2_subdev *sd)
1031{
1032 /* CP has detected a non standard number of lines on the incoming
1033 video compared to what it is configured to receive by s_dv_timings */
1034 return io_read(sd, 0x12) & 0x01;
1035}
1036
1037static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status)
1038{
1039 struct adv7604_state *state = to_state(sd);
1040
1041 *status = 0;
1042 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1043 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1044 if (no_lock_cp(sd))
1045 *status |= DIGITAL_INPUT ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1046
1047 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1048
1049 return 0;
1050}
1051
1052/* ----------------------------------------------------------------------- */
1053
54450f59
HV		 1054struct stdi_readback {
1055 u16 bl, lcf, lcvs;
1056 u8 hs_pol, vs_pol;
1057 bool interlaced;
1058};
1059
1060static int stdi2dv_timings(struct v4l2_subdev *sd,
1061 struct stdi_readback *stdi,
1062 struct v4l2_dv_timings *timings)
1063{
1064 struct adv7604_state *state = to_state(sd);
1065 u32 hfreq = (ADV7604_fsc * 8) / stdi->bl;
1066 u32 pix_clk;
1067 int i;
1068
1069 for (i = 0; adv7604_timings[i].bt.height; i++) {
1070 if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1)
1071 continue;
1072 if (adv7604_timings[i].bt.vsync != stdi->lcvs)
1073 continue;
1074
1075 pix_clk = hfreq * htotal(&adv7604_timings[i].bt);
1076
1077 if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) &&
1078 (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) {
1079 *timings = adv7604_timings[i];
1080 return 0;
1081 }
1082 }
1083
1084 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1085 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1086 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1087 timings))
1088 return 0;
1089 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1090 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1091 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1092 state->aspect_ratio, timings))
1093 return 0;
1094
ccbd5bc4
HV		 1095 v4l2_dbg(2, debug, sd,
1096 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1097 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1098 stdi->hs_pol, stdi->vs_pol);
54450f59
HV		 1099 return -1;
1100}
1101
1102static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1103{
1104 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1105 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1106 return -1;
1107 }
1108
1109 /* read STDI */
1110 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1111 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1112 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1113 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1114
1115 /* read SSPD */
1116 if ((cp_read(sd, 0xb5) & 0x03) == 0x01) {
1117 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1118 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1119 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1120 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1121 } else {
1122 stdi->hs_pol = 'x';
1123 stdi->vs_pol = 'x';
1124 }
1125
1126 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1127 v4l2_dbg(2, debug, sd,
1128 "%s: signal lost during readout of STDI/SSPD\n", __func__);
1129 return -1;
1130 }
1131
1132 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1133 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1134 memset(stdi, 0, sizeof(struct stdi_readback));
1135 return -1;
1136 }
1137
1138 v4l2_dbg(2, debug, sd,
1139 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1140 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1141 stdi->hs_pol, stdi->vs_pol,
1142 stdi->interlaced ? "interlaced" : "progressive");
1143
1144 return 0;
1145}
1146
1147static int adv7604_enum_dv_timings(struct v4l2_subdev *sd,
1148 struct v4l2_enum_dv_timings *timings)
1149{
1150 if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1)
1151 return -EINVAL;
1152 memset(timings->reserved, 0, sizeof(timings->reserved));
1153 timings->timings = adv7604_timings[timings->index];
1154 return 0;
1155}
1156
1157static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
1158 struct v4l2_dv_timings_cap *cap)
1159{
1160 struct adv7604_state *state = to_state(sd);
1161
1162 cap->type = V4L2_DV_BT_656_1120;
1163 cap->bt.max_width = 1920;
1164 cap->bt.max_height = 1200;
fe9c2564 1165 cap->bt.min_pixelclock = 25000000;
54450f59
HV		 1166 if (DIGITAL_INPUT)
1167 cap->bt.max_pixelclock = 225000000;
1168 else
1169 cap->bt.max_pixelclock = 170000000;
1170 cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1171 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1172 cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1173 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1174 return 0;
1175}
1176
1177/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1178 if the format is listed in adv7604_timings[] */
1179static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1180 struct v4l2_dv_timings *timings)
1181{
1182 struct adv7604_state *state = to_state(sd);
1183 int i;
1184
1185 for (i = 0; adv7604_timings[i].bt.width; i++) {
ef1ed8f5 1186 if (v4l2_match_dv_timings(timings, &adv7604_timings[i],
54450f59
HV		 1187 DIGITAL_INPUT ? 250000 : 1000000)) {
1188 *timings = adv7604_timings[i];
1189 break;
1190 }
1191 }
1192}
1193
1194static int adv7604_query_dv_timings(struct v4l2_subdev *sd,
1195 struct v4l2_dv_timings *timings)
1196{
1197 struct adv7604_state *state = to_state(sd);
1198 struct v4l2_bt_timings *bt = &timings->bt;
1199 struct stdi_readback stdi;
1200
1201 if (!timings)
1202 return -EINVAL;
1203
1204 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1205
1206 if (no_signal(sd)) {
1207 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1208 return -ENOLINK;
1209 }
1210
1211 /* read STDI */
1212 if (read_stdi(sd, &stdi)) {
1213 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1214 return -ENOLINK;
1215 }
1216 bt->interlaced = stdi.interlaced ?
1217 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1218
1219 if (DIGITAL_INPUT) {
bb88f325
MB		 1220 uint32_t freq;
1221
54450f59
HV		 1222 timings->type = V4L2_DV_BT_656_1120;
1223
1224 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1225 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
bb88f325 1226 freq = (hdmi_read(sd, 0x06) * 1000000) +
54450f59 1227 ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000;
bb88f325
MB		 1228 if (is_hdmi(sd)) {
1229 /* adjust for deep color mode */
1230 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1231
1232 freq = freq * 8 / bits_per_channel;
1233 }
1234 bt->pixelclock = freq;
54450f59
HV		 1235 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1236 hdmi_read(sd, 0x21);
1237 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1238 hdmi_read(sd, 0x23);
1239 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1240 hdmi_read(sd, 0x25);
1241 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1242 hdmi_read(sd, 0x2b)) / 2;
1243 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1244 hdmi_read(sd, 0x2f)) / 2;
1245 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1246 hdmi_read(sd, 0x33)) / 2;
1247 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1248 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1249 if (bt->interlaced == V4L2_DV_INTERLACED) {
1250 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1251 hdmi_read(sd, 0x0c);
1252 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1253 hdmi_read(sd, 0x2d)) / 2;
1254 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1255 hdmi_read(sd, 0x31)) / 2;
1256 bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1257 hdmi_read(sd, 0x35)) / 2;
1258 }
1259 adv7604_fill_optional_dv_timings_fields(sd, timings);
1260 } else {
1261 /* find format
80939647 1262 * Since LCVS values are inaccurate [REF_03, p. 275-276],
54450f59
HV		 1263 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1264 */
1265 if (!stdi2dv_timings(sd, &stdi, timings))
1266 goto found;
1267 stdi.lcvs += 1;
1268 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1269 if (!stdi2dv_timings(sd, &stdi, timings))
1270 goto found;
1271 stdi.lcvs -= 2;
1272 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1273 if (stdi2dv_timings(sd, &stdi, timings)) {
cf9afb1d
HV		 1274 /*
1275 * The STDI block may measure wrong values, especially
1276 * for lcvs and lcf. If the driver can not find any
1277 * valid timing, the STDI block is restarted to measure
1278 * the video timings again. The function will return an
1279 * error, but the restart of STDI will generate a new
1280 * STDI interrupt and the format detection process will
1281 * restart.
1282 */
1283 if (state->restart_stdi_once) {
1284 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1285 /* TODO restart STDI for Sync Channel 2 */
1286 /* enter one-shot mode */
1287 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1288 /* trigger STDI restart */
1289 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1290 /* reset to continuous mode */
1291 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1292 state->restart_stdi_once = false;
1293 return -ENOLINK;
1294 }
54450f59
HV		 1295 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1296 return -ERANGE;
1297 }
cf9afb1d 1298 state->restart_stdi_once = true;
54450f59
HV		 1299 }
1300found:
1301
1302 if (no_signal(sd)) {
1303 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1304 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1305 return -ENOLINK;
1306 }
1307
1308 if ((!DIGITAL_INPUT && bt->pixelclock > 170000000) ||
1309 (DIGITAL_INPUT && bt->pixelclock > 225000000)) {
1310 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1311 __func__, (u32)bt->pixelclock);
1312 return -ERANGE;
1313 }
1314
1315 if (debug > 1)
11d034c8
HV		 1316 v4l2_print_dv_timings(sd->name, "adv7604_query_dv_timings: ",
1317 timings, true);
54450f59
HV		 1318
1319 return 0;
1320}
1321
1322static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
1323 struct v4l2_dv_timings *timings)
1324{
1325 struct adv7604_state *state = to_state(sd);
1326 struct v4l2_bt_timings *bt;
ccbd5bc4 1327 int err;
54450f59
HV		 1328
1329 if (!timings)
1330 return -EINVAL;
1331
1332 bt = &timings->bt;
1333
1334 if ((!DIGITAL_INPUT && bt->pixelclock > 170000000) ||
1335 (DIGITAL_INPUT && bt->pixelclock > 225000000)) {
1336 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1337 __func__, (u32)bt->pixelclock);
1338 return -ERANGE;
1339 }
ccbd5bc4 1340
54450f59
HV		 1341 adv7604_fill_optional_dv_timings_fields(sd, timings);
1342
1343 state->timings = *timings;
1344
ccbd5bc4
HV		 1345 cp_write(sd, 0x91, bt->interlaced ? 0x50 : 0x10);
1346
1347 /* Use prim_mode and vid_std when available */
1348 err = configure_predefined_video_timings(sd, timings);
1349 if (err) {
1350 /* custom settings when the video format
1351 does not have prim_mode/vid_std */
1352 configure_custom_video_timings(sd, bt);
1353 }
54450f59
HV		 1354
1355 set_rgb_quantization_range(sd);
1356
1357
1358 if (debug > 1)
11d034c8
HV		 1359 v4l2_print_dv_timings(sd->name, "adv7604_s_dv_timings: ",
1360 timings, true);
54450f59
HV		 1361 return 0;
1362}
1363
1364static int adv7604_g_dv_timings(struct v4l2_subdev *sd,
1365 struct v4l2_dv_timings *timings)
1366{
1367 struct adv7604_state *state = to_state(sd);
1368
1369 *timings = state->timings;
1370 return 0;
1371}
1372
6b0d5d34 1373static void enable_input(struct v4l2_subdev *sd)
54450f59 1374{
6b0d5d34
HV		 1375 struct adv7604_state *state = to_state(sd);
1376
1377 switch (state->mode) {
1378 case ADV7604_MODE_COMP:
1379 case ADV7604_MODE_GR:
54450f59
HV		 1380 /* enable */
1381 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1382 break;
6b0d5d34 1383 case ADV7604_MODE_HDMI:
54450f59
HV		 1384 /* enable */
1385 hdmi_write(sd, 0x1a, 0x0a); /* Unmute audio */
1386 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1387 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
1388 break;
1389 default:
6b0d5d34
HV		 1390 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1391 __func__, state->mode);
54450f59
HV		 1392 break;
1393 }
1394}
1395
1396static void disable_input(struct v4l2_subdev *sd)
1397{
1398 /* disable */
1399 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
1400 hdmi_write(sd, 0x1a, 0x1a); /* Mute audio */
1401 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1402}
1403
6b0d5d34 1404static void select_input(struct v4l2_subdev *sd)
54450f59 1405{
6b0d5d34 1406 struct adv7604_state *state = to_state(sd);
54450f59 1407
6b0d5d34
HV		 1408 switch (state->mode) {
1409 case ADV7604_MODE_COMP:
1410 case ADV7604_MODE_GR:
54450f59
HV		 1411 /* reset ADI recommended settings for HDMI: */
1412 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1413 hdmi_write(sd, 0x0d, 0x04); /* HDMI filter optimization */
1414 hdmi_write(sd, 0x3d, 0x00); /* DDC bus active pull-up control */
1415 hdmi_write(sd, 0x3e, 0x74); /* TMDS PLL optimization */
1416 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1417 hdmi_write(sd, 0x57, 0x74); /* TMDS PLL optimization */
1418 hdmi_write(sd, 0x58, 0x63); /* TMDS PLL optimization */
1419 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1420 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1421 hdmi_write(sd, 0x93, 0x88); /* equaliser */
1422 hdmi_write(sd, 0x94, 0x2e); /* equaliser */
1423 hdmi_write(sd, 0x96, 0x00); /* enable automatic EQ changing */
1424
1425 afe_write(sd, 0x00, 0x08); /* power up ADC */
1426 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1427 afe_write(sd, 0xc8, 0x00); /* phase control */
1428
1429 /* set ADI recommended settings for digitizer */
1430 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1431 afe_write(sd, 0x12, 0x7b); /* ADC noise shaping filter controls */
1432 afe_write(sd, 0x0c, 0x1f); /* CP core gain controls */
1433 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1434 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1435 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1436 break;
1437
6b0d5d34 1438 case ADV7604_MODE_HDMI:
54450f59
HV		 1439 /* set ADI recommended settings for HDMI: */
1440 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1441 hdmi_write(sd, 0x0d, 0x84); /* HDMI filter optimization */
1442 hdmi_write(sd, 0x3d, 0x10); /* DDC bus active pull-up control */
1443 hdmi_write(sd, 0x3e, 0x39); /* TMDS PLL optimization */
1444 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1445 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1446 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1447 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1448 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1449 hdmi_write(sd, 0x93, 0x8b); /* equaliser */
1450 hdmi_write(sd, 0x94, 0x2d); /* equaliser */
1451 hdmi_write(sd, 0x96, 0x01); /* enable automatic EQ changing */
1452
1453 afe_write(sd, 0x00, 0xff); /* power down ADC */
1454 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1455 afe_write(sd, 0xc8, 0x40); /* phase control */
1456
1457 /* reset ADI recommended settings for digitizer */
1458 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1459 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1460 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1461 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1462 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1463 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1464
1465 break;
1466 default:
6b0d5d34
HV		 1467 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1468 __func__, state->mode);
54450f59
HV		 1469 break;
1470 }
1471}
1472
1473static int adv7604_s_routing(struct v4l2_subdev *sd,
1474 u32 input, u32 output, u32 config)
1475{
1476 struct adv7604_state *state = to_state(sd);
1477
1478 v4l2_dbg(2, debug, sd, "%s: input %d", __func__, input);
1479
6b0d5d34 1480 state->mode = input;
54450f59
HV		 1481
1482 disable_input(sd);
1483
6b0d5d34 1484 select_input(sd);
54450f59 1485
6b0d5d34 1486 enable_input(sd);
54450f59
HV		 1487
1488 return 0;
1489}
1490
1491static int adv7604_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1492 enum v4l2_mbus_pixelcode *code)
1493{
1494 if (index)
1495 return -EINVAL;
1496 /* Good enough for now */
1497 *code = V4L2_MBUS_FMT_FIXED;
1498 return 0;
1499}
1500
1501static int adv7604_g_mbus_fmt(struct v4l2_subdev *sd,
1502 struct v4l2_mbus_framefmt *fmt)
1503{
1504 struct adv7604_state *state = to_state(sd);
1505
1506 fmt->width = state->timings.bt.width;
1507 fmt->height = state->timings.bt.height;
1508 fmt->code = V4L2_MBUS_FMT_FIXED;
1509 fmt->field = V4L2_FIELD_NONE;
1510 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1511 fmt->colorspace = (state->timings.bt.height <= 576) ?
1512 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1513 }
1514 return 0;
1515}
1516
1517static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1518{
1519 struct adv7604_state *state = to_state(sd);
1520 u8 fmt_change, fmt_change_digital, tx_5v;
25a64ac9 1521 u32 input_status;
54450f59
HV		 1522
1523 /* format change */
1524 fmt_change = io_read(sd, 0x43) & 0x98;
1525 if (fmt_change)
1526 io_write(sd, 0x44, fmt_change);
1527 fmt_change_digital = DIGITAL_INPUT ? (io_read(sd, 0x6b) & 0xc0) : 0;
1528 if (fmt_change_digital)
1529 io_write(sd, 0x6c, fmt_change_digital);
1530 if (fmt_change || fmt_change_digital) {
1531 v4l2_dbg(1, debug, sd,
25a64ac9 1532 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
54450f59 1533 __func__, fmt_change, fmt_change_digital);
25a64ac9
MR		 1534
1535 adv7604_g_input_status(sd, &input_status);
1536 if (input_status != state->prev_input_status) {
1537 v4l2_dbg(1, debug, sd,
1538 "%s: input_status = 0x%x, prev_input_status = 0x%x\n",
1539 __func__, input_status, state->prev_input_status);
1540 state->prev_input_status = input_status;
1541 v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL);
1542 }
1543
54450f59
HV		 1544 if (handled)
1545 *handled = true;
1546 }
1547 /* tx 5v detect */
1548 tx_5v = io_read(sd, 0x70) & 0x10;
1549 if (tx_5v) {
1550 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1551 io_write(sd, 0x71, tx_5v);
1552 adv7604_s_detect_tx_5v_ctrl(sd);
1553 if (handled)
1554 *handled = true;
1555 }
1556 return 0;
1557}
1558
1559static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1560{
1561 struct adv7604_state *state = to_state(sd);
1562
1563 if (edid->pad != 0)
1564 return -EINVAL;
1565 if (edid->blocks == 0)
1566 return -EINVAL;
1567 if (edid->start_block >= state->edid_blocks)
1568 return -EINVAL;
1569 if (edid->start_block + edid->blocks > state->edid_blocks)
1570 edid->blocks = state->edid_blocks - edid->start_block;
1571 if (!edid->edid)
1572 return -EINVAL;
1573 memcpy(edid->edid + edid->start_block * 128,
1574 state->edid + edid->start_block * 128,
1575 edid->blocks * 128);
1576 return 0;
1577}
1578
1579static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1580{
1581 struct adv7604_state *state = to_state(sd);
1582 int err;
1583
1584 if (edid->pad != 0)
1585 return -EINVAL;
1586 if (edid->start_block != 0)
1587 return -EINVAL;
1588 if (edid->blocks == 0) {
1589 /* Pull down the hotplug pin */
1590 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)0);
1591 /* Disables I2C access to internal EDID ram from DDC port */
1592 rep_write_and_or(sd, 0x77, 0xf0, 0x0);
1593 state->edid_blocks = 0;
1594 /* Fall back to a 16:9 aspect ratio */
1595 state->aspect_ratio.numerator = 16;
1596 state->aspect_ratio.denominator = 9;
1597 return 0;
1598 }
1599 if (edid->blocks > 2)
1600 return -E2BIG;
1601 if (!edid->edid)
1602 return -EINVAL;
1603 memcpy(state->edid, edid->edid, 128 * edid->blocks);
1604 state->edid_blocks = edid->blocks;
1605 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
1606 edid->edid[0x16]);
1607 err = edid_write_block(sd, 128 * edid->blocks, state->edid);
1608 if (err < 0)
1609 v4l2_err(sd, "error %d writing edid\n", err);
1610 return err;
1611}
1612
1613/*********** avi info frame CEA-861-E **************/
1614
1615static void print_avi_infoframe(struct v4l2_subdev *sd)
1616{
1617 int i;
1618 u8 buf[14];
1619 u8 avi_len;
1620 u8 avi_ver;
1621
bb88f325 1622 if (!is_hdmi(sd)) {
54450f59
HV		 1623 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
1624 return;
1625 }
1626 if (!(io_read(sd, 0x60) & 0x01)) {
1627 v4l2_info(sd, "AVI infoframe not received\n");
1628 return;
1629 }
1630
1631 if (io_read(sd, 0x83) & 0x01) {
1632 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
1633 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1634 if (io_read(sd, 0x83) & 0x01) {
1635 v4l2_info(sd, "AVI infoframe checksum error still present\n");
1636 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1637 }
1638 }
1639
1640 avi_len = infoframe_read(sd, 0xe2);
1641 avi_ver = infoframe_read(sd, 0xe1);
1642 v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
1643 avi_ver, avi_len);
1644
1645 if (avi_ver != 0x02)
1646 return;
1647
1648 for (i = 0; i < 14; i++)
1649 buf[i] = infoframe_read(sd, i);
1650
1651 v4l2_info(sd,
1652 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
1653 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
1654 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
1655}
1656
1657static int adv7604_log_status(struct v4l2_subdev *sd)
1658{
1659 struct adv7604_state *state = to_state(sd);
1660 struct v4l2_dv_timings timings;
1661 struct stdi_readback stdi;
1662 u8 reg_io_0x02 = io_read(sd, 0x02);
1663
1664 char *csc_coeff_sel_rb[16] = {
1665 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
1666 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
1667 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
1668 "reserved", "reserved", "reserved", "reserved", "manual"
1669 };
1670 char *input_color_space_txt[16] = {
1671 "RGB limited range (16-235)", "RGB full range (0-255)",
1672 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
1673 "XvYCC Bt.601", "XvYCC Bt.709",
1674 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
1675 "invalid", "invalid", "invalid", "invalid", "invalid",
1676 "invalid", "invalid", "automatic"
1677 };
1678 char *rgb_quantization_range_txt[] = {
1679 "Automatic",
1680 "RGB limited range (16-235)",
1681 "RGB full range (0-255)",
1682 };
bb88f325
MB		 1683 char *deep_color_mode_txt[4] = {
1684 "8-bits per channel",
1685 "10-bits per channel",
1686 "12-bits per channel",
1687 "16-bits per channel (not supported)"
1688 };
54450f59
HV		 1689
1690 v4l2_info(sd, "-----Chip status-----\n");
1691 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
1692 v4l2_info(sd, "Connector type: %s\n", state->connector_hdmi ?
1693 "HDMI" : (DIGITAL_INPUT ? "DVI-D" : "DVI-A"));
1694 v4l2_info(sd, "EDID: %s\n", ((rep_read(sd, 0x7d) & 0x01) &&
1695 (rep_read(sd, 0x77) & 0x01)) ? "enabled" : "disabled ");
1696 v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
1697 "enabled" : "disabled");
1698
1699 v4l2_info(sd, "-----Signal status-----\n");
1700 v4l2_info(sd, "Cable detected (+5V power): %s\n",
1701 (io_read(sd, 0x6f) & 0x10) ? "true" : "false");
1702 v4l2_info(sd, "TMDS signal detected: %s\n",
1703 no_signal_tmds(sd) ? "false" : "true");
1704 v4l2_info(sd, "TMDS signal locked: %s\n",
1705 no_lock_tmds(sd) ? "false" : "true");
1706 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
1707 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
1708 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
1709 v4l2_info(sd, "CP free run: %s\n",
1710 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
ccbd5bc4
HV		 1711 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
1712 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
1713 (io_read(sd, 0x01) & 0x70) >> 4);
54450f59
HV		 1714
1715 v4l2_info(sd, "-----Video Timings-----\n");
1716 if (read_stdi(sd, &stdi))
1717 v4l2_info(sd, "STDI: not locked\n");
1718 else
1719 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
1720 stdi.lcf, stdi.bl, stdi.lcvs,
1721 stdi.interlaced ? "interlaced" : "progressive",
1722 stdi.hs_pol, stdi.vs_pol);
1723 if (adv7604_query_dv_timings(sd, &timings))
1724 v4l2_info(sd, "No video detected\n");
1725 else
11d034c8
HV		 1726 v4l2_print_dv_timings(sd->name, "Detected format: ",
1727 &timings, true);
1728 v4l2_print_dv_timings(sd->name, "Configured format: ",
1729 &state->timings, true);
54450f59 1730
76eb2d30
MR		 1731 if (no_signal(sd))
1732 return 0;
1733
54450f59
HV		 1734 v4l2_info(sd, "-----Color space-----\n");
1735 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
1736 rgb_quantization_range_txt[state->rgb_quantization_range]);
1737 v4l2_info(sd, "Input color space: %s\n",
1738 input_color_space_txt[reg_io_0x02 >> 4]);
1739 v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
1740 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
1741 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
1742 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
76eb2d30 1743 "enabled" : "disabled");
54450f59
HV		 1744 v4l2_info(sd, "Color space conversion: %s\n",
1745 csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]);
1746
76eb2d30
MR		 1747 if (!DIGITAL_INPUT)
1748 return 0;
1749
1750 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
1751 v4l2_info(sd, "HDCP encrypted content: %s\n", (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
1752 v4l2_info(sd, "HDCP keys read: %s%s\n",
1753 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
1754 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
1755 if (!is_hdmi(sd)) {
1756 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
1757 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
1758 bool audio_mute = io_read(sd, 0x65) & 0x40;
1759
1760 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
1761 audio_pll_locked ? "locked" : "not locked",
1762 audio_sample_packet_detect ? "detected" : "not detected",
1763 audio_mute ? "muted" : "enabled");
1764 if (audio_pll_locked && audio_sample_packet_detect) {
1765 v4l2_info(sd, "Audio format: %s\n",
1766 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
1767 }
1768 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
1769 (hdmi_read(sd, 0x5c) << 8) +
1770 (hdmi_read(sd, 0x5d) & 0xf0));
1771 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
1772 (hdmi_read(sd, 0x5e) << 8) +
1773 hdmi_read(sd, 0x5f));
1774 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
1775
1776 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
1777
54450f59
HV		 1778 print_avi_infoframe(sd);
1779 }
1780
1781 return 0;
1782}
1783
1784/* ----------------------------------------------------------------------- */
1785
1786static const struct v4l2_ctrl_ops adv7604_ctrl_ops = {
1787 .s_ctrl = adv7604_s_ctrl,
1788};
1789
1790static const struct v4l2_subdev_core_ops adv7604_core_ops = {
1791 .log_status = adv7604_log_status,
1792 .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
1793 .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
1794 .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
1795 .g_ctrl = v4l2_subdev_g_ctrl,
1796 .s_ctrl = v4l2_subdev_s_ctrl,
1797 .queryctrl = v4l2_subdev_queryctrl,
1798 .querymenu = v4l2_subdev_querymenu,
54450f59
HV		 1799 .interrupt_service_routine = adv7604_isr,
1800#ifdef CONFIG_VIDEO_ADV_DEBUG
1801 .g_register = adv7604_g_register,
1802 .s_register = adv7604_s_register,
1803#endif
1804};
1805
1806static const struct v4l2_subdev_video_ops adv7604_video_ops = {
1807 .s_routing = adv7604_s_routing,
1808 .g_input_status = adv7604_g_input_status,
1809 .s_dv_timings = adv7604_s_dv_timings,
1810 .g_dv_timings = adv7604_g_dv_timings,
1811 .query_dv_timings = adv7604_query_dv_timings,
1812 .enum_dv_timings = adv7604_enum_dv_timings,
1813 .dv_timings_cap = adv7604_dv_timings_cap,
1814 .enum_mbus_fmt = adv7604_enum_mbus_fmt,
1815 .g_mbus_fmt = adv7604_g_mbus_fmt,
1816 .try_mbus_fmt = adv7604_g_mbus_fmt,
1817 .s_mbus_fmt = adv7604_g_mbus_fmt,
1818};
1819
1820static const struct v4l2_subdev_pad_ops adv7604_pad_ops = {
1821 .get_edid = adv7604_get_edid,
1822 .set_edid = adv7604_set_edid,
1823};
1824
1825static const struct v4l2_subdev_ops adv7604_ops = {
1826 .core = &adv7604_core_ops,
1827 .video = &adv7604_video_ops,
1828 .pad = &adv7604_pad_ops,
1829};
1830
1831/* -------------------------- custom ctrls ---------------------------------- */
1832
1833static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
1834 .ops = &adv7604_ctrl_ops,
1835 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
1836 .name = "Analog Sampling Phase",
1837 .type = V4L2_CTRL_TYPE_INTEGER,
1838 .min = 0,
1839 .max = 0x1f,
1840 .step = 1,
1841 .def = 0,
1842};
1843
1844static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = {
1845 .ops = &adv7604_ctrl_ops,
1846 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
1847 .name = "Free Running Color, Manual",
1848 .type = V4L2_CTRL_TYPE_BOOLEAN,
1849 .min = false,
1850 .max = true,
1851 .step = 1,
1852 .def = false,
1853};
1854
1855static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = {
1856 .ops = &adv7604_ctrl_ops,
1857 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
1858 .name = "Free Running Color",
1859 .type = V4L2_CTRL_TYPE_INTEGER,
1860 .min = 0x0,
1861 .max = 0xffffff,
1862 .step = 0x1,
1863 .def = 0x0,
1864};
1865
1866/* ----------------------------------------------------------------------- */
1867
1868static int adv7604_core_init(struct v4l2_subdev *sd)
1869{
1870 struct adv7604_state *state = to_state(sd);
1871 struct adv7604_platform_data *pdata = &state->pdata;
1872
1873 hdmi_write(sd, 0x48,
1874 (pdata->disable_pwrdnb ? 0x80 : 0) |
1875 (pdata->disable_cable_det_rst ? 0x40 : 0));
1876
1877 disable_input(sd);
1878
1879 /* power */
1880 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
1881 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
1882 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
1883
1884 /* video format */
1885 io_write_and_or(sd, 0x02, 0xf0,
1886 pdata->alt_gamma << 3 |
1887 pdata->op_656_range << 2 |
1888 pdata->rgb_out << 1 |
1889 pdata->alt_data_sat << 0);
1890 io_write(sd, 0x03, pdata->op_format_sel);
1891 io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
1892 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
1893 pdata->insert_av_codes << 2 |
1894 pdata->replicate_av_codes << 1 |
1895 pdata->invert_cbcr << 0);
1896
1897 /* TODO from platform data */
1898 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
1899 io_write(sd, 0x06, 0xa6); /* positive VS and HS */
1900 io_write(sd, 0x14, 0x7f); /* Drive strength adjusted to max */
1901 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
1902 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
1903 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
80939647 1904 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59 1905 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
80939647 1906 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59
HV		 1907 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
1908 for digital formats */
1909
1910 /* TODO from platform data */
1911 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
1912
1913 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
1914 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
1915
54450f59
HV		 1916 /* interrupts */
1917 io_write(sd, 0x40, 0xc2); /* Configure INT1 */
1918 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
1919 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
1920 io_write(sd, 0x6e, 0xc0); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
1921 io_write(sd, 0x73, 0x10); /* Enable CABLE_DET_A_ST (+5v) interrupt */
1922
1923 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
1924}
1925
1926static void adv7604_unregister_clients(struct adv7604_state *state)
1927{
1928 if (state->i2c_avlink)
1929 i2c_unregister_device(state->i2c_avlink);
1930 if (state->i2c_cec)
1931 i2c_unregister_device(state->i2c_cec);
1932 if (state->i2c_infoframe)
1933 i2c_unregister_device(state->i2c_infoframe);
1934 if (state->i2c_esdp)
1935 i2c_unregister_device(state->i2c_esdp);
1936 if (state->i2c_dpp)
1937 i2c_unregister_device(state->i2c_dpp);
1938 if (state->i2c_afe)
1939 i2c_unregister_device(state->i2c_afe);
1940 if (state->i2c_repeater)
1941 i2c_unregister_device(state->i2c_repeater);
1942 if (state->i2c_edid)
1943 i2c_unregister_device(state->i2c_edid);
1944 if (state->i2c_hdmi)
1945 i2c_unregister_device(state->i2c_hdmi);
1946 if (state->i2c_test)
1947 i2c_unregister_device(state->i2c_test);
1948 if (state->i2c_cp)
1949 i2c_unregister_device(state->i2c_cp);
1950 if (state->i2c_vdp)
1951 i2c_unregister_device(state->i2c_vdp);
1952}
1953
1954static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd,
1955 u8 addr, u8 io_reg)
1956{
1957 struct i2c_client *client = v4l2_get_subdevdata(sd);
1958
1959 if (addr)
1960 io_write(sd, io_reg, addr << 1);
1961 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
1962}
1963
1964static int adv7604_probe(struct i2c_client *client,
1965 const struct i2c_device_id *id)
1966{
1967 struct adv7604_state *state;
1968 struct adv7604_platform_data *pdata = client->dev.platform_data;
1969 struct v4l2_ctrl_handler *hdl;
1970 struct v4l2_subdev *sd;
1971 int err;
1972
1973 /* Check if the adapter supports the needed features */
1974 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1975 return -EIO;
1976 v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n",
1977 client->addr << 1);
1978
c02b211d 1979 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
54450f59
HV		 1980 if (!state) {
1981 v4l_err(client, "Could not allocate adv7604_state memory!\n");
1982 return -ENOMEM;
1983 }
1984
25a64ac9
MR		 1985 /* initialize variables */
1986 state->restart_stdi_once = true;
1987 state->prev_input_status = ~0;
1988
54450f59
HV		 1989 /* platform data */
1990 if (!pdata) {
1991 v4l_err(client, "No platform data!\n");
c02b211d 1992 return -ENODEV;
54450f59
HV		 1993 }
1994 memcpy(&state->pdata, pdata, sizeof(state->pdata));
1995
1996 sd = &state->sd;
1997 v4l2_i2c_subdev_init(sd, client, &adv7604_ops);
1998 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1999 state->connector_hdmi = pdata->connector_hdmi;
2000
2001 /* i2c access to adv7604? */
2002 if (adv_smbus_read_byte_data_check(client, 0xfb, false) != 0x68) {
2003 v4l2_info(sd, "not an adv7604 on address 0x%x\n",
2004 client->addr << 1);
c02b211d 2005 return -ENODEV;
54450f59
HV		 2006 }
2007
2008 /* control handlers */
2009 hdl = &state->hdl;
2010 v4l2_ctrl_handler_init(hdl, 9);
2011
2012 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2013 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2014 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2015 V4L2_CID_CONTRAST, 0, 255, 1, 128);
2016 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2017 V4L2_CID_SATURATION, 0, 255, 1, 128);
2018 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2019 V4L2_CID_HUE, 0, 128, 1, 0);
2020
2021 /* private controls */
2022 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
2023 V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);
54450f59
HV		 2024 state->rgb_quantization_range_ctrl =
2025 v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops,
2026 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2027 0, V4L2_DV_RGB_RANGE_AUTO);
54450f59
HV		 2028
2029 /* custom controls */
2030 state->analog_sampling_phase_ctrl =
2031 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
54450f59
HV		 2032 state->free_run_color_manual_ctrl =
2033 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL);
54450f59
HV		 2034 state->free_run_color_ctrl =
2035 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL);
54450f59
HV		 2036
2037 sd->ctrl_handler = hdl;
2038 if (hdl->error) {
2039 err = hdl->error;
2040 goto err_hdl;
2041 }
8c0eadb8
HV		 2042 state->detect_tx_5v_ctrl->is_private = true;
2043 state->rgb_quantization_range_ctrl->is_private = true;
2044 state->analog_sampling_phase_ctrl->is_private = true;
2045 state->free_run_color_manual_ctrl->is_private = true;
2046 state->free_run_color_ctrl->is_private = true;
2047
54450f59
HV		 2048 if (adv7604_s_detect_tx_5v_ctrl(sd)) {
2049 err = -ENODEV;
2050 goto err_hdl;
2051 }
2052
2053 state->i2c_avlink = adv7604_dummy_client(sd, pdata->i2c_avlink, 0xf3);
2054 state->i2c_cec = adv7604_dummy_client(sd, pdata->i2c_cec, 0xf4);
2055 state->i2c_infoframe = adv7604_dummy_client(sd, pdata->i2c_infoframe, 0xf5);
2056 state->i2c_esdp = adv7604_dummy_client(sd, pdata->i2c_esdp, 0xf6);
2057 state->i2c_dpp = adv7604_dummy_client(sd, pdata->i2c_dpp, 0xf7);
2058 state->i2c_afe = adv7604_dummy_client(sd, pdata->i2c_afe, 0xf8);
2059 state->i2c_repeater = adv7604_dummy_client(sd, pdata->i2c_repeater, 0xf9);
2060 state->i2c_edid = adv7604_dummy_client(sd, pdata->i2c_edid, 0xfa);
2061 state->i2c_hdmi = adv7604_dummy_client(sd, pdata->i2c_hdmi, 0xfb);
2062 state->i2c_test = adv7604_dummy_client(sd, pdata->i2c_test, 0xfc);
2063 state->i2c_cp = adv7604_dummy_client(sd, pdata->i2c_cp, 0xfd);
2064 state->i2c_vdp = adv7604_dummy_client(sd, pdata->i2c_vdp, 0xfe);
2065 if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe ||
2066 !state->i2c_esdp || !state->i2c_dpp || !state->i2c_afe ||
2067 !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi ||
2068 !state->i2c_test || !state->i2c_cp || !state->i2c_vdp) {
2069 err = -ENOMEM;
2070 v4l2_err(sd, "failed to create all i2c clients\n");
2071 goto err_i2c;
2072 }
2073
2074 /* work queues */
2075 state->work_queues = create_singlethread_workqueue(client->name);
2076 if (!state->work_queues) {
2077 v4l2_err(sd, "Could not create work queue\n");
2078 err = -ENOMEM;
2079 goto err_i2c;
2080 }
2081
2082 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2083 adv7604_delayed_work_enable_hotplug);
2084
2085 state->pad.flags = MEDIA_PAD_FL_SOURCE;
2086 err = media_entity_init(&sd->entity, 1, &state->pad, 0);
2087 if (err)
2088 goto err_work_queues;
2089
2090 err = adv7604_core_init(sd);
2091 if (err)
2092 goto err_entity;
2093 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2094 client->addr << 1, client->adapter->name);
2095 return 0;
2096
2097err_entity:
2098 media_entity_cleanup(&sd->entity);
2099err_work_queues:
2100 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2101 destroy_workqueue(state->work_queues);
2102err_i2c:
2103 adv7604_unregister_clients(state);
2104err_hdl:
2105 v4l2_ctrl_handler_free(hdl);
54450f59
HV		 2106 return err;
2107}
2108
2109/* ----------------------------------------------------------------------- */
2110
2111static int adv7604_remove(struct i2c_client *client)
2112{
2113 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2114 struct adv7604_state *state = to_state(sd);
2115
2116 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2117 destroy_workqueue(state->work_queues);
2118 v4l2_device_unregister_subdev(sd);
2119 media_entity_cleanup(&sd->entity);
2120 adv7604_unregister_clients(to_state(sd));
2121 v4l2_ctrl_handler_free(sd->ctrl_handler);
54450f59
HV		 2122 return 0;
2123}
2124
2125/* ----------------------------------------------------------------------- */
2126
2127static struct i2c_device_id adv7604_id[] = {
2128 { "adv7604", 0 },
2129 { }
2130};
2131MODULE_DEVICE_TABLE(i2c, adv7604_id);
2132
2133static struct i2c_driver adv7604_driver = {
2134 .driver = {
2135 .owner = THIS_MODULE,
2136 .name = "adv7604",
2137 },
2138 .probe = adv7604_probe,
2139 .remove = adv7604_remove,
2140 .id_table = adv7604_id,
2141};
2142
2143module_i2c_driver(adv7604_driver);
Linux 6.x block layer and io_uring tree(s)