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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[linux-2.6-block.git] / drivers / media / i2c / ad9389b.c
CommitLineData
117a55b6
HV		 1/*
2 * Analog Devices AD9389B/AD9889B video encoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 */
19
20/*
21 * References (c = chapter, p = page):
22 * REF_01 - Analog Devices, Programming Guide, AD9889B/AD9389B,
23 * HDMI Transitter, Rev. A, October 2010
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/slab.h>
29#include <linux/i2c.h>
30#include <linux/delay.h>
31#include <linux/videodev2.h>
32#include <linux/workqueue.h>
33#include <linux/v4l2-dv-timings.h>
34#include <media/v4l2-device.h>
117a55b6 35#include <media/v4l2-common.h>
25764158 36#include <media/v4l2-dv-timings.h>
117a55b6
HV		 37#include <media/v4l2-ctrls.h>
38#include <media/ad9389b.h>
39
40static int debug;
41module_param(debug, int, 0644);
42MODULE_PARM_DESC(debug, "debug level (0-2)");
43
44MODULE_DESCRIPTION("Analog Devices AD9389B/AD9889B video encoder driver");
45MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
46MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
47MODULE_LICENSE("GPL");
48
49#define MASK_AD9389B_EDID_RDY_INT 0x04
50#define MASK_AD9389B_MSEN_INT 0x40
51#define MASK_AD9389B_HPD_INT 0x80
52
53#define MASK_AD9389B_HPD_DETECT 0x40
54#define MASK_AD9389B_MSEN_DETECT 0x20
55#define MASK_AD9389B_EDID_RDY 0x10
56
57#define EDID_MAX_RETRIES (8)
58#define EDID_DELAY 250
59#define EDID_MAX_SEGM 8
60
61/*
62**********************************************************************
63*
64* Arrays with configuration parameters for the AD9389B
65*
66**********************************************************************
67*/
68
117a55b6
HV		 69struct ad9389b_state_edid {
70 /* total number of blocks */
71 u32 blocks;
72 /* Number of segments read */
73 u32 segments;
74 u8 data[EDID_MAX_SEGM * 256];
75 /* Number of EDID read retries left */
76 unsigned read_retries;
77};
78
79struct ad9389b_state {
80 struct ad9389b_platform_data pdata;
81 struct v4l2_subdev sd;
82 struct media_pad pad;
83 struct v4l2_ctrl_handler hdl;
84 int chip_revision;
85 /* Is the ad9389b powered on? */
86 bool power_on;
87 /* Did we receive hotplug and rx-sense signals? */
88 bool have_monitor;
89 /* timings from s_dv_timings */
90 struct v4l2_dv_timings dv_timings;
91 /* controls */
92 struct v4l2_ctrl *hdmi_mode_ctrl;
93 struct v4l2_ctrl *hotplug_ctrl;
94 struct v4l2_ctrl *rx_sense_ctrl;
95 struct v4l2_ctrl *have_edid0_ctrl;
96 struct v4l2_ctrl *rgb_quantization_range_ctrl;
97 struct i2c_client *edid_i2c_client;
98 struct ad9389b_state_edid edid;
99 /* Running counter of the number of detected EDIDs (for debugging) */
100 unsigned edid_detect_counter;
101 struct workqueue_struct *work_queue;
102 struct delayed_work edid_handler; /* work entry */
103};
104
105static void ad9389b_check_monitor_present_status(struct v4l2_subdev *sd);
106static bool ad9389b_check_edid_status(struct v4l2_subdev *sd);
107static void ad9389b_setup(struct v4l2_subdev *sd);
108static int ad9389b_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq);
109static int ad9389b_s_clock_freq(struct v4l2_subdev *sd, u32 freq);
110
111static inline struct ad9389b_state *get_ad9389b_state(struct v4l2_subdev *sd)
112{
113 return container_of(sd, struct ad9389b_state, sd);
114}
115
116static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
117{
118 return &container_of(ctrl->handler, struct ad9389b_state, hdl)->sd;
119}
120
121/* ------------------------ I2C ----------------------------------------------- */
122
123static int ad9389b_rd(struct v4l2_subdev *sd, u8 reg)
124{
125 struct i2c_client *client = v4l2_get_subdevdata(sd);
126
127 return i2c_smbus_read_byte_data(client, reg);
128}
129
130static int ad9389b_wr(struct v4l2_subdev *sd, u8 reg, u8 val)
131{
132 struct i2c_client *client = v4l2_get_subdevdata(sd);
133 int ret;
134 int i;
135
136 for (i = 0; i < 3; i++) {
137 ret = i2c_smbus_write_byte_data(client, reg, val);
138 if (ret == 0)
139 return 0;
140 }
51af70bf 141 v4l2_err(sd, "%s: failed reg 0x%x, val 0x%x\n", __func__, reg, val);
117a55b6
HV		 142 return ret;
143}
144
145/* To set specific bits in the register, a clear-mask is given (to be AND-ed),
146 and then the value-mask (to be OR-ed). */
147static inline void ad9389b_wr_and_or(struct v4l2_subdev *sd, u8 reg,
d3ec7de4 148 u8 clr_mask, u8 val_mask)
117a55b6
HV		 149{
150 ad9389b_wr(sd, reg, (ad9389b_rd(sd, reg) & clr_mask) | val_mask);
151}
152
153static void ad9389b_edid_rd(struct v4l2_subdev *sd, u16 len, u8 *buf)
154{
155 struct ad9389b_state *state = get_ad9389b_state(sd);
156 int i;
157
158 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
159
160 for (i = 0; i < len; i++)
161 buf[i] = i2c_smbus_read_byte_data(state->edid_i2c_client, i);
162}
163
164static inline bool ad9389b_have_hotplug(struct v4l2_subdev *sd)
165{
166 return ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT;
167}
168
169static inline bool ad9389b_have_rx_sense(struct v4l2_subdev *sd)
170{
171 return ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT;
172}
173
174static void ad9389b_csc_conversion_mode(struct v4l2_subdev *sd, u8 mode)
175{
176 ad9389b_wr_and_or(sd, 0x17, 0xe7, (mode & 0x3)<<3);
177 ad9389b_wr_and_or(sd, 0x18, 0x9f, (mode & 0x3)<<5);
178}
179
180static void ad9389b_csc_coeff(struct v4l2_subdev *sd,
181 u16 A1, u16 A2, u16 A3, u16 A4,
182 u16 B1, u16 B2, u16 B3, u16 B4,
183 u16 C1, u16 C2, u16 C3, u16 C4)
184{
185 /* A */
186 ad9389b_wr_and_or(sd, 0x18, 0xe0, A1>>8);
187 ad9389b_wr(sd, 0x19, A1);
188 ad9389b_wr_and_or(sd, 0x1A, 0xe0, A2>>8);
189 ad9389b_wr(sd, 0x1B, A2);
190 ad9389b_wr_and_or(sd, 0x1c, 0xe0, A3>>8);
191 ad9389b_wr(sd, 0x1d, A3);
192 ad9389b_wr_and_or(sd, 0x1e, 0xe0, A4>>8);
193 ad9389b_wr(sd, 0x1f, A4);
194
195 /* B */
196 ad9389b_wr_and_or(sd, 0x20, 0xe0, B1>>8);
197 ad9389b_wr(sd, 0x21, B1);
198 ad9389b_wr_and_or(sd, 0x22, 0xe0, B2>>8);
199 ad9389b_wr(sd, 0x23, B2);
200 ad9389b_wr_and_or(sd, 0x24, 0xe0, B3>>8);
201 ad9389b_wr(sd, 0x25, B3);
202 ad9389b_wr_and_or(sd, 0x26, 0xe0, B4>>8);
203 ad9389b_wr(sd, 0x27, B4);
204
205 /* C */
206 ad9389b_wr_and_or(sd, 0x28, 0xe0, C1>>8);
207 ad9389b_wr(sd, 0x29, C1);
208 ad9389b_wr_and_or(sd, 0x2A, 0xe0, C2>>8);
209 ad9389b_wr(sd, 0x2B, C2);
210 ad9389b_wr_and_or(sd, 0x2C, 0xe0, C3>>8);
211 ad9389b_wr(sd, 0x2D, C3);
212 ad9389b_wr_and_or(sd, 0x2E, 0xe0, C4>>8);
213 ad9389b_wr(sd, 0x2F, C4);
214}
215
216static void ad9389b_csc_rgb_full2limit(struct v4l2_subdev *sd, bool enable)
217{
218 if (enable) {
219 u8 csc_mode = 0;
220
221 ad9389b_csc_conversion_mode(sd, csc_mode);
222 ad9389b_csc_coeff(sd,
223 4096-564, 0, 0, 256,
224 0, 4096-564, 0, 256,
225 0, 0, 4096-564, 256);
226 /* enable CSC */
227 ad9389b_wr_and_or(sd, 0x3b, 0xfe, 0x1);
228 /* AVI infoframe: Limited range RGB (16-235) */
229 ad9389b_wr_and_or(sd, 0xcd, 0xf9, 0x02);
230 } else {
231 /* disable CSC */
232 ad9389b_wr_and_or(sd, 0x3b, 0xfe, 0x0);
233 /* AVI infoframe: Full range RGB (0-255) */
234 ad9389b_wr_and_or(sd, 0xcd, 0xf9, 0x04);
235 }
236}
237
238static void ad9389b_set_IT_content_AVI_InfoFrame(struct v4l2_subdev *sd)
239{
240 struct ad9389b_state *state = get_ad9389b_state(sd);
241
680fee04
HV		 242 if (state->dv_timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
243 /* CE format, not IT */
117a55b6
HV		 244 ad9389b_wr_and_or(sd, 0xcd, 0xbf, 0x00);
245 } else {
246 /* IT format */
247 ad9389b_wr_and_or(sd, 0xcd, 0xbf, 0x40);
248 }
249}
250
251static int ad9389b_set_rgb_quantization_mode(struct v4l2_subdev *sd, struct v4l2_ctrl *ctrl)
252{
253 struct ad9389b_state *state = get_ad9389b_state(sd);
254
255 switch (ctrl->val) {
256 case V4L2_DV_RGB_RANGE_AUTO:
257 /* automatic */
680fee04
HV		 258 if (state->dv_timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
259 /* CE format, RGB limited range (16-235) */
117a55b6
HV		 260 ad9389b_csc_rgb_full2limit(sd, true);
261 } else {
680fee04 262 /* not CE format, RGB full range (0-255) */
117a55b6
HV		 263 ad9389b_csc_rgb_full2limit(sd, false);
264 }
265 break;
266 case V4L2_DV_RGB_RANGE_LIMITED:
267 /* RGB limited range (16-235) */
268 ad9389b_csc_rgb_full2limit(sd, true);
269 break;
270 case V4L2_DV_RGB_RANGE_FULL:
271 /* RGB full range (0-255) */
272 ad9389b_csc_rgb_full2limit(sd, false);
273 break;
274 default:
275 return -EINVAL;
276 }
277 return 0;
278}
279
280static void ad9389b_set_manual_pll_gear(struct v4l2_subdev *sd, u32 pixelclock)
281{
282 u8 gear;
283
284 /* Workaround for TMDS PLL problem
285 * The TMDS PLL in AD9389b change gear when the chip is heated above a
286 * certain temperature. The output is disabled when the PLL change gear
287 * so the monitor has to lock on the signal again. A workaround for
288 * this is to use the manual PLL gears. This is a solution from Analog
289 * Devices that is not documented in the datasheets.
290 * 0x98 [7] = enable manual gearing. 0x98 [6:4] = gear
291 *
292 * The pixel frequency ranges are based on readout of the gear the
293 * automatic gearing selects for different pixel clocks
294 * (read from 0x9e [3:1]).
295 */
296
297 if (pixelclock > 140000000)
298 gear = 0xc0; /* 4th gear */
299 else if (pixelclock > 117000000)
300 gear = 0xb0; /* 3rd gear */
301 else if (pixelclock > 87000000)
302 gear = 0xa0; /* 2nd gear */
303 else if (pixelclock > 60000000)
304 gear = 0x90; /* 1st gear */
305 else
306 gear = 0x80; /* 0th gear */
307
308 ad9389b_wr_and_or(sd, 0x98, 0x0f, gear);
309}
310
311/* ------------------------------ CTRL OPS ------------------------------ */
312
313static int ad9389b_s_ctrl(struct v4l2_ctrl *ctrl)
314{
315 struct v4l2_subdev *sd = to_sd(ctrl);
316 struct ad9389b_state *state = get_ad9389b_state(sd);
317
318 v4l2_dbg(1, debug, sd,
d3ec7de4 319 "%s: ctrl id: %d, ctrl->val %d\n", __func__, ctrl->id, ctrl->val);
117a55b6
HV		 320
321 if (state->hdmi_mode_ctrl == ctrl) {
322 /* Set HDMI or DVI-D */
323 ad9389b_wr_and_or(sd, 0xaf, 0xfd,
d3ec7de4 324 ctrl->val == V4L2_DV_TX_MODE_HDMI ? 0x02 : 0x00);
117a55b6
HV		 325 return 0;
326 }
327 if (state->rgb_quantization_range_ctrl == ctrl)
328 return ad9389b_set_rgb_quantization_mode(sd, ctrl);
329 return -EINVAL;
330}
331
332static const struct v4l2_ctrl_ops ad9389b_ctrl_ops = {
333 .s_ctrl = ad9389b_s_ctrl,
334};
335
336/* ---------------------------- CORE OPS ------------------------------------------- */
337
338#ifdef CONFIG_VIDEO_ADV_DEBUG
339static int ad9389b_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
340{
117a55b6
HV		 341 reg->val = ad9389b_rd(sd, reg->reg & 0xff);
342 reg->size = 1;
343 return 0;
344}
345
977ba3b1 346static int ad9389b_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
117a55b6 347{
117a55b6
HV		 348 ad9389b_wr(sd, reg->reg & 0xff, reg->val & 0xff);
349 return 0;
350}
351#endif
352
117a55b6
HV		 353static int ad9389b_log_status(struct v4l2_subdev *sd)
354{
355 struct ad9389b_state *state = get_ad9389b_state(sd);
356 struct ad9389b_state_edid *edid = &state->edid;
357
358 static const char * const states[] = {
359 "in reset",
360 "reading EDID",
361 "idle",
362 "initializing HDCP",
363 "HDCP enabled",
364 "initializing HDCP repeater",
365 "6", "7", "8", "9", "A", "B", "C", "D", "E", "F"
366 };
367 static const char * const errors[] = {
368 "no error",
369 "bad receiver BKSV",
370 "Ri mismatch",
371 "Pj mismatch",
372 "i2c error",
373 "timed out",
374 "max repeater cascade exceeded",
375 "hash check failed",
376 "too many devices",
377 "9", "A", "B", "C", "D", "E", "F"
378 };
379
380 u8 manual_gear;
381
382 v4l2_info(sd, "chip revision %d\n", state->chip_revision);
383 v4l2_info(sd, "power %s\n", state->power_on ? "on" : "off");
384 v4l2_info(sd, "%s hotplug, %s Rx Sense, %s EDID (%d block(s))\n",
d3ec7de4
MB		 385 (ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT) ?
386 "detected" : "no",
387 (ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT) ?
388 "detected" : "no",
389 edid->segments ? "found" : "no", edid->blocks);
51af70bf
MB		 390 v4l2_info(sd, "%s output %s\n",
391 (ad9389b_rd(sd, 0xaf) & 0x02) ?
392 "HDMI" : "DVI-D",
393 (ad9389b_rd(sd, 0xa1) & 0x3c) ?
394 "disabled" : "enabled");
117a55b6 395 v4l2_info(sd, "ad9389b: %s\n", (ad9389b_rd(sd, 0xb8) & 0x40) ?
d3ec7de4 396 "encrypted" : "no encryption");
117a55b6 397 v4l2_info(sd, "state: %s, error: %s, detect count: %u, msk/irq: %02x/%02x\n",
d3ec7de4
MB		 398 states[ad9389b_rd(sd, 0xc8) & 0xf],
399 errors[ad9389b_rd(sd, 0xc8) >> 4],
400 state->edid_detect_counter,
401 ad9389b_rd(sd, 0x94), ad9389b_rd(sd, 0x96));
117a55b6
HV		 402 manual_gear = ad9389b_rd(sd, 0x98) & 0x80;
403 v4l2_info(sd, "ad9389b: RGB quantization: %s range\n",
d3ec7de4 404 ad9389b_rd(sd, 0x3b) & 0x01 ? "limited" : "full");
117a55b6
HV		 405 v4l2_info(sd, "ad9389b: %s gear %d\n",
406 manual_gear ? "manual" : "automatic",
407 manual_gear ? ((ad9389b_rd(sd, 0x98) & 0x70) >> 4) :
d3ec7de4 408 ((ad9389b_rd(sd, 0x9e) & 0x0e) >> 1));
51af70bf
MB		 409 if (ad9389b_rd(sd, 0xaf) & 0x02) {
410 /* HDMI only */
411 u8 manual_cts = ad9389b_rd(sd, 0x0a) & 0x80;
412 u32 N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
413 ad9389b_rd(sd, 0x02) << 8 |
414 ad9389b_rd(sd, 0x03);
415 u8 vic_detect = ad9389b_rd(sd, 0x3e) >> 2;
416 u8 vic_sent = ad9389b_rd(sd, 0x3d) & 0x3f;
417 u32 CTS;
418
419 if (manual_cts)
420 CTS = (ad9389b_rd(sd, 0x07) & 0xf) << 16 |
421 ad9389b_rd(sd, 0x08) << 8 |
422 ad9389b_rd(sd, 0x09);
423 else
424 CTS = (ad9389b_rd(sd, 0x04) & 0xf) << 16 |
425 ad9389b_rd(sd, 0x05) << 8 |
426 ad9389b_rd(sd, 0x06);
427 N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
428 ad9389b_rd(sd, 0x02) << 8 |
429 ad9389b_rd(sd, 0x03);
430
431 v4l2_info(sd, "ad9389b: CTS %s mode: N %d, CTS %d\n",
432 manual_cts ? "manual" : "automatic", N, CTS);
433
434 v4l2_info(sd, "ad9389b: VIC: detected %d, sent %d\n",
435 vic_detect, vic_sent);
117a55b6 436 }
11d034c8
HV		 437 if (state->dv_timings.type == V4L2_DV_BT_656_1120)
438 v4l2_print_dv_timings(sd->name, "timings: ",
439 &state->dv_timings, false);
440 else
117a55b6 441 v4l2_info(sd, "no timings set\n");
117a55b6
HV		 442 return 0;
443}
444
445/* Power up/down ad9389b */
446static int ad9389b_s_power(struct v4l2_subdev *sd, int on)
447{
448 struct ad9389b_state *state = get_ad9389b_state(sd);
449 struct ad9389b_platform_data *pdata = &state->pdata;
450 const int retries = 20;
451 int i;
452
453 v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off");
454
455 state->power_on = on;
456
457 if (!on) {
458 /* Power down */
459 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x40);
460 return true;
461 }
462
463 /* Power up */
464 /* The ad9389b does not always come up immediately.
465 Retry multiple times. */
466 for (i = 0; i < retries; i++) {
467 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x0);
468 if ((ad9389b_rd(sd, 0x41) & 0x40) == 0)
469 break;
470 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x40);
471 msleep(10);
472 }
473 if (i == retries) {
474 v4l2_dbg(1, debug, sd, "failed to powerup the ad9389b\n");
475 ad9389b_s_power(sd, 0);
476 return false;
477 }
478 if (i > 1)
479 v4l2_dbg(1, debug, sd,
d3ec7de4 480 "needed %d retries to powerup the ad9389b\n", i);
117a55b6
HV		 481
482 /* Select chip: AD9389B */
483 ad9389b_wr_and_or(sd, 0xba, 0xef, 0x10);
484
485 /* Reserved registers that must be set according to REF_01 p. 11*/
486 ad9389b_wr_and_or(sd, 0x98, 0xf0, 0x07);
487 ad9389b_wr(sd, 0x9c, 0x38);
488 ad9389b_wr_and_or(sd, 0x9d, 0xfc, 0x01);
489
490 /* Differential output drive strength */
491 if (pdata->diff_data_drive_strength > 0)
492 ad9389b_wr(sd, 0xa2, pdata->diff_data_drive_strength);
493 else
494 ad9389b_wr(sd, 0xa2, 0x87);
495
496 if (pdata->diff_clk_drive_strength > 0)
497 ad9389b_wr(sd, 0xa3, pdata->diff_clk_drive_strength);
498 else
499 ad9389b_wr(sd, 0xa3, 0x87);
500
501 ad9389b_wr(sd, 0x0a, 0x01);
502 ad9389b_wr(sd, 0xbb, 0xff);
503
504 /* Set number of attempts to read the EDID */
505 ad9389b_wr(sd, 0xc9, 0xf);
506 return true;
507}
508
509/* Enable interrupts */
510static void ad9389b_set_isr(struct v4l2_subdev *sd, bool enable)
511{
512 u8 irqs = MASK_AD9389B_HPD_INT | MASK_AD9389B_MSEN_INT;
513 u8 irqs_rd;
514 int retries = 100;
515
516 /* The datasheet says that the EDID ready interrupt should be
517 disabled if there is no hotplug. */
518 if (!enable)
519 irqs = 0;
520 else if (ad9389b_have_hotplug(sd))
521 irqs |= MASK_AD9389B_EDID_RDY_INT;
522
523 /*
524 * This i2c write can fail (approx. 1 in 1000 writes). But it
525 * is essential that this register is correct, so retry it
526 * multiple times.
527 *
528 * Note that the i2c write does not report an error, but the readback
529 * clearly shows the wrong value.
530 */
531 do {
532 ad9389b_wr(sd, 0x94, irqs);
533 irqs_rd = ad9389b_rd(sd, 0x94);
534 } while (retries-- && irqs_rd != irqs);
535
536 if (irqs_rd != irqs)
537 v4l2_err(sd, "Could not set interrupts: hw failure?\n");
538}
539
540/* Interrupt handler */
541static int ad9389b_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
542{
543 u8 irq_status;
544
545 /* disable interrupts to prevent a race condition */
546 ad9389b_set_isr(sd, false);
547 irq_status = ad9389b_rd(sd, 0x96);
548 /* clear detected interrupts */
549 ad9389b_wr(sd, 0x96, irq_status);
51af70bf
MB		 550 /* enable interrupts */
551 ad9389b_set_isr(sd, true);
117a55b6 552
51af70bf
MB		 553 v4l2_dbg(1, debug, sd, "%s: irq_status 0x%x\n", __func__, irq_status);
554
555 if (irq_status & (MASK_AD9389B_HPD_INT))
117a55b6
HV		 556 ad9389b_check_monitor_present_status(sd);
557 if (irq_status & MASK_AD9389B_EDID_RDY_INT)
558 ad9389b_check_edid_status(sd);
559
117a55b6
HV		 560 *handled = true;
561 return 0;
562}
563
564static const struct v4l2_subdev_core_ops ad9389b_core_ops = {
565 .log_status = ad9389b_log_status,
117a55b6
HV		 566#ifdef CONFIG_VIDEO_ADV_DEBUG
567 .g_register = ad9389b_g_register,
568 .s_register = ad9389b_s_register,
569#endif
570 .s_power = ad9389b_s_power,
571 .interrupt_service_routine = ad9389b_isr,
572};
573
117a55b6
HV		 574/* ------------------------------ VIDEO OPS ------------------------------ */
575
576/* Enable/disable ad9389b output */
577static int ad9389b_s_stream(struct v4l2_subdev *sd, int enable)
578{
117a55b6
HV		 579 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
580
581 ad9389b_wr_and_or(sd, 0xa1, ~0x3c, (enable ? 0 : 0x3c));
582 if (enable) {
583 ad9389b_check_monitor_present_status(sd);
584 } else {
585 ad9389b_s_power(sd, 0);
117a55b6
HV		 586 }
587 return 0;
588}
589
04164904
HV		 590static const struct v4l2_dv_timings_cap ad9389b_timings_cap = {
591 .type = V4L2_DV_BT_656_1120,
8f110d68
GG		 592 /* keep this initialization for compatibility with GCC < 4.4.6 */
593 .reserved = { 0 },
594 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
595 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
04164904 596 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
8f110d68
GG		 597 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
598 V4L2_DV_BT_CAP_CUSTOM)
117a55b6
HV		 599};
600
601static int ad9389b_s_dv_timings(struct v4l2_subdev *sd,
602 struct v4l2_dv_timings *timings)
603{
604 struct ad9389b_state *state = get_ad9389b_state(sd);
117a55b6
HV		 605
606 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
607
608 /* quick sanity check */
b8f0fff4 609 if (!v4l2_valid_dv_timings(timings, &ad9389b_timings_cap, NULL, NULL))
117a55b6
HV		 610 return -EINVAL;
611
612 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
04164904 613 if the format is one of the CEA or DMT timings. */
b8f0fff4 614 v4l2_find_dv_timings_cap(timings, &ad9389b_timings_cap, 0, NULL, NULL);
117a55b6
HV		 615
616 timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS;
617
618 /* save timings */
619 state->dv_timings = *timings;
620
621 /* update quantization range based on new dv_timings */
622 ad9389b_set_rgb_quantization_mode(sd, state->rgb_quantization_range_ctrl);
623
624 /* update PLL gear based on new dv_timings */
625 if (state->pdata.tmds_pll_gear == AD9389B_TMDS_PLL_GEAR_SEMI_AUTOMATIC)
626 ad9389b_set_manual_pll_gear(sd, (u32)timings->bt.pixelclock);
627
628 /* update AVI infoframe */
629 ad9389b_set_IT_content_AVI_InfoFrame(sd);
630
631 return 0;
632}
633
634static int ad9389b_g_dv_timings(struct v4l2_subdev *sd,
635 struct v4l2_dv_timings *timings)
636{
637 struct ad9389b_state *state = get_ad9389b_state(sd);
638
639 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
640
641 if (!timings)
642 return -EINVAL;
643
644 *timings = state->dv_timings;
645
646 return 0;
647}
648
649static int ad9389b_enum_dv_timings(struct v4l2_subdev *sd,
d3ec7de4 650 struct v4l2_enum_dv_timings *timings)
117a55b6 651{
22c25b48
LP		 652 if (timings->pad != 0)
653 return -EINVAL;
654
b8f0fff4
HV		 655 return v4l2_enum_dv_timings_cap(timings, &ad9389b_timings_cap,
656 NULL, NULL);
117a55b6
HV		 657}
658
659static int ad9389b_dv_timings_cap(struct v4l2_subdev *sd,
d3ec7de4 660 struct v4l2_dv_timings_cap *cap)
117a55b6 661{
22c25b48
LP		 662 if (cap->pad != 0)
663 return -EINVAL;
664
04164904 665 *cap = ad9389b_timings_cap;
117a55b6
HV		 666 return 0;
667}
668
669static const struct v4l2_subdev_video_ops ad9389b_video_ops = {
670 .s_stream = ad9389b_s_stream,
671 .s_dv_timings = ad9389b_s_dv_timings,
672 .g_dv_timings = ad9389b_g_dv_timings,
117a55b6
HV		 673};
674
22c25b48
LP		 675/* ------------------------------ PAD OPS ------------------------------ */
676
677static int ad9389b_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
678{
679 struct ad9389b_state *state = get_ad9389b_state(sd);
680
681 if (edid->pad != 0)
682 return -EINVAL;
683 if (edid->blocks == 0 || edid->blocks > 256)
684 return -EINVAL;
22c25b48
LP		 685 if (!state->edid.segments) {
686 v4l2_dbg(1, debug, sd, "EDID segment 0 not found\n");
687 return -ENODATA;
688 }
689 if (edid->start_block >= state->edid.segments * 2)
690 return -E2BIG;
691 if (edid->blocks + edid->start_block >= state->edid.segments * 2)
692 edid->blocks = state->edid.segments * 2 - edid->start_block;
693 memcpy(edid->edid, &state->edid.data[edid->start_block * 128],
694 128 * edid->blocks);
695 return 0;
696}
697
698static const struct v4l2_subdev_pad_ops ad9389b_pad_ops = {
699 .get_edid = ad9389b_get_edid,
700 .enum_dv_timings = ad9389b_enum_dv_timings,
701 .dv_timings_cap = ad9389b_dv_timings_cap,
702};
703
704/* ------------------------------ AUDIO OPS ------------------------------ */
705
117a55b6
HV		 706static int ad9389b_s_audio_stream(struct v4l2_subdev *sd, int enable)
707{
708 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
709
710 if (enable)
711 ad9389b_wr_and_or(sd, 0x45, 0x3f, 0x80);
712 else
713 ad9389b_wr_and_or(sd, 0x45, 0x3f, 0x40);
714
715 return 0;
716}
717
718static int ad9389b_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
719{
720 u32 N;
721
722 switch (freq) {
d3ec7de4
MB		 723 case 32000: N = 4096; break;
724 case 44100: N = 6272; break;
725 case 48000: N = 6144; break;
726 case 88200: N = 12544; break;
727 case 96000: N = 12288; break;
117a55b6
HV		 728 case 176400: N = 25088; break;
729 case 192000: N = 24576; break;
730 default:
d3ec7de4 731 return -EINVAL;
117a55b6
HV		 732 }
733
734 /* Set N (used with CTS to regenerate the audio clock) */
735 ad9389b_wr(sd, 0x01, (N >> 16) & 0xf);
736 ad9389b_wr(sd, 0x02, (N >> 8) & 0xff);
737 ad9389b_wr(sd, 0x03, N & 0xff);
738
739 return 0;
740}
741
742static int ad9389b_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq)
743{
744 u32 i2s_sf;
745
746 switch (freq) {
d3ec7de4
MB		 747 case 32000: i2s_sf = 0x30; break;
748 case 44100: i2s_sf = 0x00; break;
749 case 48000: i2s_sf = 0x20; break;
750 case 88200: i2s_sf = 0x80; break;
751 case 96000: i2s_sf = 0xa0; break;
117a55b6
HV		 752 case 176400: i2s_sf = 0xc0; break;
753 case 192000: i2s_sf = 0xe0; break;
754 default:
d3ec7de4 755 return -EINVAL;
117a55b6
HV		 756 }
757
758 /* Set sampling frequency for I2S audio to 48 kHz */
759 ad9389b_wr_and_or(sd, 0x15, 0xf, i2s_sf);
760
761 return 0;
762}
763
764static int ad9389b_s_routing(struct v4l2_subdev *sd, u32 input, u32 output, u32 config)
765{
766 /* TODO based on input/output/config */
767 /* TODO See datasheet "Programmers guide" p. 39-40 */
768
769 /* Only 2 channels in use for application */
770 ad9389b_wr_and_or(sd, 0x50, 0x1f, 0x20);
771 /* Speaker mapping */
772 ad9389b_wr(sd, 0x51, 0x00);
773
774 /* TODO Where should this be placed? */
775 /* 16 bit audio word length */
776 ad9389b_wr_and_or(sd, 0x14, 0xf0, 0x02);
777
778 return 0;
779}
780
781static const struct v4l2_subdev_audio_ops ad9389b_audio_ops = {
782 .s_stream = ad9389b_s_audio_stream,
783 .s_clock_freq = ad9389b_s_clock_freq,
784 .s_i2s_clock_freq = ad9389b_s_i2s_clock_freq,
785 .s_routing = ad9389b_s_routing,
786};
787
788/* --------------------- SUBDEV OPS --------------------------------------- */
789
790static const struct v4l2_subdev_ops ad9389b_ops = {
791 .core = &ad9389b_core_ops,
792 .video = &ad9389b_video_ops,
793 .audio = &ad9389b_audio_ops,
794 .pad = &ad9389b_pad_ops,
795};
796
797/* ----------------------------------------------------------------------- */
798static void ad9389b_dbg_dump_edid(int lvl, int debug, struct v4l2_subdev *sd,
d3ec7de4 799 int segment, u8 *buf)
117a55b6
HV		 800{
801 int i, j;
802
803 if (debug < lvl)
804 return;
805
806 v4l2_dbg(lvl, debug, sd, "edid segment %d\n", segment);
807 for (i = 0; i < 256; i += 16) {
808 u8 b[128];
809 u8 *bp = b;
810
811 if (i == 128)
812 v4l2_dbg(lvl, debug, sd, "\n");
813 for (j = i; j < i + 16; j++) {
814 sprintf(bp, "0x%02x, ", buf[j]);
815 bp += 6;
816 }
817 bp[0] = '\0';
818 v4l2_dbg(lvl, debug, sd, "%s\n", b);
819 }
820}
821
822static void ad9389b_edid_handler(struct work_struct *work)
823{
824 struct delayed_work *dwork = to_delayed_work(work);
d3ec7de4
MB		 825 struct ad9389b_state *state =
826 container_of(dwork, struct ad9389b_state, edid_handler);
117a55b6
HV		 827 struct v4l2_subdev *sd = &state->sd;
828 struct ad9389b_edid_detect ed;
829
830 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
831
832 if (ad9389b_check_edid_status(sd)) {
833 /* Return if we received the EDID. */
834 return;
835 }
836
837 if (ad9389b_have_hotplug(sd)) {
838 /* We must retry reading the EDID several times, it is possible
839 * that initially the EDID couldn't be read due to i2c errors
840 * (DVI connectors are particularly prone to this problem). */
841 if (state->edid.read_retries) {
842 state->edid.read_retries--;
15edc1cc 843 v4l2_dbg(1, debug, sd, "%s: edid read failed\n", __func__);
15edc1cc
MB		 844 ad9389b_s_power(sd, false);
845 ad9389b_s_power(sd, true);
117a55b6 846 queue_delayed_work(state->work_queue,
d3ec7de4 847 &state->edid_handler, EDID_DELAY);
117a55b6
HV		 848 return;
849 }
850 }
851
852 /* We failed to read the EDID, so send an event for this. */
853 ed.present = false;
854 ed.segment = ad9389b_rd(sd, 0xc4);
855 v4l2_subdev_notify(sd, AD9389B_EDID_DETECT, (void *)&ed);
856 v4l2_dbg(1, debug, sd, "%s: no edid found\n", __func__);
857}
858
859static void ad9389b_audio_setup(struct v4l2_subdev *sd)
860{
861 v4l2_dbg(1, debug, sd, "%s\n", __func__);
862
863 ad9389b_s_i2s_clock_freq(sd, 48000);
864 ad9389b_s_clock_freq(sd, 48000);
865 ad9389b_s_routing(sd, 0, 0, 0);
866}
867
868/* Initial setup of AD9389b */
869
870/* Configure hdmi transmitter. */
871static void ad9389b_setup(struct v4l2_subdev *sd)
872{
873 struct ad9389b_state *state = get_ad9389b_state(sd);
874
875 v4l2_dbg(1, debug, sd, "%s\n", __func__);
876
877 /* Input format: RGB 4:4:4 */
878 ad9389b_wr_and_or(sd, 0x15, 0xf1, 0x0);
879 /* Output format: RGB 4:4:4 */
880 ad9389b_wr_and_or(sd, 0x16, 0x3f, 0x0);
f3b33ede
MR		 881 /* 1st order interpolation 4:2:2 -> 4:4:4 up conversion,
882 Aspect ratio: 16:9 */
883 ad9389b_wr_and_or(sd, 0x17, 0xf9, 0x06);
117a55b6
HV		 884 /* Output format: RGB 4:4:4, Active Format Information is valid. */
885 ad9389b_wr_and_or(sd, 0x45, 0xc7, 0x08);
886 /* Underscanned */
887 ad9389b_wr_and_or(sd, 0x46, 0x3f, 0x80);
888 /* Setup video format */
889 ad9389b_wr(sd, 0x3c, 0x0);
890 /* Active format aspect ratio: same as picure. */
891 ad9389b_wr(sd, 0x47, 0x80);
892 /* No encryption */
893 ad9389b_wr_and_or(sd, 0xaf, 0xef, 0x0);
894 /* Positive clk edge capture for input video clock */
895 ad9389b_wr_and_or(sd, 0xba, 0x1f, 0x60);
896
897 ad9389b_audio_setup(sd);
898
899 v4l2_ctrl_handler_setup(&state->hdl);
900
901 ad9389b_set_IT_content_AVI_InfoFrame(sd);
902}
903
904static void ad9389b_notify_monitor_detect(struct v4l2_subdev *sd)
905{
906 struct ad9389b_monitor_detect mdt;
907 struct ad9389b_state *state = get_ad9389b_state(sd);
908
909 mdt.present = state->have_monitor;
910 v4l2_subdev_notify(sd, AD9389B_MONITOR_DETECT, (void *)&mdt);
911}
912
a6c98f56 913static void ad9389b_update_monitor_present_status(struct v4l2_subdev *sd)
117a55b6
HV		 914{
915 struct ad9389b_state *state = get_ad9389b_state(sd);
916 /* read hotplug and rx-sense state */
917 u8 status = ad9389b_rd(sd, 0x42);
918
919 v4l2_dbg(1, debug, sd, "%s: status: 0x%x%s%s\n",
51af70bf
MB		 920 __func__,
921 status,
922 status & MASK_AD9389B_HPD_DETECT ? ", hotplug" : "",
923 status & MASK_AD9389B_MSEN_DETECT ? ", rx-sense" : "");
117a55b6 924
51af70bf 925 if (status & MASK_AD9389B_HPD_DETECT) {
117a55b6 926 v4l2_dbg(1, debug, sd, "%s: hotplug detected\n", __func__);
51af70bf
MB		 927 state->have_monitor = true;
928 if (!ad9389b_s_power(sd, true)) {
929 v4l2_dbg(1, debug, sd,
930 "%s: monitor detected, powerup failed\n", __func__);
931 return;
932 }
933 ad9389b_setup(sd);
934 ad9389b_notify_monitor_detect(sd);
117a55b6
HV		 935 state->edid.read_retries = EDID_MAX_RETRIES;
936 queue_delayed_work(state->work_queue,
51af70bf 937 &state->edid_handler, EDID_DELAY);
117a55b6
HV		 938 } else if (!(status & MASK_AD9389B_HPD_DETECT)) {
939 v4l2_dbg(1, debug, sd, "%s: hotplug not detected\n", __func__);
51af70bf
MB		 940 state->have_monitor = false;
941 ad9389b_notify_monitor_detect(sd);
117a55b6
HV		 942 ad9389b_s_power(sd, false);
943 memset(&state->edid, 0, sizeof(struct ad9389b_state_edid));
944 }
945
946 /* update read only ctrls */
947 v4l2_ctrl_s_ctrl(state->hotplug_ctrl, ad9389b_have_hotplug(sd) ? 0x1 : 0x0);
948 v4l2_ctrl_s_ctrl(state->rx_sense_ctrl, ad9389b_have_rx_sense(sd) ? 0x1 : 0x0);
949 v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, state->edid.segments ? 0x1 : 0x0);
51af70bf
MB		 950
951 /* update with setting from ctrls */
952 ad9389b_s_ctrl(state->rgb_quantization_range_ctrl);
953 ad9389b_s_ctrl(state->hdmi_mode_ctrl);
117a55b6
HV		 954}
955
a6c98f56
MB		 956static void ad9389b_check_monitor_present_status(struct v4l2_subdev *sd)
957{
958 struct ad9389b_state *state = get_ad9389b_state(sd);
959 int retry = 0;
960
961 ad9389b_update_monitor_present_status(sd);
962
963 /*
964 * Rapid toggling of the hotplug may leave the chip powered off,
965 * even if we think it is on. In that case reset and power up again.
966 */
967 while (state->power_on && (ad9389b_rd(sd, 0x41) & 0x40)) {
968 if (++retry > 5) {
969 v4l2_err(sd, "retried %d times, give up\n", retry);
970 return;
971 }
972 v4l2_dbg(1, debug, sd, "%s: reset and re-check status (%d)\n", __func__, retry);
973 ad9389b_notify_monitor_detect(sd);
974 cancel_delayed_work_sync(&state->edid_handler);
975 memset(&state->edid, 0, sizeof(struct ad9389b_state_edid));
976 ad9389b_s_power(sd, false);
977 ad9389b_update_monitor_present_status(sd);
978 }
979}
980
117a55b6
HV		 981static bool edid_block_verify_crc(u8 *edid_block)
982{
117a55b6 983 u8 sum = 0;
350a1815 984 int i;
117a55b6 985
350a1815
MB		 986 for (i = 0; i < 128; i++)
987 sum += edid_block[i];
988 return sum == 0;
117a55b6
HV		 989}
990
bafd5d79 991static bool edid_verify_crc(struct v4l2_subdev *sd, u32 segment)
117a55b6
HV		 992{
993 struct ad9389b_state *state = get_ad9389b_state(sd);
994 u32 blocks = state->edid.blocks;
995 u8 *data = state->edid.data;
996
997 if (edid_block_verify_crc(&data[segment * 256])) {
998 if ((segment + 1) * 2 <= blocks)
999 return edid_block_verify_crc(&data[segment * 256 + 128]);
1000 return true;
1001 }
1002 return false;
1003}
1004
bafd5d79
MR		 1005static bool edid_verify_header(struct v4l2_subdev *sd, u32 segment)
1006{
1007 static const u8 hdmi_header[] = {
1008 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1009 };
1010 struct ad9389b_state *state = get_ad9389b_state(sd);
1011 u8 *data = state->edid.data;
1012 int i;
1013
1014 if (segment)
1015 return true;
1016
1017 for (i = 0; i < ARRAY_SIZE(hdmi_header); i++)
1018 if (data[i] != hdmi_header[i])
1019 return false;
1020
1021 return true;
1022}
1023
117a55b6
HV		 1024static bool ad9389b_check_edid_status(struct v4l2_subdev *sd)
1025{
1026 struct ad9389b_state *state = get_ad9389b_state(sd);
1027 struct ad9389b_edid_detect ed;
1028 int segment;
1029 u8 edidRdy = ad9389b_rd(sd, 0xc5);
1030
1031 v4l2_dbg(1, debug, sd, "%s: edid ready (retries: %d)\n",
d3ec7de4 1032 __func__, EDID_MAX_RETRIES - state->edid.read_retries);
117a55b6
HV		 1033
1034 if (!(edidRdy & MASK_AD9389B_EDID_RDY))
1035 return false;
1036
1037 segment = ad9389b_rd(sd, 0xc4);
1038 if (segment >= EDID_MAX_SEGM) {
1039 v4l2_err(sd, "edid segment number too big\n");
1040 return false;
1041 }
1042 v4l2_dbg(1, debug, sd, "%s: got segment %d\n", __func__, segment);
1043 ad9389b_edid_rd(sd, 256, &state->edid.data[segment * 256]);
1044 ad9389b_dbg_dump_edid(2, debug, sd, segment,
d3ec7de4 1045 &state->edid.data[segment * 256]);
117a55b6
HV		 1046 if (segment == 0) {
1047 state->edid.blocks = state->edid.data[0x7e] + 1;
1048 v4l2_dbg(1, debug, sd, "%s: %d blocks in total\n",
d3ec7de4 1049 __func__, state->edid.blocks);
117a55b6 1050 }
bafd5d79 1051 if (!edid_verify_crc(sd, segment) ||
d3ec7de4 1052 !edid_verify_header(sd, segment)) {
117a55b6 1053 /* edid crc error, force reread of edid segment */
bafd5d79 1054 v4l2_err(sd, "%s: edid crc or header error\n", __func__);
117a55b6
HV		 1055 ad9389b_s_power(sd, false);
1056 ad9389b_s_power(sd, true);
1057 return false;
1058 }
1059 /* one more segment read ok */
1060 state->edid.segments = segment + 1;
1061 if (((state->edid.data[0x7e] >> 1) + 1) > state->edid.segments) {
1062 /* Request next EDID segment */
1063 v4l2_dbg(1, debug, sd, "%s: request segment %d\n",
d3ec7de4 1064 __func__, state->edid.segments);
117a55b6
HV		 1065 ad9389b_wr(sd, 0xc9, 0xf);
1066 ad9389b_wr(sd, 0xc4, state->edid.segments);
1067 state->edid.read_retries = EDID_MAX_RETRIES;
1068 queue_delayed_work(state->work_queue,
d3ec7de4 1069 &state->edid_handler, EDID_DELAY);
117a55b6
HV		 1070 return false;
1071 }
1072
1073 /* report when we have all segments but report only for segment 0 */
1074 ed.present = true;
1075 ed.segment = 0;
1076 v4l2_subdev_notify(sd, AD9389B_EDID_DETECT, (void *)&ed);
1077 state->edid_detect_counter++;
1078 v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, state->edid.segments ? 0x1 : 0x0);
1079 return ed.present;
1080}
1081
1082/* ----------------------------------------------------------------------- */
1083
1084static void ad9389b_init_setup(struct v4l2_subdev *sd)
1085{
1086 struct ad9389b_state *state = get_ad9389b_state(sd);
1087 struct ad9389b_state_edid *edid = &state->edid;
1088
1089 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1090
1091 /* clear all interrupts */
1092 ad9389b_wr(sd, 0x96, 0xff);
1093
1094 memset(edid, 0, sizeof(struct ad9389b_state_edid));
1095 state->have_monitor = false;
1096 ad9389b_set_isr(sd, false);
1097}
1098
1099static int ad9389b_probe(struct i2c_client *client, const struct i2c_device_id *id)
1100{
1101 const struct v4l2_dv_timings dv1080p60 = V4L2_DV_BT_CEA_1920X1080P60;
1102 struct ad9389b_state *state;
1103 struct ad9389b_platform_data *pdata = client->dev.platform_data;
1104 struct v4l2_ctrl_handler *hdl;
1105 struct v4l2_subdev *sd;
1106 int err = -EIO;
1107
1108 /* Check if the adapter supports the needed features */
1109 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1110 return -EIO;
1111
1112 v4l_dbg(1, debug, client, "detecting ad9389b client on address 0x%x\n",
d3ec7de4 1113 client->addr << 1);
117a55b6 1114
c02b211d 1115 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
117a55b6
HV		 1116 if (!state)
1117 return -ENOMEM;
1118
1119 /* Platform data */
1120 if (pdata == NULL) {
1121 v4l_err(client, "No platform data!\n");
c02b211d 1122 return -ENODEV;
117a55b6
HV		 1123 }
1124 memcpy(&state->pdata, pdata, sizeof(state->pdata));
1125
1126 sd = &state->sd;
1127 v4l2_i2c_subdev_init(sd, client, &ad9389b_ops);
1128 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1129
1130 hdl = &state->hdl;
1131 v4l2_ctrl_handler_init(hdl, 5);
1132
1133 /* private controls */
1134
1135 state->hdmi_mode_ctrl = v4l2_ctrl_new_std_menu(hdl, &ad9389b_ctrl_ops,
1136 V4L2_CID_DV_TX_MODE, V4L2_DV_TX_MODE_HDMI,
1137 0, V4L2_DV_TX_MODE_DVI_D);
117a55b6
HV		 1138 state->hotplug_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1139 V4L2_CID_DV_TX_HOTPLUG, 0, 1, 0, 0);
117a55b6
HV		 1140 state->rx_sense_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1141 V4L2_CID_DV_TX_RXSENSE, 0, 1, 0, 0);
117a55b6
HV		 1142 state->have_edid0_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1143 V4L2_CID_DV_TX_EDID_PRESENT, 0, 1, 0, 0);
117a55b6
HV		 1144 state->rgb_quantization_range_ctrl =
1145 v4l2_ctrl_new_std_menu(hdl, &ad9389b_ctrl_ops,
1146 V4L2_CID_DV_TX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
1147 0, V4L2_DV_RGB_RANGE_AUTO);
117a55b6
HV		 1148 sd->ctrl_handler = hdl;
1149 if (hdl->error) {
1150 err = hdl->error;
1151
1152 goto err_hdl;
1153 }
265d3b55
HV		 1154 state->hdmi_mode_ctrl->is_private = true;
1155 state->hotplug_ctrl->is_private = true;
1156 state->rx_sense_ctrl->is_private = true;
1157 state->have_edid0_ctrl->is_private = true;
1158 state->rgb_quantization_range_ctrl->is_private = true;
117a55b6
HV		 1159
1160 state->pad.flags = MEDIA_PAD_FL_SINK;
1161 err = media_entity_init(&sd->entity, 1, &state->pad, 0);
1162 if (err)
1163 goto err_hdl;
1164
1165 state->chip_revision = ad9389b_rd(sd, 0x0);
1166 if (state->chip_revision != 2) {
1167 v4l2_err(sd, "chip_revision %d != 2\n", state->chip_revision);
1168 err = -EIO;
1169 goto err_entity;
1170 }
1171 v4l2_dbg(1, debug, sd, "reg 0x41 0x%x, chip version (reg 0x00) 0x%x\n",
d3ec7de4 1172 ad9389b_rd(sd, 0x41), state->chip_revision);
117a55b6
HV		 1173
1174 state->edid_i2c_client = i2c_new_dummy(client->adapter, (0x7e>>1));
1175 if (state->edid_i2c_client == NULL) {
1176 v4l2_err(sd, "failed to register edid i2c client\n");
6ec735df 1177 err = -ENOMEM;
117a55b6
HV		 1178 goto err_entity;
1179 }
1180
1181 state->work_queue = create_singlethread_workqueue(sd->name);
1182 if (state->work_queue == NULL) {
1183 v4l2_err(sd, "could not create workqueue\n");
6ec735df 1184 err = -ENOMEM;
117a55b6
HV		 1185 goto err_unreg;
1186 }
1187
1188 INIT_DELAYED_WORK(&state->edid_handler, ad9389b_edid_handler);
1189 state->dv_timings = dv1080p60;
1190
1191 ad9389b_init_setup(sd);
1192 ad9389b_set_isr(sd, true);
1193
1194 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
d3ec7de4 1195 client->addr << 1, client->adapter->name);
117a55b6
HV		 1196 return 0;
1197
1198err_unreg:
1199 i2c_unregister_device(state->edid_i2c_client);
1200err_entity:
1201 media_entity_cleanup(&sd->entity);
1202err_hdl:
1203 v4l2_ctrl_handler_free(&state->hdl);
117a55b6
HV		 1204 return err;
1205}
1206
1207/* ----------------------------------------------------------------------- */
1208
1209static int ad9389b_remove(struct i2c_client *client)
1210{
1211 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1212 struct ad9389b_state *state = get_ad9389b_state(sd);
1213
1214 state->chip_revision = -1;
1215
1216 v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name,
1217 client->addr << 1, client->adapter->name);
1218
1219 ad9389b_s_stream(sd, false);
1220 ad9389b_s_audio_stream(sd, false);
1221 ad9389b_init_setup(sd);
1222 cancel_delayed_work(&state->edid_handler);
1223 i2c_unregister_device(state->edid_i2c_client);
1224 destroy_workqueue(state->work_queue);
1225 v4l2_device_unregister_subdev(sd);
1226 media_entity_cleanup(&sd->entity);
1227 v4l2_ctrl_handler_free(sd->ctrl_handler);
117a55b6
HV		 1228 return 0;
1229}
1230
1231/* ----------------------------------------------------------------------- */
1232
1233static struct i2c_device_id ad9389b_id[] = {
e1277110
HV		 1234 { "ad9389b", 0 },
1235 { "ad9889b", 0 },
117a55b6
HV		 1236 { }
1237};
1238MODULE_DEVICE_TABLE(i2c, ad9389b_id);
1239
1240static struct i2c_driver ad9389b_driver = {
1241 .driver = {
1242 .owner = THIS_MODULE,
1243 .name = "ad9389b",
1244 },
1245 .probe = ad9389b_probe,
1246 .remove = ad9389b_remove,
1247 .id_table = ad9389b_id,
1248};
1249
1250module_i2c_driver(ad9389b_driver);
Linux 6.x block layer and io_uring tree(s)