[linux-2.6-block.git] / drivers / media / dvb-frontends / zl10353.c

/*
 * Driver for Zarlink DVB-T ZL10353 demodulator
 *
 * Copyright (C) 2006, 2007 Christopher Pascoe <c.pascoe@itee.uq.edu.au>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <asm/div64.h>

#include "dvb_frontend.h"
#include "zl10353_priv.h"
#include "zl10353.h"

struct zl10353_state {
	struct i2c_adapter *i2c;
	struct dvb_frontend frontend;

	struct zl10353_config config;

	u32 bandwidth;
	u32 ucblocks;
	u32 frequency;
};

static int debug;
#define dprintk(args...) \
	do { \
		if (debug) printk(KERN_DEBUG "zl10353: " args); \
	} while (0)

static int debug_regs;

static int zl10353_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
{
	struct zl10353_state *state = fe->demodulator_priv;
	u8 buf[2] = { reg, val };
	struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0,
			       .buf = buf, .len = 2 };
	int err = i2c_transfer(state->i2c, &msg, 1);
	if (err != 1) {
		printk("zl10353: write to reg %x failed (err = %d)!\n", reg, err);
		return err;
	}
	return 0;
}

static int zl10353_write(struct dvb_frontend *fe, const u8 ibuf[], int ilen)
{
	int err, i;
	for (i = 0; i < ilen - 1; i++)
		if ((err = zl10353_single_write(fe, ibuf[0] + i, ibuf[i + 1])))
			return err;

	return 0;
}

static int zl10353_read_register(struct zl10353_state *state, u8 reg)
{
	int ret;
	u8 b0[1] = { reg };
	u8 b1[1] = { 0 };
	struct i2c_msg msg[2] = { { .addr = state->config.demod_address,
				    .flags = 0,
				    .buf = b0, .len = 1 },
				  { .addr = state->config.demod_address,
				    .flags = I2C_M_RD,
				    .buf = b1, .len = 1 } };

	ret = i2c_transfer(state->i2c, msg, 2);

	if (ret != 2) {
		printk("%s: readreg error (reg=%d, ret==%i)\n",
		       __func__, reg, ret);
		return ret;
	}

	return b1[0];
}

static void zl10353_dump_regs(struct dvb_frontend *fe)
{
	struct zl10353_state *state = fe->demodulator_priv;
	int ret;
	u8 reg;

	/* Dump all registers. */
	for (reg = 0; ; reg++) {
		if (reg % 16 == 0) {
			if (reg)
				printk(KERN_CONT "\n");
			printk(KERN_DEBUG "%02x:", reg);
		}
		ret = zl10353_read_register(state, reg);
		if (ret >= 0)
			printk(KERN_CONT " %02x", (u8)ret);
		else
			printk(KERN_CONT " --");
		if (reg == 0xff)
			break;
	}
	printk(KERN_CONT "\n");
}

static void zl10353_calc_nominal_rate(struct dvb_frontend *fe,
				      u32 bandwidth,
				      u16 *nominal_rate)
{
	struct zl10353_state *state = fe->demodulator_priv;
	u32 adc_clock = 450560; /* 45.056 MHz */
	u64 value;
	u8 bw = bandwidth / 1000000;

	if (state->config.adc_clock)
		adc_clock = state->config.adc_clock;

	value = (u64)10 * (1 << 23) / 7 * 125;
	value = (bw * value) + adc_clock / 2;
	*nominal_rate = div_u64(value, adc_clock);

	dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
		__func__, bw, adc_clock, *nominal_rate);
}

static void zl10353_calc_input_freq(struct dvb_frontend *fe,
				    u16 *input_freq)
{
	struct zl10353_state *state = fe->demodulator_priv;
	u32 adc_clock = 450560;	/* 45.056  MHz */
	int if2 = 361667;	/* 36.1667 MHz */
	int ife;
	u64 value;

	if (state->config.adc_clock)
		adc_clock = state->config.adc_clock;
	if (state->config.if2)
		if2 = state->config.if2;

	if (adc_clock >= if2 * 2)
		ife = if2;
	else {
		ife = adc_clock - (if2 % adc_clock);
		if (ife > adc_clock / 2)
			ife = adc_clock - ife;
	}
	value = div_u64((u64)65536 * ife + adc_clock / 2, adc_clock);
	*input_freq = -value;

	dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
		__func__, if2, ife, adc_clock, -(int)value, *input_freq);
}

static int zl10353_sleep(struct dvb_frontend *fe)
{
	static u8 zl10353_softdown[] = { 0x50, 0x0C, 0x44 };

	zl10353_write(fe, zl10353_softdown, sizeof(zl10353_softdown));
	return 0;
}

static int zl10353_set_parameters(struct dvb_frontend *fe)
{
	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
	struct zl10353_state *state = fe->demodulator_priv;
	u16 nominal_rate, input_freq;
	u8 pllbuf[6] = { 0x67 }, acq_ctl = 0;
	u16 tps = 0;

	state->frequency = c->frequency;

	zl10353_single_write(fe, RESET, 0x80);
	udelay(200);
	zl10353_single_write(fe, 0xEA, 0x01);
	udelay(200);
	zl10353_single_write(fe, 0xEA, 0x00);

	zl10353_single_write(fe, AGC_TARGET, 0x28);

	if (c->transmission_mode != TRANSMISSION_MODE_AUTO)
		acq_ctl |= (1 << 0);
	if (c->guard_interval != GUARD_INTERVAL_AUTO)
		acq_ctl |= (1 << 1);
	zl10353_single_write(fe, ACQ_CTL, acq_ctl);

	switch (c->bandwidth_hz) {
	case 6000000:
		/* These are extrapolated from the 7 and 8MHz values */
		zl10353_single_write(fe, MCLK_RATIO, 0x97);
		zl10353_single_write(fe, 0x64, 0x34);
		zl10353_single_write(fe, 0xcc, 0xdd);
		break;
	case 7000000:
		zl10353_single_write(fe, MCLK_RATIO, 0x86);
		zl10353_single_write(fe, 0x64, 0x35);
		zl10353_single_write(fe, 0xcc, 0x73);
		break;
	default:
		c->bandwidth_hz = 8000000;
		/* fall through */
	case 8000000:
		zl10353_single_write(fe, MCLK_RATIO, 0x75);
		zl10353_single_write(fe, 0x64, 0x36);
		zl10353_single_write(fe, 0xcc, 0x73);
	}

	zl10353_calc_nominal_rate(fe, c->bandwidth_hz, &nominal_rate);
	zl10353_single_write(fe, TRL_NOMINAL_RATE_1, msb(nominal_rate));
	zl10353_single_write(fe, TRL_NOMINAL_RATE_0, lsb(nominal_rate));
	state->bandwidth = c->bandwidth_hz;

	zl10353_calc_input_freq(fe, &input_freq);
	zl10353_single_write(fe, INPUT_FREQ_1, msb(input_freq));
	zl10353_single_write(fe, INPUT_FREQ_0, lsb(input_freq));

	/* Hint at TPS settings */
	switch (c->code_rate_HP) {
	case FEC_2_3:
		tps |= (1 << 7);
		break;
	case FEC_3_4:
		tps |= (2 << 7);
		break;
	case FEC_5_6:
		tps |= (3 << 7);
		break;
	case FEC_7_8:
		tps |= (4 << 7);
		break;
	case FEC_1_2:
	case FEC_AUTO:
		break;
	default:
		return -EINVAL;
	}

	switch (c->code_rate_LP) {
	case FEC_2_3:
		tps |= (1 << 4);
		break;
	case FEC_3_4:
		tps |= (2 << 4);
		break;
	case FEC_5_6:
		tps |= (3 << 4);
		break;
	case FEC_7_8:
		tps |= (4 << 4);
		break;
	case FEC_1_2:
	case FEC_AUTO:
		break;
	case FEC_NONE:
		if (c->hierarchy == HIERARCHY_AUTO ||
		    c->hierarchy == HIERARCHY_NONE)
			break;
		/* fall through */
	default:
		return -EINVAL;
	}

	switch (c->modulation) {
	case QPSK:
		break;
	case QAM_AUTO:
	case QAM_16:
		tps |= (1 << 13);
		break;
	case QAM_64:
		tps |= (2 << 13);
		break;
	default:
		return -EINVAL;
	}

	switch (c->transmission_mode) {
	case TRANSMISSION_MODE_2K:
	case TRANSMISSION_MODE_AUTO:
		break;
	case TRANSMISSION_MODE_8K:
		tps |= (1 << 0);
		break;
	default:
		return -EINVAL;
	}

	switch (c->guard_interval) {
	case GUARD_INTERVAL_1_32:
	case GUARD_INTERVAL_AUTO:
		break;
	case GUARD_INTERVAL_1_16:
		tps |= (1 << 2);
		break;
	case GUARD_INTERVAL_1_8:
		tps |= (2 << 2);
		break;
	case GUARD_INTERVAL_1_4:
		tps |= (3 << 2);
		break;
	default:
		return -EINVAL;
	}

	switch (c->hierarchy) {
	case HIERARCHY_AUTO:
	case HIERARCHY_NONE:
		break;
	case HIERARCHY_1:
		tps |= (1 << 10);
		break;
	case HIERARCHY_2:
		tps |= (2 << 10);
		break;
	case HIERARCHY_4:
		tps |= (3 << 10);
		break;
	default:
		return -EINVAL;
	}

	zl10353_single_write(fe, TPS_GIVEN_1, msb(tps));
	zl10353_single_write(fe, TPS_GIVEN_0, lsb(tps));

	if (fe->ops.i2c_gate_ctrl)
		fe->ops.i2c_gate_ctrl(fe, 0);

	/*
	 * If there is no tuner attached to the secondary I2C bus, we call
	 * set_params to program a potential tuner attached somewhere else.
	 * Otherwise, we update the PLL registers via calc_regs.
	 */
	if (state->config.no_tuner) {
		if (fe->ops.tuner_ops.set_params) {
			fe->ops.tuner_ops.set_params(fe);
			if (fe->ops.i2c_gate_ctrl)
				fe->ops.i2c_gate_ctrl(fe, 0);
		}
	} else if (fe->ops.tuner_ops.calc_regs) {
		fe->ops.tuner_ops.calc_regs(fe, pllbuf + 1, 5);
		pllbuf[1] <<= 1;
		zl10353_write(fe, pllbuf, sizeof(pllbuf));
	}

	zl10353_single_write(fe, 0x5F, 0x13);

	/* If no attached tuner or invalid PLL registers, just start the FSM. */
	if (state->config.no_tuner || fe->ops.tuner_ops.calc_regs == NULL)
		zl10353_single_write(fe, FSM_GO, 0x01);
	else
		zl10353_single_write(fe, TUNER_GO, 0x01);

	return 0;
}

static int zl10353_get_parameters(struct dvb_frontend *fe,
				  struct dtv_frontend_properties *c)
{
	struct zl10353_state *state = fe->demodulator_priv;
	int s6, s9;
	u16 tps;
	static const u8 tps_fec_to_api[8] = {
		FEC_1_2,
		FEC_2_3,
		FEC_3_4,
		FEC_5_6,
		FEC_7_8,
		FEC_AUTO,
		FEC_AUTO,
		FEC_AUTO
	};

	s6 = zl10353_read_register(state, STATUS_6);
	s9 = zl10353_read_register(state, STATUS_9);
	if (s6 < 0 || s9 < 0)
		return -EREMOTEIO;
	if ((s6 & (1 << 5)) == 0 || (s9 & (1 << 4)) == 0)
		return -EINVAL;	/* no FE or TPS lock */

	tps = zl10353_read_register(state, TPS_RECEIVED_1) << 8 |
	      zl10353_read_register(state, TPS_RECEIVED_0);

	c->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
	c->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];

	switch ((tps >> 13) & 3) {
	case 0:
		c->modulation = QPSK;
		break;
	case 1:
		c->modulation = QAM_16;
		break;
	case 2:
		c->modulation = QAM_64;
		break;
	default:
		c->modulation = QAM_AUTO;
		break;
	}

	c->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K :
					       TRANSMISSION_MODE_2K;

	switch ((tps >> 2) & 3) {
	case 0:
		c->guard_interval = GUARD_INTERVAL_1_32;
		break;
	case 1:
		c->guard_interval = GUARD_INTERVAL_1_16;
		break;
	case 2:
		c->guard_interval = GUARD_INTERVAL_1_8;
		break;
	case 3:
		c->guard_interval = GUARD_INTERVAL_1_4;
		break;
	default:
		c->guard_interval = GUARD_INTERVAL_AUTO;
		break;
	}

	switch ((tps >> 10) & 7) {
	case 0:
		c->hierarchy = HIERARCHY_NONE;
		break;
	case 1:
		c->hierarchy = HIERARCHY_1;
		break;
	case 2:
		c->hierarchy = HIERARCHY_2;
		break;
	case 3:
		c->hierarchy = HIERARCHY_4;
		break;
	default:
		c->hierarchy = HIERARCHY_AUTO;
		break;
	}

	c->frequency = state->frequency;
	c->bandwidth_hz = state->bandwidth;
	c->inversion = INVERSION_AUTO;

	return 0;
}

static int zl10353_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
	struct zl10353_state *state = fe->demodulator_priv;
	int s6, s7, s8;

	if ((s6 = zl10353_read_register(state, STATUS_6)) < 0)
		return -EREMOTEIO;
	if ((s7 = zl10353_read_register(state, STATUS_7)) < 0)
		return -EREMOTEIO;
	if ((s8 = zl10353_read_register(state, STATUS_8)) < 0)
		return -EREMOTEIO;

	*status = 0;
	if (s6 & (1 << 2))
		*status |= FE_HAS_CARRIER;
	if (s6 & (1 << 1))
		*status |= FE_HAS_VITERBI;
	if (s6 & (1 << 5))
		*status |= FE_HAS_LOCK;
	if (s7 & (1 << 4))
		*status |= FE_HAS_SYNC;
	if (s8 & (1 << 6))
		*status |= FE_HAS_SIGNAL;

	if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) !=
	    (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC))
		*status &= ~FE_HAS_LOCK;

	return 0;
}

static int zl10353_read_ber(struct dvb_frontend *fe, u32 *ber)
{
	struct zl10353_state *state = fe->demodulator_priv;

	*ber = zl10353_read_register(state, RS_ERR_CNT_2) << 16 |
	       zl10353_read_register(state, RS_ERR_CNT_1) << 8 |
	       zl10353_read_register(state, RS_ERR_CNT_0);

	return 0;
}

static int zl10353_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
{
	struct zl10353_state *state = fe->demodulator_priv;

	u16 signal = zl10353_read_register(state, AGC_GAIN_1) << 10 |
		     zl10353_read_register(state, AGC_GAIN_0) << 2 | 3;

	*strength = ~signal;

	return 0;
}

static int zl10353_read_snr(struct dvb_frontend *fe, u16 *snr)
{
	struct zl10353_state *state = fe->demodulator_priv;
	u8 _snr;

	if (debug_regs)
		zl10353_dump_regs(fe);

	_snr = zl10353_read_register(state, SNR);
	*snr = 10 * _snr / 8;

	return 0;
}

static int zl10353_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
	struct zl10353_state *state = fe->demodulator_priv;
	u32 ubl = 0;

	ubl = zl10353_read_register(state, RS_UBC_1) << 8 |
	      zl10353_read_register(state, RS_UBC_0);

	state->ucblocks += ubl;
	*ucblocks = state->ucblocks;

	return 0;
}

static int zl10353_get_tune_settings(struct dvb_frontend *fe,
				     struct dvb_frontend_tune_settings
					 *fe_tune_settings)
{
	fe_tune_settings->min_delay_ms = 1000;
	fe_tune_settings->step_size = 0;
	fe_tune_settings->max_drift = 0;

	return 0;
}

static int zl10353_init(struct dvb_frontend *fe)
{
	struct zl10353_state *state = fe->demodulator_priv;
	u8 zl10353_reset_attach[6] = { 0x50, 0x03, 0x64, 0x46, 0x15, 0x0F };

	if (debug_regs)
		zl10353_dump_regs(fe);
	if (state->config.parallel_ts)
		zl10353_reset_attach[2] &= ~0x20;
	if (state->config.clock_ctl_1)
		zl10353_reset_attach[3] = state->config.clock_ctl_1;
	if (state->config.pll_0)
		zl10353_reset_attach[4] = state->config.pll_0;

	/* Do a "hard" reset if not already done */
	if (zl10353_read_register(state, 0x50) != zl10353_reset_attach[1] ||
	    zl10353_read_register(state, 0x51) != zl10353_reset_attach[2]) {
		zl10353_write(fe, zl10353_reset_attach,
				   sizeof(zl10353_reset_attach));
		if (debug_regs)
			zl10353_dump_regs(fe);
	}

	return 0;
}

static int zl10353_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
{
	struct zl10353_state *state = fe->demodulator_priv;
	u8 val = 0x0a;

	if (state->config.disable_i2c_gate_ctrl) {
		/* No tuner attached to the internal I2C bus */
		/* If set enable I2C bridge, the main I2C bus stopped hardly */
		return 0;
	}

	if (enable)
		val |= 0x10;

	return zl10353_single_write(fe, 0x62, val);
}

static void zl10353_release(struct dvb_frontend *fe)
{
	struct zl10353_state *state = fe->demodulator_priv;
	kfree(state);
}

static const struct dvb_frontend_ops zl10353_ops;

struct dvb_frontend *zl10353_attach(const struct zl10353_config *config,
				    struct i2c_adapter *i2c)
{
	struct zl10353_state *state = NULL;
	int id;

	/* allocate memory for the internal state */
	state = kzalloc(sizeof(struct zl10353_state), GFP_KERNEL);
	if (state == NULL)
		goto error;

	/* setup the state */
	state->i2c = i2c;
	memcpy(&state->config, config, sizeof(struct zl10353_config));

	/* check if the demod is there */
	id = zl10353_read_register(state, CHIP_ID);
	if ((id != ID_ZL10353) && (id != ID_CE6230) && (id != ID_CE6231))
		goto error;

	/* create dvb_frontend */
	memcpy(&state->frontend.ops, &zl10353_ops, sizeof(struct dvb_frontend_ops));
	state->frontend.demodulator_priv = state;

	return &state->frontend;
error:
	kfree(state);
	return NULL;
}

static const struct dvb_frontend_ops zl10353_ops = {
	.delsys = { SYS_DVBT },
	.info = {
		.name			= "Zarlink ZL10353 DVB-T",
		.frequency_min		= 174000000,
		.frequency_max		= 862000000,
		.frequency_stepsize	= 166667,
		.frequency_tolerance	= 0,
		.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
			FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
			FE_CAN_FEC_AUTO |
			FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
			FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
			FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
			FE_CAN_MUTE_TS
	},

	.release = zl10353_release,

	.init = zl10353_init,
	.sleep = zl10353_sleep,
	.i2c_gate_ctrl = zl10353_i2c_gate_ctrl,
	.write = zl10353_write,

	.set_frontend = zl10353_set_parameters,
	.get_frontend = zl10353_get_parameters,
	.get_tune_settings = zl10353_get_tune_settings,

	.read_status = zl10353_read_status,
	.read_ber = zl10353_read_ber,
	.read_signal_strength = zl10353_read_signal_strength,
	.read_snr = zl10353_read_snr,
	.read_ucblocks = zl10353_read_ucblocks,
};

module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");

module_param(debug_regs, int, 0644);
MODULE_PARM_DESC(debug_regs, "Turn on/off frontend register dumps (default:off).");

MODULE_DESCRIPTION("Zarlink ZL10353 DVB-T demodulator driver");
MODULE_AUTHOR("Chris Pascoe");
MODULE_LICENSE("GPL");

EXPORT_SYMBOL(zl10353_attach);
Commit	Line	Data
780dfef3 CP	1	/*
	2	* Driver for Zarlink DVB-T ZL10353 demodulator
	3	*
794604c3	4	* Copyright (C) 2006, 2007 Christopher Pascoe <c.pascoe@itee.uq.edu.au>
780dfef3 CP	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	*
	15	* GNU General Public License for more details.
780dfef3 CP	16	*/
	17
	18	#include <linux/kernel.h>
	19	#include <linux/module.h>
780dfef3 CP	20	#include <linux/init.h>
	21	#include <linux/delay.h>
	22	#include <linux/string.h>
	23	#include <linux/slab.h>
794604c3	24	#include <asm/div64.h>
780dfef3 CP	25
	26	#include "dvb_frontend.h"
	27	#include "zl10353_priv.h"
	28	#include "zl10353.h"
	29
	30	struct zl10353_state {
	31	struct i2c_adapter *i2c;
	32	struct dvb_frontend frontend;
780dfef3 CP	33
780dfef3 CP	34	struct zl10353_config config;
bc514710	35
4e4d2bcf MCC	36	u32 bandwidth;
	37	u32 ucblocks;
	38	u32 frequency;
780dfef3 CP	39	};
780dfef3 CP	40
f7f57770 AP	41	static int debug;
	42	#define dprintk(args...) \
	43	do { \
	44	if (debug) printk(KERN_DEBUG "zl10353: " args); \
	45	} while (0)
	46
ff699e6b	47	static int debug_regs;
780dfef3 CP	48
	49	static int zl10353_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
	50	{
	51	struct zl10353_state *state = fe->demodulator_priv;
	52	u8 buf[2] = { reg, val };
	53	struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0,
	54	.buf = buf, .len = 2 };
	55	int err = i2c_transfer(state->i2c, &msg, 1);
	56	if (err != 1) {
	57	printk("zl10353: write to reg %x failed (err = %d)!\n", reg, err);
	58	return err;
	59	}
	60	return 0;
	61	}
	62
2e4e98e7	63	static int zl10353_write(struct dvb_frontend *fe, const u8 ibuf[], int ilen)
780dfef3 CP	64	{
	65	int err, i;
	66	for (i = 0; i < ilen - 1; i++)
	67	if ((err = zl10353_single_write(fe, ibuf[0] + i, ibuf[i + 1])))
	68	return err;
	69
	70	return 0;
	71	}
	72
	73	static int zl10353_read_register(struct zl10353_state *state, u8 reg)
	74	{
	75	int ret;
	76	u8 b0[1] = { reg };
	77	u8 b1[1] = { 0 };
	78	struct i2c_msg msg[2] = { { .addr = state->config.demod_address,
	79	.flags = 0,
	80	.buf = b0, .len = 1 },
	81	{ .addr = state->config.demod_address,
	82	.flags = I2C_M_RD,
	83	.buf = b1, .len = 1 } };
	84
	85	ret = i2c_transfer(state->i2c, msg, 2);
	86
	87	if (ret != 2) {
	88	printk("%s: readreg error (reg=%d, ret==%i)\n",
271ddbf7	89	__func__, reg, ret);
780dfef3 CP	90	return ret;
	91	}
	92
	93	return b1[0];
	94	}
	95
c04e89b1	96	static void zl10353_dump_regs(struct dvb_frontend *fe)
780dfef3 CP	97	{
780dfef3 CP	98	struct zl10353_state *state = fe->demodulator_priv;
780dfef3 CP	99	int ret;
	100	u8 reg;
	101
	102	/* Dump all registers. */
	103	for (reg = 0; ; reg++) {
	104	if (reg % 16 == 0) {
	105	if (reg)
458f9aa3 JN	106	printk(KERN_CONT "\n");
458f9aa3 JN	107	printk(KERN_DEBUG "%02x:", reg);
780dfef3 CP	108	}
	109	ret = zl10353_read_register(state, reg);
	110	if (ret >= 0)
458f9aa3	111	printk(KERN_CONT " %02x", (u8)ret);
780dfef3	112	else
458f9aa3	113	printk(KERN_CONT " --");
780dfef3 CP	114	if (reg == 0xff)
	115	break;
	116	}
458f9aa3	117	printk(KERN_CONT "\n");
780dfef3 CP	118	}
780dfef3 CP	119
f7f57770	120	static void zl10353_calc_nominal_rate(struct dvb_frontend *fe,
4e4d2bcf	121	u32 bandwidth,
f7f57770 AP	122	u16 *nominal_rate)
f7f57770 AP	123	{
f7f57770	124	struct zl10353_state *state = fe->demodulator_priv;
a1dcd9de CP	125	u32 adc_clock = 450560; /* 45.056 MHz */
a1dcd9de CP	126	u64 value;
4e4d2bcf	127	u8 bw = bandwidth / 1000000;
f7f57770 AP	128
	129	if (state->config.adc_clock)
	130	adc_clock = state->config.adc_clock;
	131
18ff605a AM	132	value = (u64)10 * (1 << 23) / 7 * 125;
18ff605a AM	133	value = (bw * value) + adc_clock / 2;
8a73faab	134	*nominal_rate = div_u64(value, adc_clock);
f7f57770 AP	135
f7f57770 AP	136	dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
271ddbf7	137	__func__, bw, adc_clock, *nominal_rate);
f7f57770 AP	138	}
f7f57770 AP	139
794604c3 CP	140	static void zl10353_calc_input_freq(struct dvb_frontend *fe,
	141	u16 *input_freq)
	142	{
	143	struct zl10353_state *state = fe->demodulator_priv;
a1dcd9de CP	144	u32 adc_clock = 450560; /* 45.056 MHz */
a1dcd9de CP	145	int if2 = 361667; /* 36.1667 MHz */
794604c3 CP	146	int ife;
	147	u64 value;
	148
	149	if (state->config.adc_clock)
	150	adc_clock = state->config.adc_clock;
	151	if (state->config.if2)
	152	if2 = state->config.if2;
	153
	154	if (adc_clock >= if2 * 2)
	155	ife = if2;
	156	else {
	157	ife = adc_clock - (if2 % adc_clock);
	158	if (ife > adc_clock / 2)
	159	ife = adc_clock - ife;
	160	}
8a73faab	161	value = div_u64((u64)65536 * ife + adc_clock / 2, adc_clock);
794604c3 CP	162	*input_freq = -value;
	163
	164	dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
271ddbf7	165	__func__, if2, ife, adc_clock, -(int)value, *input_freq);
794604c3 CP	166	}
794604c3 CP	167
780dfef3 CP	168	static int zl10353_sleep(struct dvb_frontend *fe)
	169	{
	170	static u8 zl10353_softdown[] = { 0x50, 0x0C, 0x44 };
	171
	172	zl10353_write(fe, zl10353_softdown, sizeof(zl10353_softdown));
	173	return 0;
	174	}
	175
4e4d2bcf	176	static int zl10353_set_parameters(struct dvb_frontend *fe)
780dfef3	177	{
4e4d2bcf	178	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
8dec0732	179	struct zl10353_state *state = fe->demodulator_priv;
794604c3	180	u16 nominal_rate, input_freq;
bc514710 CP	181	u8 pllbuf[6] = { 0x67 }, acq_ctl = 0;
bc514710 CP	182	u16 tps = 0;
780dfef3	183
4e4d2bcf	184	state->frequency = c->frequency;
decee2e8	185
bc514710	186	zl10353_single_write(fe, RESET, 0x80);
780dfef3 CP	187	udelay(200);
	188	zl10353_single_write(fe, 0xEA, 0x01);
	189	udelay(200);
	190	zl10353_single_write(fe, 0xEA, 0x00);
	191
bc514710 CP	192	zl10353_single_write(fe, AGC_TARGET, 0x28);
bc514710 CP	193
4e4d2bcf	194	if (c->transmission_mode != TRANSMISSION_MODE_AUTO)
bc514710	195	acq_ctl \|= (1 << 0);
4e4d2bcf	196	if (c->guard_interval != GUARD_INTERVAL_AUTO)
bc514710 CP	197	acq_ctl \|= (1 << 1);
bc514710 CP	198	zl10353_single_write(fe, ACQ_CTL, acq_ctl);
f7f57770	199
4e4d2bcf MCC	200	switch (c->bandwidth_hz) {
4e4d2bcf MCC	201	case 6000000:
bc514710 CP	202	/* These are extrapolated from the 7 and 8MHz values */
	203	zl10353_single_write(fe, MCLK_RATIO, 0x97);
	204	zl10353_single_write(fe, 0x64, 0x34);
a9dbe5dc	205	zl10353_single_write(fe, 0xcc, 0xdd);
bc514710	206	break;
4e4d2bcf	207	case 7000000:
bc514710 CP	208	zl10353_single_write(fe, MCLK_RATIO, 0x86);
bc514710 CP	209	zl10353_single_write(fe, 0x64, 0x35);
a9dbe5dc	210	zl10353_single_write(fe, 0xcc, 0x73);
bc514710	211	break;
bc514710	212	default:
4e4d2bcf	213	c->bandwidth_hz = 8000000;
06eeefe8	214	/* fall through */
4e4d2bcf	215	case 8000000:
bc514710 CP	216	zl10353_single_write(fe, MCLK_RATIO, 0x75);
bc514710 CP	217	zl10353_single_write(fe, 0x64, 0x36);
a9dbe5dc	218	zl10353_single_write(fe, 0xcc, 0x73);
bc514710 CP	219	}
bc514710 CP	220
4e4d2bcf	221	zl10353_calc_nominal_rate(fe, c->bandwidth_hz, &nominal_rate);
f7f57770 AP	222	zl10353_single_write(fe, TRL_NOMINAL_RATE_1, msb(nominal_rate));
f7f57770 AP	223	zl10353_single_write(fe, TRL_NOMINAL_RATE_0, lsb(nominal_rate));
4e4d2bcf	224	state->bandwidth = c->bandwidth_hz;
f7f57770	225
794604c3 CP	226	zl10353_calc_input_freq(fe, &input_freq);
	227	zl10353_single_write(fe, INPUT_FREQ_1, msb(input_freq));
	228	zl10353_single_write(fe, INPUT_FREQ_0, lsb(input_freq));
	229
bc514710	230	/* Hint at TPS settings */
4e4d2bcf	231	switch (c->code_rate_HP) {
bc514710 CP	232	case FEC_2_3:
	233	tps \|= (1 << 7);
	234	break;
	235	case FEC_3_4:
	236	tps \|= (2 << 7);
	237	break;
	238	case FEC_5_6:
	239	tps \|= (3 << 7);
	240	break;
	241	case FEC_7_8:
	242	tps \|= (4 << 7);
	243	break;
	244	case FEC_1_2:
	245	case FEC_AUTO:
	246	break;
	247	default:
	248	return -EINVAL;
	249	}
	250
4e4d2bcf	251	switch (c->code_rate_LP) {
bc514710 CP	252	case FEC_2_3:
	253	tps \|= (1 << 4);
	254	break;
	255	case FEC_3_4:
	256	tps \|= (2 << 4);
	257	break;
	258	case FEC_5_6:
	259	tps \|= (3 << 4);
	260	break;
	261	case FEC_7_8:
	262	tps \|= (4 << 4);
	263	break;
	264	case FEC_1_2:
	265	case FEC_AUTO:
	266	break;
	267	case FEC_NONE:
4e4d2bcf MCC	268	if (c->hierarchy == HIERARCHY_AUTO \|\|
4e4d2bcf MCC	269	c->hierarchy == HIERARCHY_NONE)
bc514710	270	break;
06eeefe8	271	/* fall through */
bc514710 CP	272	default:
	273	return -EINVAL;
	274	}
	275
4e4d2bcf	276	switch (c->modulation) {
bc514710 CP	277	case QPSK:
	278	break;
	279	case QAM_AUTO:
	280	case QAM_16:
	281	tps \|= (1 << 13);
	282	break;
	283	case QAM_64:
	284	tps \|= (2 << 13);
	285	break;
	286	default:
	287	return -EINVAL;
	288	}
	289
4e4d2bcf	290	switch (c->transmission_mode) {
bc514710 CP	291	case TRANSMISSION_MODE_2K:
	292	case TRANSMISSION_MODE_AUTO:
	293	break;
	294	case TRANSMISSION_MODE_8K:
	295	tps \|= (1 << 0);
	296	break;
	297	default:
	298	return -EINVAL;
	299	}
	300
4e4d2bcf	301	switch (c->guard_interval) {
bc514710 CP	302	case GUARD_INTERVAL_1_32:
	303	case GUARD_INTERVAL_AUTO:
	304	break;
	305	case GUARD_INTERVAL_1_16:
	306	tps \|= (1 << 2);
	307	break;
	308	case GUARD_INTERVAL_1_8:
	309	tps \|= (2 << 2);
	310	break;
	311	case GUARD_INTERVAL_1_4:
	312	tps \|= (3 << 2);
	313	break;
	314	default:
	315	return -EINVAL;
	316	}
	317
4e4d2bcf	318	switch (c->hierarchy) {
bc514710 CP	319	case HIERARCHY_AUTO:
	320	case HIERARCHY_NONE:
	321	break;
	322	case HIERARCHY_1:
	323	tps \|= (1 << 10);
	324	break;
	325	case HIERARCHY_2:
	326	tps \|= (2 << 10);
	327	break;
	328	case HIERARCHY_4:
	329	tps \|= (3 << 10);
	330	break;
	331	default:
	332	return -EINVAL;
	333	}
	334
	335	zl10353_single_write(fe, TPS_GIVEN_1, msb(tps));
	336	zl10353_single_write(fe, TPS_GIVEN_0, lsb(tps));
	337
0a11bb86 AP	338	if (fe->ops.i2c_gate_ctrl)
0a11bb86 AP	339	fe->ops.i2c_gate_ctrl(fe, 0);
780dfef3	340
58d834ea CP	341	/*
	342	* If there is no tuner attached to the secondary I2C bus, we call
	343	* set_params to program a potential tuner attached somewhere else.
	344	* Otherwise, we update the PLL registers via calc_regs.
	345	*/
8dec0732	346	if (state->config.no_tuner) {
dea74869	347	if (fe->ops.tuner_ops.set_params) {
14d24d14	348	fe->ops.tuner_ops.set_params(fe);
0a11bb86 AP	349	if (fe->ops.i2c_gate_ctrl)
0a11bb86 AP	350	fe->ops.i2c_gate_ctrl(fe, 0);
8dec0732	351	}
58d834ea	352	} else if (fe->ops.tuner_ops.calc_regs) {
249fa0b0	353	fe->ops.tuner_ops.calc_regs(fe, pllbuf + 1, 5);
e994b8d9	354	pllbuf[1] <<= 1;
58d834ea	355	zl10353_write(fe, pllbuf, sizeof(pllbuf));
e994b8d9	356	}
780dfef3	357
fc3398d8	358	zl10353_single_write(fe, 0x5F, 0x13);
58d834ea CP	359
	360	/* If no attached tuner or invalid PLL registers, just start the FSM. */
	361	if (state->config.no_tuner \|\| fe->ops.tuner_ops.calc_regs == NULL)
	362	zl10353_single_write(fe, FSM_GO, 0x01);
	363	else
	364	zl10353_single_write(fe, TUNER_GO, 0x01);
	365
bc514710 CP	366	return 0;
	367	}
	368
7e3e68bc MCC	369	static int zl10353_get_parameters(struct dvb_frontend *fe,
7e3e68bc MCC	370	struct dtv_frontend_properties *c)
bc514710 CP	371	{
bc514710 CP	372	struct zl10353_state *state = fe->demodulator_priv;
bc514710 CP	373	int s6, s9;
	374	u16 tps;
	375	static const u8 tps_fec_to_api[8] = {
	376	FEC_1_2,
	377	FEC_2_3,
	378	FEC_3_4,
	379	FEC_5_6,
	380	FEC_7_8,
	381	FEC_AUTO,
	382	FEC_AUTO,
	383	FEC_AUTO
	384	};
	385
	386	s6 = zl10353_read_register(state, STATUS_6);
	387	s9 = zl10353_read_register(state, STATUS_9);
	388	if (s6 < 0 \|\| s9 < 0)
	389	return -EREMOTEIO;
	390	if ((s6 & (1 << 5)) == 0 \|\| (s9 & (1 << 4)) == 0)
	391	return -EINVAL; /* no FE or TPS lock */
	392
	393	tps = zl10353_read_register(state, TPS_RECEIVED_1) << 8 \|
	394	zl10353_read_register(state, TPS_RECEIVED_0);
	395
4e4d2bcf MCC	396	c->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
4e4d2bcf MCC	397	c->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];
bc514710 CP	398
	399	switch ((tps >> 13) & 3) {
	400	case 0:
4e4d2bcf	401	c->modulation = QPSK;
bc514710 CP	402	break;
bc514710 CP	403	case 1:
4e4d2bcf	404	c->modulation = QAM_16;
bc514710 CP	405	break;
bc514710 CP	406	case 2:
4e4d2bcf	407	c->modulation = QAM_64;
bc514710 CP	408	break;
bc514710 CP	409	default:
4e4d2bcf	410	c->modulation = QAM_AUTO;
bc514710 CP	411	break;
	412	}
	413
4e4d2bcf	414	c->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K :
bc514710 CP	415	TRANSMISSION_MODE_2K;
	416
	417	switch ((tps >> 2) & 3) {
	418	case 0:
4e4d2bcf	419	c->guard_interval = GUARD_INTERVAL_1_32;
bc514710 CP	420	break;
bc514710 CP	421	case 1:
4e4d2bcf	422	c->guard_interval = GUARD_INTERVAL_1_16;
bc514710 CP	423	break;
bc514710 CP	424	case 2:
4e4d2bcf	425	c->guard_interval = GUARD_INTERVAL_1_8;
bc514710 CP	426	break;
bc514710 CP	427	case 3:
4e4d2bcf	428	c->guard_interval = GUARD_INTERVAL_1_4;
bc514710 CP	429	break;
bc514710 CP	430	default:
4e4d2bcf	431	c->guard_interval = GUARD_INTERVAL_AUTO;
bc514710 CP	432	break;
	433	}
	434
	435	switch ((tps >> 10) & 7) {
	436	case 0:
4e4d2bcf	437	c->hierarchy = HIERARCHY_NONE;
bc514710 CP	438	break;
bc514710 CP	439	case 1:
4e4d2bcf	440	c->hierarchy = HIERARCHY_1;
bc514710 CP	441	break;
bc514710 CP	442	case 2:
4e4d2bcf	443	c->hierarchy = HIERARCHY_2;
bc514710 CP	444	break;
bc514710 CP	445	case 3:
4e4d2bcf	446	c->hierarchy = HIERARCHY_4;
bc514710 CP	447	break;
bc514710 CP	448	default:
4e4d2bcf	449	c->hierarchy = HIERARCHY_AUTO;
bc514710 CP	450	break;
	451	}
	452
4e4d2bcf MCC	453	c->frequency = state->frequency;
	454	c->bandwidth_hz = state->bandwidth;
	455	c->inversion = INVERSION_AUTO;
780dfef3 CP	456
	457	return 0;
	458	}
	459
0df289a2	460	static int zl10353_read_status(struct dvb_frontend fe, enum fe_status status)
780dfef3 CP	461	{
	462	struct zl10353_state *state = fe->demodulator_priv;
	463	int s6, s7, s8;
	464
	465	if ((s6 = zl10353_read_register(state, STATUS_6)) < 0)
	466	return -EREMOTEIO;
	467	if ((s7 = zl10353_read_register(state, STATUS_7)) < 0)
	468	return -EREMOTEIO;
	469	if ((s8 = zl10353_read_register(state, STATUS_8)) < 0)
	470	return -EREMOTEIO;
	471
	472	*status = 0;
	473	if (s6 & (1 << 2))
	474	*status \|= FE_HAS_CARRIER;
	475	if (s6 & (1 << 1))
	476	*status \|= FE_HAS_VITERBI;
	477	if (s6 & (1 << 5))
	478	*status \|= FE_HAS_LOCK;
	479	if (s7 & (1 << 4))
	480	*status \|= FE_HAS_SYNC;
	481	if (s8 & (1 << 6))
	482	*status \|= FE_HAS_SIGNAL;
	483
	484	if ((*status & (FE_HAS_CARRIER \| FE_HAS_VITERBI \| FE_HAS_SYNC)) !=
	485	(FE_HAS_CARRIER \| FE_HAS_VITERBI \| FE_HAS_SYNC))
	486	*status &= ~FE_HAS_LOCK;
	487
	488	return 0;
	489	}
	490
67b60aad CP	491	static int zl10353_read_ber(struct dvb_frontend fe, u32 ber)
	492	{
	493	struct zl10353_state *state = fe->demodulator_priv;
	494
6345f0f6 CP	495	*ber = zl10353_read_register(state, RS_ERR_CNT_2) << 16 \|
	496	zl10353_read_register(state, RS_ERR_CNT_1) << 8 \|
	497	zl10353_read_register(state, RS_ERR_CNT_0);
67b60aad CP	498
	499	return 0;
	500	}
	501
	502	static int zl10353_read_signal_strength(struct dvb_frontend fe, u16 strength)
	503	{
	504	struct zl10353_state *state = fe->demodulator_priv;
	505
6345f0f6 CP	506	u16 signal = zl10353_read_register(state, AGC_GAIN_1) << 10 \|
6345f0f6 CP	507	zl10353_read_register(state, AGC_GAIN_0) << 2 \| 3;
67b60aad CP	508
	509	*strength = ~signal;
	510
	511	return 0;
	512	}
	513
780dfef3 CP	514	static int zl10353_read_snr(struct dvb_frontend fe, u16 snr)
	515	{
	516	struct zl10353_state *state = fe->demodulator_priv;
	517	u8 _snr;
	518
	519	if (debug_regs)
	520	zl10353_dump_regs(fe);
	521
	522	_snr = zl10353_read_register(state, SNR);
13c6a9f7	523	snr = 10 _snr / 8;
780dfef3 CP	524
	525	return 0;
	526	}
	527
67b60aad CP	528	static int zl10353_read_ucblocks(struct dvb_frontend fe, u32 ucblocks)
	529	{
	530	struct zl10353_state *state = fe->demodulator_priv;
2267d2d7	531	u32 ubl = 0;
decee2e8	532
2267d2d7 MCC	533	ubl = zl10353_read_register(state, RS_UBC_1) << 8 \|
2267d2d7 MCC	534	zl10353_read_register(state, RS_UBC_0);
67b60aad	535
2267d2d7 MCC	536	state->ucblocks += ubl;
2267d2d7 MCC	537	*ucblocks = state->ucblocks;
67b60aad CP	538
	539	return 0;
	540	}
	541
780dfef3 CP	542	static int zl10353_get_tune_settings(struct dvb_frontend *fe,
	543	struct dvb_frontend_tune_settings
	544	*fe_tune_settings)
	545	{
	546	fe_tune_settings->min_delay_ms = 1000;
	547	fe_tune_settings->step_size = 0;
	548	fe_tune_settings->max_drift = 0;
	549
	550	return 0;
	551	}
	552
	553	static int zl10353_init(struct dvb_frontend *fe)
	554	{
	555	struct zl10353_state *state = fe->demodulator_priv;
	556	u8 zl10353_reset_attach[6] = { 0x50, 0x03, 0x64, 0x46, 0x15, 0x0F };
780dfef3 CP	557
	558	if (debug_regs)
	559	zl10353_dump_regs(fe);
8fb95784 CP	560	if (state->config.parallel_ts)
8fb95784 CP	561	zl10353_reset_attach[2] &= ~0x20;
378a2793 AP	562	if (state->config.clock_ctl_1)
	563	zl10353_reset_attach[3] = state->config.clock_ctl_1;
	564	if (state->config.pll_0)
	565	zl10353_reset_attach[4] = state->config.pll_0;
780dfef3 CP	566
780dfef3 CP	567	/* Do a "hard" reset if not already done */
8fb95784 CP	568	if (zl10353_read_register(state, 0x50) != zl10353_reset_attach[1] \|\|
8fb95784 CP	569	zl10353_read_register(state, 0x51) != zl10353_reset_attach[2]) {
fdf07b02	570	zl10353_write(fe, zl10353_reset_attach,
780dfef3 CP	571	sizeof(zl10353_reset_attach));
	572	if (debug_regs)
	573	zl10353_dump_regs(fe);
	574	}
	575
	576	return 0;
	577	}
	578
0a11bb86 AP	579	static int zl10353_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
0a11bb86 AP	580	{
899a6f67	581	struct zl10353_state *state = fe->demodulator_priv;
0a11bb86 AP	582	u8 val = 0x0a;
0a11bb86 AP	583
5f77af93	584	if (state->config.disable_i2c_gate_ctrl) {
899a6f67 DB	585	/* No tuner attached to the internal I2C bus */
	586	/* If set enable I2C bridge, the main I2C bus stopped hardly */
	587	return 0;
	588	}
	589
0a11bb86 AP	590	if (enable)
	591	val \|= 0x10;
	592
	593	return zl10353_single_write(fe, 0x62, val);
	594	}
	595
780dfef3 CP	596	static void zl10353_release(struct dvb_frontend *fe)
	597	{
	598	struct zl10353_state *state = fe->demodulator_priv;
780dfef3 CP	599	kfree(state);
	600	}
	601
bd336e63	602	static const struct dvb_frontend_ops zl10353_ops;
780dfef3 CP	603
	604	struct dvb_frontend zl10353_attach(const struct zl10353_config config,
	605	struct i2c_adapter *i2c)
	606	{
	607	struct zl10353_state *state = NULL;
378a2793	608	int id;
780dfef3 CP	609
	610	/* allocate memory for the internal state */
	611	state = kzalloc(sizeof(struct zl10353_state), GFP_KERNEL);
	612	if (state == NULL)
	613	goto error;
	614
	615	/* setup the state */
	616	state->i2c = i2c;
	617	memcpy(&state->config, config, sizeof(struct zl10353_config));
780dfef3 CP	618
780dfef3 CP	619	/* check if the demod is there */
378a2793 AP	620	id = zl10353_read_register(state, CHIP_ID);
378a2793 AP	621	if ((id != ID_ZL10353) && (id != ID_CE6230) && (id != ID_CE6231))
780dfef3 CP	622	goto error;
	623
	624	/* create dvb_frontend */
dea74869	625	memcpy(&state->frontend.ops, &zl10353_ops, sizeof(struct dvb_frontend_ops));
780dfef3 CP	626	state->frontend.demodulator_priv = state;
	627
	628	return &state->frontend;
	629	error:
	630	kfree(state);
	631	return NULL;
	632	}
	633
bd336e63	634	static const struct dvb_frontend_ops zl10353_ops = {
4e4d2bcf	635	.delsys = { SYS_DVBT },
780dfef3 CP	636	.info = {
780dfef3 CP	637	.name = "Zarlink ZL10353 DVB-T",
780dfef3 CP	638	.frequency_min = 174000000,
	639	.frequency_max = 862000000,
	640	.frequency_stepsize = 166667,
	641	.frequency_tolerance = 0,
	642	.caps = FE_CAN_FEC_1_2 \| FE_CAN_FEC_2_3 \|
	643	FE_CAN_FEC_3_4 \| FE_CAN_FEC_5_6 \| FE_CAN_FEC_7_8 \|
	644	FE_CAN_FEC_AUTO \|
	645	FE_CAN_QPSK \| FE_CAN_QAM_16 \| FE_CAN_QAM_64 \| FE_CAN_QAM_AUTO \|
	646	FE_CAN_TRANSMISSION_MODE_AUTO \| FE_CAN_GUARD_INTERVAL_AUTO \|
	647	FE_CAN_HIERARCHY_AUTO \| FE_CAN_RECOVER \|
	648	FE_CAN_MUTE_TS
	649	},
	650
	651	.release = zl10353_release,
	652
	653	.init = zl10353_init,
	654	.sleep = zl10353_sleep,
0a11bb86	655	.i2c_gate_ctrl = zl10353_i2c_gate_ctrl,
c10d14d6	656	.write = zl10353_write,
780dfef3	657
4e4d2bcf MCC	658	.set_frontend = zl10353_set_parameters,
4e4d2bcf MCC	659	.get_frontend = zl10353_get_parameters,
780dfef3 CP	660	.get_tune_settings = zl10353_get_tune_settings,
	661
	662	.read_status = zl10353_read_status,
67b60aad CP	663	.read_ber = zl10353_read_ber,
67b60aad CP	664	.read_signal_strength = zl10353_read_signal_strength,
780dfef3	665	.read_snr = zl10353_read_snr,
67b60aad	666	.read_ucblocks = zl10353_read_ucblocks,
780dfef3 CP	667	};
780dfef3 CP	668
f7f57770 AP	669	module_param(debug, int, 0644);
	670	MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
	671
780dfef3 CP	672	module_param(debug_regs, int, 0644);
	673	MODULE_PARM_DESC(debug_regs, "Turn on/off frontend register dumps (default:off).");
	674
	675	MODULE_DESCRIPTION("Zarlink ZL10353 DVB-T demodulator driver");
	676	MODULE_AUTHOR("Chris Pascoe");
	677	MODULE_LICENSE("GPL");
	678
	679	EXPORT_SYMBOL(zl10353_attach);