Commit | Line | Data |
---|---|---|
c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
780dfef3 CP |
2 | /* |
3 | * Driver for Zarlink DVB-T ZL10353 demodulator | |
4 | * | |
794604c3 | 5 | * Copyright (C) 2006, 2007 Christopher Pascoe <c.pascoe@itee.uq.edu.au> |
780dfef3 CP |
6 | */ |
7 | ||
8 | #include <linux/kernel.h> | |
9 | #include <linux/module.h> | |
780dfef3 CP |
10 | #include <linux/init.h> |
11 | #include <linux/delay.h> | |
12 | #include <linux/string.h> | |
13 | #include <linux/slab.h> | |
794604c3 | 14 | #include <asm/div64.h> |
780dfef3 | 15 | |
fada1935 | 16 | #include <media/dvb_frontend.h> |
780dfef3 CP |
17 | #include "zl10353_priv.h" |
18 | #include "zl10353.h" | |
19 | ||
20 | struct zl10353_state { | |
21 | struct i2c_adapter *i2c; | |
22 | struct dvb_frontend frontend; | |
780dfef3 CP |
23 | |
24 | struct zl10353_config config; | |
bc514710 | 25 | |
4e4d2bcf MCC |
26 | u32 bandwidth; |
27 | u32 ucblocks; | |
28 | u32 frequency; | |
780dfef3 CP |
29 | }; |
30 | ||
f7f57770 AP |
31 | static int debug; |
32 | #define dprintk(args...) \ | |
33 | do { \ | |
34 | if (debug) printk(KERN_DEBUG "zl10353: " args); \ | |
35 | } while (0) | |
36 | ||
ff699e6b | 37 | static int debug_regs; |
780dfef3 CP |
38 | |
39 | static int zl10353_single_write(struct dvb_frontend *fe, u8 reg, u8 val) | |
40 | { | |
41 | struct zl10353_state *state = fe->demodulator_priv; | |
42 | u8 buf[2] = { reg, val }; | |
43 | struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0, | |
44 | .buf = buf, .len = 2 }; | |
45 | int err = i2c_transfer(state->i2c, &msg, 1); | |
46 | if (err != 1) { | |
47 | printk("zl10353: write to reg %x failed (err = %d)!\n", reg, err); | |
48 | return err; | |
49 | } | |
50 | return 0; | |
51 | } | |
52 | ||
2e4e98e7 | 53 | static int zl10353_write(struct dvb_frontend *fe, const u8 ibuf[], int ilen) |
780dfef3 CP |
54 | { |
55 | int err, i; | |
56 | for (i = 0; i < ilen - 1; i++) | |
57 | if ((err = zl10353_single_write(fe, ibuf[0] + i, ibuf[i + 1]))) | |
58 | return err; | |
59 | ||
60 | return 0; | |
61 | } | |
62 | ||
63 | static int zl10353_read_register(struct zl10353_state *state, u8 reg) | |
64 | { | |
65 | int ret; | |
66 | u8 b0[1] = { reg }; | |
67 | u8 b1[1] = { 0 }; | |
68 | struct i2c_msg msg[2] = { { .addr = state->config.demod_address, | |
69 | .flags = 0, | |
70 | .buf = b0, .len = 1 }, | |
71 | { .addr = state->config.demod_address, | |
72 | .flags = I2C_M_RD, | |
73 | .buf = b1, .len = 1 } }; | |
74 | ||
75 | ret = i2c_transfer(state->i2c, msg, 2); | |
76 | ||
77 | if (ret != 2) { | |
78 | printk("%s: readreg error (reg=%d, ret==%i)\n", | |
271ddbf7 | 79 | __func__, reg, ret); |
780dfef3 CP |
80 | return ret; |
81 | } | |
82 | ||
83 | return b1[0]; | |
84 | } | |
85 | ||
c04e89b1 | 86 | static void zl10353_dump_regs(struct dvb_frontend *fe) |
780dfef3 CP |
87 | { |
88 | struct zl10353_state *state = fe->demodulator_priv; | |
780dfef3 CP |
89 | int ret; |
90 | u8 reg; | |
91 | ||
92 | /* Dump all registers. */ | |
93 | for (reg = 0; ; reg++) { | |
94 | if (reg % 16 == 0) { | |
95 | if (reg) | |
458f9aa3 JN |
96 | printk(KERN_CONT "\n"); |
97 | printk(KERN_DEBUG "%02x:", reg); | |
780dfef3 CP |
98 | } |
99 | ret = zl10353_read_register(state, reg); | |
100 | if (ret >= 0) | |
458f9aa3 | 101 | printk(KERN_CONT " %02x", (u8)ret); |
780dfef3 | 102 | else |
458f9aa3 | 103 | printk(KERN_CONT " --"); |
780dfef3 CP |
104 | if (reg == 0xff) |
105 | break; | |
106 | } | |
458f9aa3 | 107 | printk(KERN_CONT "\n"); |
780dfef3 CP |
108 | } |
109 | ||
f7f57770 | 110 | static void zl10353_calc_nominal_rate(struct dvb_frontend *fe, |
4e4d2bcf | 111 | u32 bandwidth, |
f7f57770 AP |
112 | u16 *nominal_rate) |
113 | { | |
f7f57770 | 114 | struct zl10353_state *state = fe->demodulator_priv; |
a1dcd9de CP |
115 | u32 adc_clock = 450560; /* 45.056 MHz */ |
116 | u64 value; | |
4e4d2bcf | 117 | u8 bw = bandwidth / 1000000; |
f7f57770 AP |
118 | |
119 | if (state->config.adc_clock) | |
120 | adc_clock = state->config.adc_clock; | |
121 | ||
18ff605a AM |
122 | value = (u64)10 * (1 << 23) / 7 * 125; |
123 | value = (bw * value) + adc_clock / 2; | |
8a73faab | 124 | *nominal_rate = div_u64(value, adc_clock); |
f7f57770 AP |
125 | |
126 | dprintk("%s: bw %d, adc_clock %d => 0x%x\n", | |
271ddbf7 | 127 | __func__, bw, adc_clock, *nominal_rate); |
f7f57770 AP |
128 | } |
129 | ||
794604c3 CP |
130 | static void zl10353_calc_input_freq(struct dvb_frontend *fe, |
131 | u16 *input_freq) | |
132 | { | |
133 | struct zl10353_state *state = fe->demodulator_priv; | |
a1dcd9de CP |
134 | u32 adc_clock = 450560; /* 45.056 MHz */ |
135 | int if2 = 361667; /* 36.1667 MHz */ | |
794604c3 CP |
136 | int ife; |
137 | u64 value; | |
138 | ||
139 | if (state->config.adc_clock) | |
140 | adc_clock = state->config.adc_clock; | |
141 | if (state->config.if2) | |
142 | if2 = state->config.if2; | |
143 | ||
144 | if (adc_clock >= if2 * 2) | |
145 | ife = if2; | |
146 | else { | |
147 | ife = adc_clock - (if2 % adc_clock); | |
148 | if (ife > adc_clock / 2) | |
149 | ife = adc_clock - ife; | |
150 | } | |
8a73faab | 151 | value = div_u64((u64)65536 * ife + adc_clock / 2, adc_clock); |
794604c3 CP |
152 | *input_freq = -value; |
153 | ||
154 | dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n", | |
271ddbf7 | 155 | __func__, if2, ife, adc_clock, -(int)value, *input_freq); |
794604c3 CP |
156 | } |
157 | ||
780dfef3 CP |
158 | static int zl10353_sleep(struct dvb_frontend *fe) |
159 | { | |
160 | static u8 zl10353_softdown[] = { 0x50, 0x0C, 0x44 }; | |
161 | ||
162 | zl10353_write(fe, zl10353_softdown, sizeof(zl10353_softdown)); | |
163 | return 0; | |
164 | } | |
165 | ||
4e4d2bcf | 166 | static int zl10353_set_parameters(struct dvb_frontend *fe) |
780dfef3 | 167 | { |
4e4d2bcf | 168 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
8dec0732 | 169 | struct zl10353_state *state = fe->demodulator_priv; |
794604c3 | 170 | u16 nominal_rate, input_freq; |
bc514710 CP |
171 | u8 pllbuf[6] = { 0x67 }, acq_ctl = 0; |
172 | u16 tps = 0; | |
780dfef3 | 173 | |
4e4d2bcf | 174 | state->frequency = c->frequency; |
decee2e8 | 175 | |
bc514710 | 176 | zl10353_single_write(fe, RESET, 0x80); |
780dfef3 CP |
177 | udelay(200); |
178 | zl10353_single_write(fe, 0xEA, 0x01); | |
179 | udelay(200); | |
180 | zl10353_single_write(fe, 0xEA, 0x00); | |
181 | ||
bc514710 CP |
182 | zl10353_single_write(fe, AGC_TARGET, 0x28); |
183 | ||
4e4d2bcf | 184 | if (c->transmission_mode != TRANSMISSION_MODE_AUTO) |
bc514710 | 185 | acq_ctl |= (1 << 0); |
4e4d2bcf | 186 | if (c->guard_interval != GUARD_INTERVAL_AUTO) |
bc514710 CP |
187 | acq_ctl |= (1 << 1); |
188 | zl10353_single_write(fe, ACQ_CTL, acq_ctl); | |
f7f57770 | 189 | |
4e4d2bcf MCC |
190 | switch (c->bandwidth_hz) { |
191 | case 6000000: | |
bc514710 CP |
192 | /* These are extrapolated from the 7 and 8MHz values */ |
193 | zl10353_single_write(fe, MCLK_RATIO, 0x97); | |
194 | zl10353_single_write(fe, 0x64, 0x34); | |
a9dbe5dc | 195 | zl10353_single_write(fe, 0xcc, 0xdd); |
bc514710 | 196 | break; |
4e4d2bcf | 197 | case 7000000: |
bc514710 CP |
198 | zl10353_single_write(fe, MCLK_RATIO, 0x86); |
199 | zl10353_single_write(fe, 0x64, 0x35); | |
a9dbe5dc | 200 | zl10353_single_write(fe, 0xcc, 0x73); |
bc514710 | 201 | break; |
bc514710 | 202 | default: |
4e4d2bcf | 203 | c->bandwidth_hz = 8000000; |
06eeefe8 | 204 | /* fall through */ |
4e4d2bcf | 205 | case 8000000: |
bc514710 CP |
206 | zl10353_single_write(fe, MCLK_RATIO, 0x75); |
207 | zl10353_single_write(fe, 0x64, 0x36); | |
a9dbe5dc | 208 | zl10353_single_write(fe, 0xcc, 0x73); |
bc514710 CP |
209 | } |
210 | ||
4e4d2bcf | 211 | zl10353_calc_nominal_rate(fe, c->bandwidth_hz, &nominal_rate); |
f7f57770 AP |
212 | zl10353_single_write(fe, TRL_NOMINAL_RATE_1, msb(nominal_rate)); |
213 | zl10353_single_write(fe, TRL_NOMINAL_RATE_0, lsb(nominal_rate)); | |
4e4d2bcf | 214 | state->bandwidth = c->bandwidth_hz; |
f7f57770 | 215 | |
794604c3 CP |
216 | zl10353_calc_input_freq(fe, &input_freq); |
217 | zl10353_single_write(fe, INPUT_FREQ_1, msb(input_freq)); | |
218 | zl10353_single_write(fe, INPUT_FREQ_0, lsb(input_freq)); | |
219 | ||
bc514710 | 220 | /* Hint at TPS settings */ |
4e4d2bcf | 221 | switch (c->code_rate_HP) { |
bc514710 CP |
222 | case FEC_2_3: |
223 | tps |= (1 << 7); | |
224 | break; | |
225 | case FEC_3_4: | |
226 | tps |= (2 << 7); | |
227 | break; | |
228 | case FEC_5_6: | |
229 | tps |= (3 << 7); | |
230 | break; | |
231 | case FEC_7_8: | |
232 | tps |= (4 << 7); | |
233 | break; | |
234 | case FEC_1_2: | |
235 | case FEC_AUTO: | |
236 | break; | |
237 | default: | |
238 | return -EINVAL; | |
239 | } | |
240 | ||
4e4d2bcf | 241 | switch (c->code_rate_LP) { |
bc514710 CP |
242 | case FEC_2_3: |
243 | tps |= (1 << 4); | |
244 | break; | |
245 | case FEC_3_4: | |
246 | tps |= (2 << 4); | |
247 | break; | |
248 | case FEC_5_6: | |
249 | tps |= (3 << 4); | |
250 | break; | |
251 | case FEC_7_8: | |
252 | tps |= (4 << 4); | |
253 | break; | |
254 | case FEC_1_2: | |
255 | case FEC_AUTO: | |
256 | break; | |
257 | case FEC_NONE: | |
4e4d2bcf MCC |
258 | if (c->hierarchy == HIERARCHY_AUTO || |
259 | c->hierarchy == HIERARCHY_NONE) | |
bc514710 | 260 | break; |
06eeefe8 | 261 | /* fall through */ |
bc514710 CP |
262 | default: |
263 | return -EINVAL; | |
264 | } | |
265 | ||
4e4d2bcf | 266 | switch (c->modulation) { |
bc514710 CP |
267 | case QPSK: |
268 | break; | |
269 | case QAM_AUTO: | |
270 | case QAM_16: | |
271 | tps |= (1 << 13); | |
272 | break; | |
273 | case QAM_64: | |
274 | tps |= (2 << 13); | |
275 | break; | |
276 | default: | |
277 | return -EINVAL; | |
278 | } | |
279 | ||
4e4d2bcf | 280 | switch (c->transmission_mode) { |
bc514710 CP |
281 | case TRANSMISSION_MODE_2K: |
282 | case TRANSMISSION_MODE_AUTO: | |
283 | break; | |
284 | case TRANSMISSION_MODE_8K: | |
285 | tps |= (1 << 0); | |
286 | break; | |
287 | default: | |
288 | return -EINVAL; | |
289 | } | |
290 | ||
4e4d2bcf | 291 | switch (c->guard_interval) { |
bc514710 CP |
292 | case GUARD_INTERVAL_1_32: |
293 | case GUARD_INTERVAL_AUTO: | |
294 | break; | |
295 | case GUARD_INTERVAL_1_16: | |
296 | tps |= (1 << 2); | |
297 | break; | |
298 | case GUARD_INTERVAL_1_8: | |
299 | tps |= (2 << 2); | |
300 | break; | |
301 | case GUARD_INTERVAL_1_4: | |
302 | tps |= (3 << 2); | |
303 | break; | |
304 | default: | |
305 | return -EINVAL; | |
306 | } | |
307 | ||
4e4d2bcf | 308 | switch (c->hierarchy) { |
bc514710 CP |
309 | case HIERARCHY_AUTO: |
310 | case HIERARCHY_NONE: | |
311 | break; | |
312 | case HIERARCHY_1: | |
313 | tps |= (1 << 10); | |
314 | break; | |
315 | case HIERARCHY_2: | |
316 | tps |= (2 << 10); | |
317 | break; | |
318 | case HIERARCHY_4: | |
319 | tps |= (3 << 10); | |
320 | break; | |
321 | default: | |
322 | return -EINVAL; | |
323 | } | |
324 | ||
325 | zl10353_single_write(fe, TPS_GIVEN_1, msb(tps)); | |
326 | zl10353_single_write(fe, TPS_GIVEN_0, lsb(tps)); | |
327 | ||
0a11bb86 AP |
328 | if (fe->ops.i2c_gate_ctrl) |
329 | fe->ops.i2c_gate_ctrl(fe, 0); | |
780dfef3 | 330 | |
58d834ea CP |
331 | /* |
332 | * If there is no tuner attached to the secondary I2C bus, we call | |
333 | * set_params to program a potential tuner attached somewhere else. | |
334 | * Otherwise, we update the PLL registers via calc_regs. | |
335 | */ | |
8dec0732 | 336 | if (state->config.no_tuner) { |
dea74869 | 337 | if (fe->ops.tuner_ops.set_params) { |
14d24d14 | 338 | fe->ops.tuner_ops.set_params(fe); |
0a11bb86 AP |
339 | if (fe->ops.i2c_gate_ctrl) |
340 | fe->ops.i2c_gate_ctrl(fe, 0); | |
8dec0732 | 341 | } |
58d834ea | 342 | } else if (fe->ops.tuner_ops.calc_regs) { |
249fa0b0 | 343 | fe->ops.tuner_ops.calc_regs(fe, pllbuf + 1, 5); |
e994b8d9 | 344 | pllbuf[1] <<= 1; |
58d834ea | 345 | zl10353_write(fe, pllbuf, sizeof(pllbuf)); |
e994b8d9 | 346 | } |
780dfef3 | 347 | |
fc3398d8 | 348 | zl10353_single_write(fe, 0x5F, 0x13); |
58d834ea CP |
349 | |
350 | /* If no attached tuner or invalid PLL registers, just start the FSM. */ | |
351 | if (state->config.no_tuner || fe->ops.tuner_ops.calc_regs == NULL) | |
352 | zl10353_single_write(fe, FSM_GO, 0x01); | |
353 | else | |
354 | zl10353_single_write(fe, TUNER_GO, 0x01); | |
355 | ||
bc514710 CP |
356 | return 0; |
357 | } | |
358 | ||
7e3e68bc MCC |
359 | static int zl10353_get_parameters(struct dvb_frontend *fe, |
360 | struct dtv_frontend_properties *c) | |
bc514710 CP |
361 | { |
362 | struct zl10353_state *state = fe->demodulator_priv; | |
bc514710 CP |
363 | int s6, s9; |
364 | u16 tps; | |
365 | static const u8 tps_fec_to_api[8] = { | |
366 | FEC_1_2, | |
367 | FEC_2_3, | |
368 | FEC_3_4, | |
369 | FEC_5_6, | |
370 | FEC_7_8, | |
371 | FEC_AUTO, | |
372 | FEC_AUTO, | |
373 | FEC_AUTO | |
374 | }; | |
375 | ||
376 | s6 = zl10353_read_register(state, STATUS_6); | |
377 | s9 = zl10353_read_register(state, STATUS_9); | |
378 | if (s6 < 0 || s9 < 0) | |
379 | return -EREMOTEIO; | |
380 | if ((s6 & (1 << 5)) == 0 || (s9 & (1 << 4)) == 0) | |
381 | return -EINVAL; /* no FE or TPS lock */ | |
382 | ||
383 | tps = zl10353_read_register(state, TPS_RECEIVED_1) << 8 | | |
384 | zl10353_read_register(state, TPS_RECEIVED_0); | |
385 | ||
4e4d2bcf MCC |
386 | c->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7]; |
387 | c->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7]; | |
bc514710 CP |
388 | |
389 | switch ((tps >> 13) & 3) { | |
390 | case 0: | |
4e4d2bcf | 391 | c->modulation = QPSK; |
bc514710 CP |
392 | break; |
393 | case 1: | |
4e4d2bcf | 394 | c->modulation = QAM_16; |
bc514710 CP |
395 | break; |
396 | case 2: | |
4e4d2bcf | 397 | c->modulation = QAM_64; |
bc514710 CP |
398 | break; |
399 | default: | |
4e4d2bcf | 400 | c->modulation = QAM_AUTO; |
bc514710 CP |
401 | break; |
402 | } | |
403 | ||
4e4d2bcf | 404 | c->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K : |
bc514710 CP |
405 | TRANSMISSION_MODE_2K; |
406 | ||
407 | switch ((tps >> 2) & 3) { | |
408 | case 0: | |
4e4d2bcf | 409 | c->guard_interval = GUARD_INTERVAL_1_32; |
bc514710 CP |
410 | break; |
411 | case 1: | |
4e4d2bcf | 412 | c->guard_interval = GUARD_INTERVAL_1_16; |
bc514710 CP |
413 | break; |
414 | case 2: | |
4e4d2bcf | 415 | c->guard_interval = GUARD_INTERVAL_1_8; |
bc514710 CP |
416 | break; |
417 | case 3: | |
4e4d2bcf | 418 | c->guard_interval = GUARD_INTERVAL_1_4; |
bc514710 CP |
419 | break; |
420 | default: | |
4e4d2bcf | 421 | c->guard_interval = GUARD_INTERVAL_AUTO; |
bc514710 CP |
422 | break; |
423 | } | |
424 | ||
425 | switch ((tps >> 10) & 7) { | |
426 | case 0: | |
4e4d2bcf | 427 | c->hierarchy = HIERARCHY_NONE; |
bc514710 CP |
428 | break; |
429 | case 1: | |
4e4d2bcf | 430 | c->hierarchy = HIERARCHY_1; |
bc514710 CP |
431 | break; |
432 | case 2: | |
4e4d2bcf | 433 | c->hierarchy = HIERARCHY_2; |
bc514710 CP |
434 | break; |
435 | case 3: | |
4e4d2bcf | 436 | c->hierarchy = HIERARCHY_4; |
bc514710 CP |
437 | break; |
438 | default: | |
4e4d2bcf | 439 | c->hierarchy = HIERARCHY_AUTO; |
bc514710 CP |
440 | break; |
441 | } | |
442 | ||
4e4d2bcf MCC |
443 | c->frequency = state->frequency; |
444 | c->bandwidth_hz = state->bandwidth; | |
445 | c->inversion = INVERSION_AUTO; | |
780dfef3 CP |
446 | |
447 | return 0; | |
448 | } | |
449 | ||
0df289a2 | 450 | static int zl10353_read_status(struct dvb_frontend *fe, enum fe_status *status) |
780dfef3 CP |
451 | { |
452 | struct zl10353_state *state = fe->demodulator_priv; | |
453 | int s6, s7, s8; | |
454 | ||
455 | if ((s6 = zl10353_read_register(state, STATUS_6)) < 0) | |
456 | return -EREMOTEIO; | |
457 | if ((s7 = zl10353_read_register(state, STATUS_7)) < 0) | |
458 | return -EREMOTEIO; | |
459 | if ((s8 = zl10353_read_register(state, STATUS_8)) < 0) | |
460 | return -EREMOTEIO; | |
461 | ||
462 | *status = 0; | |
463 | if (s6 & (1 << 2)) | |
464 | *status |= FE_HAS_CARRIER; | |
465 | if (s6 & (1 << 1)) | |
466 | *status |= FE_HAS_VITERBI; | |
467 | if (s6 & (1 << 5)) | |
468 | *status |= FE_HAS_LOCK; | |
469 | if (s7 & (1 << 4)) | |
470 | *status |= FE_HAS_SYNC; | |
471 | if (s8 & (1 << 6)) | |
472 | *status |= FE_HAS_SIGNAL; | |
473 | ||
474 | if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) != | |
475 | (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) | |
476 | *status &= ~FE_HAS_LOCK; | |
477 | ||
478 | return 0; | |
479 | } | |
480 | ||
67b60aad CP |
481 | static int zl10353_read_ber(struct dvb_frontend *fe, u32 *ber) |
482 | { | |
483 | struct zl10353_state *state = fe->demodulator_priv; | |
484 | ||
6345f0f6 CP |
485 | *ber = zl10353_read_register(state, RS_ERR_CNT_2) << 16 | |
486 | zl10353_read_register(state, RS_ERR_CNT_1) << 8 | | |
487 | zl10353_read_register(state, RS_ERR_CNT_0); | |
67b60aad CP |
488 | |
489 | return 0; | |
490 | } | |
491 | ||
492 | static int zl10353_read_signal_strength(struct dvb_frontend *fe, u16 *strength) | |
493 | { | |
494 | struct zl10353_state *state = fe->demodulator_priv; | |
495 | ||
6345f0f6 CP |
496 | u16 signal = zl10353_read_register(state, AGC_GAIN_1) << 10 | |
497 | zl10353_read_register(state, AGC_GAIN_0) << 2 | 3; | |
67b60aad CP |
498 | |
499 | *strength = ~signal; | |
500 | ||
501 | return 0; | |
502 | } | |
503 | ||
780dfef3 CP |
504 | static int zl10353_read_snr(struct dvb_frontend *fe, u16 *snr) |
505 | { | |
506 | struct zl10353_state *state = fe->demodulator_priv; | |
507 | u8 _snr; | |
508 | ||
509 | if (debug_regs) | |
510 | zl10353_dump_regs(fe); | |
511 | ||
512 | _snr = zl10353_read_register(state, SNR); | |
13c6a9f7 | 513 | *snr = 10 * _snr / 8; |
780dfef3 CP |
514 | |
515 | return 0; | |
516 | } | |
517 | ||
67b60aad CP |
518 | static int zl10353_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) |
519 | { | |
520 | struct zl10353_state *state = fe->demodulator_priv; | |
2267d2d7 | 521 | u32 ubl = 0; |
decee2e8 | 522 | |
2267d2d7 MCC |
523 | ubl = zl10353_read_register(state, RS_UBC_1) << 8 | |
524 | zl10353_read_register(state, RS_UBC_0); | |
67b60aad | 525 | |
2267d2d7 MCC |
526 | state->ucblocks += ubl; |
527 | *ucblocks = state->ucblocks; | |
67b60aad CP |
528 | |
529 | return 0; | |
530 | } | |
531 | ||
780dfef3 CP |
532 | static int zl10353_get_tune_settings(struct dvb_frontend *fe, |
533 | struct dvb_frontend_tune_settings | |
534 | *fe_tune_settings) | |
535 | { | |
536 | fe_tune_settings->min_delay_ms = 1000; | |
537 | fe_tune_settings->step_size = 0; | |
538 | fe_tune_settings->max_drift = 0; | |
539 | ||
540 | return 0; | |
541 | } | |
542 | ||
543 | static int zl10353_init(struct dvb_frontend *fe) | |
544 | { | |
545 | struct zl10353_state *state = fe->demodulator_priv; | |
546 | u8 zl10353_reset_attach[6] = { 0x50, 0x03, 0x64, 0x46, 0x15, 0x0F }; | |
780dfef3 CP |
547 | |
548 | if (debug_regs) | |
549 | zl10353_dump_regs(fe); | |
8fb95784 CP |
550 | if (state->config.parallel_ts) |
551 | zl10353_reset_attach[2] &= ~0x20; | |
378a2793 AP |
552 | if (state->config.clock_ctl_1) |
553 | zl10353_reset_attach[3] = state->config.clock_ctl_1; | |
554 | if (state->config.pll_0) | |
555 | zl10353_reset_attach[4] = state->config.pll_0; | |
780dfef3 CP |
556 | |
557 | /* Do a "hard" reset if not already done */ | |
8fb95784 CP |
558 | if (zl10353_read_register(state, 0x50) != zl10353_reset_attach[1] || |
559 | zl10353_read_register(state, 0x51) != zl10353_reset_attach[2]) { | |
fdf07b02 | 560 | zl10353_write(fe, zl10353_reset_attach, |
780dfef3 CP |
561 | sizeof(zl10353_reset_attach)); |
562 | if (debug_regs) | |
563 | zl10353_dump_regs(fe); | |
564 | } | |
565 | ||
566 | return 0; | |
567 | } | |
568 | ||
0a11bb86 AP |
569 | static int zl10353_i2c_gate_ctrl(struct dvb_frontend* fe, int enable) |
570 | { | |
899a6f67 | 571 | struct zl10353_state *state = fe->demodulator_priv; |
0a11bb86 AP |
572 | u8 val = 0x0a; |
573 | ||
5f77af93 | 574 | if (state->config.disable_i2c_gate_ctrl) { |
899a6f67 DB |
575 | /* No tuner attached to the internal I2C bus */ |
576 | /* If set enable I2C bridge, the main I2C bus stopped hardly */ | |
577 | return 0; | |
578 | } | |
579 | ||
0a11bb86 AP |
580 | if (enable) |
581 | val |= 0x10; | |
582 | ||
583 | return zl10353_single_write(fe, 0x62, val); | |
584 | } | |
585 | ||
780dfef3 CP |
586 | static void zl10353_release(struct dvb_frontend *fe) |
587 | { | |
588 | struct zl10353_state *state = fe->demodulator_priv; | |
780dfef3 CP |
589 | kfree(state); |
590 | } | |
591 | ||
bd336e63 | 592 | static const struct dvb_frontend_ops zl10353_ops; |
780dfef3 CP |
593 | |
594 | struct dvb_frontend *zl10353_attach(const struct zl10353_config *config, | |
595 | struct i2c_adapter *i2c) | |
596 | { | |
597 | struct zl10353_state *state = NULL; | |
378a2793 | 598 | int id; |
780dfef3 CP |
599 | |
600 | /* allocate memory for the internal state */ | |
601 | state = kzalloc(sizeof(struct zl10353_state), GFP_KERNEL); | |
602 | if (state == NULL) | |
603 | goto error; | |
604 | ||
605 | /* setup the state */ | |
606 | state->i2c = i2c; | |
607 | memcpy(&state->config, config, sizeof(struct zl10353_config)); | |
780dfef3 CP |
608 | |
609 | /* check if the demod is there */ | |
378a2793 AP |
610 | id = zl10353_read_register(state, CHIP_ID); |
611 | if ((id != ID_ZL10353) && (id != ID_CE6230) && (id != ID_CE6231)) | |
780dfef3 CP |
612 | goto error; |
613 | ||
614 | /* create dvb_frontend */ | |
dea74869 | 615 | memcpy(&state->frontend.ops, &zl10353_ops, sizeof(struct dvb_frontend_ops)); |
780dfef3 CP |
616 | state->frontend.demodulator_priv = state; |
617 | ||
618 | return &state->frontend; | |
619 | error: | |
620 | kfree(state); | |
621 | return NULL; | |
622 | } | |
623 | ||
bd336e63 | 624 | static const struct dvb_frontend_ops zl10353_ops = { |
4e4d2bcf | 625 | .delsys = { SYS_DVBT }, |
780dfef3 CP |
626 | .info = { |
627 | .name = "Zarlink ZL10353 DVB-T", | |
f1b1eabf MCC |
628 | .frequency_min_hz = 174 * MHz, |
629 | .frequency_max_hz = 862 * MHz, | |
630 | .frequency_stepsize_hz = 166667, | |
780dfef3 CP |
631 | .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | |
632 | FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | | |
633 | FE_CAN_FEC_AUTO | | |
634 | FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | | |
635 | FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | | |
636 | FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | | |
637 | FE_CAN_MUTE_TS | |
638 | }, | |
639 | ||
640 | .release = zl10353_release, | |
641 | ||
642 | .init = zl10353_init, | |
643 | .sleep = zl10353_sleep, | |
0a11bb86 | 644 | .i2c_gate_ctrl = zl10353_i2c_gate_ctrl, |
c10d14d6 | 645 | .write = zl10353_write, |
780dfef3 | 646 | |
4e4d2bcf MCC |
647 | .set_frontend = zl10353_set_parameters, |
648 | .get_frontend = zl10353_get_parameters, | |
780dfef3 CP |
649 | .get_tune_settings = zl10353_get_tune_settings, |
650 | ||
651 | .read_status = zl10353_read_status, | |
67b60aad CP |
652 | .read_ber = zl10353_read_ber, |
653 | .read_signal_strength = zl10353_read_signal_strength, | |
780dfef3 | 654 | .read_snr = zl10353_read_snr, |
67b60aad | 655 | .read_ucblocks = zl10353_read_ucblocks, |
780dfef3 CP |
656 | }; |
657 | ||
f7f57770 AP |
658 | module_param(debug, int, 0644); |
659 | MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); | |
660 | ||
780dfef3 CP |
661 | module_param(debug_regs, int, 0644); |
662 | MODULE_PARM_DESC(debug_regs, "Turn on/off frontend register dumps (default:off)."); | |
663 | ||
664 | MODULE_DESCRIPTION("Zarlink ZL10353 DVB-T demodulator driver"); | |
665 | MODULE_AUTHOR("Chris Pascoe"); | |
666 | MODULE_LICENSE("GPL"); | |
667 | ||
668 | EXPORT_SYMBOL(zl10353_attach); |