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68b3289f MS |
1 | /** |
2 | * Driver for Zarlink zl10036 DVB-S silicon tuner | |
3 | * | |
4 | * Copyright (C) 2006 Tino Reichardt | |
5 | * Copyright (C) 2007-2009 Matthias Schwarzott <zzam@gentoo.de> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License Version 2, as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | * | |
20 | ** | |
21 | * The data sheet for this tuner can be found at: | |
22 | * http://www.mcmilk.de/projects/dvb-card/datasheets/ZL10036.pdf | |
23 | * | |
24 | * This one is working: (at my Avermedia DVB-S Pro) | |
25 | * - zl10036 (40pin, FTA) | |
26 | * | |
27 | * A driver for zl10038 should be very similar. | |
28 | */ | |
29 | ||
30 | #include <linux/module.h> | |
31 | #include <linux/dvb/frontend.h> | |
5a0e3ad6 | 32 | #include <linux/slab.h> |
0389b34e | 33 | #include <linux/types.h> |
68b3289f MS |
34 | |
35 | #include "zl10036.h" | |
36 | ||
37 | static int zl10036_debug; | |
38 | #define dprintk(level, args...) \ | |
39 | do { if (zl10036_debug & level) printk(KERN_DEBUG "zl10036: " args); \ | |
40 | } while (0) | |
41 | ||
42 | #define deb_info(args...) dprintk(0x01, args) | |
43 | #define deb_i2c(args...) dprintk(0x02, args) | |
44 | ||
45 | struct zl10036_state { | |
46 | struct i2c_adapter *i2c; | |
47 | const struct zl10036_config *config; | |
48 | u32 frequency; | |
49 | u8 br, bf; | |
50 | }; | |
51 | ||
52 | ||
53 | /* This driver assumes the tuner is driven by a 10.111MHz Cristal */ | |
54 | #define _XTAL 10111 | |
55 | ||
56 | /* Some of the possible dividers: | |
57 | * 64, (write 0x05 to reg), freq step size 158kHz | |
58 | * 10, (write 0x0a to reg), freq step size 1.011kHz (used here) | |
59 | * 5, (write 0x09 to reg), freq step size 2.022kHz | |
60 | */ | |
61 | ||
62 | #define _RDIV 10 | |
63 | #define _RDIV_REG 0x0a | |
64 | #define _FR (_XTAL/_RDIV) | |
65 | ||
66 | #define STATUS_POR 0x80 /* Power on Reset */ | |
67 | #define STATUS_FL 0x40 /* Frequency & Phase Lock */ | |
68 | ||
69 | /* read/write for zl10036 and zl10038 */ | |
70 | ||
71 | static int zl10036_read_status_reg(struct zl10036_state *state) | |
72 | { | |
73 | u8 status; | |
74 | struct i2c_msg msg[1] = { | |
75 | { .addr = state->config->tuner_address, .flags = I2C_M_RD, | |
76 | .buf = &status, .len = sizeof(status) }, | |
77 | }; | |
78 | ||
79 | if (i2c_transfer(state->i2c, msg, 1) != 1) { | |
80 | printk(KERN_ERR "%s: i2c read failed at addr=%02x\n", | |
81 | __func__, state->config->tuner_address); | |
82 | return -EIO; | |
83 | } | |
84 | ||
85 | deb_i2c("R(status): %02x [FL=%d]\n", status, | |
86 | (status & STATUS_FL) ? 1 : 0); | |
87 | if (status & STATUS_POR) | |
4bd69e7b MCC |
88 | deb_info("%s: Power-On-Reset bit enabled - need to initialize the tuner\n", |
89 | __func__); | |
68b3289f MS |
90 | |
91 | return status; | |
92 | } | |
93 | ||
94 | static int zl10036_write(struct zl10036_state *state, u8 buf[], u8 count) | |
95 | { | |
96 | struct i2c_msg msg[1] = { | |
97 | { .addr = state->config->tuner_address, .flags = 0, | |
98 | .buf = buf, .len = count }, | |
99 | }; | |
100 | u8 reg = 0; | |
101 | int ret; | |
102 | ||
103 | if (zl10036_debug & 0x02) { | |
104 | /* every 8bit-value satisifes this! | |
105 | * so only check for debug log */ | |
106 | if ((buf[0] & 0x80) == 0x00) | |
107 | reg = 2; | |
108 | else if ((buf[0] & 0xc0) == 0x80) | |
109 | reg = 4; | |
110 | else if ((buf[0] & 0xf0) == 0xc0) | |
111 | reg = 6; | |
112 | else if ((buf[0] & 0xf0) == 0xd0) | |
113 | reg = 8; | |
114 | else if ((buf[0] & 0xf0) == 0xe0) | |
115 | reg = 10; | |
116 | else if ((buf[0] & 0xf0) == 0xf0) | |
117 | reg = 12; | |
118 | ||
119 | deb_i2c("W(%d):", reg); | |
120 | { | |
121 | int i; | |
122 | for (i = 0; i < count; i++) | |
123 | printk(KERN_CONT " %02x", buf[i]); | |
124 | printk(KERN_CONT "\n"); | |
125 | } | |
126 | } | |
127 | ||
128 | ret = i2c_transfer(state->i2c, msg, 1); | |
129 | if (ret != 1) { | |
130 | printk(KERN_ERR "%s: i2c error, ret=%d\n", __func__, ret); | |
131 | return -EIO; | |
132 | } | |
133 | ||
134 | return 0; | |
135 | } | |
136 | ||
68b3289f MS |
137 | static int zl10036_sleep(struct dvb_frontend *fe) |
138 | { | |
139 | struct zl10036_state *state = fe->tuner_priv; | |
140 | u8 buf[] = { 0xf0, 0x80 }; /* regs 12/13 */ | |
141 | int ret; | |
142 | ||
143 | deb_info("%s\n", __func__); | |
144 | ||
145 | if (fe->ops.i2c_gate_ctrl) | |
146 | fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */ | |
147 | ||
148 | ret = zl10036_write(state, buf, sizeof(buf)); | |
149 | ||
150 | if (fe->ops.i2c_gate_ctrl) | |
151 | fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */ | |
152 | ||
153 | return ret; | |
154 | } | |
155 | ||
156 | /** | |
157 | * register map of the ZL10036/ZL10038 | |
158 | * | |
159 | * reg[default] content | |
160 | * 2[0x00]: 0 | N14 | N13 | N12 | N11 | N10 | N9 | N8 | |
161 | * 3[0x00]: N7 | N6 | N5 | N4 | N3 | N2 | N1 | N0 | |
162 | * 4[0x80]: 1 | 0 | RFG | BA1 | BA0 | BG1 | BG0 | LEN | |
163 | * 5[0x00]: P0 | C1 | C0 | R4 | R3 | R2 | R1 | R0 | |
164 | * 6[0xc0]: 1 | 1 | 0 | 0 | RSD | 0 | 0 | 0 | |
165 | * 7[0x20]: P1 | BF6 | BF5 | BF4 | BF3 | BF2 | BF1 | 0 | |
166 | * 8[0xdb]: 1 | 1 | 0 | 1 | 0 | CC | 1 | 1 | |
167 | * 9[0x30]: VSD | V2 | V1 | V0 | S3 | S2 | S1 | S0 | |
168 | * 10[0xe1]: 1 | 1 | 1 | 0 | 0 | LS2 | LS1 | LS0 | |
169 | * 11[0xf5]: WS | WH2 | WH1 | WH0 | WL2 | WL1 | WL0 | WRE | |
170 | * 12[0xf0]: 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | |
171 | * 13[0x28]: PD | BR4 | BR3 | BR2 | BR1 | BR0 | CLR | TL | |
172 | */ | |
173 | ||
174 | static int zl10036_set_frequency(struct zl10036_state *state, u32 frequency) | |
175 | { | |
176 | u8 buf[2]; | |
177 | u32 div, foffset; | |
178 | ||
179 | div = (frequency + _FR/2) / _FR; | |
180 | state->frequency = div * _FR; | |
181 | ||
182 | foffset = frequency - state->frequency; | |
183 | ||
184 | buf[0] = (div >> 8) & 0x7f; | |
185 | buf[1] = (div >> 0) & 0xff; | |
186 | ||
187 | deb_info("%s: ftodo=%u fpriv=%u ferr=%d div=%u\n", __func__, | |
188 | frequency, state->frequency, foffset, div); | |
189 | ||
190 | return zl10036_write(state, buf, sizeof(buf)); | |
191 | } | |
192 | ||
193 | static int zl10036_set_bandwidth(struct zl10036_state *state, u32 fbw) | |
194 | { | |
195 | /* fbw is measured in kHz */ | |
196 | u8 br, bf; | |
197 | int ret; | |
198 | u8 buf_bf[] = { | |
199 | 0xc0, 0x00, /* 6/7: rsd=0 bf=0 */ | |
200 | }; | |
201 | u8 buf_br[] = { | |
202 | 0xf0, 0x00, /* 12/13: br=0xa clr=0 tl=0*/ | |
203 | }; | |
204 | u8 zl10036_rsd_off[] = { 0xc8 }; /* set RSD=1 */ | |
205 | ||
206 | /* ensure correct values */ | |
207 | if (fbw > 35000) | |
208 | fbw = 35000; | |
209 | if (fbw < 8000) | |
210 | fbw = 8000; | |
211 | ||
212 | #define _BR_MAXIMUM (_XTAL/575) /* _XTAL / 575kHz = 17 */ | |
213 | ||
214 | /* <= 28,82 MHz */ | |
215 | if (fbw <= 28820) { | |
216 | br = _BR_MAXIMUM; | |
217 | } else { | |
218 | /** | |
219 | * f(bw)=34,6MHz f(xtal)=10.111MHz | |
220 | * br = (10111/34600) * 63 * 1/K = 14; | |
221 | */ | |
222 | br = ((_XTAL * 21 * 1000) / (fbw * 419)); | |
223 | } | |
224 | ||
225 | /* ensure correct values */ | |
226 | if (br < 4) | |
227 | br = 4; | |
228 | if (br > _BR_MAXIMUM) | |
229 | br = _BR_MAXIMUM; | |
230 | ||
231 | /* | |
232 | * k = 1.257 | |
233 | * bf = fbw/_XTAL * br * k - 1 */ | |
234 | ||
235 | bf = (fbw * br * 1257) / (_XTAL * 1000) - 1; | |
236 | ||
237 | /* ensure correct values */ | |
238 | if (bf > 62) | |
239 | bf = 62; | |
240 | ||
241 | buf_bf[1] = (bf << 1) & 0x7e; | |
242 | buf_br[1] = (br << 2) & 0x7c; | |
243 | deb_info("%s: BW=%d br=%u bf=%u\n", __func__, fbw, br, bf); | |
244 | ||
245 | if (br != state->br) { | |
246 | ret = zl10036_write(state, buf_br, sizeof(buf_br)); | |
247 | if (ret < 0) | |
248 | return ret; | |
249 | } | |
250 | ||
251 | if (bf != state->bf) { | |
252 | ret = zl10036_write(state, buf_bf, sizeof(buf_bf)); | |
253 | if (ret < 0) | |
254 | return ret; | |
255 | ||
256 | /* time = br/(32* fxtal) */ | |
257 | /* minimal sleep time to be calculated | |
258 | * maximum br is 63 -> max time = 2 /10 MHz = 2e-7 */ | |
259 | msleep(1); | |
260 | ||
261 | ret = zl10036_write(state, zl10036_rsd_off, | |
262 | sizeof(zl10036_rsd_off)); | |
263 | if (ret < 0) | |
264 | return ret; | |
265 | } | |
266 | ||
267 | state->br = br; | |
268 | state->bf = bf; | |
269 | ||
270 | return 0; | |
271 | } | |
272 | ||
273 | static int zl10036_set_gain_params(struct zl10036_state *state, | |
274 | int c) | |
275 | { | |
276 | u8 buf[2]; | |
277 | u8 rfg, ba, bg; | |
278 | ||
279 | /* default values */ | |
280 | rfg = 0; /* enable when using an lna */ | |
281 | ba = 1; | |
282 | bg = 1; | |
283 | ||
284 | /* reg 4 */ | |
285 | buf[0] = 0x80 | ((rfg << 5) & 0x20) | |
286 | | ((ba << 3) & 0x18) | ((bg << 1) & 0x06); | |
287 | ||
288 | if (!state->config->rf_loop_enable) | |
289 | buf[0] |= 0x01; | |
290 | ||
291 | /* P0=0 */ | |
292 | buf[1] = _RDIV_REG | ((c << 5) & 0x60); | |
293 | ||
294 | deb_info("%s: c=%u rfg=%u ba=%u bg=%u\n", __func__, c, rfg, ba, bg); | |
295 | return zl10036_write(state, buf, sizeof(buf)); | |
296 | } | |
297 | ||
14d24d14 | 298 | static int zl10036_set_params(struct dvb_frontend *fe) |
68b3289f | 299 | { |
f40d0f01 | 300 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
68b3289f MS |
301 | struct zl10036_state *state = fe->tuner_priv; |
302 | int ret = 0; | |
f40d0f01 | 303 | u32 frequency = p->frequency; |
68b3289f MS |
304 | u32 fbw; |
305 | int i; | |
306 | u8 c; | |
307 | ||
308 | /* ensure correct values | |
309 | * maybe redundant as core already checks this */ | |
310 | if ((frequency < fe->ops.info.frequency_min) | |
311 | || (frequency > fe->ops.info.frequency_max)) | |
312 | return -EINVAL; | |
313 | ||
314 | /** | |
315 | * alpha = 1.35 for dvb-s | |
316 | * fBW = (alpha*symbolrate)/(2*0.8) | |
317 | * 1.35 / (2*0.8) = 27 / 32 | |
318 | */ | |
f40d0f01 | 319 | fbw = (27 * p->symbol_rate) / 32; |
68b3289f MS |
320 | |
321 | /* scale to kHz */ | |
322 | fbw /= 1000; | |
323 | ||
324 | /* Add safe margin of 3MHz */ | |
325 | fbw += 3000; | |
326 | ||
327 | /* setting the charge pump - guessed values */ | |
328 | if (frequency < 950000) | |
329 | return -EINVAL; | |
330 | else if (frequency < 1250000) | |
331 | c = 0; | |
332 | else if (frequency < 1750000) | |
333 | c = 1; | |
334 | else if (frequency < 2175000) | |
335 | c = 2; | |
336 | else | |
337 | return -EINVAL; | |
338 | ||
339 | if (fe->ops.i2c_gate_ctrl) | |
340 | fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */ | |
341 | ||
342 | ret = zl10036_set_gain_params(state, c); | |
343 | if (ret < 0) | |
344 | goto error; | |
345 | ||
f40d0f01 | 346 | ret = zl10036_set_frequency(state, p->frequency); |
68b3289f MS |
347 | if (ret < 0) |
348 | goto error; | |
349 | ||
350 | ret = zl10036_set_bandwidth(state, fbw); | |
351 | if (ret < 0) | |
352 | goto error; | |
353 | ||
354 | /* wait for tuner lock - no idea if this is really needed */ | |
355 | for (i = 0; i < 20; i++) { | |
356 | ret = zl10036_read_status_reg(state); | |
357 | if (ret < 0) | |
358 | goto error; | |
359 | ||
360 | /* check Frequency & Phase Lock Bit */ | |
361 | if (ret & STATUS_FL) | |
362 | break; | |
363 | ||
364 | msleep(10); | |
365 | } | |
366 | ||
367 | error: | |
368 | if (fe->ops.i2c_gate_ctrl) | |
369 | fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */ | |
370 | ||
371 | return ret; | |
372 | } | |
373 | ||
374 | static int zl10036_get_frequency(struct dvb_frontend *fe, u32 *frequency) | |
375 | { | |
376 | struct zl10036_state *state = fe->tuner_priv; | |
377 | ||
378 | *frequency = state->frequency; | |
379 | ||
380 | return 0; | |
381 | } | |
382 | ||
383 | static int zl10036_init_regs(struct zl10036_state *state) | |
384 | { | |
385 | int ret; | |
386 | int i; | |
387 | ||
388 | /* could also be one block from reg 2 to 13 and additional 10/11 */ | |
389 | u8 zl10036_init_tab[][2] = { | |
390 | { 0x04, 0x00 }, /* 2/3: div=0x400 - arbitrary value */ | |
391 | { 0x8b, _RDIV_REG }, /* 4/5: rfg=0 ba=1 bg=1 len=? */ | |
392 | /* p0=0 c=0 r=_RDIV_REG */ | |
393 | { 0xc0, 0x20 }, /* 6/7: rsd=0 bf=0x10 */ | |
394 | { 0xd3, 0x40 }, /* 8/9: from datasheet */ | |
395 | { 0xe3, 0x5b }, /* 10/11: lock window level */ | |
396 | { 0xf0, 0x28 }, /* 12/13: br=0xa clr=0 tl=0*/ | |
397 | { 0xe3, 0xf9 }, /* 10/11: unlock window level */ | |
398 | }; | |
399 | ||
400 | /* invalid values to trigger writing */ | |
401 | state->br = 0xff; | |
402 | state->bf = 0xff; | |
403 | ||
404 | if (!state->config->rf_loop_enable) | |
21163565 | 405 | zl10036_init_tab[1][0] |= 0x01; |
68b3289f MS |
406 | |
407 | deb_info("%s\n", __func__); | |
408 | ||
409 | for (i = 0; i < ARRAY_SIZE(zl10036_init_tab); i++) { | |
410 | ret = zl10036_write(state, zl10036_init_tab[i], 2); | |
411 | if (ret < 0) | |
412 | return ret; | |
413 | } | |
414 | ||
415 | return 0; | |
416 | } | |
417 | ||
418 | static int zl10036_init(struct dvb_frontend *fe) | |
419 | { | |
420 | struct zl10036_state *state = fe->tuner_priv; | |
421 | int ret = 0; | |
422 | ||
423 | if (fe->ops.i2c_gate_ctrl) | |
424 | fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */ | |
425 | ||
426 | ret = zl10036_read_status_reg(state); | |
427 | if (ret < 0) | |
428 | return ret; | |
429 | ||
430 | /* Only init if Power-on-Reset bit is set? */ | |
431 | ret = zl10036_init_regs(state); | |
432 | ||
433 | if (fe->ops.i2c_gate_ctrl) | |
434 | fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */ | |
435 | ||
436 | return ret; | |
437 | } | |
438 | ||
14c4bf3c | 439 | static const struct dvb_tuner_ops zl10036_tuner_ops = { |
68b3289f MS |
440 | .info = { |
441 | .name = "Zarlink ZL10036", | |
442 | .frequency_min = 950000, | |
443 | .frequency_max = 2175000 | |
444 | }, | |
445 | .init = zl10036_init, | |
22a613e8 | 446 | .release = dvb_tuner_simple_release, |
68b3289f MS |
447 | .sleep = zl10036_sleep, |
448 | .set_params = zl10036_set_params, | |
449 | .get_frequency = zl10036_get_frequency, | |
450 | }; | |
451 | ||
452 | struct dvb_frontend *zl10036_attach(struct dvb_frontend *fe, | |
453 | const struct zl10036_config *config, | |
454 | struct i2c_adapter *i2c) | |
455 | { | |
7e270941 | 456 | struct zl10036_state *state; |
68b3289f MS |
457 | int ret; |
458 | ||
7e270941 | 459 | if (!config) { |
68b3289f | 460 | printk(KERN_ERR "%s: no config specified", __func__); |
7e270941 | 461 | return NULL; |
68b3289f MS |
462 | } |
463 | ||
464 | state = kzalloc(sizeof(struct zl10036_state), GFP_KERNEL); | |
7e270941 | 465 | if (!state) |
68b3289f MS |
466 | return NULL; |
467 | ||
468 | state->config = config; | |
469 | state->i2c = i2c; | |
470 | ||
471 | if (fe->ops.i2c_gate_ctrl) | |
472 | fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */ | |
473 | ||
474 | ret = zl10036_read_status_reg(state); | |
475 | if (ret < 0) { | |
476 | printk(KERN_ERR "%s: No zl10036 found\n", __func__); | |
477 | goto error; | |
478 | } | |
479 | ||
480 | ret = zl10036_init_regs(state); | |
481 | if (ret < 0) { | |
482 | printk(KERN_ERR "%s: tuner initialization failed\n", | |
483 | __func__); | |
484 | goto error; | |
485 | } | |
486 | ||
487 | if (fe->ops.i2c_gate_ctrl) | |
488 | fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */ | |
489 | ||
490 | fe->tuner_priv = state; | |
491 | ||
492 | memcpy(&fe->ops.tuner_ops, &zl10036_tuner_ops, | |
493 | sizeof(struct dvb_tuner_ops)); | |
494 | printk(KERN_INFO "%s: tuner initialization (%s addr=0x%02x) ok\n", | |
495 | __func__, fe->ops.tuner_ops.info.name, config->tuner_address); | |
496 | ||
497 | return fe; | |
498 | ||
499 | error: | |
7e270941 | 500 | kfree(state); |
68b3289f MS |
501 | return NULL; |
502 | } | |
503 | EXPORT_SYMBOL(zl10036_attach); | |
504 | ||
505 | module_param_named(debug, zl10036_debug, int, 0644); | |
506 | MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); | |
507 | MODULE_DESCRIPTION("DVB ZL10036 driver"); | |
508 | MODULE_AUTHOR("Tino Reichardt"); | |
509 | MODULE_AUTHOR("Matthias Schwarzott"); | |
510 | MODULE_LICENSE("GPL"); |