[linux-2.6-block.git] / drivers / media / dvb-frontends / ves1x93.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
    Driver for VES1893 and VES1993 QPSK Demodulators

    Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
    Copyright (C) 2001 Ronny Strutz <3des@elitedvb.de>
    Copyright (C) 2002 Dennis Noermann <dennis.noermann@noernet.de>
    Copyright (C) 2002-2003 Andreas Oberritter <obi@linuxtv.org>


*/

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/delay.h>

#include <media/dvb_frontend.h>
#include "ves1x93.h"


struct ves1x93_state {
	struct i2c_adapter* i2c;
	/* configuration settings */
	const struct ves1x93_config* config;
	struct dvb_frontend frontend;

	/* previous uncorrected block counter */
	enum fe_spectral_inversion inversion;
	u8 *init_1x93_tab;
	u8 *init_1x93_wtab;
	u8 tab_size;
	u8 demod_type;
	u32 frequency;
};

static int debug;
#define dprintk	if (debug) printk

#define DEMOD_VES1893		0
#define DEMOD_VES1993		1

static u8 init_1893_tab [] = {
	0x01, 0xa4, 0x35, 0x80, 0x2a, 0x0b, 0x55, 0xc4,
	0x09, 0x69, 0x00, 0x86, 0x4c, 0x28, 0x7f, 0x00,
	0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x80, 0x00, 0x21, 0xb0, 0x14, 0x00, 0xdc, 0x00,
	0x81, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x55, 0x00, 0x00, 0x7f, 0x00
};

static u8 init_1993_tab [] = {
	0x00, 0x9c, 0x35, 0x80, 0x6a, 0x09, 0x72, 0x8c,
	0x09, 0x6b, 0x00, 0x00, 0x4c, 0x08, 0x00, 0x00,
	0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x80, 0x40, 0x21, 0xb0, 0x00, 0x00, 0x00, 0x10,
	0x81, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x55, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03,
	0x00, 0x00, 0x0e, 0x80, 0x00
};

static u8 init_1893_wtab[] =
{
	1,1,1,1,1,1,1,1, 1,1,0,0,1,1,0,0,
	0,1,0,0,0,0,0,0, 1,0,1,1,0,0,0,1,
	1,1,1,0,0,0,0,0, 0,0,1,1,0,0,0,0,
	1,1,1,0,1,1
};

static u8 init_1993_wtab[] =
{
	1,1,1,1,1,1,1,1, 1,1,0,0,1,1,0,0,
	0,1,0,0,0,0,0,0, 1,1,1,1,0,0,0,1,
	1,1,1,0,0,0,0,0, 0,0,1,1,0,0,0,0,
	1,1,1,0,1,1,1,1, 1,1,1,1,1
};

static int ves1x93_writereg (struct ves1x93_state* state, u8 reg, u8 data)
{
	u8 buf [] = { 0x00, reg, data };
	struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 3 };
	int err;

	if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
		dprintk ("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __func__, err, reg, data);
		return -EREMOTEIO;
	}

	return 0;
}

static u8 ves1x93_readreg (struct ves1x93_state* state, u8 reg)
{
	int ret;
	u8 b0 [] = { 0x00, reg };
	u8 b1 [] = { 0 };
	struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 2 },
			   { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };

	ret = i2c_transfer (state->i2c, msg, 2);

	if (ret != 2) return ret;

	return b1[0];
}

static int ves1x93_clr_bit (struct ves1x93_state* state)
{
	msleep(10);
	ves1x93_writereg (state, 0, state->init_1x93_tab[0] & 0xfe);
	ves1x93_writereg (state, 0, state->init_1x93_tab[0]);
	msleep(50);
	return 0;
}

static int ves1x93_set_inversion(struct ves1x93_state *state,
				 enum fe_spectral_inversion inversion)
{
	u8 val;

	/*
	 * inversion on/off are interchanged because i and q seem to
	 * be swapped on the hardware
	 */

	switch (inversion) {
	case INVERSION_OFF:
		val = 0xc0;
		break;
	case INVERSION_ON:
		val = 0x80;
		break;
	case INVERSION_AUTO:
		val = 0x00;
		break;
	default:
		return -EINVAL;
	}

	return ves1x93_writereg (state, 0x0c, (state->init_1x93_tab[0x0c] & 0x3f) | val);
}

static int ves1x93_set_fec(struct ves1x93_state *state, enum fe_code_rate fec)
{
	if (fec == FEC_AUTO)
		return ves1x93_writereg (state, 0x0d, 0x08);
	else if (fec < FEC_1_2 || fec > FEC_8_9)
		return -EINVAL;
	else
		return ves1x93_writereg (state, 0x0d, fec - FEC_1_2);
}

static enum fe_code_rate ves1x93_get_fec(struct ves1x93_state *state)
{
	return FEC_1_2 + ((ves1x93_readreg (state, 0x0d) >> 4) & 0x7);
}

static int ves1x93_set_symbolrate (struct ves1x93_state* state, u32 srate)
{
	u32 BDR;
	u32 ratio;
	u8  ADCONF, FCONF, FNR, AGCR;
	u32 BDRI;
	u32 tmp;
	u32 FIN;

	dprintk("%s: srate == %d\n", __func__, (unsigned int) srate);

	if (srate > state->config->xin/2)
		srate = state->config->xin/2;

	if (srate < 500000)
		srate = 500000;

#define MUL (1UL<<26)

	FIN = (state->config->xin + 6000) >> 4;

	tmp = srate << 6;
	ratio = tmp / FIN;

	tmp = (tmp % FIN) << 8;
	ratio = (ratio << 8) + tmp / FIN;

	tmp = (tmp % FIN) << 8;
	ratio = (ratio << 8) + tmp / FIN;

	FNR = 0xff;

	if (ratio < MUL/3)	     FNR = 0;
	if (ratio < (MUL*11)/50)     FNR = 1;
	if (ratio < MUL/6)	     FNR = 2;
	if (ratio < MUL/9)	     FNR = 3;
	if (ratio < MUL/12)	     FNR = 4;
	if (ratio < (MUL*11)/200)    FNR = 5;
	if (ratio < MUL/24)	     FNR = 6;
	if (ratio < (MUL*27)/1000)   FNR = 7;
	if (ratio < MUL/48)	     FNR = 8;
	if (ratio < (MUL*137)/10000) FNR = 9;

	if (FNR == 0xff) {
		ADCONF = 0x89;
		FCONF  = 0x80;
		FNR	= 0;
	} else {
		ADCONF = 0x81;
		FCONF  = 0x88 | (FNR >> 1) | ((FNR & 0x01) << 5);
		/*FCONF	 = 0x80 | ((FNR & 0x01) << 5) | (((FNR > 1) & 0x03) << 3) | ((FNR >> 1) & 0x07);*/
	}

	BDR = (( (ratio << (FNR >> 1)) >> 4) + 1) >> 1;
	BDRI = ( ((FIN << 8) / ((srate << (FNR >> 1)) >> 2)) + 1) >> 1;

	dprintk("FNR= %d\n", FNR);
	dprintk("ratio= %08x\n", (unsigned int) ratio);
	dprintk("BDR= %08x\n", (unsigned int) BDR);
	dprintk("BDRI= %02x\n", (unsigned int) BDRI);

	if (BDRI > 0xff)
		BDRI = 0xff;

	ves1x93_writereg (state, 0x06, 0xff & BDR);
	ves1x93_writereg (state, 0x07, 0xff & (BDR >> 8));
	ves1x93_writereg (state, 0x08, 0x0f & (BDR >> 16));

	ves1x93_writereg (state, 0x09, BDRI);
	ves1x93_writereg (state, 0x20, ADCONF);
	ves1x93_writereg (state, 0x21, FCONF);

	AGCR = state->init_1x93_tab[0x05];
	if (state->config->invert_pwm)
		AGCR |= 0x20;

	if (srate < 6000000)
		AGCR |= 0x80;
	else
		AGCR &= ~0x80;

	ves1x93_writereg (state, 0x05, AGCR);

	/* ves1993 hates this, will lose lock */
	if (state->demod_type != DEMOD_VES1993)
		ves1x93_clr_bit (state);

	return 0;
}

static int ves1x93_init (struct dvb_frontend* fe)
{
	struct ves1x93_state* state = fe->demodulator_priv;
	int i;
	int val;

	dprintk("%s: init chip\n", __func__);

	for (i = 0; i < state->tab_size; i++) {
		if (state->init_1x93_wtab[i]) {
			val = state->init_1x93_tab[i];

			if (state->config->invert_pwm && (i == 0x05)) val |= 0x20; /* invert PWM */
			ves1x93_writereg (state, i, val);
		}
	}

	return 0;
}

static int ves1x93_set_voltage(struct dvb_frontend *fe,
			       enum fe_sec_voltage voltage)
{
	struct ves1x93_state* state = fe->demodulator_priv;

	switch (voltage) {
	case SEC_VOLTAGE_13:
		return ves1x93_writereg (state, 0x1f, 0x20);
	case SEC_VOLTAGE_18:
		return ves1x93_writereg (state, 0x1f, 0x30);
	case SEC_VOLTAGE_OFF:
		return ves1x93_writereg (state, 0x1f, 0x00);
	default:
		return -EINVAL;
	}
}

static int ves1x93_read_status(struct dvb_frontend *fe,
			       enum fe_status *status)
{
	struct ves1x93_state* state = fe->demodulator_priv;

	u8 sync = ves1x93_readreg (state, 0x0e);

	/*
	 * The ves1893 sometimes returns sync values that make no sense,
	 * because, e.g., the SIGNAL bit is 0, while some of the higher
	 * bits are 1 (and how can there be a CARRIER w/o a SIGNAL?).
	 * Tests showed that the VITERBI and SYNC bits are returned
	 * reliably, while the SIGNAL and CARRIER bits ar sometimes wrong.
	 * If such a case occurs, we read the value again, until we get a
	 * valid value.
	 */
	int maxtry = 10; /* just for safety - let's not get stuck here */
	while ((sync & 0x03) != 0x03 && (sync & 0x0c) && maxtry--) {
		msleep(10);
		sync = ves1x93_readreg (state, 0x0e);
	}

	*status = 0;

	if (sync & 1)
		*status |= FE_HAS_SIGNAL;

	if (sync & 2)
		*status |= FE_HAS_CARRIER;

	if (sync & 4)
		*status |= FE_HAS_VITERBI;

	if (sync & 8)
		*status |= FE_HAS_SYNC;

	if ((sync & 0x1f) == 0x1f)
		*status |= FE_HAS_LOCK;

	return 0;
}

static int ves1x93_read_ber(struct dvb_frontend* fe, u32* ber)
{
	struct ves1x93_state* state = fe->demodulator_priv;

	*ber = ves1x93_readreg (state, 0x15);
	*ber |= (ves1x93_readreg (state, 0x16) << 8);
	*ber |= ((ves1x93_readreg (state, 0x17) & 0x0F) << 16);
	*ber *= 10;

	return 0;
}

static int ves1x93_read_signal_strength(struct dvb_frontend* fe, u16* strength)
{
	struct ves1x93_state* state = fe->demodulator_priv;

	u8 signal = ~ves1x93_readreg (state, 0x0b);
	*strength = (signal << 8) | signal;

	return 0;
}

static int ves1x93_read_snr(struct dvb_frontend* fe, u16* snr)
{
	struct ves1x93_state* state = fe->demodulator_priv;

	u8 _snr = ~ves1x93_readreg (state, 0x1c);
	*snr = (_snr << 8) | _snr;

	return 0;
}

static int ves1x93_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
{
	struct ves1x93_state* state = fe->demodulator_priv;

	*ucblocks = ves1x93_readreg (state, 0x18) & 0x7f;

	if (*ucblocks == 0x7f)
		*ucblocks = 0xffffffff;   /* counter overflow... */

	ves1x93_writereg (state, 0x18, 0x00);  /* reset the counter */
	ves1x93_writereg (state, 0x18, 0x80);  /* dto. */

	return 0;
}

static int ves1x93_set_frontend(struct dvb_frontend *fe)
{
	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
	struct ves1x93_state* state = fe->demodulator_priv;

	if (fe->ops.tuner_ops.set_params) {
		fe->ops.tuner_ops.set_params(fe);
		if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
	}
	ves1x93_set_inversion (state, p->inversion);
	ves1x93_set_fec(state, p->fec_inner);
	ves1x93_set_symbolrate(state, p->symbol_rate);
	state->inversion = p->inversion;
	state->frequency = p->frequency;

	return 0;
}

static int ves1x93_get_frontend(struct dvb_frontend *fe,
				struct dtv_frontend_properties *p)
{
	struct ves1x93_state* state = fe->demodulator_priv;
	int afc;

	afc = ((int)((char)(ves1x93_readreg (state, 0x0a) << 1)))/2;
	afc = (afc * (int)(p->symbol_rate/1000/8))/16;

	p->frequency = state->frequency - afc;

	/*
	 * inversion indicator is only valid
	 * if auto inversion was used
	 */
	if (state->inversion == INVERSION_AUTO)
		p->inversion = (ves1x93_readreg (state, 0x0f) & 2) ?
				INVERSION_OFF : INVERSION_ON;
	p->fec_inner = ves1x93_get_fec(state);
	/*  XXX FIXME: timing offset !! */

	return 0;
}

static int ves1x93_sleep(struct dvb_frontend* fe)
{
	struct ves1x93_state* state = fe->demodulator_priv;

	return ves1x93_writereg (state, 0x00, 0x08);
}

static void ves1x93_release(struct dvb_frontend* fe)
{
	struct ves1x93_state* state = fe->demodulator_priv;
	kfree(state);
}

static int ves1x93_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
{
	struct ves1x93_state* state = fe->demodulator_priv;

	if (enable) {
		return ves1x93_writereg(state, 0x00, 0x11);
	} else {
		return ves1x93_writereg(state, 0x00, 0x01);
	}
}

static const struct dvb_frontend_ops ves1x93_ops;

struct dvb_frontend* ves1x93_attach(const struct ves1x93_config* config,
				    struct i2c_adapter* i2c)
{
	struct ves1x93_state* state = NULL;
	u8 identity;

	/* allocate memory for the internal state */
	state = kzalloc(sizeof(struct ves1x93_state), GFP_KERNEL);
	if (state == NULL) goto error;

	/* setup the state */
	state->config = config;
	state->i2c = i2c;
	state->inversion = INVERSION_OFF;

	/* check if the demod is there + identify it */
	identity = ves1x93_readreg(state, 0x1e);
	switch (identity) {
	case 0xdc: /* VES1893A rev1 */
		printk("ves1x93: Detected ves1893a rev1\n");
		state->demod_type = DEMOD_VES1893;
		state->init_1x93_tab = init_1893_tab;
		state->init_1x93_wtab = init_1893_wtab;
		state->tab_size = sizeof(init_1893_tab);
		break;

	case 0xdd: /* VES1893A rev2 */
		printk("ves1x93: Detected ves1893a rev2\n");
		state->demod_type = DEMOD_VES1893;
		state->init_1x93_tab = init_1893_tab;
		state->init_1x93_wtab = init_1893_wtab;
		state->tab_size = sizeof(init_1893_tab);
		break;

	case 0xde: /* VES1993 */
		printk("ves1x93: Detected ves1993\n");
		state->demod_type = DEMOD_VES1993;
		state->init_1x93_tab = init_1993_tab;
		state->init_1x93_wtab = init_1993_wtab;
		state->tab_size = sizeof(init_1993_tab);
		break;

	default:
		goto error;
	}

	/* create dvb_frontend */
	memcpy(&state->frontend.ops, &ves1x93_ops, sizeof(struct dvb_frontend_ops));
	state->frontend.demodulator_priv = state;
	return &state->frontend;

error:
	kfree(state);
	return NULL;
}

static const struct dvb_frontend_ops ves1x93_ops = {
	.delsys = { SYS_DVBS },
	.info = {
		.name			= "VLSI VES1x93 DVB-S",
		.frequency_min_hz	=   950 * MHz,
		.frequency_max_hz	=  2150 * MHz,
		.frequency_stepsize_hz	=   125 * kHz,
		.frequency_tolerance_hz	= 29500 * kHz,
		.symbol_rate_min	= 1000000,
		.symbol_rate_max	= 45000000,
	/*	.symbol_rate_tolerance	=	???,*/
		.caps = FE_CAN_INVERSION_AUTO |
			FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
			FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
			FE_CAN_QPSK
	},

	.release = ves1x93_release,

	.init = ves1x93_init,
	.sleep = ves1x93_sleep,
	.i2c_gate_ctrl = ves1x93_i2c_gate_ctrl,

	.set_frontend = ves1x93_set_frontend,
	.get_frontend = ves1x93_get_frontend,

	.read_status = ves1x93_read_status,
	.read_ber = ves1x93_read_ber,
	.read_signal_strength = ves1x93_read_signal_strength,
	.read_snr = ves1x93_read_snr,
	.read_ucblocks = ves1x93_read_ucblocks,

	.set_voltage = ves1x93_set_voltage,
};

module_param(debug, int, 0644);

MODULE_DESCRIPTION("VLSI VES1x93 DVB-S Demodulator driver");
MODULE_AUTHOR("Ralph Metzler");
MODULE_LICENSE("GPL");

EXPORT_SYMBOL(ves1x93_attach);
Commit	Line	Data
74ba9207	1	// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4 LT	2	/*
	3	Driver for VES1893 and VES1993 QPSK Demodulators
	4
	5	Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
	6	Copyright (C) 2001 Ronny Strutz <3des@elitedvb.de>
	7	Copyright (C) 2002 Dennis Noermann <dennis.noermann@noernet.de>
	8	Copyright (C) 2002-2003 Andreas Oberritter <obi@linuxtv.org>
	9
1da177e4 LT	10
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/module.h>
	15	#include <linux/init.h>
	16	#include <linux/string.h>
	17	#include <linux/slab.h>
	18	#include <linux/delay.h>
	19
fada1935	20	#include <media/dvb_frontend.h>
1da177e4 LT	21	#include "ves1x93.h"
	22
	23
	24	struct ves1x93_state {
	25	struct i2c_adapter* i2c;
1da177e4 LT	26	/* configuration settings */
	27	const struct ves1x93_config* config;
	28	struct dvb_frontend frontend;
	29
	30	/* previous uncorrected block counter */
0df289a2	31	enum fe_spectral_inversion inversion;
1da177e4 LT	32	u8 *init_1x93_tab;
	33	u8 *init_1x93_wtab;
	34	u8 tab_size;
	35	u8 demod_type;
dba2b0c8	36	u32 frequency;
1da177e4 LT	37	};
1da177e4 LT	38
ff699e6b	39	static int debug;
1da177e4 LT	40	#define dprintk if (debug) printk
	41
	42	#define DEMOD_VES1893 0
	43	#define DEMOD_VES1993 1
	44
	45	static u8 init_1893_tab [] = {
	46	0x01, 0xa4, 0x35, 0x80, 0x2a, 0x0b, 0x55, 0xc4,
	47	0x09, 0x69, 0x00, 0x86, 0x4c, 0x28, 0x7f, 0x00,
	48	0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	49	0x80, 0x00, 0x21, 0xb0, 0x14, 0x00, 0xdc, 0x00,
	50	0x81, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	51	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	52	0x00, 0x55, 0x00, 0x00, 0x7f, 0x00
	53	};
	54
	55	static u8 init_1993_tab [] = {
	56	0x00, 0x9c, 0x35, 0x80, 0x6a, 0x09, 0x72, 0x8c,
	57	0x09, 0x6b, 0x00, 0x00, 0x4c, 0x08, 0x00, 0x00,
	58	0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	59	0x80, 0x40, 0x21, 0xb0, 0x00, 0x00, 0x00, 0x10,
	60	0x81, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	61	0x00, 0x00, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
	62	0x00, 0x55, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03,
	63	0x00, 0x00, 0x0e, 0x80, 0x00
	64	};
	65
	66	static u8 init_1893_wtab[] =
	67	{
	68	1,1,1,1,1,1,1,1, 1,1,0,0,1,1,0,0,
	69	0,1,0,0,0,0,0,0, 1,0,1,1,0,0,0,1,
	70	1,1,1,0,0,0,0,0, 0,0,1,1,0,0,0,0,
	71	1,1,1,0,1,1
	72	};
	73
	74	static u8 init_1993_wtab[] =
	75	{
	76	1,1,1,1,1,1,1,1, 1,1,0,0,1,1,0,0,
	77	0,1,0,0,0,0,0,0, 1,1,1,1,0,0,0,1,
	78	1,1,1,0,0,0,0,0, 0,0,1,1,0,0,0,0,
	79	1,1,1,0,1,1,1,1, 1,1,1,1,1
	80	};
	81
	82	static int ves1x93_writereg (struct ves1x93_state* state, u8 reg, u8 data)
	83	{
	84	u8 buf [] = { 0x00, reg, data };
	85	struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 3 };
	86	int err;
	87
	88	if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
271ddbf7	89	dprintk ("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __func__, err, reg, data);
1da177e4 LT	90	return -EREMOTEIO;
	91	}
	92
	93	return 0;
	94	}
	95
	96	static u8 ves1x93_readreg (struct ves1x93_state* state, u8 reg)
	97	{
	98	int ret;
	99	u8 b0 [] = { 0x00, reg };
	100	u8 b1 [] = { 0 };
	101	struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 2 },
	102	{ .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
	103
	104	ret = i2c_transfer (state->i2c, msg, 2);
	105
	106	if (ret != 2) return ret;
	107
	108	return b1[0];
	109	}
	110
	111	static int ves1x93_clr_bit (struct ves1x93_state* state)
	112	{
	113	msleep(10);
	114	ves1x93_writereg (state, 0, state->init_1x93_tab[0] & 0xfe);
	115	ves1x93_writereg (state, 0, state->init_1x93_tab[0]);
	116	msleep(50);
	117	return 0;
	118	}
	119
0df289a2 MCC	120	static int ves1x93_set_inversion(struct ves1x93_state *state,
0df289a2 MCC	121	enum fe_spectral_inversion inversion)
1da177e4 LT	122	{
	123	u8 val;
	124
	125	/*
	126	* inversion on/off are interchanged because i and q seem to
	127	* be swapped on the hardware
	128	*/
	129
	130	switch (inversion) {
	131	case INVERSION_OFF:
	132	val = 0xc0;
	133	break;
	134	case INVERSION_ON:
	135	val = 0x80;
	136	break;
	137	case INVERSION_AUTO:
	138	val = 0x00;
	139	break;
	140	default:
	141	return -EINVAL;
	142	}
	143
	144	return ves1x93_writereg (state, 0x0c, (state->init_1x93_tab[0x0c] & 0x3f) \| val);
	145	}
	146
0df289a2	147	static int ves1x93_set_fec(struct ves1x93_state *state, enum fe_code_rate fec)
1da177e4 LT	148	{
	149	if (fec == FEC_AUTO)
	150	return ves1x93_writereg (state, 0x0d, 0x08);
	151	else if (fec < FEC_1_2 \|\| fec > FEC_8_9)
	152	return -EINVAL;
	153	else
	154	return ves1x93_writereg (state, 0x0d, fec - FEC_1_2);
	155	}
	156
0df289a2	157	static enum fe_code_rate ves1x93_get_fec(struct ves1x93_state *state)
1da177e4 LT	158	{
	159	return FEC_1_2 + ((ves1x93_readreg (state, 0x0d) >> 4) & 0x7);
	160	}
	161
	162	static int ves1x93_set_symbolrate (struct ves1x93_state* state, u32 srate)
	163	{
	164	u32 BDR;
	165	u32 ratio;
	166	u8 ADCONF, FCONF, FNR, AGCR;
	167	u32 BDRI;
	168	u32 tmp;
	169	u32 FIN;
	170
271ddbf7	171	dprintk("%s: srate == %d\n", __func__, (unsigned int) srate);
1da177e4 LT	172
	173	if (srate > state->config->xin/2)
	174	srate = state->config->xin/2;
	175
	176	if (srate < 500000)
	177	srate = 500000;
	178
	179	#define MUL (1UL<<26)
	180
	181	FIN = (state->config->xin + 6000) >> 4;
	182
	183	tmp = srate << 6;
	184	ratio = tmp / FIN;
	185
	186	tmp = (tmp % FIN) << 8;
	187	ratio = (ratio << 8) + tmp / FIN;
	188
	189	tmp = (tmp % FIN) << 8;
	190	ratio = (ratio << 8) + tmp / FIN;
	191
	192	FNR = 0xff;
	193
	194	if (ratio < MUL/3) FNR = 0;
	195	if (ratio < (MUL*11)/50) FNR = 1;
	196	if (ratio < MUL/6) FNR = 2;
	197	if (ratio < MUL/9) FNR = 3;
	198	if (ratio < MUL/12) FNR = 4;
	199	if (ratio < (MUL*11)/200) FNR = 5;
	200	if (ratio < MUL/24) FNR = 6;
	201	if (ratio < (MUL*27)/1000) FNR = 7;
	202	if (ratio < MUL/48) FNR = 8;
	203	if (ratio < (MUL*137)/10000) FNR = 9;
	204
	205	if (FNR == 0xff) {
	206	ADCONF = 0x89;
	207	FCONF = 0x80;
	208	FNR = 0;
	209	} else {
	210	ADCONF = 0x81;
	211	FCONF = 0x88 \| (FNR >> 1) \| ((FNR & 0x01) << 5);
	212	/FCONF = 0x80 \| ((FNR & 0x01) << 5) \| (((FNR > 1) & 0x03) << 3) \| ((FNR >> 1) & 0x07);/
	213	}
	214
	215	BDR = (( (ratio << (FNR >> 1)) >> 4) + 1) >> 1;
	216	BDRI = ( ((FIN << 8) / ((srate << (FNR >> 1)) >> 2)) + 1) >> 1;
	217
	218	dprintk("FNR= %d\n", FNR);
	219	dprintk("ratio= %08x\n", (unsigned int) ratio);
	220	dprintk("BDR= %08x\n", (unsigned int) BDR);
	221	dprintk("BDRI= %02x\n", (unsigned int) BDRI);
	222
	223	if (BDRI > 0xff)
	224	BDRI = 0xff;
	225
	226	ves1x93_writereg (state, 0x06, 0xff & BDR);
	227	ves1x93_writereg (state, 0x07, 0xff & (BDR >> 8));
	228	ves1x93_writereg (state, 0x08, 0x0f & (BDR >> 16));
	229
	230	ves1x93_writereg (state, 0x09, BDRI);
	231	ves1x93_writereg (state, 0x20, ADCONF);
	232	ves1x93_writereg (state, 0x21, FCONF);
	233
	234	AGCR = state->init_1x93_tab[0x05];
	235	if (state->config->invert_pwm)
236	AGCR \|= 0x20;
237
238	if (srate < 6000000)
239	AGCR \|= 0x80;
240	else
241	AGCR &= ~0x80;
242
243	ves1x93_writereg (state, 0x05, AGCR);
244
245	/* ves1993 hates this, will lose lock */
246	if (state->demod_type != DEMOD_VES1993)
247	ves1x93_clr_bit (state);
248
249	return 0;
250	}
251
252	static int ves1x93_init (struct dvb_frontend* fe)
253	{
b8742700	254	struct ves1x93_state* state = fe->demodulator_priv;
1da177e4 LT	255	int i;
	256	int val;
	257
271ddbf7	258	dprintk("%s: init chip\n", __func__);
1da177e4 LT	259
	260	for (i = 0; i < state->tab_size; i++) {
	261	if (state->init_1x93_wtab[i]) {
	262	val = state->init_1x93_tab[i];
	263
	264	if (state->config->invert_pwm && (i == 0x05)) val \|= 0x20; /* invert PWM */
	265	ves1x93_writereg (state, i, val);
	266	}
	267	}
	268
1da177e4 LT	269	return 0;
	270	}
	271
0df289a2 MCC	272	static int ves1x93_set_voltage(struct dvb_frontend *fe,
0df289a2 MCC	273	enum fe_sec_voltage voltage)
1da177e4	274	{
b8742700	275	struct ves1x93_state* state = fe->demodulator_priv;
1da177e4 LT	276
	277	switch (voltage) {
	278	case SEC_VOLTAGE_13:
	279	return ves1x93_writereg (state, 0x1f, 0x20);
	280	case SEC_VOLTAGE_18:
	281	return ves1x93_writereg (state, 0x1f, 0x30);
	282	case SEC_VOLTAGE_OFF:
	283	return ves1x93_writereg (state, 0x1f, 0x00);
	284	default:
	285	return -EINVAL;
	286	}
	287	}
	288
0df289a2 MCC	289	static int ves1x93_read_status(struct dvb_frontend *fe,
0df289a2 MCC	290	enum fe_status *status)
1da177e4	291	{
b8742700	292	struct ves1x93_state* state = fe->demodulator_priv;
1da177e4 LT	293
	294	u8 sync = ves1x93_readreg (state, 0x0e);
	295
	296	/*
	297	* The ves1893 sometimes returns sync values that make no sense,
	298	* because, e.g., the SIGNAL bit is 0, while some of the higher
	299	* bits are 1 (and how can there be a CARRIER w/o a SIGNAL?).
59c51591	300	* Tests showed that the VITERBI and SYNC bits are returned
1da177e4 LT	301	* reliably, while the SIGNAL and CARRIER bits ar sometimes wrong.
	302	* If such a case occurs, we read the value again, until we get a
	303	* valid value.
	304	*/
	305	int maxtry = 10; /* just for safety - let's not get stuck here */
	306	while ((sync & 0x03) != 0x03 && (sync & 0x0c) && maxtry--) {
	307	msleep(10);
	308	sync = ves1x93_readreg (state, 0x0e);
	309	}
	310
	311	*status = 0;
	312
	313	if (sync & 1)
	314	*status \|= FE_HAS_SIGNAL;
	315
	316	if (sync & 2)
	317	*status \|= FE_HAS_CARRIER;
	318
	319	if (sync & 4)
	320	*status \|= FE_HAS_VITERBI;
	321
	322	if (sync & 8)
	323	*status \|= FE_HAS_SYNC;
	324
	325	if ((sync & 0x1f) == 0x1f)
	326	*status \|= FE_HAS_LOCK;
	327
	328	return 0;
	329	}
	330
	331	static int ves1x93_read_ber(struct dvb_frontend* fe, u32* ber)
	332	{
b8742700	333	struct ves1x93_state* state = fe->demodulator_priv;
1da177e4 LT	334
	335	*ber = ves1x93_readreg (state, 0x15);
	336	*ber \|= (ves1x93_readreg (state, 0x16) << 8);
	337	*ber \|= ((ves1x93_readreg (state, 0x17) & 0x0F) << 16);
	338	ber = 10;
	339
	340	return 0;
	341	}
	342
	343	static int ves1x93_read_signal_strength(struct dvb_frontend* fe, u16* strength)
	344	{
b8742700	345	struct ves1x93_state* state = fe->demodulator_priv;
1da177e4 LT	346
	347	u8 signal = ~ves1x93_readreg (state, 0x0b);
	348	*strength = (signal << 8) \| signal;
	349
	350	return 0;
	351	}
	352
	353	static int ves1x93_read_snr(struct dvb_frontend* fe, u16* snr)
	354	{
b8742700	355	struct ves1x93_state* state = fe->demodulator_priv;
1da177e4 LT	356
	357	u8 _snr = ~ves1x93_readreg (state, 0x1c);
	358	*snr = (_snr << 8) \| _snr;
	359
	360	return 0;
	361	}
	362
	363	static int ves1x93_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
	364	{
b8742700	365	struct ves1x93_state* state = fe->demodulator_priv;
1da177e4 LT	366
	367	*ucblocks = ves1x93_readreg (state, 0x18) & 0x7f;
	368
	369	if (*ucblocks == 0x7f)
	370	ucblocks = 0xffffffff; / counter overflow... */
	371
	372	ves1x93_writereg (state, 0x18, 0x00); /* reset the counter */
	373	ves1x93_writereg (state, 0x18, 0x80); /* dto. */
	374
	375	return 0;
	376	}
	377
dba2b0c8	378	static int ves1x93_set_frontend(struct dvb_frontend *fe)
1da177e4	379	{
dba2b0c8	380	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
b8742700	381	struct ves1x93_state* state = fe->demodulator_priv;
1da177e4	382
dea74869	383	if (fe->ops.tuner_ops.set_params) {
14d24d14	384	fe->ops.tuner_ops.set_params(fe);
dea74869	385	if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
66292ebe	386	}
1da177e4	387	ves1x93_set_inversion (state, p->inversion);
dba2b0c8 MCC	388	ves1x93_set_fec(state, p->fec_inner);
dba2b0c8 MCC	389	ves1x93_set_symbolrate(state, p->symbol_rate);
1da177e4	390	state->inversion = p->inversion;
dba2b0c8	391	state->frequency = p->frequency;
1da177e4 LT	392
	393	return 0;
	394	}
	395
7e3e68bc MCC	396	static int ves1x93_get_frontend(struct dvb_frontend *fe,
7e3e68bc MCC	397	struct dtv_frontend_properties *p)
1da177e4	398	{
b8742700	399	struct ves1x93_state* state = fe->demodulator_priv;
1da177e4 LT	400	int afc;
	401
	402	afc = ((int)((char)(ves1x93_readreg (state, 0x0a) << 1)))/2;
dba2b0c8	403	afc = (afc * (int)(p->symbol_rate/1000/8))/16;
1da177e4	404
dba2b0c8	405	p->frequency = state->frequency - afc;
1da177e4 LT	406
	407	/*
	408	* inversion indicator is only valid
	409	* if auto inversion was used
	410	*/
	411	if (state->inversion == INVERSION_AUTO)
	412	p->inversion = (ves1x93_readreg (state, 0x0f) & 2) ?
	413	INVERSION_OFF : INVERSION_ON;
dba2b0c8	414	p->fec_inner = ves1x93_get_fec(state);
1da177e4 LT	415	/* XXX FIXME: timing offset !! */
	416
	417	return 0;
	418	}
	419
	420	static int ves1x93_sleep(struct dvb_frontend* fe)
	421	{
b8742700	422	struct ves1x93_state* state = fe->demodulator_priv;
1da177e4 LT	423
	424	return ves1x93_writereg (state, 0x00, 0x08);
	425	}
	426
	427	static void ves1x93_release(struct dvb_frontend* fe)
	428	{
b8742700	429	struct ves1x93_state* state = fe->demodulator_priv;
1da177e4 LT	430	kfree(state);
	431	}
	432
66292ebe AQ	433	static int ves1x93_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
	434	{
	435	struct ves1x93_state* state = fe->demodulator_priv;
	436
	437	if (enable) {
	438	return ves1x93_writereg(state, 0x00, 0x11);
	439	} else {
	440	return ves1x93_writereg(state, 0x00, 0x01);
	441	}
	442	}
	443
bd336e63	444	static const struct dvb_frontend_ops ves1x93_ops;
1da177e4 LT	445
	446	struct dvb_frontend* ves1x93_attach(const struct ves1x93_config* config,
	447	struct i2c_adapter* i2c)
	448	{
	449	struct ves1x93_state* state = NULL;
	450	u8 identity;
	451
	452	/* allocate memory for the internal state */
084e24ac	453	state = kzalloc(sizeof(struct ves1x93_state), GFP_KERNEL);
1da177e4 LT	454	if (state == NULL) goto error;
	455
	456	/* setup the state */
	457	state->config = config;
	458	state->i2c = i2c;
1da177e4 LT	459	state->inversion = INVERSION_OFF;
	460
	461	/* check if the demod is there + identify it */
	462	identity = ves1x93_readreg(state, 0x1e);
	463	switch (identity) {
	464	case 0xdc: /* VES1893A rev1 */
	465	printk("ves1x93: Detected ves1893a rev1\n");
	466	state->demod_type = DEMOD_VES1893;
	467	state->init_1x93_tab = init_1893_tab;
	468	state->init_1x93_wtab = init_1893_wtab;
	469	state->tab_size = sizeof(init_1893_tab);
	470	break;
	471
	472	case 0xdd: /* VES1893A rev2 */
	473	printk("ves1x93: Detected ves1893a rev2\n");
	474	state->demod_type = DEMOD_VES1893;
	475	state->init_1x93_tab = init_1893_tab;
	476	state->init_1x93_wtab = init_1893_wtab;
	477	state->tab_size = sizeof(init_1893_tab);
	478	break;
	479
	480	case 0xde: /* VES1993 */
	481	printk("ves1x93: Detected ves1993\n");
	482	state->demod_type = DEMOD_VES1993;
	483	state->init_1x93_tab = init_1993_tab;
	484	state->init_1x93_wtab = init_1993_wtab;
	485	state->tab_size = sizeof(init_1993_tab);
	486	break;
	487
	488	default:
	489	goto error;
	490	}
	491
	492	/* create dvb_frontend */
dea74869	493	memcpy(&state->frontend.ops, &ves1x93_ops, sizeof(struct dvb_frontend_ops));
1da177e4 LT	494	state->frontend.demodulator_priv = state;
	495	return &state->frontend;
	496
	497	error:
	498	kfree(state);
	499	return NULL;
	500	}
	501
bd336e63	502	static const struct dvb_frontend_ops ves1x93_ops = {
dba2b0c8	503	.delsys = { SYS_DVBS },
1da177e4 LT	504	.info = {
1da177e4 LT	505	.name = "VLSI VES1x93 DVB-S",
f1b1eabf MCC	506	.frequency_min_hz = 950 * MHz,
	507	.frequency_max_hz = 2150 * MHz,
	508	.frequency_stepsize_hz = 125 * kHz,
	509	.frequency_tolerance_hz = 29500 * kHz,
1da177e4 LT	510	.symbol_rate_min = 1000000,
	511	.symbol_rate_max = 45000000,
	512	/* .symbol_rate_tolerance = ???,*/
	513	.caps = FE_CAN_INVERSION_AUTO \|
	514	FE_CAN_FEC_1_2 \| FE_CAN_FEC_2_3 \| FE_CAN_FEC_3_4 \|
	515	FE_CAN_FEC_5_6 \| FE_CAN_FEC_7_8 \| FE_CAN_FEC_AUTO \|
	516	FE_CAN_QPSK
	517	},
	518
	519	.release = ves1x93_release,
	520
	521	.init = ves1x93_init,
	522	.sleep = ves1x93_sleep,
66292ebe	523	.i2c_gate_ctrl = ves1x93_i2c_gate_ctrl,
1da177e4	524
dba2b0c8 MCC	525	.set_frontend = ves1x93_set_frontend,
dba2b0c8 MCC	526	.get_frontend = ves1x93_get_frontend,
1da177e4 LT	527
	528	.read_status = ves1x93_read_status,
	529	.read_ber = ves1x93_read_ber,
	530	.read_signal_strength = ves1x93_read_signal_strength,
	531	.read_snr = ves1x93_read_snr,
	532	.read_ucblocks = ves1x93_read_ucblocks,
	533
	534	.set_voltage = ves1x93_set_voltage,
	535	};
	536
	537	module_param(debug, int, 0644);
	538
	539	MODULE_DESCRIPTION("VLSI VES1x93 DVB-S Demodulator driver");
	540	MODULE_AUTHOR("Ralph Metzler");
	541	MODULE_LICENSE("GPL");
	542
	543	EXPORT_SYMBOL(ves1x93_attach);