[linux-2.6-block.git] / drivers / media / dvb-frontends / tda10023.c

/*
    TDA10023  - DVB-C decoder
    (as used in Philips CU1216-3 NIM and the Reelbox DVB-C tuner card)

    Copyright (C) 2005 Georg Acher, BayCom GmbH (acher at baycom dot de)
    Copyright (c) 2006 Hartmut Birr (e9hack at gmail dot com)

    Remotely based on tda10021.c
    Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
    Copyright (C) 2004 Markus Schulz <msc@antzsystem.de>
		   Support for TDA10021

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/

#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>

#include <asm/div64.h>

#include <media/dvb_frontend.h>
#include "tda1002x.h"

#define REG0_INIT_VAL 0x23

struct tda10023_state {
	struct i2c_adapter* i2c;
	/* configuration settings */
	const struct tda10023_config *config;
	struct dvb_frontend frontend;

	u8 pwm;
	u8 reg0;

	/* clock settings */
	u32 xtal;
	u8 pll_m;
	u8 pll_p;
	u8 pll_n;
	u32 sysclk;
};

#define dprintk(x...)

static int verbose;

static u8 tda10023_readreg (struct tda10023_state* state, u8 reg)
{
	u8 b0 [] = { reg };
	u8 b1 [] = { 0 };
	struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
				  { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
	int ret;

	ret = i2c_transfer (state->i2c, msg, 2);
	if (ret != 2) {
		int num = state->frontend.dvb ? state->frontend.dvb->num : -1;
		printk(KERN_ERR "DVB: TDA10023(%d): %s: readreg error (reg == 0x%02x, ret == %i)\n",
			num, __func__, reg, ret);
	}
	return b1[0];
}

static int tda10023_writereg (struct tda10023_state* state, u8 reg, u8 data)
{
	u8 buf[] = { reg, data };
	struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
	int ret;

	ret = i2c_transfer (state->i2c, &msg, 1);
	if (ret != 1) {
		int num = state->frontend.dvb ? state->frontend.dvb->num : -1;
		printk(KERN_ERR "DVB: TDA10023(%d): %s, writereg error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
			num, __func__, reg, data, ret);
	}
	return (ret != 1) ? -EREMOTEIO : 0;
}


static int tda10023_writebit (struct tda10023_state* state, u8 reg, u8 mask,u8 data)
{
	if (mask==0xff)
		return tda10023_writereg(state, reg, data);
	else {
		u8 val;
		val=tda10023_readreg(state,reg);
		val&=~mask;
		val|=(data&mask);
		return tda10023_writereg(state, reg, val);
	}
}

static void tda10023_writetab(struct tda10023_state* state, u8* tab)
{
	u8 r,m,v;
	while (1) {
		r=*tab++;
		m=*tab++;
		v=*tab++;
		if (r==0xff) {
			if (m==0xff)
				break;
			else
				msleep(m);
		}
		else
			tda10023_writebit(state,r,m,v);
	}
}

//get access to tuner
static int lock_tuner(struct tda10023_state* state)
{
	u8 buf[2] = { 0x0f, 0xc0 };
	struct i2c_msg msg = {.addr=state->config->demod_address, .flags=0, .buf=buf, .len=2};

	if(i2c_transfer(state->i2c, &msg, 1) != 1)
	{
		printk("tda10023: lock tuner fails\n");
		return -EREMOTEIO;
	}
	return 0;
}

//release access from tuner
static int unlock_tuner(struct tda10023_state* state)
{
	u8 buf[2] = { 0x0f, 0x40 };
	struct i2c_msg msg_post={.addr=state->config->demod_address, .flags=0, .buf=buf, .len=2};

	if(i2c_transfer(state->i2c, &msg_post, 1) != 1)
	{
		printk("tda10023: unlock tuner fails\n");
		return -EREMOTEIO;
	}
	return 0;
}

static int tda10023_setup_reg0 (struct tda10023_state* state, u8 reg0)
{
	reg0 |= state->reg0 & 0x63;

	tda10023_writereg (state, 0x00, reg0 & 0xfe);
	tda10023_writereg (state, 0x00, reg0 | 0x01);

	state->reg0 = reg0;
	return 0;
}

static int tda10023_set_symbolrate (struct tda10023_state* state, u32 sr)
{
	s32 BDR;
	s32 BDRI;
	s16 SFIL=0;
	u16 NDEC = 0;

	/* avoid floating point operations multiplying syscloc and divider
	   by 10 */
	u32 sysclk_x_10 = state->sysclk * 10;

	if (sr < (u32)(sysclk_x_10/984)) {
		NDEC=3;
		SFIL=1;
	} else if (sr < (u32)(sysclk_x_10/640)) {
		NDEC=3;
		SFIL=0;
	} else if (sr < (u32)(sysclk_x_10/492)) {
		NDEC=2;
		SFIL=1;
	} else if (sr < (u32)(sysclk_x_10/320)) {
		NDEC=2;
		SFIL=0;
	} else if (sr < (u32)(sysclk_x_10/246)) {
		NDEC=1;
		SFIL=1;
	} else if (sr < (u32)(sysclk_x_10/160)) {
		NDEC=1;
		SFIL=0;
	} else if (sr < (u32)(sysclk_x_10/123)) {
		NDEC=0;
		SFIL=1;
	}

	BDRI = (state->sysclk)*16;
	BDRI>>=NDEC;
	BDRI +=sr/2;
	BDRI /=sr;

	if (BDRI>255)
		BDRI=255;

	{
		u64 BDRX;

		BDRX=1<<(24+NDEC);
		BDRX*=sr;
		do_div(BDRX, state->sysclk);	/* BDRX/=SYSCLK; */

		BDR=(s32)BDRX;
	}
	dprintk("Symbolrate %i, BDR %i BDRI %i, NDEC %i\n",
		sr, BDR, BDRI, NDEC);
	tda10023_writebit (state, 0x03, 0xc0, NDEC<<6);
	tda10023_writereg (state, 0x0a, BDR&255);
	tda10023_writereg (state, 0x0b, (BDR>>8)&255);
	tda10023_writereg (state, 0x0c, (BDR>>16)&31);
	tda10023_writereg (state, 0x0d, BDRI);
	tda10023_writereg (state, 0x3d, (SFIL<<7));
	return 0;
}

static int tda10023_init (struct dvb_frontend *fe)
{
	struct tda10023_state* state = fe->demodulator_priv;
	u8 tda10023_inittab[] = {
/*        reg  mask val */
/* 000 */ 0x2a, 0xff, 0x02,  /* PLL3, Bypass, Power Down */
/* 003 */ 0xff, 0x64, 0x00,  /* Sleep 100ms */
/* 006 */ 0x2a, 0xff, 0x03,  /* PLL3, Bypass, Power Down */
/* 009 */ 0xff, 0x64, 0x00,  /* Sleep 100ms */
			   /* PLL1 */
/* 012 */ 0x28, 0xff, (state->pll_m-1),
			   /* PLL2 */
/* 015 */ 0x29, 0xff, ((state->pll_p-1)<<6)|(state->pll_n-1),
			   /* GPR FSAMPLING=1 */
/* 018 */ 0x00, 0xff, REG0_INIT_VAL,
/* 021 */ 0x2a, 0xff, 0x08,  /* PLL3 PSACLK=1 */
/* 024 */ 0xff, 0x64, 0x00,  /* Sleep 100ms */
/* 027 */ 0x1f, 0xff, 0x00,  /* RESET */
/* 030 */ 0xff, 0x64, 0x00,  /* Sleep 100ms */
/* 033 */ 0xe6, 0x0c, 0x04,  /* RSCFG_IND */
/* 036 */ 0x10, 0xc0, 0x80,  /* DECDVBCFG1 PBER=1 */

/* 039 */ 0x0e, 0xff, 0x82,  /* GAIN1 */
/* 042 */ 0x03, 0x08, 0x08,  /* CLKCONF DYN=1 */
/* 045 */ 0x2e, 0xbf, 0x30,  /* AGCCONF2 TRIAGC=0,POSAGC=ENAGCIF=1
				       PPWMTUN=0 PPWMIF=0 */
/* 048 */ 0x01, 0xff, 0x30,  /* AGCREF */
/* 051 */ 0x1e, 0x84, 0x84,  /* CONTROL SACLK_ON=1 */
/* 054 */ 0x1b, 0xff, 0xc8,  /* ADC TWOS=1 */
/* 057 */ 0x3b, 0xff, 0xff,  /* IFMAX */
/* 060 */ 0x3c, 0xff, 0x00,  /* IFMIN */
/* 063 */ 0x34, 0xff, 0x00,  /* PWMREF */
/* 066 */ 0x35, 0xff, 0xff,  /* TUNMAX */
/* 069 */ 0x36, 0xff, 0x00,  /* TUNMIN */
/* 072 */ 0x06, 0xff, 0x7f,  /* EQCONF1 POSI=7 ENADAPT=ENEQUAL=DFE=1 */
/* 075 */ 0x1c, 0x30, 0x30,  /* EQCONF2 STEPALGO=SGNALGO=1 */
/* 078 */ 0x37, 0xff, 0xf6,  /* DELTAF_LSB */
/* 081 */ 0x38, 0xff, 0xff,  /* DELTAF_MSB */
/* 084 */ 0x02, 0xff, 0x93,  /* AGCCONF1  IFS=1 KAGCIF=2 KAGCTUN=3 */
/* 087 */ 0x2d, 0xff, 0xf6,  /* SWEEP SWPOS=1 SWDYN=7 SWSTEP=1 SWLEN=2 */
/* 090 */ 0x04, 0x10, 0x00,  /* SWRAMP=1 */
/* 093 */ 0x12, 0xff, TDA10023_OUTPUT_MODE_PARALLEL_B, /*
				INTP1 POCLKP=1 FEL=1 MFS=0 */
/* 096 */ 0x2b, 0x01, 0xa1,  /* INTS1 */
/* 099 */ 0x20, 0xff, 0x04,  /* INTP2 SWAPP=? MSBFIRSTP=? INTPSEL=? */
/* 102 */ 0x2c, 0xff, 0x0d,  /* INTP/S TRIP=0 TRIS=0 */
/* 105 */ 0xc4, 0xff, 0x00,
/* 108 */ 0xc3, 0x30, 0x00,
/* 111 */ 0xb5, 0xff, 0x19,  /* ERAGC_THD */
/* 114 */ 0x00, 0x03, 0x01,  /* GPR, CLBS soft reset */
/* 117 */ 0x00, 0x03, 0x03,  /* GPR, CLBS soft reset */
/* 120 */ 0xff, 0x64, 0x00,  /* Sleep 100ms */
/* 123 */ 0xff, 0xff, 0xff
};
	dprintk("DVB: TDA10023(%d): init chip\n", fe->dvb->num);

	/* override default values if set in config */
	if (state->config->deltaf) {
		tda10023_inittab[80] = (state->config->deltaf & 0xff);
		tda10023_inittab[83] = (state->config->deltaf >> 8);
	}

	if (state->config->output_mode)
		tda10023_inittab[95] = state->config->output_mode;

	tda10023_writetab(state, tda10023_inittab);

	return 0;
}

struct qam_params {
	u8 qam, lockthr, mseth, aref, agcrefnyq, eragnyq_thd;
};

static int tda10023_set_parameters(struct dvb_frontend *fe)
{
	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
	u32 delsys  = c->delivery_system;
	unsigned qam = c->modulation;
	bool is_annex_c;
	struct tda10023_state* state = fe->demodulator_priv;
	static const struct qam_params qam_params[] = {
		/* Modulation  QAM    LOCKTHR   MSETH   AREF AGCREFNYQ ERAGCNYQ_THD */
		[QPSK]    = { (5<<2),  0x78,    0x8c,   0x96,   0x78,   0x4c  },
		[QAM_16]  = { (0<<2),  0x87,    0xa2,   0x91,   0x8c,   0x57  },
		[QAM_32]  = { (1<<2),  0x64,    0x74,   0x96,   0x8c,   0x57  },
		[QAM_64]  = { (2<<2),  0x46,    0x43,   0x6a,   0x6a,   0x44  },
		[QAM_128] = { (3<<2),  0x36,    0x34,   0x7e,   0x78,   0x4c  },
		[QAM_256] = { (4<<2),  0x26,    0x23,   0x6c,   0x5c,   0x3c  },
	};

	switch (delsys) {
	case SYS_DVBC_ANNEX_A:
		is_annex_c = false;
		break;
	case SYS_DVBC_ANNEX_C:
		is_annex_c = true;
		break;
	default:
		return -EINVAL;
	}

	/*
	 * gcc optimizes the code below the same way as it would code:
	 *		 "if (qam > 5) return -EINVAL;"
	 * Yet, the code is clearer, as it shows what QAM standards are
	 * supported by the driver, and avoids the usage of magic numbers on
	 * it.
	 */
	switch (qam) {
	case QPSK:
	case QAM_16:
	case QAM_32:
	case QAM_64:
	case QAM_128:
	case QAM_256:
		break;
	default:
		return -EINVAL;
	}

	if (fe->ops.tuner_ops.set_params) {
		fe->ops.tuner_ops.set_params(fe);
		if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
	}

	tda10023_set_symbolrate(state, c->symbol_rate);
	tda10023_writereg(state, 0x05, qam_params[qam].lockthr);
	tda10023_writereg(state, 0x08, qam_params[qam].mseth);
	tda10023_writereg(state, 0x09, qam_params[qam].aref);
	tda10023_writereg(state, 0xb4, qam_params[qam].agcrefnyq);
	tda10023_writereg(state, 0xb6, qam_params[qam].eragnyq_thd);
#if 0
	tda10023_writereg(state, 0x04, (c->inversion ? 0x12 : 0x32));
	tda10023_writebit(state, 0x04, 0x60, (c->inversion ? 0 : 0x20));
#endif
	tda10023_writebit(state, 0x04, 0x40, 0x40);

	if (is_annex_c)
		tda10023_writebit(state, 0x3d, 0xfc, 0x03);
	else
		tda10023_writebit(state, 0x3d, 0xfc, 0x02);

	tda10023_setup_reg0(state, qam_params[qam].qam);

	return 0;
}

static int tda10023_read_status(struct dvb_frontend *fe,
				enum fe_status *status)
{
	struct tda10023_state* state = fe->demodulator_priv;
	int sync;

	*status = 0;

	//0x11[1] == CARLOCK -> Carrier locked
	//0x11[2] == FSYNC -> Frame synchronisation
	//0x11[3] == FEL -> Front End locked
	//0x11[6] == NODVB -> DVB Mode Information
	sync = tda10023_readreg (state, 0x11);

	if (sync & 2)
		*status |= FE_HAS_SIGNAL|FE_HAS_CARRIER;

	if (sync & 4)
		*status |= FE_HAS_SYNC|FE_HAS_VITERBI;

	if (sync & 8)
		*status |= FE_HAS_LOCK;

	return 0;
}

static int tda10023_read_ber(struct dvb_frontend* fe, u32* ber)
{
	struct tda10023_state* state = fe->demodulator_priv;
	u8 a,b,c;
	a=tda10023_readreg(state, 0x14);
	b=tda10023_readreg(state, 0x15);
	c=tda10023_readreg(state, 0x16)&0xf;
	tda10023_writebit (state, 0x10, 0xc0, 0x00);

	*ber = a | (b<<8)| (c<<16);
	return 0;
}

static int tda10023_read_signal_strength(struct dvb_frontend* fe, u16* strength)
{
	struct tda10023_state* state = fe->demodulator_priv;
	u8 ifgain=tda10023_readreg(state, 0x2f);

	u16 gain = ((255-tda10023_readreg(state, 0x17))) + (255-ifgain)/16;
	// Max raw value is about 0xb0 -> Normalize to >0xf0 after 0x90
	if (gain>0x90)
		gain=gain+2*(gain-0x90);
	if (gain>255)
		gain=255;

	*strength = (gain<<8)|gain;
	return 0;
}

static int tda10023_read_snr(struct dvb_frontend* fe, u16* snr)
{
	struct tda10023_state* state = fe->demodulator_priv;

	u8 quality = ~tda10023_readreg(state, 0x18);
	*snr = (quality << 8) | quality;
	return 0;
}

static int tda10023_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
{
	struct tda10023_state* state = fe->demodulator_priv;
	u8 a,b,c,d;
	a= tda10023_readreg (state, 0x74);
	b= tda10023_readreg (state, 0x75);
	c= tda10023_readreg (state, 0x76);
	d= tda10023_readreg (state, 0x77);
	*ucblocks = a | (b<<8)|(c<<16)|(d<<24);

	tda10023_writebit (state, 0x10, 0x20,0x00);
	tda10023_writebit (state, 0x10, 0x20,0x20);
	tda10023_writebit (state, 0x13, 0x01, 0x00);

	return 0;
}

static int tda10023_get_frontend(struct dvb_frontend *fe,
				 struct dtv_frontend_properties *p)
{
	struct tda10023_state* state = fe->demodulator_priv;
	int sync,inv;
	s8 afc = 0;

	sync = tda10023_readreg(state, 0x11);
	afc = tda10023_readreg(state, 0x19);
	inv = tda10023_readreg(state, 0x04);

	if (verbose) {
		/* AFC only valid when carrier has been recovered */
		printk(sync & 2 ? "DVB: TDA10023(%d): AFC (%d) %dHz\n" :
				  "DVB: TDA10023(%d): [AFC (%d) %dHz]\n",
			state->frontend.dvb->num, afc,
		       -((s32)p->symbol_rate * afc) >> 10);
	}

	p->inversion = (inv&0x20?0:1);
	p->modulation = ((state->reg0 >> 2) & 7) + QAM_16;

	p->fec_inner = FEC_NONE;
	p->frequency = ((p->frequency + 31250) / 62500) * 62500;

	if (sync & 2)
		p->frequency -= ((s32)p->symbol_rate * afc) >> 10;

	return 0;
}

static int tda10023_sleep(struct dvb_frontend* fe)
{
	struct tda10023_state* state = fe->demodulator_priv;

	tda10023_writereg (state, 0x1b, 0x02);  /* pdown ADC */
	tda10023_writereg (state, 0x00, 0x80);  /* standby */

	return 0;
}

static int tda10023_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
{
	struct tda10023_state* state = fe->demodulator_priv;

	if (enable) {
		lock_tuner(state);
	} else {
		unlock_tuner(state);
	}
	return 0;
}

static void tda10023_release(struct dvb_frontend* fe)
{
	struct tda10023_state* state = fe->demodulator_priv;
	kfree(state);
}

static const struct dvb_frontend_ops tda10023_ops;

struct dvb_frontend *tda10023_attach(const struct tda10023_config *config,
				     struct i2c_adapter *i2c,
				     u8 pwm)
{
	struct tda10023_state* state = NULL;

	/* allocate memory for the internal state */
	state = kzalloc(sizeof(struct tda10023_state), GFP_KERNEL);
	if (state == NULL) goto error;

	/* setup the state */
	state->config = config;
	state->i2c = i2c;

	/* wakeup if in standby */
	tda10023_writereg (state, 0x00, 0x33);
	/* check if the demod is there */
	if ((tda10023_readreg(state, 0x1a) & 0xf0) != 0x70) goto error;

	/* create dvb_frontend */
	memcpy(&state->frontend.ops, &tda10023_ops, sizeof(struct dvb_frontend_ops));
	state->pwm = pwm;
	state->reg0 = REG0_INIT_VAL;
	if (state->config->xtal) {
		state->xtal  = state->config->xtal;
		state->pll_m = state->config->pll_m;
		state->pll_p = state->config->pll_p;
		state->pll_n = state->config->pll_n;
	} else {
		/* set default values if not defined in config */
		state->xtal  = 28920000;
		state->pll_m = 8;
		state->pll_p = 4;
		state->pll_n = 1;
	}

	/* calc sysclk */
	state->sysclk = (state->xtal * state->pll_m / \
			(state->pll_n * state->pll_p));

	state->frontend.ops.info.symbol_rate_min = (state->sysclk/2)/64;
	state->frontend.ops.info.symbol_rate_max = (state->sysclk/2)/4;

	dprintk("DVB: TDA10023 %s: xtal:%d pll_m:%d pll_p:%d pll_n:%d\n",
		__func__, state->xtal, state->pll_m, state->pll_p,
		state->pll_n);

	state->frontend.demodulator_priv = state;
	return &state->frontend;

error:
	kfree(state);
	return NULL;
}

static const struct dvb_frontend_ops tda10023_ops = {
	.delsys = { SYS_DVBC_ANNEX_A, SYS_DVBC_ANNEX_C },
	.info = {
		.name = "Philips TDA10023 DVB-C",
		.frequency_min_hz =  47 * MHz,
		.frequency_max_hz = 862 * MHz,
		.frequency_stepsize_hz = 62500,
		.symbol_rate_min = 0,  /* set in tda10023_attach */
		.symbol_rate_max = 0,  /* set in tda10023_attach */
		.caps = 0x400 | //FE_CAN_QAM_4
			FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
			FE_CAN_QAM_128 | FE_CAN_QAM_256 |
			FE_CAN_FEC_AUTO
	},

	.release = tda10023_release,

	.init = tda10023_init,
	.sleep = tda10023_sleep,
	.i2c_gate_ctrl = tda10023_i2c_gate_ctrl,

	.set_frontend = tda10023_set_parameters,
	.get_frontend = tda10023_get_frontend,
	.read_status = tda10023_read_status,
	.read_ber = tda10023_read_ber,
	.read_signal_strength = tda10023_read_signal_strength,
	.read_snr = tda10023_read_snr,
	.read_ucblocks = tda10023_read_ucblocks,
};


MODULE_DESCRIPTION("Philips TDA10023 DVB-C demodulator driver");
MODULE_AUTHOR("Georg Acher, Hartmut Birr");
MODULE_LICENSE("GPL");

EXPORT_SYMBOL(tda10023_attach);
Commit	Line	Data
aa323ac8 HB	1	/*
	2	TDA10023 - DVB-C decoder
	3	(as used in Philips CU1216-3 NIM and the Reelbox DVB-C tuner card)
	4
	5	Copyright (C) 2005 Georg Acher, BayCom GmbH (acher at baycom dot de)
	6	Copyright (c) 2006 Hartmut Birr (e9hack at gmail dot com)
	7
	8	Remotely based on tda10021.c
	9	Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
	10	Copyright (C) 2004 Markus Schulz <msc@antzsystem.de>
	11	Support for TDA10021
	12
	13	This program is free software; you can redistribute it and/or modify
	14	it under the terms of the GNU General Public License as published by
	15	the Free Software Foundation; either version 2 of the License, or
	16	(at your option) any later version.
	17
	18	This program is distributed in the hope that it will be useful,
	19	but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	GNU General Public License for more details.
	22
	23	You should have received a copy of the GNU General Public License
	24	along with this program; if not, write to the Free Software
	25	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	26	*/
	27
	28	#include <linux/delay.h>
	29	#include <linux/errno.h>
	30	#include <linux/init.h>
	31	#include <linux/kernel.h>
	32	#include <linux/module.h>
	33	#include <linux/string.h>
	34	#include <linux/slab.h>
	35
	36	#include <asm/div64.h>
	37
fada1935	38	#include <media/dvb_frontend.h>
aa323ac8 HB	39	#include "tda1002x.h"
aa323ac8 HB	40
4388c3b4	41	#define REG0_INIT_VAL 0x23
aa323ac8 HB	42
	43	struct tda10023_state {
	44	struct i2c_adapter* i2c;
	45	/* configuration settings */
4388c3b4	46	const struct tda10023_config *config;
aa323ac8 HB	47	struct dvb_frontend frontend;
	48
	49	u8 pwm;
	50	u8 reg0;
aa323ac8	51
4388c3b4 AP	52	/* clock settings */
	53	u32 xtal;
	54	u8 pll_m;
	55	u8 pll_p;
	56	u8 pll_n;
	57	u32 sysclk;
	58	};
aa323ac8 HB	59
	60	#define dprintk(x...)
	61
	62	static int verbose;
	63
aa323ac8 HB	64	static u8 tda10023_readreg (struct tda10023_state* state, u8 reg)
	65	{
	66	u8 b0 [] = { reg };
	67	u8 b1 [] = { 0 };
	68	struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
	69	{ .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
	70	int ret;
	71
	72	ret = i2c_transfer (state->i2c, msg, 2);
c9fa2b1e OE	73	if (ret != 2) {
c9fa2b1e OE	74	int num = state->frontend.dvb ? state->frontend.dvb->num : -1;
4bd69e7b	75	printk(KERN_ERR "DVB: TDA10023(%d): %s: readreg error (reg == 0x%02x, ret == %i)\n",
c9fa2b1e OE	76	num, __func__, reg, ret);
c9fa2b1e OE	77	}
aa323ac8 HB	78	return b1[0];
	79	}
	80
	81	static int tda10023_writereg (struct tda10023_state* state, u8 reg, u8 data)
	82	{
	83	u8 buf[] = { reg, data };
	84	struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
	85	int ret;
	86
	87	ret = i2c_transfer (state->i2c, &msg, 1);
c9fa2b1e OE	88	if (ret != 1) {
c9fa2b1e OE	89	int num = state->frontend.dvb ? state->frontend.dvb->num : -1;
4bd69e7b	90	printk(KERN_ERR "DVB: TDA10023(%d): %s, writereg error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
c9fa2b1e OE	91	num, __func__, reg, data, ret);
c9fa2b1e OE	92	}
aa323ac8 HB	93	return (ret != 1) ? -EREMOTEIO : 0;
	94	}
	95
	96
	97	static int tda10023_writebit (struct tda10023_state* state, u8 reg, u8 mask,u8 data)
	98	{
	99	if (mask==0xff)
	100	return tda10023_writereg(state, reg, data);
	101	else {
	102	u8 val;
	103	val=tda10023_readreg(state,reg);
	104	val&=~mask;
	105	val\|=(data&mask);
	106	return tda10023_writereg(state, reg, val);
	107	}
	108	}
	109
	110	static void tda10023_writetab(struct tda10023_state* state, u8* tab)
	111	{
	112	u8 r,m,v;
	113	while (1) {
	114	r=*tab++;
	115	m=*tab++;
	116	v=*tab++;
	117	if (r==0xff) {
	118	if (m==0xff)
	119	break;
	120	else
	121	msleep(m);
	122	}
	123	else
	124	tda10023_writebit(state,r,m,v);
	125	}
	126	}
	127
	128	//get access to tuner
	129	static int lock_tuner(struct tda10023_state* state)
	130	{
	131	u8 buf[2] = { 0x0f, 0xc0 };
	132	struct i2c_msg msg = {.addr=state->config->demod_address, .flags=0, .buf=buf, .len=2};
	133
	134	if(i2c_transfer(state->i2c, &msg, 1) != 1)
	135	{
	136	printk("tda10023: lock tuner fails\n");
	137	return -EREMOTEIO;
	138	}
	139	return 0;
	140	}
	141
	142	//release access from tuner
	143	static int unlock_tuner(struct tda10023_state* state)
	144	{
	145	u8 buf[2] = { 0x0f, 0x40 };
	146	struct i2c_msg msg_post={.addr=state->config->demod_address, .flags=0, .buf=buf, .len=2};
	147
	148	if(i2c_transfer(state->i2c, &msg_post, 1) != 1)
	149	{
	150	printk("tda10023: unlock tuner fails\n");
	151	return -EREMOTEIO;
	152	}
	153	return 0;
	154	}
	155
	156	static int tda10023_setup_reg0 (struct tda10023_state* state, u8 reg0)
157	{
158	reg0 \|= state->reg0 & 0x63;
159
160	tda10023_writereg (state, 0x00, reg0 & 0xfe);
161	tda10023_writereg (state, 0x00, reg0 \| 0x01);
162
163	state->reg0 = reg0;
164	return 0;
165	}
166
167	static int tda10023_set_symbolrate (struct tda10023_state* state, u32 sr)
168	{
169	s32 BDR;
170	s32 BDRI;
171	s16 SFIL=0;
172	u16 NDEC = 0;
173
4388c3b4 AP	174	/* avoid floating point operations multiplying syscloc and divider
	175	by 10 */
	176	u32 sysclk_x_10 = state->sysclk * 10;
	177
	178	if (sr < (u32)(sysclk_x_10/984)) {
aa323ac8 HB	179	NDEC=3;
aa323ac8 HB	180	SFIL=1;
4388c3b4	181	} else if (sr < (u32)(sysclk_x_10/640)) {
aa323ac8 HB	182	NDEC=3;
aa323ac8 HB	183	SFIL=0;
4388c3b4	184	} else if (sr < (u32)(sysclk_x_10/492)) {
aa323ac8 HB	185	NDEC=2;
aa323ac8 HB	186	SFIL=1;
4388c3b4	187	} else if (sr < (u32)(sysclk_x_10/320)) {
aa323ac8 HB	188	NDEC=2;
aa323ac8 HB	189	SFIL=0;
4388c3b4	190	} else if (sr < (u32)(sysclk_x_10/246)) {
aa323ac8 HB	191	NDEC=1;
aa323ac8 HB	192	SFIL=1;
4388c3b4	193	} else if (sr < (u32)(sysclk_x_10/160)) {
aa323ac8 HB	194	NDEC=1;
aa323ac8 HB	195	SFIL=0;
4388c3b4	196	} else if (sr < (u32)(sysclk_x_10/123)) {
aa323ac8 HB	197	NDEC=0;
	198	SFIL=1;
	199	}
	200
4388c3b4	201	BDRI = (state->sysclk)*16;
aa323ac8 HB	202	BDRI>>=NDEC;
	203	BDRI +=sr/2;
	204	BDRI /=sr;
	205
	206	if (BDRI>255)
	207	BDRI=255;
	208
	209	{
	210	u64 BDRX;
	211
	212	BDRX=1<<(24+NDEC);
	213	BDRX*=sr;
6e6a8b5a	214	do_div(BDRX, state->sysclk); /* BDRX/=SYSCLK; */
aa323ac8 HB	215
	216	BDR=(s32)BDRX;
	217	}
4388c3b4 AP	218	dprintk("Symbolrate %i, BDR %i BDRI %i, NDEC %i\n",
4388c3b4 AP	219	sr, BDR, BDRI, NDEC);
aa323ac8 HB	220	tda10023_writebit (state, 0x03, 0xc0, NDEC<<6);
	221	tda10023_writereg (state, 0x0a, BDR&255);
	222	tda10023_writereg (state, 0x0b, (BDR>>8)&255);
	223	tda10023_writereg (state, 0x0c, (BDR>>16)&31);
	224	tda10023_writereg (state, 0x0d, BDRI);
	225	tda10023_writereg (state, 0x3d, (SFIL<<7));
	226	return 0;
	227	}
	228
	229	static int tda10023_init (struct dvb_frontend *fe)
	230	{
	231	struct tda10023_state* state = fe->demodulator_priv;
4388c3b4 AP	232	u8 tda10023_inittab[] = {
	233	/* reg mask val */
	234	/* 000 / 0x2a, 0xff, 0x02, / PLL3, Bypass, Power Down */
	235	/* 003 / 0xff, 0x64, 0x00, / Sleep 100ms */
	236	/* 006 / 0x2a, 0xff, 0x03, / PLL3, Bypass, Power Down */
	237	/* 009 / 0xff, 0x64, 0x00, / Sleep 100ms */
	238	/* PLL1 */
	239	/* 012 */ 0x28, 0xff, (state->pll_m-1),
	240	/* PLL2 */
	241	/* 015 */ 0x29, 0xff, ((state->pll_p-1)<<6)\|(state->pll_n-1),
	242	/* GPR FSAMPLING=1 */
	243	/* 018 */ 0x00, 0xff, REG0_INIT_VAL,
	244	/* 021 / 0x2a, 0xff, 0x08, / PLL3 PSACLK=1 */
	245	/* 024 / 0xff, 0x64, 0x00, / Sleep 100ms */
	246	/* 027 / 0x1f, 0xff, 0x00, / RESET */
	247	/* 030 / 0xff, 0x64, 0x00, / Sleep 100ms */
	248	/* 033 / 0xe6, 0x0c, 0x04, / RSCFG_IND */
	249	/* 036 / 0x10, 0xc0, 0x80, / DECDVBCFG1 PBER=1 */
	250
	251	/* 039 / 0x0e, 0xff, 0x82, / GAIN1 */
	252	/* 042 / 0x03, 0x08, 0x08, / CLKCONF DYN=1 */
	253	/* 045 / 0x2e, 0xbf, 0x30, / AGCCONF2 TRIAGC=0,POSAGC=ENAGCIF=1
	254	PPWMTUN=0 PPWMIF=0 */
	255	/* 048 / 0x01, 0xff, 0x30, / AGCREF */
	256	/* 051 / 0x1e, 0x84, 0x84, / CONTROL SACLK_ON=1 */
	257	/* 054 / 0x1b, 0xff, 0xc8, / ADC TWOS=1 */
	258	/* 057 / 0x3b, 0xff, 0xff, / IFMAX */
	259	/* 060 / 0x3c, 0xff, 0x00, / IFMIN */
	260	/* 063 / 0x34, 0xff, 0x00, / PWMREF */
	261	/* 066 / 0x35, 0xff, 0xff, / TUNMAX */
	262	/* 069 / 0x36, 0xff, 0x00, / TUNMIN */
	263	/* 072 / 0x06, 0xff, 0x7f, / EQCONF1 POSI=7 ENADAPT=ENEQUAL=DFE=1 */
	264	/* 075 / 0x1c, 0x30, 0x30, / EQCONF2 STEPALGO=SGNALGO=1 */
	265	/* 078 / 0x37, 0xff, 0xf6, / DELTAF_LSB */
	266	/* 081 / 0x38, 0xff, 0xff, / DELTAF_MSB */
	267	/* 084 / 0x02, 0xff, 0x93, / AGCCONF1 IFS=1 KAGCIF=2 KAGCTUN=3 */
	268	/* 087 / 0x2d, 0xff, 0xf6, / SWEEP SWPOS=1 SWDYN=7 SWSTEP=1 SWLEN=2 */
	269	/* 090 / 0x04, 0x10, 0x00, / SWRAMP=1 */
e7588866 AP	270	/* 093 / 0x12, 0xff, TDA10023_OUTPUT_MODE_PARALLEL_B, /
e7588866 AP	271	INTP1 POCLKP=1 FEL=1 MFS=0 */
4388c3b4 AP	272	/* 096 / 0x2b, 0x01, 0xa1, / INTS1 */
	273	/* 099 / 0x20, 0xff, 0x04, / INTP2 SWAPP=? MSBFIRSTP=? INTPSEL=? */
	274	/* 102 / 0x2c, 0xff, 0x0d, / INTP/S TRIP=0 TRIS=0 */
	275	/* 105 */ 0xc4, 0xff, 0x00,
	276	/* 108 */ 0xc3, 0x30, 0x00,
	277	/* 111 / 0xb5, 0xff, 0x19, / ERAGC_THD */
	278	/* 114 / 0x00, 0x03, 0x01, / GPR, CLBS soft reset */
	279	/* 117 / 0x00, 0x03, 0x03, / GPR, CLBS soft reset */
	280	/* 120 / 0xff, 0x64, 0x00, / Sleep 100ms */
	281	/* 123 */ 0xff, 0xff, 0xff
	282	};
	283	dprintk("DVB: TDA10023(%d): init chip\n", fe->dvb->num);
aa323ac8	284
4388c3b4 AP	285	/* override default values if set in config */
	286	if (state->config->deltaf) {
	287	tda10023_inittab[80] = (state->config->deltaf & 0xff);
	288	tda10023_inittab[83] = (state->config->deltaf >> 8);
	289	}
aa323ac8	290
e7588866 AP	291	if (state->config->output_mode)
	292	tda10023_inittab[95] = state->config->output_mode;
	293
aa323ac8 HB	294	tda10023_writetab(state, tda10023_inittab);
	295
	296	return 0;
	297	}
	298
37c52abd MCC	299	struct qam_params {
	300	u8 qam, lockthr, mseth, aref, agcrefnyq, eragnyq_thd;
	301	};
	302
787d92e1	303	static int tda10023_set_parameters(struct dvb_frontend *fe)
aa323ac8	304	{
74b4576e MCC	305	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
	306	u32 delsys = c->delivery_system;
	307	unsigned qam = c->modulation;
	308	bool is_annex_c;
aa323ac8	309	struct tda10023_state* state = fe->demodulator_priv;
37c52abd MCC	310	static const struct qam_params qam_params[] = {
	311	/* Modulation QAM LOCKTHR MSETH AREF AGCREFNYQ ERAGCNYQ_THD */
	312	[QPSK] = { (5<<2), 0x78, 0x8c, 0x96, 0x78, 0x4c },
	313	[QAM_16] = { (0<<2), 0x87, 0xa2, 0x91, 0x8c, 0x57 },
	314	[QAM_32] = { (1<<2), 0x64, 0x74, 0x96, 0x8c, 0x57 },
	315	[QAM_64] = { (2<<2), 0x46, 0x43, 0x6a, 0x6a, 0x44 },
	316	[QAM_128] = { (3<<2), 0x36, 0x34, 0x7e, 0x78, 0x4c },
	317	[QAM_256] = { (4<<2), 0x26, 0x23, 0x6c, 0x5c, 0x3c },
aa323ac8	318	};
74b4576e MCC	319
	320	switch (delsys) {
	321	case SYS_DVBC_ANNEX_A:
	322	is_annex_c = false;
	323	break;
	324	case SYS_DVBC_ANNEX_C:
	325	is_annex_c = true;
	326	break;
	327	default:
	328	return -EINVAL;
	329	}
37c52abd MCC	330
37c52abd MCC	331	/*
5a13e40b	332	* gcc optimizes the code below the same way as it would code:
37c52abd MCC	333	* "if (qam > 5) return -EINVAL;"
	334	* Yet, the code is clearer, as it shows what QAM standards are
	335	* supported by the driver, and avoids the usage of magic numbers on
	336	* it.
	337	*/
	338	switch (qam) {
	339	case QPSK:
	340	case QAM_16:
	341	case QAM_32:
	342	case QAM_64:
	343	case QAM_128:
	344	case QAM_256:
	345	break;
	346	default:
aa323ac8	347	return -EINVAL;
37c52abd	348	}
aa323ac8 HB	349
aa323ac8 HB	350	if (fe->ops.tuner_ops.set_params) {
14d24d14	351	fe->ops.tuner_ops.set_params(fe);
aa323ac8 HB	352	if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
	353	}
	354
74b4576e	355	tda10023_set_symbolrate(state, c->symbol_rate);
37c52abd MCC	356	tda10023_writereg(state, 0x05, qam_params[qam].lockthr);
	357	tda10023_writereg(state, 0x08, qam_params[qam].mseth);
	358	tda10023_writereg(state, 0x09, qam_params[qam].aref);
	359	tda10023_writereg(state, 0xb4, qam_params[qam].agcrefnyq);
	360	tda10023_writereg(state, 0xb6, qam_params[qam].eragnyq_thd);
37c52abd	361	#if 0
74b4576e MCC	362	tda10023_writereg(state, 0x04, (c->inversion ? 0x12 : 0x32));
74b4576e MCC	363	tda10023_writebit(state, 0x04, 0x60, (c->inversion ? 0 : 0x20));
37c52abd MCC	364	#endif
37c52abd MCC	365	tda10023_writebit(state, 0x04, 0x40, 0x40);
74b4576e MCC	366
	367	if (is_annex_c)
	368	tda10023_writebit(state, 0x3d, 0xfc, 0x03);
	369	else
	370	tda10023_writebit(state, 0x3d, 0xfc, 0x02);
	371
37c52abd	372	tda10023_setup_reg0(state, qam_params[qam].qam);
aa323ac8 HB	373
	374	return 0;
	375	}
	376
0df289a2 MCC	377	static int tda10023_read_status(struct dvb_frontend *fe,
0df289a2 MCC	378	enum fe_status *status)
aa323ac8 HB	379	{
	380	struct tda10023_state* state = fe->demodulator_priv;
	381	int sync;
	382
	383	*status = 0;
	384
	385	//0x11[1] == CARLOCK -> Carrier locked
	386	//0x11[2] == FSYNC -> Frame synchronisation
	387	//0x11[3] == FEL -> Front End locked
	388	//0x11[6] == NODVB -> DVB Mode Information
	389	sync = tda10023_readreg (state, 0x11);
	390
	391	if (sync & 2)
	392	*status \|= FE_HAS_SIGNAL\|FE_HAS_CARRIER;
	393
	394	if (sync & 4)
	395	*status \|= FE_HAS_SYNC\|FE_HAS_VITERBI;
	396
	397	if (sync & 8)
	398	*status \|= FE_HAS_LOCK;
	399
	400	return 0;
	401	}
	402
	403	static int tda10023_read_ber(struct dvb_frontend* fe, u32* ber)
	404	{
	405	struct tda10023_state* state = fe->demodulator_priv;
	406	u8 a,b,c;
	407	a=tda10023_readreg(state, 0x14);
	408	b=tda10023_readreg(state, 0x15);
	409	c=tda10023_readreg(state, 0x16)&0xf;
	410	tda10023_writebit (state, 0x10, 0xc0, 0x00);
	411
	412	*ber = a \| (b<<8)\| (c<<16);
	413	return 0;
	414	}
	415
	416	static int tda10023_read_signal_strength(struct dvb_frontend* fe, u16* strength)
	417	{
	418	struct tda10023_state* state = fe->demodulator_priv;
	419	u8 ifgain=tda10023_readreg(state, 0x2f);
	420
	421	u16 gain = ((255-tda10023_readreg(state, 0x17))) + (255-ifgain)/16;
	422	// Max raw value is about 0xb0 -> Normalize to >0xf0 after 0x90
	423	if (gain>0x90)
	424	gain=gain+2*(gain-0x90);
	425	if (gain>255)
	426	gain=255;
	427
	428	*strength = (gain<<8)\|gain;
	429	return 0;
	430	}
	431
	432	static int tda10023_read_snr(struct dvb_frontend* fe, u16* snr)
	433	{
	434	struct tda10023_state* state = fe->demodulator_priv;
	435
	436	u8 quality = ~tda10023_readreg(state, 0x18);
	437	*snr = (quality << 8) \| quality;
	438	return 0;
	439	}
	440
	441	static int tda10023_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
	442	{
443	struct tda10023_state* state = fe->demodulator_priv;
444	u8 a,b,c,d;
445	a= tda10023_readreg (state, 0x74);
446	b= tda10023_readreg (state, 0x75);
447	c= tda10023_readreg (state, 0x76);
448	d= tda10023_readreg (state, 0x77);
449	*ucblocks = a \| (b<<8)\|(c<<16)\|(d<<24);
450
451	tda10023_writebit (state, 0x10, 0x20,0x00);
452	tda10023_writebit (state, 0x10, 0x20,0x20);
453	tda10023_writebit (state, 0x13, 0x01, 0x00);
454
455	return 0;
456	}
457
7e3e68bc MCC	458	static int tda10023_get_frontend(struct dvb_frontend *fe,
7e3e68bc MCC	459	struct dtv_frontend_properties *p)
aa323ac8 HB	460	{
	461	struct tda10023_state* state = fe->demodulator_priv;
	462	int sync,inv;
	463	s8 afc = 0;
	464
	465	sync = tda10023_readreg(state, 0x11);
	466	afc = tda10023_readreg(state, 0x19);
	467	inv = tda10023_readreg(state, 0x04);
	468
	469	if (verbose) {
	470	/* AFC only valid when carrier has been recovered */
	471	printk(sync & 2 ? "DVB: TDA10023(%d): AFC (%d) %dHz\n" :
	472	"DVB: TDA10023(%d): [AFC (%d) %dHz]\n",
	473	state->frontend.dvb->num, afc,
787d92e1	474	-((s32)p->symbol_rate * afc) >> 10);
aa323ac8 HB	475	}
	476
	477	p->inversion = (inv&0x20?0:1);
787d92e1	478	p->modulation = ((state->reg0 >> 2) & 7) + QAM_16;
aa323ac8	479
787d92e1	480	p->fec_inner = FEC_NONE;
aa323ac8 HB	481	p->frequency = ((p->frequency + 31250) / 62500) * 62500;
	482
	483	if (sync & 2)
787d92e1	484	p->frequency -= ((s32)p->symbol_rate * afc) >> 10;
aa323ac8 HB	485
	486	return 0;
	487	}
	488
	489	static int tda10023_sleep(struct dvb_frontend* fe)
	490	{
	491	struct tda10023_state* state = fe->demodulator_priv;
	492
	493	tda10023_writereg (state, 0x1b, 0x02); /* pdown ADC */
	494	tda10023_writereg (state, 0x00, 0x80); /* standby */
	495
	496	return 0;
	497	}
	498
	499	static int tda10023_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
	500	{
	501	struct tda10023_state* state = fe->demodulator_priv;
	502
	503	if (enable) {
	504	lock_tuner(state);
	505	} else {
	506	unlock_tuner(state);
	507	}
	508	return 0;
	509	}
	510
	511	static void tda10023_release(struct dvb_frontend* fe)
	512	{
	513	struct tda10023_state* state = fe->demodulator_priv;
	514	kfree(state);
	515	}
	516
bd336e63	517	static const struct dvb_frontend_ops tda10023_ops;
aa323ac8	518
4388c3b4 AP	519	struct dvb_frontend tda10023_attach(const struct tda10023_config config,
4388c3b4 AP	520	struct i2c_adapter *i2c,
aa323ac8 HB	521	u8 pwm)
	522	{
	523	struct tda10023_state* state = NULL;
aa323ac8 HB	524
aa323ac8 HB	525	/* allocate memory for the internal state */
c9fa2b1e	526	state = kzalloc(sizeof(struct tda10023_state), GFP_KERNEL);
aa323ac8 HB	527	if (state == NULL) goto error;
	528
	529	/* setup the state */
	530	state->config = config;
	531	state->i2c = i2c;
aa323ac8	532
4388c3b4	533	/* wakeup if in standby */
aa323ac8 HB	534	tda10023_writereg (state, 0x00, 0x33);
	535	/* check if the demod is there */
	536	if ((tda10023_readreg(state, 0x1a) & 0xf0) != 0x70) goto error;
	537
	538	/* create dvb_frontend */
	539	memcpy(&state->frontend.ops, &tda10023_ops, sizeof(struct dvb_frontend_ops));
4388c3b4 AP	540	state->pwm = pwm;
	541	state->reg0 = REG0_INIT_VAL;
	542	if (state->config->xtal) {
	543	state->xtal = state->config->xtal;
	544	state->pll_m = state->config->pll_m;
	545	state->pll_p = state->config->pll_p;
	546	state->pll_n = state->config->pll_n;
	547	} else {
	548	/* set default values if not defined in config */
	549	state->xtal = 28920000;
	550	state->pll_m = 8;
	551	state->pll_p = 4;
	552	state->pll_n = 1;
	553	}
	554
	555	/* calc sysclk */
	556	state->sysclk = (state->xtal * state->pll_m / \
	557	(state->pll_n * state->pll_p));
	558
	559	state->frontend.ops.info.symbol_rate_min = (state->sysclk/2)/64;
	560	state->frontend.ops.info.symbol_rate_max = (state->sysclk/2)/4;
	561
	562	dprintk("DVB: TDA10023 %s: xtal:%d pll_m:%d pll_p:%d pll_n:%d\n",
	563	__func__, state->xtal, state->pll_m, state->pll_p,
	564	state->pll_n);
	565
aa323ac8 HB	566	state->frontend.demodulator_priv = state;
	567	return &state->frontend;
	568
	569	error:
	570	kfree(state);
	571	return NULL;
	572	}
	573
bd336e63	574	static const struct dvb_frontend_ops tda10023_ops = {
787d92e1	575	.delsys = { SYS_DVBC_ANNEX_A, SYS_DVBC_ANNEX_C },
aa323ac8 HB	576	.info = {
aa323ac8 HB	577	.name = "Philips TDA10023 DVB-C",
f1b1eabf MCC	578	.frequency_min_hz = 47 * MHz,
	579	.frequency_max_hz = 862 * MHz,
	580	.frequency_stepsize_hz = 62500,
4388c3b4 AP	581	.symbol_rate_min = 0, /* set in tda10023_attach */
4388c3b4 AP	582	.symbol_rate_max = 0, /* set in tda10023_attach */
aa323ac8 HB	583	.caps = 0x400 \| //FE_CAN_QAM_4
	584	FE_CAN_QAM_16 \| FE_CAN_QAM_32 \| FE_CAN_QAM_64 \|
	585	FE_CAN_QAM_128 \| FE_CAN_QAM_256 \|
	586	FE_CAN_FEC_AUTO
	587	},
	588
	589	.release = tda10023_release,
	590
	591	.init = tda10023_init,
	592	.sleep = tda10023_sleep,
	593	.i2c_gate_ctrl = tda10023_i2c_gate_ctrl,
	594
787d92e1 MCC	595	.set_frontend = tda10023_set_parameters,
787d92e1 MCC	596	.get_frontend = tda10023_get_frontend,
aa323ac8 HB	597	.read_status = tda10023_read_status,
	598	.read_ber = tda10023_read_ber,
	599	.read_signal_strength = tda10023_read_signal_strength,
	600	.read_snr = tda10023_read_snr,
	601	.read_ucblocks = tda10023_read_ucblocks,
	602	};
	603
	604
	605	MODULE_DESCRIPTION("Philips TDA10023 DVB-C demodulator driver");
	606	MODULE_AUTHOR("Georg Acher, Hartmut Birr");
	607	MODULE_LICENSE("GPL");
	608
	609	EXPORT_SYMBOL(tda10023_attach);