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[media] dvb-core: set default properties of ISDB-S
[linux-2.6-block.git] / drivers / media / dvb-frontends / tc90522.c
CommitLineData
f5d82a75
AT		 1/*
2 * Toshiba TC90522 Demodulator
3 *
4 * Copyright (C) 2014 Akihiro Tsukada <tskd08@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17/*
18 * NOTICE:
19 * This driver is incomplete and lacks init/config of the chips,
20 * as the necessary info is not disclosed.
21 * It assumes that users of this driver (such as a PCI bridge of
22 * DTV receiver cards) properly init and configure the chip
23 * via I2C *before* calling this driver's init() function.
24 *
25 * Currently, PT3 driver is the only one that uses this driver,
26 * and contains init/config code in its firmware.
27 * Thus some part of the code might be dependent on PT3 specific config.
28 */
29
30#include <linux/kernel.h>
2ea12442 31#include <linux/math64.h>
f5d82a75
AT		 32#include <linux/dvb/frontend.h>
33#include "dvb_math.h"
34#include "tc90522.h"
35
36#define TC90522_I2C_THRU_REG 0xfe
37
38#define TC90522_MODULE_IDX(addr) (((u8)(addr) & 0x02U) >> 1)
39
40struct tc90522_state {
41 struct tc90522_config cfg;
42 struct dvb_frontend fe;
43 struct i2c_client *i2c_client;
44 struct i2c_adapter tuner_i2c;
45
46 bool lna;
47};
48
49struct reg_val {
50 u8 reg;
51 u8 val;
52};
53
54static int
55reg_write(struct tc90522_state *state, const struct reg_val *regs, int num)
56{
57 int i, ret;
58 struct i2c_msg msg;
59
60 ret = 0;
61 msg.addr = state->i2c_client->addr;
62 msg.flags = 0;
63 msg.len = 2;
64 for (i = 0; i < num; i++) {
65 msg.buf = (u8 *)&regs[i];
66 ret = i2c_transfer(state->i2c_client->adapter, &msg, 1);
67 if (ret == 0)
68 ret = -EIO;
69 if (ret < 0)
70 return ret;
71 }
72 return 0;
73}
74
75static int reg_read(struct tc90522_state *state, u8 reg, u8 *val, u8 len)
76{
77 struct i2c_msg msgs[2] = {
78 {
79 .addr = state->i2c_client->addr,
80 .flags = 0,
81 .buf = &reg,
82 .len = 1,
83 },
84 {
85 .addr = state->i2c_client->addr,
86 .flags = I2C_M_RD,
87 .buf = val,
88 .len = len,
89 },
90 };
91 int ret;
92
93 ret = i2c_transfer(state->i2c_client->adapter, msgs, ARRAY_SIZE(msgs));
94 if (ret == ARRAY_SIZE(msgs))
95 ret = 0;
96 else if (ret >= 0)
97 ret = -EIO;
98 return ret;
99}
100
101static struct tc90522_state *cfg_to_state(struct tc90522_config *c)
102{
103 return container_of(c, struct tc90522_state, cfg);
104}
105
106
107static int tc90522s_set_tsid(struct dvb_frontend *fe)
108{
109 struct reg_val set_tsid[] = {
110 { 0x8f, 00 },
111 { 0x90, 00 }
112 };
113
114 set_tsid[0].val = (fe->dtv_property_cache.stream_id & 0xff00) >> 8;
115 set_tsid[1].val = fe->dtv_property_cache.stream_id & 0xff;
116 return reg_write(fe->demodulator_priv, set_tsid, ARRAY_SIZE(set_tsid));
117}
118
119static int tc90522t_set_layers(struct dvb_frontend *fe)
120{
121 struct reg_val rv;
122 u8 laysel;
123
124 laysel = ~fe->dtv_property_cache.isdbt_layer_enabled & 0x07;
125 laysel = (laysel & 0x01) << 2 | (laysel & 0x02) | (laysel & 0x04) >> 2;
126 rv.reg = 0x71;
127 rv.val = laysel;
128 return reg_write(fe->demodulator_priv, &rv, 1);
129}
130
131/* frontend ops */
132
133static int tc90522s_read_status(struct dvb_frontend *fe, fe_status_t *status)
134{
135 struct tc90522_state *state;
136 int ret;
137 u8 reg;
138
139 state = fe->demodulator_priv;
140 ret = reg_read(state, 0xc3, &reg, 1);
141 if (ret < 0)
142 return ret;
143
144 *status = 0;
145 if (reg & 0x80) /* input level under min ? */
146 return 0;
147 *status |= FE_HAS_SIGNAL;
148
149 if (reg & 0x60) /* carrier? */
150 return 0;
151 *status |= FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC;
152
153 if (reg & 0x10)
154 return 0;
155 if (reg_read(state, 0xc5, &reg, 1) < 0 || !(reg & 0x03))
156 return 0;
157 *status |= FE_HAS_LOCK;
158 return 0;
159}
160
161static int tc90522t_read_status(struct dvb_frontend *fe, fe_status_t *status)
162{
163 struct tc90522_state *state;
164 int ret;
165 u8 reg;
166
167 state = fe->demodulator_priv;
168 ret = reg_read(state, 0x96, &reg, 1);
169 if (ret < 0)
170 return ret;
171
172 *status = 0;
173 if (reg & 0xe0) {
174 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI
175 | FE_HAS_SYNC | FE_HAS_LOCK;
176 return 0;
177 }
178
179 ret = reg_read(state, 0x80, &reg, 1);
180 if (ret < 0)
181 return ret;
182
183 if (reg & 0xf0)
184 return 0;
185 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
186
187 if (reg & 0x0c)
188 return 0;
189 *status |= FE_HAS_SYNC | FE_HAS_VITERBI;
190
191 if (reg & 0x02)
192 return 0;
193 *status |= FE_HAS_LOCK;
194 return 0;
195}
196
197static const fe_code_rate_t fec_conv_sat[] = {
198 FEC_NONE, /* unused */
199 FEC_1_2, /* for BPSK */
200 FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_7_8, /* for QPSK */
201 FEC_2_3, /* for 8PSK. (trellis code) */
202};
203
204static int tc90522s_get_frontend(struct dvb_frontend *fe)
205{
206 struct tc90522_state *state;
207 struct dtv_frontend_properties *c;
208 struct dtv_fe_stats *stats;
209 int ret, i;
210 int layers;
211 u8 val[10];
212 u32 cndat;
213
214 state = fe->demodulator_priv;
215 c = &fe->dtv_property_cache;
216 c->delivery_system = SYS_ISDBS;
217
218 layers = 0;
906aaf5a 219 ret = reg_read(state, 0xe6, val, 5);
f5d82a75 220 if (ret == 0) {
f5d82a75
AT		 221 u8 v;
222
906aaf5a
AT		 223 c->stream_id = val[0] << 8 | val[1];
224
f5d82a75 225 /* high/single layer */
906aaf5a 226 v = (val[2] & 0x70) >> 4;
f5d82a75
AT		 227 c->modulation = (v == 7) ? PSK_8 : QPSK;
228 c->fec_inner = fec_conv_sat[v];
229 c->layer[0].fec = c->fec_inner;
230 c->layer[0].modulation = c->modulation;
906aaf5a 231 c->layer[0].segment_count = val[3] & 0x3f; /* slots */
f5d82a75
AT		 232
233 /* low layer */
906aaf5a 234 v = (val[2] & 0x07);
f5d82a75
AT		 235 c->layer[1].fec = fec_conv_sat[v];
236 if (v == 0) /* no low layer */
237 c->layer[1].segment_count = 0;
238 else
906aaf5a 239 c->layer[1].segment_count = val[4] & 0x3f; /* slots */
f5d82a75
AT		 240 /* actually, BPSK if v==1, but not defined in fe_modulation_t */
241 c->layer[1].modulation = QPSK;
242 layers = (v > 0) ? 2 : 1;
f5d82a75
AT		 243 }
244
245 /* statistics */
246
247 stats = &c->strength;
248 stats->len = 0;
249 /* let the connected tuner set RSSI property cache */
250 if (fe->ops.tuner_ops.get_rf_strength) {
251 u16 dummy;
252
253 fe->ops.tuner_ops.get_rf_strength(fe, &dummy);
254 }
255
256 stats = &c->cnr;
257 stats->len = 1;
258 stats->stat[0].scale = FE_SCALE_NOT_AVAILABLE;
259 cndat = 0;
260 ret = reg_read(state, 0xbc, val, 2);
261 if (ret == 0)
262 cndat = val[0] << 8 | val[1];
263 if (cndat >= 3000) {
264 u32 p, p4;
265 s64 cn;
266
267 cndat -= 3000; /* cndat: 4.12 fixed point float */
268 /*
269 * cnr[mdB] = -1634.6 * P^5 + 14341 * P^4 - 50259 * P^3
270 * + 88977 * P^2 - 89565 * P + 58857
271 * (P = sqrt(cndat) / 64)
272 */
273 /* p := sqrt(cndat) << 8 = P << 14, 2.14 fixed point float */
274 /* cn = cnr << 3 */
275 p = int_sqrt(cndat << 16);
276 p4 = cndat * cndat;
2ea12442 277 cn = div64_s64(-16346LL * p4 * p, 10) >> 35;
f5d82a75
AT		 278 cn += (14341LL * p4) >> 21;
279 cn -= (50259LL * cndat * p) >> 23;
280 cn += (88977LL * cndat) >> 9;
281 cn -= (89565LL * p) >> 11;
282 cn += 58857 << 3;
283 stats->stat[0].svalue = cn >> 3;
284 stats->stat[0].scale = FE_SCALE_DECIBEL;
285 }
286
287 /* per-layer post viterbi BER (or PER? config dependent?) */
288 stats = &c->post_bit_error;
289 memset(stats, 0, sizeof(*stats));
290 stats->len = layers;
291 ret = reg_read(state, 0xeb, val, 10);
292 if (ret < 0)
293 for (i = 0; i < layers; i++)
294 stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE;
295 else {
296 for (i = 0; i < layers; i++) {
297 stats->stat[i].scale = FE_SCALE_COUNTER;
298 stats->stat[i].uvalue = val[i * 5] << 16
299 | val[i * 5 + 1] << 8 | val[i * 5 + 2];
300 }
301 }
302 stats = &c->post_bit_count;
303 memset(stats, 0, sizeof(*stats));
304 stats->len = layers;
305 if (ret < 0)
306 for (i = 0; i < layers; i++)
307 stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE;
308 else {
309 for (i = 0; i < layers; i++) {
310 stats->stat[i].scale = FE_SCALE_COUNTER;
311 stats->stat[i].uvalue =
312 val[i * 5 + 3] << 8 | val[i * 5 + 4];
313 stats->stat[i].uvalue *= 204 * 8;
314 }
315 }
316
317 return 0;
318}
319
320
321static const fe_transmit_mode_t tm_conv[] = {
322 TRANSMISSION_MODE_2K,
323 TRANSMISSION_MODE_4K,
324 TRANSMISSION_MODE_8K,
325 0
326};
327
328static const fe_code_rate_t fec_conv_ter[] = {
329 FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_7_8, 0, 0, 0
330};
331
332static const fe_modulation_t mod_conv[] = {
333 DQPSK, QPSK, QAM_16, QAM_64, 0, 0, 0, 0
334};
335
336static int tc90522t_get_frontend(struct dvb_frontend *fe)
337{
338 struct tc90522_state *state;
339 struct dtv_frontend_properties *c;
340 struct dtv_fe_stats *stats;
341 int ret, i;
342 int layers;
343 u8 val[15], mode;
344 u32 cndat;
345
346 state = fe->demodulator_priv;
347 c = &fe->dtv_property_cache;
348 c->delivery_system = SYS_ISDBT;
349 c->bandwidth_hz = 6000000;
350 mode = 1;
351 ret = reg_read(state, 0xb0, val, 1);
352 if (ret == 0) {
353 mode = (val[0] & 0xc0) >> 2;
354 c->transmission_mode = tm_conv[mode];
355 c->guard_interval = (val[0] & 0x30) >> 4;
356 }
357
358 ret = reg_read(state, 0xb2, val, 6);
359 layers = 0;
360 if (ret == 0) {
361 u8 v;
362
363 c->isdbt_partial_reception = val[0] & 0x01;
364 c->isdbt_sb_mode = (val[0] & 0xc0) == 0x01;
365
366 /* layer A */
367 v = (val[2] & 0x78) >> 3;
368 if (v == 0x0f)
369 c->layer[0].segment_count = 0;
370 else {
371 layers++;
372 c->layer[0].segment_count = v;
373 c->layer[0].fec = fec_conv_ter[(val[1] & 0x1c) >> 2];
374 c->layer[0].modulation = mod_conv[(val[1] & 0xe0) >> 5];
375 v = (val[1] & 0x03) << 1 | (val[2] & 0x80) >> 7;
376 c->layer[0].interleaving = v;
377 }
378
379 /* layer B */
380 v = (val[3] & 0x03) << 1 | (val[4] & 0xc0) >> 6;
381 if (v == 0x0f)
382 c->layer[1].segment_count = 0;
383 else {
384 layers++;
385 c->layer[1].segment_count = v;
386 c->layer[1].fec = fec_conv_ter[(val[3] & 0xe0) >> 5];
387 c->layer[1].modulation = mod_conv[(val[2] & 0x07)];
388 c->layer[1].interleaving = (val[3] & 0x1c) >> 2;
389 }
390
391 /* layer C */
392 v = (val[5] & 0x1e) >> 1;
393 if (v == 0x0f)
394 c->layer[2].segment_count = 0;
395 else {
396 layers++;
397 c->layer[2].segment_count = v;
398 c->layer[2].fec = fec_conv_ter[(val[4] & 0x07)];
399 c->layer[2].modulation = mod_conv[(val[4] & 0x38) >> 3];
400 c->layer[2].interleaving = (val[5] & 0xe0) >> 5;
401 }
402 }
403
404 /* statistics */
405
406 stats = &c->strength;
407 stats->len = 0;
408 /* let the connected tuner set RSSI property cache */
409 if (fe->ops.tuner_ops.get_rf_strength) {
410 u16 dummy;
411
412 fe->ops.tuner_ops.get_rf_strength(fe, &dummy);
413 }
414
415 stats = &c->cnr;
416 stats->len = 1;
417 stats->stat[0].scale = FE_SCALE_NOT_AVAILABLE;
418 cndat = 0;
419 ret = reg_read(state, 0x8b, val, 3);
420 if (ret == 0)
421 cndat = val[0] << 16 | val[1] << 8 | val[2];
422 if (cndat != 0) {
423 u32 p, tmp;
424 s64 cn;
425
426 /*
427 * cnr[mdB] = 0.024 P^4 - 1.6 P^3 + 39.8 P^2 + 549.1 P + 3096.5
428 * (P = 10log10(5505024/cndat))
429 */
430 /* cn = cnr << 3 (61.3 fixed point float */
431 /* p = 10log10(5505024/cndat) << 24 (8.24 fixed point float)*/
432 p = intlog10(5505024) - intlog10(cndat);
433 p *= 10;
434
435 cn = 24772;
2ea12442 436 cn += div64_s64(43827LL * p, 10) >> 24;
f5d82a75 437 tmp = p >> 8;
2ea12442 438 cn += div64_s64(3184LL * tmp * tmp, 10) >> 32;
f5d82a75 439 tmp = p >> 13;
2ea12442 440 cn -= div64_s64(128LL * tmp * tmp * tmp, 10) >> 33;
f5d82a75 441 tmp = p >> 18;
2ea12442 442 cn += div64_s64(192LL * tmp * tmp * tmp * tmp, 1000) >> 24;
f5d82a75
AT		 443
444 stats->stat[0].svalue = cn >> 3;
445 stats->stat[0].scale = FE_SCALE_DECIBEL;
446 }
447
448 /* per-layer post viterbi BER (or PER? config dependent?) */
449 stats = &c->post_bit_error;
450 memset(stats, 0, sizeof(*stats));
451 stats->len = layers;
452 ret = reg_read(state, 0x9d, val, 15);
453 if (ret < 0)
454 for (i = 0; i < layers; i++)
455 stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE;
456 else {
457 for (i = 0; i < layers; i++) {
458 stats->stat[i].scale = FE_SCALE_COUNTER;
459 stats->stat[i].uvalue = val[i * 3] << 16
460 | val[i * 3 + 1] << 8 | val[i * 3 + 2];
461 }
462 }
463 stats = &c->post_bit_count;
464 memset(stats, 0, sizeof(*stats));
465 stats->len = layers;
466 if (ret < 0)
467 for (i = 0; i < layers; i++)
468 stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE;
469 else {
470 for (i = 0; i < layers; i++) {
471 stats->stat[i].scale = FE_SCALE_COUNTER;
472 stats->stat[i].uvalue =
473 val[9 + i * 2] << 8 | val[9 + i * 2 + 1];
474 stats->stat[i].uvalue *= 204 * 8;
475 }
476 }
477
478 return 0;
479}
480
481static const struct reg_val reset_sat = { 0x03, 0x01 };
482static const struct reg_val reset_ter = { 0x01, 0x40 };
483
484static int tc90522_set_frontend(struct dvb_frontend *fe)
485{
486 struct tc90522_state *state;
487 int ret;
488
489 state = fe->demodulator_priv;
490
491 if (fe->ops.tuner_ops.set_params)
492 ret = fe->ops.tuner_ops.set_params(fe);
493 else
494 ret = -ENODEV;
495 if (ret < 0)
496 goto failed;
497
498 if (fe->ops.delsys[0] == SYS_ISDBS) {
499 ret = tc90522s_set_tsid(fe);
500 if (ret < 0)
501 goto failed;
502 ret = reg_write(state, &reset_sat, 1);
503 } else {
504 ret = tc90522t_set_layers(fe);
505 if (ret < 0)
506 goto failed;
507 ret = reg_write(state, &reset_ter, 1);
508 }
509 if (ret < 0)
510 goto failed;
511
512 return 0;
513
514failed:
515 dev_warn(&state->tuner_i2c.dev, "(%s) failed. [adap%d-fe%d]\n",
516 __func__, fe->dvb->num, fe->id);
517 return ret;
518}
519
520static int tc90522_get_tune_settings(struct dvb_frontend *fe,
521 struct dvb_frontend_tune_settings *settings)
522{
523 if (fe->ops.delsys[0] == SYS_ISDBS) {
524 settings->min_delay_ms = 250;
525 settings->step_size = 1000;
526 settings->max_drift = settings->step_size * 2;
527 } else {
528 settings->min_delay_ms = 400;
529 settings->step_size = 142857;
530 settings->max_drift = settings->step_size;
531 }
532 return 0;
533}
534
535static int tc90522_set_if_agc(struct dvb_frontend *fe, bool on)
536{
537 struct reg_val agc_sat[] = {
538 { 0x0a, 0x00 },
539 { 0x10, 0x30 },
540 { 0x11, 0x00 },
541 { 0x03, 0x01 },
542 };
543 struct reg_val agc_ter[] = {
544 { 0x25, 0x00 },
545 { 0x23, 0x4c },
546 { 0x01, 0x40 },
547 };
548 struct tc90522_state *state;
549 struct reg_val *rv;
550 int num;
551
552 state = fe->demodulator_priv;
553 if (fe->ops.delsys[0] == SYS_ISDBS) {
554 agc_sat[0].val = on ? 0xff : 0x00;
555 agc_sat[1].val |= 0x80;
556 agc_sat[1].val |= on ? 0x01 : 0x00;
557 agc_sat[2].val |= on ? 0x40 : 0x00;
558 rv = agc_sat;
559 num = ARRAY_SIZE(agc_sat);
560 } else {
561 agc_ter[0].val = on ? 0x40 : 0x00;
562 agc_ter[1].val |= on ? 0x00 : 0x01;
563 rv = agc_ter;
564 num = ARRAY_SIZE(agc_ter);
565 }
566 return reg_write(state, rv, num);
567}
568
569static const struct reg_val sleep_sat = { 0x17, 0x01 };
570static const struct reg_val sleep_ter = { 0x03, 0x90 };
571
572static int tc90522_sleep(struct dvb_frontend *fe)
573{
574 struct tc90522_state *state;
575 int ret;
576
577 state = fe->demodulator_priv;
578 if (fe->ops.delsys[0] == SYS_ISDBS)
579 ret = reg_write(state, &sleep_sat, 1);
580 else {
581 ret = reg_write(state, &sleep_ter, 1);
582 if (ret == 0 && fe->ops.set_lna &&
583 fe->dtv_property_cache.lna == LNA_AUTO) {
584 fe->dtv_property_cache.lna = 0;
585 ret = fe->ops.set_lna(fe);
586 fe->dtv_property_cache.lna = LNA_AUTO;
587 }
588 }
589 if (ret < 0)
590 dev_warn(&state->tuner_i2c.dev,
591 "(%s) failed. [adap%d-fe%d]\n",
592 __func__, fe->dvb->num, fe->id);
593 return ret;
594}
595
596static const struct reg_val wakeup_sat = { 0x17, 0x00 };
597static const struct reg_val wakeup_ter = { 0x03, 0x80 };
598
599static int tc90522_init(struct dvb_frontend *fe)
600{
601 struct tc90522_state *state;
602 int ret;
603
604 /*
605 * Because the init sequence is not public,
606 * the parent device/driver should have init'ed the device before.
607 * just wake up the device here.
608 */
609
610 state = fe->demodulator_priv;
611 if (fe->ops.delsys[0] == SYS_ISDBS)
612 ret = reg_write(state, &wakeup_sat, 1);
613 else {
614 ret = reg_write(state, &wakeup_ter, 1);
615 if (ret == 0 && fe->ops.set_lna &&
616 fe->dtv_property_cache.lna == LNA_AUTO) {
617 fe->dtv_property_cache.lna = 1;
618 ret = fe->ops.set_lna(fe);
619 fe->dtv_property_cache.lna = LNA_AUTO;
620 }
621 }
622 if (ret < 0) {
623 dev_warn(&state->tuner_i2c.dev,
624 "(%s) failed. [adap%d-fe%d]\n",
625 __func__, fe->dvb->num, fe->id);
626 return ret;
627 }
628
629 /* prefer 'all-layers' to 'none' as a default */
630 if (fe->dtv_property_cache.isdbt_layer_enabled == 0)
631 fe->dtv_property_cache.isdbt_layer_enabled = 7;
632 return tc90522_set_if_agc(fe, true);
633}
634
635
636/*
637 * tuner I2C adapter functions
638 */
639
640static int
641tc90522_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
642{
643 struct tc90522_state *state;
644 struct i2c_msg *new_msgs;
645 int i, j;
646 int ret, rd_num;
647 u8 wbuf[256];
648 u8 *p, *bufend;
649
650 if (num <= 0)
651 return -EINVAL;
652
653 rd_num = 0;
654 for (i = 0; i < num; i++)
655 if (msgs[i].flags & I2C_M_RD)
656 rd_num++;
657 new_msgs = kmalloc(sizeof(*new_msgs) * (num + rd_num), GFP_KERNEL);
658 if (!new_msgs)
659 return -ENOMEM;
660
661 state = i2c_get_adapdata(adap);
662 p = wbuf;
663 bufend = wbuf + sizeof(wbuf);
664 for (i = 0, j = 0; i < num; i++, j++) {
665 new_msgs[j].addr = state->i2c_client->addr;
666 new_msgs[j].flags = msgs[i].flags;
667
668 if (msgs[i].flags & I2C_M_RD) {
669 new_msgs[j].flags &= ~I2C_M_RD;
670 if (p + 2 > bufend)
671 break;
672 p[0] = TC90522_I2C_THRU_REG;
673 p[1] = msgs[i].addr << 1 | 0x01;
674 new_msgs[j].buf = p;
675 new_msgs[j].len = 2;
676 p += 2;
677 j++;
678 new_msgs[j].addr = state->i2c_client->addr;
679 new_msgs[j].flags = msgs[i].flags;
680 new_msgs[j].buf = msgs[i].buf;
681 new_msgs[j].len = msgs[i].len;
682 continue;
683 }
684
685 if (p + msgs[i].len + 2 > bufend)
686 break;
687 p[0] = TC90522_I2C_THRU_REG;
688 p[1] = msgs[i].addr << 1;
689 memcpy(p + 2, msgs[i].buf, msgs[i].len);
690 new_msgs[j].buf = p;
691 new_msgs[j].len = msgs[i].len + 2;
692 p += new_msgs[j].len;
693 }
694
695 if (i < num)
696 ret = -ENOMEM;
697 else
698 ret = i2c_transfer(state->i2c_client->adapter, new_msgs, j);
699 if (ret >= 0 && ret < j)
700 ret = -EIO;
701 kfree(new_msgs);
702 return (ret == j) ? num : ret;
703}
704
70dc5363 705static u32 tc90522_functionality(struct i2c_adapter *adap)
f5d82a75
AT		 706{
707 return I2C_FUNC_I2C;
708}
709
710static const struct i2c_algorithm tc90522_tuner_i2c_algo = {
711 .master_xfer = &tc90522_master_xfer,
712 .functionality = &tc90522_functionality,
713};
714
715
716/*
717 * I2C driver functions
718 */
719
720static const struct dvb_frontend_ops tc90522_ops_sat = {
721 .delsys = { SYS_ISDBS },
722 .info = {
723 .name = "Toshiba TC90522 ISDB-S module",
724 .frequency_min = 950000,
725 .frequency_max = 2150000,
726 .caps = FE_CAN_INVERSION_AUTO | FE_CAN_FEC_AUTO |
727 FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
728 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
729 },
730
731 .init = tc90522_init,
732 .sleep = tc90522_sleep,
733 .set_frontend = tc90522_set_frontend,
734 .get_tune_settings = tc90522_get_tune_settings,
735
736 .get_frontend = tc90522s_get_frontend,
737 .read_status = tc90522s_read_status,
738};
739
740static const struct dvb_frontend_ops tc90522_ops_ter = {
741 .delsys = { SYS_ISDBT },
742 .info = {
743 .name = "Toshiba TC90522 ISDB-T module",
744 .frequency_min = 470000000,
745 .frequency_max = 770000000,
746 .frequency_stepsize = 142857,
747 .caps = FE_CAN_INVERSION_AUTO |
748 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
749 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
750 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
751 FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
752 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER |
753 FE_CAN_HIERARCHY_AUTO,
754 },
755
756 .init = tc90522_init,
757 .sleep = tc90522_sleep,
758 .set_frontend = tc90522_set_frontend,
759 .get_tune_settings = tc90522_get_tune_settings,
760
761 .get_frontend = tc90522t_get_frontend,
762 .read_status = tc90522t_read_status,
763};
764
765
766static int tc90522_probe(struct i2c_client *client,
767 const struct i2c_device_id *id)
768{
769 struct tc90522_state *state;
770 struct tc90522_config *cfg;
771 const struct dvb_frontend_ops *ops;
772 struct i2c_adapter *adap;
773 int ret;
774
775 state = kzalloc(sizeof(*state), GFP_KERNEL);
776 if (!state)
777 return -ENOMEM;
778 state->i2c_client = client;
779
780 cfg = client->dev.platform_data;
781 memcpy(&state->cfg, cfg, sizeof(state->cfg));
782 cfg->fe = state->cfg.fe = &state->fe;
783 ops = id->driver_data == 0 ? &tc90522_ops_sat : &tc90522_ops_ter;
784 memcpy(&state->fe.ops, ops, sizeof(*ops));
785 state->fe.demodulator_priv = state;
786
787 adap = &state->tuner_i2c;
788 adap->owner = THIS_MODULE;
789 adap->algo = &tc90522_tuner_i2c_algo;
790 adap->dev.parent = &client->dev;
791 strlcpy(adap->name, "tc90522_sub", sizeof(adap->name));
792 i2c_set_adapdata(adap, state);
793 ret = i2c_add_adapter(adap);
794 if (ret < 0)
795 goto err;
796 cfg->tuner_i2c = state->cfg.tuner_i2c = adap;
797
798 i2c_set_clientdata(client, &state->cfg);
799 dev_info(&client->dev, "Toshiba TC90522 attached.\n");
800 return 0;
801
802err:
803 kfree(state);
804 return ret;
805}
806
807static int tc90522_remove(struct i2c_client *client)
808{
809 struct tc90522_state *state;
810
811 state = cfg_to_state(i2c_get_clientdata(client));
812 i2c_del_adapter(&state->tuner_i2c);
813 kfree(state);
814 return 0;
815}
816
817
818static const struct i2c_device_id tc90522_id[] = {
819 { TC90522_I2C_DEV_SAT, 0 },
820 { TC90522_I2C_DEV_TER, 1 },
821 {}
822};
823MODULE_DEVICE_TABLE(i2c, tc90522_id);
824
825static struct i2c_driver tc90522_driver = {
826 .driver = {
827 .name = "tc90522",
828 },
829 .probe = tc90522_probe,
830 .remove = tc90522_remove,
831 .id_table = tc90522_id,
832};
833
834module_i2c_driver(tc90522_driver);
835
836MODULE_DESCRIPTION("Toshiba TC90522 frontend");
837MODULE_AUTHOR("Akihiro TSUKADA");
838MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)