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media: move dvb kAPI headers to include/media
[linux-2.6-block.git] / drivers / media / dvb-frontends / stv0910.c
CommitLineData
cd21b334
DS		 1/*
2 * Driver for the ST STV0910 DVB-S/S2 demodulator.
3 *
4 * Copyright (C) 2014-2015 Ralph Metzler <rjkm@metzlerbros.de>
5 * Marcus Metzler <mocm@metzlerbros.de>
6 * developed for Digital Devices GmbH
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 only, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/init.h>
22#include <linux/delay.h>
23#include <linux/firmware.h>
24#include <linux/i2c.h>
25#include <asm/div64.h>
26
fada1935 27#include <media/dvb_frontend.h>
cd21b334
DS		 28#include "stv0910.h"
29#include "stv0910_regs.h"
30
31#define EXT_CLOCK 30000000
32#define TUNING_DELAY 200
33#define BER_SRC_S 0x20
34#define BER_SRC_S2 0x20
35
c16ad5de 36static LIST_HEAD(stvlist);
cd21b334
DS		 37
38enum receive_mode { RCVMODE_NONE, RCVMODE_DVBS, RCVMODE_DVBS2, RCVMODE_AUTO };
39
40enum dvbs2_fectype { DVBS2_64K, DVBS2_16K };
41
42enum dvbs2_mod_cod {
43 DVBS2_DUMMY_PLF, DVBS2_QPSK_1_4, DVBS2_QPSK_1_3, DVBS2_QPSK_2_5,
44 DVBS2_QPSK_1_2, DVBS2_QPSK_3_5, DVBS2_QPSK_2_3, DVBS2_QPSK_3_4,
45 DVBS2_QPSK_4_5, DVBS2_QPSK_5_6, DVBS2_QPSK_8_9, DVBS2_QPSK_9_10,
46 DVBS2_8PSK_3_5, DVBS2_8PSK_2_3, DVBS2_8PSK_3_4, DVBS2_8PSK_5_6,
47 DVBS2_8PSK_8_9, DVBS2_8PSK_9_10, DVBS2_16APSK_2_3, DVBS2_16APSK_3_4,
48 DVBS2_16APSK_4_5, DVBS2_16APSK_5_6, DVBS2_16APSK_8_9, DVBS2_16APSK_9_10,
49 DVBS2_32APSK_3_4, DVBS2_32APSK_4_5, DVBS2_32APSK_5_6, DVBS2_32APSK_8_9,
50 DVBS2_32APSK_9_10
51};
52
53enum fe_stv0910_mod_cod {
54 FE_DUMMY_PLF, FE_QPSK_14, FE_QPSK_13, FE_QPSK_25,
55 FE_QPSK_12, FE_QPSK_35, FE_QPSK_23, FE_QPSK_34,
56 FE_QPSK_45, FE_QPSK_56, FE_QPSK_89, FE_QPSK_910,
57 FE_8PSK_35, FE_8PSK_23, FE_8PSK_34, FE_8PSK_56,
58 FE_8PSK_89, FE_8PSK_910, FE_16APSK_23, FE_16APSK_34,
59 FE_16APSK_45, FE_16APSK_56, FE_16APSK_89, FE_16APSK_910,
60 FE_32APSK_34, FE_32APSK_45, FE_32APSK_56, FE_32APSK_89,
61 FE_32APSK_910
62};
63
64enum fe_stv0910_roll_off { FE_SAT_35, FE_SAT_25, FE_SAT_20, FE_SAT_15 };
65
66static inline u32 muldiv32(u32 a, u32 b, u32 c)
67{
68 u64 tmp64;
69
70 tmp64 = (u64)a * (u64)b;
71 do_div(tmp64, c);
72
ddb6a90d 73 return (u32)tmp64;
cd21b334
DS		 74}
75
76struct stv_base {
77 struct list_head stvlist;
78
79 u8 adr;
80 struct i2c_adapter *i2c;
ddb6a90d
DS		 81 struct mutex i2c_lock; /* shared I2C access protect */
82 struct mutex reg_lock; /* shared register write protect */
cd21b334
DS		 83 int count;
84
85 u32 extclk;
86 u32 mclk;
87};
88
89struct stv {
90 struct stv_base *base;
91 struct dvb_frontend fe;
92 int nr;
93 u16 regoff;
94 u8 i2crpt;
95 u8 tscfgh;
96 u8 tsgeneral;
97 u8 tsspeed;
98 u8 single;
99 unsigned long tune_time;
100
101 s32 search_range;
102 u32 started;
103 u32 demod_lock_time;
104 enum receive_mode receive_mode;
105 u32 demod_timeout;
106 u32 fec_timeout;
107 u32 first_time_lock;
108 u8 demod_bits;
109 u32 symbol_rate;
110
111 u8 last_viterbi_rate;
112 enum fe_code_rate puncture_rate;
113 enum fe_stv0910_mod_cod mod_cod;
114 enum dvbs2_fectype fectype;
115 u32 pilots;
116 enum fe_stv0910_roll_off feroll_off;
117
118 int is_standard_broadcast;
119 int is_vcm;
120
ea71c62b
DS		 121 u32 cur_scrambling_code;
122
cd21b334
DS		 123 u32 last_bernumerator;
124 u32 last_berdenominator;
125 u8 berscale;
126
127 u8 vth[6];
128};
129
130struct sinit_table {
131 u16 address;
132 u8 data;
133};
134
135struct slookup {
136 s16 value;
19bb3b71 137 u32 reg_value;
cd21b334
DS		 138};
139
140static inline int i2c_write(struct i2c_adapter *adap, u8 adr,
141 u8 *data, int len)
142{
143 struct i2c_msg msg = {.addr = adr, .flags = 0,
144 .buf = data, .len = len};
145
146 if (i2c_transfer(adap, &msg, 1) != 1) {
147 dev_warn(&adap->dev, "i2c write error ([%02x] %04x: %02x)\n",
ddb6a90d
DS		 148 adr, (data[0] << 8) | data[1],
149 (len > 2 ? data[2] : 0));
cd21b334
DS		 150 return -EREMOTEIO;
151 }
152 return 0;
153}
154
155static int i2c_write_reg16(struct i2c_adapter *adap, u8 adr, u16 reg, u8 val)
156{
157 u8 msg[3] = {reg >> 8, reg & 0xff, val};
158
159 return i2c_write(adap, adr, msg, 3);
160}
161
162static int write_reg(struct stv *state, u16 reg, u8 val)
163{
164 return i2c_write_reg16(state->base->i2c, state->base->adr, reg, val);
165}
166
167static inline int i2c_read_regs16(struct i2c_adapter *adapter, u8 adr,
ddb6a90d 168 u16 reg, u8 *val, int count)
cd21b334
DS		 169{
170 u8 msg[2] = {reg >> 8, reg & 0xff};
171 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
172 .buf = msg, .len = 2},
173 {.addr = adr, .flags = I2C_M_RD,
174 .buf = val, .len = count } };
175
176 if (i2c_transfer(adapter, msgs, 2) != 2) {
177 dev_warn(&adapter->dev, "i2c read error ([%02x] %04x)\n",
ddb6a90d 178 adr, reg);
cd21b334
DS		 179 return -EREMOTEIO;
180 }
181 return 0;
182}
183
184static int read_reg(struct stv *state, u16 reg, u8 *val)
185{
186 return i2c_read_regs16(state->base->i2c, state->base->adr,
ddb6a90d 187 reg, val, 1);
cd21b334
DS		 188}
189
190static int read_regs(struct stv *state, u16 reg, u8 *val, int len)
191{
192 return i2c_read_regs16(state->base->i2c, state->base->adr,
193 reg, val, len);
194}
195
196static int write_shared_reg(struct stv *state, u16 reg, u8 mask, u8 val)
197{
198 int status;
199 u8 tmp;
200
201 mutex_lock(&state->base->reg_lock);
202 status = read_reg(state, reg, &tmp);
203 if (!status)
204 status = write_reg(state, reg, (tmp & ~mask) | (val & mask));
205 mutex_unlock(&state->base->reg_lock);
206 return status;
207}
208
20e671df 209static const struct slookup s1_sn_lookup[] = {
4f979d5c
DS		 210 { 0, 9242 }, /* C/N= 0dB */
211 { 5, 9105 }, /* C/N= 0.5dB */
212 { 10, 8950 }, /* C/N= 1.0dB */
213 { 15, 8780 }, /* C/N= 1.5dB */
214 { 20, 8566 }, /* C/N= 2.0dB */
215 { 25, 8366 }, /* C/N= 2.5dB */
216 { 30, 8146 }, /* C/N= 3.0dB */
217 { 35, 7908 }, /* C/N= 3.5dB */
218 { 40, 7666 }, /* C/N= 4.0dB */
219 { 45, 7405 }, /* C/N= 4.5dB */
220 { 50, 7136 }, /* C/N= 5.0dB */
221 { 55, 6861 }, /* C/N= 5.5dB */
222 { 60, 6576 }, /* C/N= 6.0dB */
223 { 65, 6330 }, /* C/N= 6.5dB */
224 { 70, 6048 }, /* C/N= 7.0dB */
225 { 75, 5768 }, /* C/N= 7.5dB */
226 { 80, 5492 }, /* C/N= 8.0dB */
227 { 85, 5224 }, /* C/N= 8.5dB */
228 { 90, 4959 }, /* C/N= 9.0dB */
229 { 95, 4709 }, /* C/N= 9.5dB */
230 { 100, 4467 }, /* C/N=10.0dB */
231 { 105, 4236 }, /* C/N=10.5dB */
232 { 110, 4013 }, /* C/N=11.0dB */
233 { 115, 3800 }, /* C/N=11.5dB */
234 { 120, 3598 }, /* C/N=12.0dB */
235 { 125, 3406 }, /* C/N=12.5dB */
236 { 130, 3225 }, /* C/N=13.0dB */
237 { 135, 3052 }, /* C/N=13.5dB */
238 { 140, 2889 }, /* C/N=14.0dB */
239 { 145, 2733 }, /* C/N=14.5dB */
240 { 150, 2587 }, /* C/N=15.0dB */
241 { 160, 2318 }, /* C/N=16.0dB */
242 { 170, 2077 }, /* C/N=17.0dB */
243 { 180, 1862 }, /* C/N=18.0dB */
244 { 190, 1670 }, /* C/N=19.0dB */
245 { 200, 1499 }, /* C/N=20.0dB */
246 { 210, 1347 }, /* C/N=21.0dB */
247 { 220, 1213 }, /* C/N=22.0dB */
248 { 230, 1095 }, /* C/N=23.0dB */
249 { 240, 992 }, /* C/N=24.0dB */
250 { 250, 900 }, /* C/N=25.0dB */
251 { 260, 826 }, /* C/N=26.0dB */
252 { 270, 758 }, /* C/N=27.0dB */
253 { 280, 702 }, /* C/N=28.0dB */
254 { 290, 653 }, /* C/N=29.0dB */
255 { 300, 613 }, /* C/N=30.0dB */
256 { 310, 579 }, /* C/N=31.0dB */
257 { 320, 550 }, /* C/N=32.0dB */
258 { 330, 526 }, /* C/N=33.0dB */
259 { 350, 490 }, /* C/N=33.0dB */
260 { 400, 445 }, /* C/N=40.0dB */
261 { 450, 430 }, /* C/N=45.0dB */
262 { 500, 426 }, /* C/N=50.0dB */
263 { 510, 425 } /* C/N=51.0dB */
cd21b334
DS		 264};
265
20e671df 266static const struct slookup s2_sn_lookup[] = {
4f979d5c
DS		 267 { -30, 13950 }, /* C/N=-2.5dB */
268 { -25, 13580 }, /* C/N=-2.5dB */
269 { -20, 13150 }, /* C/N=-2.0dB */
270 { -15, 12760 }, /* C/N=-1.5dB */
271 { -10, 12345 }, /* C/N=-1.0dB */
272 { -5, 11900 }, /* C/N=-0.5dB */
273 { 0, 11520 }, /* C/N= 0dB */
274 { 5, 11080 }, /* C/N= 0.5dB */
275 { 10, 10630 }, /* C/N= 1.0dB */
276 { 15, 10210 }, /* C/N= 1.5dB */
277 { 20, 9790 }, /* C/N= 2.0dB */
278 { 25, 9390 }, /* C/N= 2.5dB */
279 { 30, 8970 }, /* C/N= 3.0dB */
280 { 35, 8575 }, /* C/N= 3.5dB */
281 { 40, 8180 }, /* C/N= 4.0dB */
282 { 45, 7800 }, /* C/N= 4.5dB */
283 { 50, 7430 }, /* C/N= 5.0dB */
284 { 55, 7080 }, /* C/N= 5.5dB */
285 { 60, 6720 }, /* C/N= 6.0dB */
286 { 65, 6320 }, /* C/N= 6.5dB */
287 { 70, 6060 }, /* C/N= 7.0dB */
288 { 75, 5760 }, /* C/N= 7.5dB */
289 { 80, 5480 }, /* C/N= 8.0dB */
290 { 85, 5200 }, /* C/N= 8.5dB */
291 { 90, 4930 }, /* C/N= 9.0dB */
292 { 95, 4680 }, /* C/N= 9.5dB */
293 { 100, 4425 }, /* C/N=10.0dB */
294 { 105, 4210 }, /* C/N=10.5dB */
295 { 110, 3980 }, /* C/N=11.0dB */
296 { 115, 3765 }, /* C/N=11.5dB */
297 { 120, 3570 }, /* C/N=12.0dB */
298 { 125, 3315 }, /* C/N=12.5dB */
299 { 130, 3140 }, /* C/N=13.0dB */
300 { 135, 2980 }, /* C/N=13.5dB */
301 { 140, 2820 }, /* C/N=14.0dB */
302 { 145, 2670 }, /* C/N=14.5dB */
303 { 150, 2535 }, /* C/N=15.0dB */
304 { 160, 2270 }, /* C/N=16.0dB */
305 { 170, 2035 }, /* C/N=17.0dB */
306 { 180, 1825 }, /* C/N=18.0dB */
307 { 190, 1650 }, /* C/N=19.0dB */
308 { 200, 1485 }, /* C/N=20.0dB */
309 { 210, 1340 }, /* C/N=21.0dB */
310 { 220, 1212 }, /* C/N=22.0dB */
311 { 230, 1100 }, /* C/N=23.0dB */
312 { 240, 1000 }, /* C/N=24.0dB */
313 { 250, 910 }, /* C/N=25.0dB */
314 { 260, 836 }, /* C/N=26.0dB */
315 { 270, 772 }, /* C/N=27.0dB */
316 { 280, 718 }, /* C/N=28.0dB */
317 { 290, 671 }, /* C/N=29.0dB */
318 { 300, 635 }, /* C/N=30.0dB */
319 { 310, 602 }, /* C/N=31.0dB */
320 { 320, 575 }, /* C/N=32.0dB */
321 { 330, 550 }, /* C/N=33.0dB */
322 { 350, 517 }, /* C/N=35.0dB */
323 { 400, 480 }, /* C/N=40.0dB */
324 { 450, 466 }, /* C/N=45.0dB */
325 { 500, 464 }, /* C/N=50.0dB */
326 { 510, 463 }, /* C/N=51.0dB */
cd21b334
DS		 327};
328
20e671df 329static const struct slookup padc_lookup[] = {
4f979d5c
DS		 330 { 0, 118000 }, /* PADC= +0dBm */
331 { -100, 93600 }, /* PADC= -1dBm */
332 { -200, 74500 }, /* PADC= -2dBm */
333 { -300, 59100 }, /* PADC= -3dBm */
334 { -400, 47000 }, /* PADC= -4dBm */
335 { -500, 37300 }, /* PADC= -5dBm */
336 { -600, 29650 }, /* PADC= -6dBm */
337 { -700, 23520 }, /* PADC= -7dBm */
338 { -900, 14850 }, /* PADC= -9dBm */
19bb3b71
DS		 339 { -1100, 9380 }, /* PADC=-11dBm */
340 { -1300, 5910 }, /* PADC=-13dBm */
341 { -1500, 3730 }, /* PADC=-15dBm */
342 { -1700, 2354 }, /* PADC=-17dBm */
343 { -1900, 1485 }, /* PADC=-19dBm */
344 { -2000, 1179 }, /* PADC=-20dBm */
345 { -2100, 1000 }, /* PADC=-21dBm */
346};
347
cd21b334
DS		 348/*********************************************************************
349 * Tracking carrier loop carrier QPSK 1/4 to 8PSK 9/10 long Frame
350 *********************************************************************/
20e671df 351static const u8 s2car_loop[] = {
4f979d5c
DS		 352 /*
353 * Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff
cd21b334
DS		 354 * 20MPon 20MPoff 30MPon 30MPoff
355 */
356
357 /* FE_QPSK_14 */
358 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x2A, 0x1C, 0x3A, 0x3B,
359 /* FE_QPSK_13 */
360 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x3A, 0x0C, 0x3A, 0x2B,
361 /* FE_QPSK_25 */
362 0x1C, 0x3C, 0x1B, 0x3C, 0x3A, 0x1C, 0x3A, 0x3B, 0x3A, 0x2B,
363 /* FE_QPSK_12 */
364 0x0C, 0x1C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,
365 /* FE_QPSK_35 */
366 0x1C, 0x1C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,
367 /* FE_QPSK_23 */
368 0x2C, 0x2C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,
369 /* FE_QPSK_34 */
370 0x3C, 0x2C, 0x3B, 0x2C, 0x1B, 0x1C, 0x1B, 0x3B, 0x3A, 0x1B,
371 /* FE_QPSK_45 */
372 0x0D, 0x3C, 0x3B, 0x2C, 0x1B, 0x1C, 0x1B, 0x3B, 0x3A, 0x1B,
373 /* FE_QPSK_56 */
374 0x1D, 0x3C, 0x0C, 0x2C, 0x2B, 0x1C, 0x1B, 0x3B, 0x0B, 0x1B,
375 /* FE_QPSK_89 */
376 0x3D, 0x0D, 0x0C, 0x2C, 0x2B, 0x0C, 0x2B, 0x2B, 0x0B, 0x0B,
377 /* FE_QPSK_910 */
378 0x1E, 0x0D, 0x1C, 0x2C, 0x3B, 0x0C, 0x2B, 0x2B, 0x1B, 0x0B,
379 /* FE_8PSK_35 */
380 0x28, 0x09, 0x28, 0x09, 0x28, 0x09, 0x28, 0x08, 0x28, 0x27,
381 /* FE_8PSK_23 */
382 0x19, 0x29, 0x19, 0x29, 0x19, 0x29, 0x38, 0x19, 0x28, 0x09,
383 /* FE_8PSK_34 */
384 0x1A, 0x0B, 0x1A, 0x3A, 0x0A, 0x2A, 0x39, 0x2A, 0x39, 0x1A,
385 /* FE_8PSK_56 */
386 0x2B, 0x2B, 0x1B, 0x1B, 0x0B, 0x1B, 0x1A, 0x0B, 0x1A, 0x1A,
387 /* FE_8PSK_89 */
388 0x0C, 0x0C, 0x3B, 0x3B, 0x1B, 0x1B, 0x2A, 0x0B, 0x2A, 0x2A,
389 /* FE_8PSK_910 */
390 0x0C, 0x1C, 0x0C, 0x3B, 0x2B, 0x1B, 0x3A, 0x0B, 0x2A, 0x2A,
391
392 /**********************************************************************
393 * Tracking carrier loop carrier 16APSK 2/3 to 32APSK 9/10 long Frame
394 **********************************************************************/
395
4f979d5c
DS		 396 /*
397 * Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon
cd21b334
DS		 398 * 20MPoff 30MPon 30MPoff
399 */
400
401 /* FE_16APSK_23 */
402 0x0A, 0x0A, 0x0A, 0x0A, 0x1A, 0x0A, 0x39, 0x0A, 0x29, 0x0A,
403 /* FE_16APSK_34 */
404 0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x0A, 0x2A, 0x0A, 0x1A, 0x0A,
405 /* FE_16APSK_45 */
406 0x0A, 0x0A, 0x0A, 0x0A, 0x1B, 0x0A, 0x3A, 0x0A, 0x2A, 0x0A,
407 /* FE_16APSK_56 */
408 0x0A, 0x0A, 0x0A, 0x0A, 0x1B, 0x0A, 0x3A, 0x0A, 0x2A, 0x0A,
409 /* FE_16APSK_89 */
410 0x0A, 0x0A, 0x0A, 0x0A, 0x2B, 0x0A, 0x0B, 0x0A, 0x3A, 0x0A,
411 /* FE_16APSK_910 */
412 0x0A, 0x0A, 0x0A, 0x0A, 0x2B, 0x0A, 0x0B, 0x0A, 0x3A, 0x0A,
413 /* FE_32APSK_34 */
414 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
415 /* FE_32APSK_45 */
416 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
417 /* FE_32APSK_56 */
418 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
419 /* FE_32APSK_89 */
420 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
421 /* FE_32APSK_910 */
422 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
423};
424
425static u8 get_optim_cloop(struct stv *state,
426 enum fe_stv0910_mod_cod mod_cod, u32 pilots)
427{
428 int i = 0;
429
430 if (mod_cod >= FE_32APSK_910)
431 i = ((int)FE_32APSK_910 - (int)FE_QPSK_14) * 10;
432 else if (mod_cod >= FE_QPSK_14)
433 i = ((int)mod_cod - (int)FE_QPSK_14) * 10;
434
435 if (state->symbol_rate <= 3000000)
436 i += 0;
437 else if (state->symbol_rate <= 7000000)
438 i += 2;
439 else if (state->symbol_rate <= 15000000)
440 i += 4;
441 else if (state->symbol_rate <= 25000000)
442 i += 6;
443 else
444 i += 8;
445
446 if (!pilots)
447 i += 1;
448
449 return s2car_loop[i];
450}
451
452static int get_cur_symbol_rate(struct stv *state, u32 *p_symbol_rate)
453{
454 int status = 0;
455 u8 symb_freq0;
456 u8 symb_freq1;
457 u8 symb_freq2;
458 u8 symb_freq3;
459 u8 tim_offs0;
460 u8 tim_offs1;
461 u8 tim_offs2;
462 u32 symbol_rate;
463 s32 timing_offset;
464
465 *p_symbol_rate = 0;
466 if (!state->started)
467 return status;
468
469 read_reg(state, RSTV0910_P2_SFR3 + state->regoff, &symb_freq3);
470 read_reg(state, RSTV0910_P2_SFR2 + state->regoff, &symb_freq2);
471 read_reg(state, RSTV0910_P2_SFR1 + state->regoff, &symb_freq1);
472 read_reg(state, RSTV0910_P2_SFR0 + state->regoff, &symb_freq0);
473 read_reg(state, RSTV0910_P2_TMGREG2 + state->regoff, &tim_offs2);
474 read_reg(state, RSTV0910_P2_TMGREG1 + state->regoff, &tim_offs1);
475 read_reg(state, RSTV0910_P2_TMGREG0 + state->regoff, &tim_offs0);
476
ddb6a90d
DS		 477 symbol_rate = ((u32)symb_freq3 << 24) | ((u32)symb_freq2 << 16) |
478 ((u32)symb_freq1 << 8) | (u32)symb_freq0;
479 timing_offset = ((u32)tim_offs2 << 16) | ((u32)tim_offs1 << 8) |
480 (u32)tim_offs0;
cd21b334 481
ddb6a90d 482 if ((timing_offset & (1 << 23)) != 0)
cd21b334
DS		 483 timing_offset |= 0xFF000000; /* Sign extent */
484
ddb6a90d
DS		 485 symbol_rate = (u32)(((u64)symbol_rate * state->base->mclk) >> 32);
486 timing_offset = (s32)(((s64)symbol_rate * (s64)timing_offset) >> 29);
cd21b334
DS		 487
488 *p_symbol_rate = symbol_rate + timing_offset;
489
490 return 0;
491}
492
493static int get_signal_parameters(struct stv *state)
494{
495 u8 tmp;
496
497 if (!state->started)
498 return -EINVAL;
499
500 if (state->receive_mode == RCVMODE_DVBS2) {
501 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp);
ddb6a90d 502 state->mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2);
cd21b334 503 state->pilots = (tmp & 0x01) != 0;
ddb6a90d 504 state->fectype = (enum dvbs2_fectype)((tmp & 0x02) >> 1);
cd21b334
DS		 505
506 } else if (state->receive_mode == RCVMODE_DVBS) {
507 read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp);
508 state->puncture_rate = FEC_NONE;
509 switch (tmp & 0x1F) {
510 case 0x0d:
511 state->puncture_rate = FEC_1_2;
512 break;
513 case 0x12:
514 state->puncture_rate = FEC_2_3;
515 break;
516 case 0x15:
517 state->puncture_rate = FEC_3_4;
518 break;
519 case 0x18:
520 state->puncture_rate = FEC_5_6;
521 break;
522 case 0x1a:
523 state->puncture_rate = FEC_7_8;
524 break;
525 }
526 state->is_vcm = 0;
527 state->is_standard_broadcast = 1;
528 state->feroll_off = FE_SAT_35;
529 }
530 return 0;
531}
532
533static int tracking_optimization(struct stv *state)
534{
cd21b334
DS		 535 u8 tmp;
536
cd21b334
DS		 537 read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, &tmp);
538 tmp &= ~0xC0;
539
540 switch (state->receive_mode) {
541 case RCVMODE_DVBS:
542 tmp |= 0x40;
543 break;
544 case RCVMODE_DVBS2:
545 tmp |= 0x80;
546 break;
547 default:
548 tmp |= 0xC0;
549 break;
550 }
551 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, tmp);
552
553 if (state->receive_mode == RCVMODE_DVBS2) {
554 /* Disable Reed-Solomon */
555 write_shared_reg(state,
556 RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01,
557 0x03);
558
559 if (state->fectype == DVBS2_64K) {
560 u8 aclc = get_optim_cloop(state, state->mod_cod,
561 state->pilots);
562
563 if (state->mod_cod <= FE_QPSK_910) {
564 write_reg(state, RSTV0910_P2_ACLC2S2Q +
565 state->regoff, aclc);
566 } else if (state->mod_cod <= FE_8PSK_910) {
567 write_reg(state, RSTV0910_P2_ACLC2S2Q +
568 state->regoff, 0x2a);
569 write_reg(state, RSTV0910_P2_ACLC2S28 +
570 state->regoff, aclc);
571 } else if (state->mod_cod <= FE_16APSK_910) {
572 write_reg(state, RSTV0910_P2_ACLC2S2Q +
573 state->regoff, 0x2a);
574 write_reg(state, RSTV0910_P2_ACLC2S216A +
575 state->regoff, aclc);
576 } else if (state->mod_cod <= FE_32APSK_910) {
577 write_reg(state, RSTV0910_P2_ACLC2S2Q +
578 state->regoff, 0x2a);
579 write_reg(state, RSTV0910_P2_ACLC2S232A +
580 state->regoff, aclc);
581 }
582 }
583 }
584 return 0;
585}
586
20e671df 587static s32 table_lookup(const struct slookup *table,
ddb6a90d 588 int table_size, u32 reg_value)
cd21b334
DS		 589{
590 s32 value;
591 int imin = 0;
592 int imax = table_size - 1;
593 int i;
594 s32 reg_diff;
595
596 /* Assumes Table[0].RegValue > Table[imax].RegValue */
ddb6a90d 597 if (reg_value >= table[0].reg_value) {
cd21b334 598 value = table[0].value;
ddb6a90d 599 } else if (reg_value <= table[imax].reg_value) {
cd21b334 600 value = table[imax].value;
ddb6a90d
DS		 601 } else {
602 while ((imax - imin) > 1) {
cd21b334
DS		 603 i = (imax + imin) / 2;
604 if ((table[imin].reg_value >= reg_value) &&
ddb6a90d 605 (reg_value >= table[i].reg_value))
cd21b334
DS		 606 imax = i;
607 else
608 imin = i;
609 }
610
611 reg_diff = table[imax].reg_value - table[imin].reg_value;
612 value = table[imin].value;
613 if (reg_diff != 0)
614 value += ((s32)(reg_value - table[imin].reg_value) *
615 (s32)(table[imax].value
616 - table[imin].value))
617 / (reg_diff);
618 }
619
620 return value;
621}
622
623static int get_signal_to_noise(struct stv *state, s32 *signal_to_noise)
624{
625 u8 data0;
626 u8 data1;
627 u16 data;
628 int n_lookup;
20e671df 629 const struct slookup *lookup;
cd21b334
DS		 630
631 *signal_to_noise = 0;
632
633 if (!state->started)
634 return -EINVAL;
635
636 if (state->receive_mode == RCVMODE_DVBS2) {
637 read_reg(state, RSTV0910_P2_NNOSPLHT1 + state->regoff,
638 &data1);
639 read_reg(state, RSTV0910_P2_NNOSPLHT0 + state->regoff,
640 &data0);
641 n_lookup = ARRAY_SIZE(s2_sn_lookup);
642 lookup = s2_sn_lookup;
643 } else {
644 read_reg(state, RSTV0910_P2_NNOSDATAT1 + state->regoff,
645 &data1);
646 read_reg(state, RSTV0910_P2_NNOSDATAT0 + state->regoff,
647 &data0);
648 n_lookup = ARRAY_SIZE(s1_sn_lookup);
649 lookup = s1_sn_lookup;
650 }
ddb6a90d 651 data = (((u16)data1) << 8) | (u16)data0;
cd21b334
DS		 652 *signal_to_noise = table_lookup(lookup, n_lookup, data);
653 return 0;
654}
655
656static int get_bit_error_rate_s(struct stv *state, u32 *bernumerator,
ddb6a90d 657 u32 *berdenominator)
cd21b334
DS		 658{
659 u8 regs[3];
660
661 int status = read_regs(state,
662 RSTV0910_P2_ERRCNT12 + state->regoff,
663 regs, 3);
664
665 if (status)
666 return -EINVAL;
667
668 if ((regs[0] & 0x80) == 0) {
669 state->last_berdenominator = 1 << ((state->berscale * 2) +
670 10 + 3);
ddb6a90d
DS		 671 state->last_bernumerator = ((u32)(regs[0] & 0x7F) << 16) |
672 ((u32)regs[1] << 8) | regs[2];
cd21b334
DS		 673 if (state->last_bernumerator < 256 && state->berscale < 6) {
674 state->berscale += 1;
675 status = write_reg(state, RSTV0910_P2_ERRCTRL1 +
676 state->regoff,
677 0x20 | state->berscale);
678 } else if (state->last_bernumerator > 1024 &&
679 state->berscale > 2) {
680 state->berscale -= 1;
681 status = write_reg(state, RSTV0910_P2_ERRCTRL1 +
682 state->regoff, 0x20 |
683 state->berscale);
684 }
685 }
686 *bernumerator = state->last_bernumerator;
687 *berdenominator = state->last_berdenominator;
688 return 0;
689}
690
691static u32 dvbs2_nbch(enum dvbs2_mod_cod mod_cod, enum dvbs2_fectype fectype)
692{
20e671df 693 static const u32 nbch[][2] = {
4f979d5c
DS		 694 { 0, 0}, /* DUMMY_PLF */
695 {16200, 3240}, /* QPSK_1_4, */
696 {21600, 5400}, /* QPSK_1_3, */
697 {25920, 6480}, /* QPSK_2_5, */
698 {32400, 7200}, /* QPSK_1_2, */
699 {38880, 9720}, /* QPSK_3_5, */
700 {43200, 10800}, /* QPSK_2_3, */
701 {48600, 11880}, /* QPSK_3_4, */
702 {51840, 12600}, /* QPSK_4_5, */
703 {54000, 13320}, /* QPSK_5_6, */
704 {57600, 14400}, /* QPSK_8_9, */
705 {58320, 16000}, /* QPSK_9_10, */
706 {43200, 9720}, /* 8PSK_3_5, */
707 {48600, 10800}, /* 8PSK_2_3, */
708 {51840, 11880}, /* 8PSK_3_4, */
709 {54000, 13320}, /* 8PSK_5_6, */
710 {57600, 14400}, /* 8PSK_8_9, */
711 {58320, 16000}, /* 8PSK_9_10, */
cd21b334
DS		 712 {43200, 10800}, /* 16APSK_2_3, */
713 {48600, 11880}, /* 16APSK_3_4, */
714 {51840, 12600}, /* 16APSK_4_5, */
715 {54000, 13320}, /* 16APSK_5_6, */
716 {57600, 14400}, /* 16APSK_8_9, */
717 {58320, 16000}, /* 16APSK_9_10 */
718 {48600, 11880}, /* 32APSK_3_4, */
719 {51840, 12600}, /* 32APSK_4_5, */
720 {54000, 13320}, /* 32APSK_5_6, */
721 {57600, 14400}, /* 32APSK_8_9, */
722 {58320, 16000}, /* 32APSK_9_10 */
723 };
724
725 if (mod_cod >= DVBS2_QPSK_1_4 &&
726 mod_cod <= DVBS2_32APSK_9_10 && fectype <= DVBS2_16K)
13c81489 727 return nbch[mod_cod][fectype];
cd21b334
DS		 728 return 64800;
729}
730
731static int get_bit_error_rate_s2(struct stv *state, u32 *bernumerator,
ddb6a90d 732 u32 *berdenominator)
cd21b334
DS		 733{
734 u8 regs[3];
735
736 int status = read_regs(state, RSTV0910_P2_ERRCNT12 + state->regoff,
737 regs, 3);
738
739 if (status)
740 return -EINVAL;
741
742 if ((regs[0] & 0x80) == 0) {
743 state->last_berdenominator =
ddb6a90d 744 dvbs2_nbch((enum dvbs2_mod_cod)state->mod_cod,
cd21b334
DS		 745 state->fectype) <<
746 (state->berscale * 2);
ddb6a90d
DS		 747 state->last_bernumerator = (((u32)regs[0] & 0x7F) << 16) |
748 ((u32)regs[1] << 8) | regs[2];
cd21b334
DS		 749 if (state->last_bernumerator < 256 && state->berscale < 6) {
750 state->berscale += 1;
751 write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff,
752 0x20 | state->berscale);
753 } else if (state->last_bernumerator > 1024 &&
754 state->berscale > 2) {
755 state->berscale -= 1;
756 write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff,
757 0x20 | state->berscale);
758 }
759 }
760 *bernumerator = state->last_bernumerator;
761 *berdenominator = state->last_berdenominator;
762 return status;
763}
764
765static int get_bit_error_rate(struct stv *state, u32 *bernumerator,
ddb6a90d 766 u32 *berdenominator)
cd21b334
DS		 767{
768 *bernumerator = 0;
769 *berdenominator = 1;
770
771 switch (state->receive_mode) {
772 case RCVMODE_DVBS:
773 return get_bit_error_rate_s(state,
774 bernumerator, berdenominator);
775 case RCVMODE_DVBS2:
776 return get_bit_error_rate_s2(state,
777 bernumerator, berdenominator);
778 default:
779 break;
780 }
781 return 0;
782}
783
784static int set_mclock(struct stv *state, u32 master_clock)
785{
786 u32 idf = 1;
787 u32 odf = 4;
788 u32 quartz = state->base->extclk / 1000000;
789 u32 fphi = master_clock / 1000000;
790 u32 ndiv = (fphi * odf * idf) / quartz;
791 u32 cp = 7;
792 u32 fvco;
793
794 if (ndiv >= 7 && ndiv <= 71)
795 cp = 7;
796 else if (ndiv >= 72 && ndiv <= 79)
797 cp = 8;
798 else if (ndiv >= 80 && ndiv <= 87)
799 cp = 9;
800 else if (ndiv >= 88 && ndiv <= 95)
801 cp = 10;
802 else if (ndiv >= 96 && ndiv <= 103)
803 cp = 11;
804 else if (ndiv >= 104 && ndiv <= 111)
805 cp = 12;
806 else if (ndiv >= 112 && ndiv <= 119)
807 cp = 13;
808 else if (ndiv >= 120 && ndiv <= 127)
809 cp = 14;
810 else if (ndiv >= 128 && ndiv <= 135)
811 cp = 15;
812 else if (ndiv >= 136 && ndiv <= 143)
813 cp = 16;
814 else if (ndiv >= 144 && ndiv <= 151)
815 cp = 17;
816 else if (ndiv >= 152 && ndiv <= 159)
817 cp = 18;
818 else if (ndiv >= 160 && ndiv <= 167)
819 cp = 19;
820 else if (ndiv >= 168 && ndiv <= 175)
821 cp = 20;
822 else if (ndiv >= 176 && ndiv <= 183)
823 cp = 21;
824 else if (ndiv >= 184 && ndiv <= 191)
825 cp = 22;
826 else if (ndiv >= 192 && ndiv <= 199)
827 cp = 23;
828 else if (ndiv >= 200 && ndiv <= 207)
829 cp = 24;
830 else if (ndiv >= 208 && ndiv <= 215)
831 cp = 25;
832 else if (ndiv >= 216 && ndiv <= 223)
833 cp = 26;
834 else if (ndiv >= 224 && ndiv <= 225)
835 cp = 27;
836
837 write_reg(state, RSTV0910_NCOARSE, (cp << 3) | idf);
838 write_reg(state, RSTV0910_NCOARSE2, odf);
839 write_reg(state, RSTV0910_NCOARSE1, ndiv);
840
841 fvco = (quartz * 2 * ndiv) / idf;
842 state->base->mclk = fvco / (2 * odf) * 1000000;
843
844 return 0;
845}
846
847static int stop(struct stv *state)
848{
849 if (state->started) {
850 u8 tmp;
851
852 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
853 state->tscfgh | 0x01);
854 read_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, &tmp);
4f979d5c 855 tmp &= ~0x01; /* release reset DVBS2 packet delin */
cd21b334
DS		 856 write_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, tmp);
857 /* Blind optim*/
858 write_reg(state, RSTV0910_P2_AGC2O + state->regoff, 0x5B);
859 /* Stop the demod */
860 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5c);
861 state->started = 0;
862 }
863 state->receive_mode = RCVMODE_NONE;
864 return 0;
865}
866
867static int init_search_param(struct stv *state)
868{
869 u8 tmp;
870
871 read_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, &tmp);
4f979d5c 872 tmp |= 0x20; /* Filter_en (no effect if SIS=non-MIS */
cd21b334
DS		 873 write_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, tmp);
874
875 read_reg(state, RSTV0910_P2_PDELCTRL2 + state->regoff, &tmp);
4f979d5c 876 tmp &= ~0x02; /* frame mode = 0 */
cd21b334
DS		 877 write_reg(state, RSTV0910_P2_PDELCTRL2 + state->regoff, tmp);
878
879 write_reg(state, RSTV0910_P2_UPLCCST0 + state->regoff, 0xe0);
880 write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 0x00);
881
882 read_reg(state, RSTV0910_P2_TSSTATEM + state->regoff, &tmp);
4f979d5c 883 tmp &= ~0x01; /* nosync = 0, in case next signal is standard TS */
cd21b334
DS		 884 write_reg(state, RSTV0910_P2_TSSTATEM + state->regoff, tmp);
885
886 read_reg(state, RSTV0910_P2_TSCFGL + state->regoff, &tmp);
4f979d5c 887 tmp &= ~0x04; /* embindvb = 0 */
cd21b334
DS		 888 write_reg(state, RSTV0910_P2_TSCFGL + state->regoff, tmp);
889
890 read_reg(state, RSTV0910_P2_TSINSDELH + state->regoff, &tmp);
4f979d5c 891 tmp &= ~0x80; /* syncbyte = 0 */
cd21b334
DS		 892 write_reg(state, RSTV0910_P2_TSINSDELH + state->regoff, tmp);
893
894 read_reg(state, RSTV0910_P2_TSINSDELM + state->regoff, &tmp);
4f979d5c 895 tmp &= ~0x08; /* token = 0 */
cd21b334
DS		 896 write_reg(state, RSTV0910_P2_TSINSDELM + state->regoff, tmp);
897
898 read_reg(state, RSTV0910_P2_TSDLYSET2 + state->regoff, &tmp);
4f979d5c 899 tmp &= ~0x30; /* hysteresis threshold = 0 */
cd21b334
DS		 900 write_reg(state, RSTV0910_P2_TSDLYSET2 + state->regoff, tmp);
901
902 read_reg(state, RSTV0910_P2_PDELCTRL0 + state->regoff, &tmp);
4f979d5c 903 tmp = (tmp & ~0x30) | 0x10; /* isi obs mode = 1, observe min ISI */
cd21b334
DS		 904 write_reg(state, RSTV0910_P2_PDELCTRL0 + state->regoff, tmp);
905
906 return 0;
907}
908
909static int enable_puncture_rate(struct stv *state, enum fe_code_rate rate)
910{
911 switch (rate) {
912 case FEC_1_2:
913 return write_reg(state,
914 RSTV0910_P2_PRVIT + state->regoff, 0x01);
915 case FEC_2_3:
916 return write_reg(state,
917 RSTV0910_P2_PRVIT + state->regoff, 0x02);
918 case FEC_3_4:
919 return write_reg(state,
920 RSTV0910_P2_PRVIT + state->regoff, 0x04);
921 case FEC_5_6:
922 return write_reg(state,
923 RSTV0910_P2_PRVIT + state->regoff, 0x08);
924 case FEC_7_8:
925 return write_reg(state,
926 RSTV0910_P2_PRVIT + state->regoff, 0x20);
927 case FEC_NONE:
928 default:
929 return write_reg(state,
930 RSTV0910_P2_PRVIT + state->regoff, 0x2f);
931 }
932}
933
934static int set_vth_default(struct stv *state)
935{
936 state->vth[0] = 0xd7;
937 state->vth[1] = 0x85;
938 state->vth[2] = 0x58;
939 state->vth[3] = 0x3a;
940 state->vth[4] = 0x34;
941 state->vth[5] = 0x28;
942 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]);
943 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]);
944 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]);
945 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]);
946 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]);
947 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]);
948 return 0;
949}
950
951static int set_vth(struct stv *state)
952{
20e671df 953 static const struct slookup vthlookup_table[] = {
4f979d5c
DS		 954 {250, 8780}, /* C/N= 1.5dB */
955 {100, 7405}, /* C/N= 4.5dB */
956 {40, 6330}, /* C/N= 6.5dB */
957 {12, 5224}, /* C/N= 8.5dB */
958 {5, 4236} /* C/N=10.5dB */
cd21b334
DS		 959 };
960
961 int i;
962 u8 tmp[2];
963 int status = read_regs(state,
964 RSTV0910_P2_NNOSDATAT1 + state->regoff,
965 tmp, 2);
966 u16 reg_value = (tmp[0] << 8) | tmp[1];
967 s32 vth = table_lookup(vthlookup_table, ARRAY_SIZE(vthlookup_table),
968 reg_value);
969
970 for (i = 0; i < 6; i += 1)
971 if (state->vth[i] > vth)
972 state->vth[i] = vth;
973
974 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]);
975 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]);
976 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]);
977 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]);
978 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]);
979 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]);
980 return status;
981}
982
983static int start(struct stv *state, struct dtv_frontend_properties *p)
984{
985 s32 freq;
986 u8 reg_dmdcfgmd;
987 u16 symb;
ea71c62b 988 u32 scrambling_code = 1;
cd21b334
DS		 989
990 if (p->symbol_rate < 100000 || p->symbol_rate > 70000000)
991 return -EINVAL;
992
993 state->receive_mode = RCVMODE_NONE;
994 state->demod_lock_time = 0;
995
996 /* Demod Stop */
997 if (state->started)
998 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5C);
999
1000 init_search_param(state);
1001
ea71c62b 1002 if (p->stream_id != NO_STREAM_ID_FILTER) {
4f979d5c
DS		 1003 /*
1004 * Backwards compatibility to "crazy" API.
ea71c62b
DS		 1005 * PRBS X root cannot be 0, so this should always work.
1006 */
1007 if (p->stream_id & 0xffffff00)
1008 scrambling_code = p->stream_id >> 8;
1009 write_reg(state, RSTV0910_P2_ISIENTRY + state->regoff,
1010 p->stream_id & 0xff);
1011 write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff,
1012 0xff);
1013 }
1014
1015 if (scrambling_code != state->cur_scrambling_code) {
1016 write_reg(state, RSTV0910_P2_PLROOT0 + state->regoff,
1017 scrambling_code & 0xff);
1018 write_reg(state, RSTV0910_P2_PLROOT1 + state->regoff,
1019 (scrambling_code >> 8) & 0xff);
1020 write_reg(state, RSTV0910_P2_PLROOT2 + state->regoff,
0758ecdb 1021 (scrambling_code >> 16) & 0x0f);
ea71c62b
DS		 1022 state->cur_scrambling_code = scrambling_code;
1023 }
1024
4f979d5c 1025 if (p->symbol_rate <= 1000000) { /* SR <=1Msps */
cd21b334
DS		 1026 state->demod_timeout = 3000;
1027 state->fec_timeout = 2000;
4f979d5c 1028 } else if (p->symbol_rate <= 2000000) { /* 1Msps < SR <=2Msps */
cd21b334
DS		 1029 state->demod_timeout = 2500;
1030 state->fec_timeout = 1300;
4f979d5c 1031 } else if (p->symbol_rate <= 5000000) { /* 2Msps< SR <=5Msps */
cd21b334
DS		 1032 state->demod_timeout = 1000;
1033 state->fec_timeout = 650;
4f979d5c 1034 } else if (p->symbol_rate <= 10000000) { /* 5Msps< SR <=10Msps */
cd21b334
DS		 1035 state->demod_timeout = 700;
1036 state->fec_timeout = 350;
4f979d5c 1037 } else if (p->symbol_rate < 20000000) { /* 10Msps< SR <=20Msps */
cd21b334
DS		 1038 state->demod_timeout = 400;
1039 state->fec_timeout = 200;
4f979d5c 1040 } else { /* SR >=20Msps */
cd21b334
DS		 1041 state->demod_timeout = 300;
1042 state->fec_timeout = 200;
1043 }
1044
1045 /* Set the Init Symbol rate */
1046 symb = muldiv32(p->symbol_rate, 65536, state->base->mclk);
1047 write_reg(state, RSTV0910_P2_SFRINIT1 + state->regoff,
1048 ((symb >> 8) & 0x7F));
1049 write_reg(state, RSTV0910_P2_SFRINIT0 + state->regoff, (symb & 0xFF));
1050
1051 state->demod_bits |= 0x80;
1052 write_reg(state, RSTV0910_P2_DEMOD + state->regoff, state->demod_bits);
1053
1054 /* FE_STV0910_SetSearchStandard */
1055 read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, &reg_dmdcfgmd);
1056 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff,
1057 reg_dmdcfgmd |= 0xC0);
1058
1059 write_shared_reg(state,
1060 RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01, 0x00);
1061
1062 /* Disable DSS */
1063 write_reg(state, RSTV0910_P2_FECM + state->regoff, 0x00);
1064 write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x2F);
1065
1066 enable_puncture_rate(state, FEC_NONE);
1067
4f979d5c 1068 /* 8PSK 3/5, 8PSK 2/3 Poff tracking optimization WA */
cd21b334
DS		 1069 write_reg(state, RSTV0910_P2_ACLC2S2Q + state->regoff, 0x0B);
1070 write_reg(state, RSTV0910_P2_ACLC2S28 + state->regoff, 0x0A);
1071 write_reg(state, RSTV0910_P2_BCLC2S2Q + state->regoff, 0x84);
1072 write_reg(state, RSTV0910_P2_BCLC2S28 + state->regoff, 0x84);
1073 write_reg(state, RSTV0910_P2_CARHDR + state->regoff, 0x1C);
1074 write_reg(state, RSTV0910_P2_CARFREQ + state->regoff, 0x79);
1075
1076 write_reg(state, RSTV0910_P2_ACLC2S216A + state->regoff, 0x29);
1077 write_reg(state, RSTV0910_P2_ACLC2S232A + state->regoff, 0x09);
1078 write_reg(state, RSTV0910_P2_BCLC2S216A + state->regoff, 0x84);
1079 write_reg(state, RSTV0910_P2_BCLC2S232A + state->regoff, 0x84);
1080
4f979d5c
DS		 1081 /*
1082 * Reset CAR3, bug DVBS2->DVBS1 lock
1083 * Note: The bit is only pulsed -> no lock on shared register needed
1084 */
cd21b334
DS		 1085 write_reg(state, RSTV0910_TSTRES0, state->nr ? 0x04 : 0x08);
1086 write_reg(state, RSTV0910_TSTRES0, 0);
1087
1088 set_vth_default(state);
1089 /* Reset demod */
1090 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F);
1091
1092 write_reg(state, RSTV0910_P2_CARCFG + state->regoff, 0x46);
1093
1094 if (p->symbol_rate <= 5000000)
1095 freq = (state->search_range / 2000) + 80;
1096 else
1097 freq = (state->search_range / 2000) + 1600;
1098 freq = (freq << 16) / (state->base->mclk / 1000);
1099
1100 write_reg(state, RSTV0910_P2_CFRUP1 + state->regoff,
1101 (freq >> 8) & 0xff);
1102 write_reg(state, RSTV0910_P2_CFRUP0 + state->regoff, (freq & 0xff));
4f979d5c 1103 /* CFR Low Setting */
cd21b334
DS		 1104 freq = -freq;
1105 write_reg(state, RSTV0910_P2_CFRLOW1 + state->regoff,
1106 (freq >> 8) & 0xff);
1107 write_reg(state, RSTV0910_P2_CFRLOW0 + state->regoff, (freq & 0xff));
1108
1109 /* init the demod frequency offset to 0 */
1110 write_reg(state, RSTV0910_P2_CFRINIT1 + state->regoff, 0);
1111 write_reg(state, RSTV0910_P2_CFRINIT0 + state->regoff, 0);
1112
1113 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F);
1114 /* Trigger acq */
1115 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x15);
1116
1117 state->demod_lock_time += TUNING_DELAY;
1118 state->started = 1;
1119
1120 return 0;
1121}
1122
1123static int init_diseqc(struct stv *state)
1124{
4f979d5c 1125 u16 offs = state->nr ? 0x40 : 0; /* Address offset */
cd21b334
DS		 1126 u8 freq = ((state->base->mclk + 11000 * 32) / (22000 * 32));
1127
1128 /* Disable receiver */
1129 write_reg(state, RSTV0910_P1_DISRXCFG + offs, 0x00);
1130 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0xBA); /* Reset = 1 */
1131 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A); /* Reset = 0 */
1132 write_reg(state, RSTV0910_P1_DISTXF22 + offs, freq);
1133 return 0;
1134}
1135
1136static int probe(struct stv *state)
1137{
1138 u8 id;
1139
1140 state->receive_mode = RCVMODE_NONE;
1141 state->started = 0;
1142
1143 if (read_reg(state, RSTV0910_MID, &id) < 0)
1144 return -ENODEV;
1145
1146 if (id != 0x51)
1147 return -EINVAL;
1148
4f979d5c 1149 /* Configure the I2C repeater to off */
cd21b334
DS		 1150 write_reg(state, RSTV0910_P1_I2CRPT, 0x24);
1151 /* Configure the I2C repeater to off */
1152 write_reg(state, RSTV0910_P2_I2CRPT, 0x24);
1153 /* Set the I2C to oversampling ratio */
1154 write_reg(state, RSTV0910_I2CCFG, 0x88); /* state->i2ccfg */
1155
4f979d5c
DS		 1156 write_reg(state, RSTV0910_OUTCFG, 0x00); /* OUTCFG */
1157 write_reg(state, RSTV0910_PADCFG, 0x05); /* RFAGC Pads Dev = 05 */
1158 write_reg(state, RSTV0910_SYNTCTRL, 0x02); /* SYNTCTRL */
1159 write_reg(state, RSTV0910_TSGENERAL, state->tsgeneral); /* TSGENERAL */
1160 write_reg(state, RSTV0910_CFGEXT, 0x02); /* CFGEXT */
cd21b334
DS		 1161
1162 if (state->single)
4f979d5c 1163 write_reg(state, RSTV0910_GENCFG, 0x14); /* GENCFG */
cd21b334 1164 else
4f979d5c 1165 write_reg(state, RSTV0910_GENCFG, 0x15); /* GENCFG */
cd21b334 1166
4f979d5c
DS		 1167 write_reg(state, RSTV0910_P1_TNRCFG2, 0x02); /* IQSWAP = 0 */
1168 write_reg(state, RSTV0910_P2_TNRCFG2, 0x82); /* IQSWAP = 1 */
cd21b334
DS		 1169
1170 write_reg(state, RSTV0910_P1_CAR3CFG, 0x02);
1171 write_reg(state, RSTV0910_P2_CAR3CFG, 0x02);
1172 write_reg(state, RSTV0910_P1_DMDCFG4, 0x04);
1173 write_reg(state, RSTV0910_P2_DMDCFG4, 0x04);
1174
1175 write_reg(state, RSTV0910_TSTRES0, 0x80); /* LDPC Reset */
1176 write_reg(state, RSTV0910_TSTRES0, 0x00);
1177
1178 write_reg(state, RSTV0910_P1_TSPIDFLT1, 0x00);
1179 write_reg(state, RSTV0910_P2_TSPIDFLT1, 0x00);
1180
1181 write_reg(state, RSTV0910_P1_TMGCFG2, 0x80);
1182 write_reg(state, RSTV0910_P2_TMGCFG2, 0x80);
1183
1184 set_mclock(state, 135000000);
1185
1186 /* TS output */
1187 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01);
1188 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh);
4f979d5c 1189 write_reg(state, RSTV0910_P1_TSCFGM, 0xC0); /* Manual speed */
cd21b334
DS		 1190 write_reg(state, RSTV0910_P1_TSCFGL, 0x20);
1191
1192 /* Speed = 67.5 MHz */
1193 write_reg(state, RSTV0910_P1_TSSPEED, state->tsspeed);
1194
1195 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01);
1196 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh);
4f979d5c 1197 write_reg(state, RSTV0910_P2_TSCFGM, 0xC0); /* Manual speed */
cd21b334
DS		 1198 write_reg(state, RSTV0910_P2_TSCFGL, 0x20);
1199
1200 /* Speed = 67.5 MHz */
1201 write_reg(state, RSTV0910_P2_TSSPEED, state->tsspeed);
1202
1203 /* Reset stream merger */
1204 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01);
1205 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01);
1206 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh);
1207 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh);
1208
1209 write_reg(state, RSTV0910_P1_I2CRPT, state->i2crpt);
1210 write_reg(state, RSTV0910_P2_I2CRPT, state->i2crpt);
1211
1212 init_diseqc(state);
1213 return 0;
1214}
1215
cd21b334
DS		 1216static int gate_ctrl(struct dvb_frontend *fe, int enable)
1217{
1218 struct stv *state = fe->demodulator_priv;
1219 u8 i2crpt = state->i2crpt & ~0x86;
1220
6b852620
DS		 1221 /*
1222 * mutex_lock note: Concurrent I2C gate bus accesses must be
1223 * prevented (STV0910 = dual demod on a single IC with a single I2C
1224 * gate/bus, and two tuners attached), similar to most (if not all)
1225 * other I2C host interfaces/busses.
1226 *
1227 * enable=1 (open I2C gate) will grab the lock
1228 * enable=0 (close I2C gate) releases the lock
1229 */
cd21b334 1230
6b852620
DS		 1231 if (enable) {
1232 mutex_lock(&state->base->i2c_lock);
cd21b334 1233 i2crpt |= 0x80;
6b852620 1234 } else {
cd21b334 1235 i2crpt |= 0x02;
6b852620 1236 }
cd21b334
DS		 1237
1238 if (write_reg(state, state->nr ? RSTV0910_P2_I2CRPT :
6b852620
DS		 1239 RSTV0910_P1_I2CRPT, i2crpt) < 0) {
1240 /* don't hold the I2C bus lock on failure */
aea16005
DS		 1241 if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock)))
1242 mutex_unlock(&state->base->i2c_lock);
6b852620
DS		 1243 dev_err(&state->base->i2c->dev,
1244 "%s() write_reg failure (enable=%d)\n",
1245 __func__, enable);
cd21b334 1246 return -EIO;
6b852620 1247 }
cd21b334
DS		 1248
1249 state->i2crpt = i2crpt;
1250
1251 if (!enable)
aea16005
DS		 1252 if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock)))
1253 mutex_unlock(&state->base->i2c_lock);
cd21b334
DS		 1254 return 0;
1255}
1256
1257static void release(struct dvb_frontend *fe)
1258{
1259 struct stv *state = fe->demodulator_priv;
1260
1261 state->base->count--;
1262 if (state->base->count == 0) {
1263 list_del(&state->base->stvlist);
1264 kfree(state->base);
1265 }
1266 kfree(state);
1267}
1268
1269static int set_parameters(struct dvb_frontend *fe)
1270{
1271 int stat = 0;
1272 struct stv *state = fe->demodulator_priv;
cd21b334
DS		 1273 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1274
1275 stop(state);
1276 if (fe->ops.tuner_ops.set_params)
1277 fe->ops.tuner_ops.set_params(fe);
cd21b334
DS		 1278 state->symbol_rate = p->symbol_rate;
1279 stat = start(state, p);
1280 return stat;
1281}
1282
1283static int manage_matype_info(struct stv *state)
1284{
1285 if (!state->started)
1286 return -EINVAL;
1287 if (state->receive_mode == RCVMODE_DVBS2) {
1288 u8 bbheader[2];
1289
1290 read_regs(state, RSTV0910_P2_MATSTR1 + state->regoff,
ddb6a90d 1291 bbheader, 2);
cd21b334 1292 state->feroll_off =
ddb6a90d 1293 (enum fe_stv0910_roll_off)(bbheader[0] & 0x03);
cd21b334
DS		 1294 state->is_vcm = (bbheader[0] & 0x10) == 0;
1295 state->is_standard_broadcast = (bbheader[0] & 0xFC) == 0xF0;
1296 } else if (state->receive_mode == RCVMODE_DVBS) {
1297 state->is_vcm = 0;
1298 state->is_standard_broadcast = 1;
1299 state->feroll_off = FE_SAT_35;
1300 }
1301 return 0;
1302}
1303
1304static int read_snr(struct dvb_frontend *fe)
1305{
1306 struct stv *state = fe->demodulator_priv;
1307 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1308 s32 snrval;
1309
1310 if (!get_signal_to_noise(state, &snrval)) {
1311 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1312 p->cnr.stat[0].uvalue = 100 * snrval; /* fix scale */
ddb6a90d 1313 } else {
cd21b334 1314 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
ddb6a90d 1315 }
cd21b334
DS		 1316
1317 return 0;
1318}
1319
1320static int read_ber(struct dvb_frontend *fe)
1321{
1322 struct stv *state = fe->demodulator_priv;
1323 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1324 u32 n, d;
1325
1326 get_bit_error_rate(state, &n, &d);
1327
1328 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1329 p->pre_bit_error.stat[0].uvalue = n;
1330 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1331 p->pre_bit_count.stat[0].uvalue = d;
1332
1333 return 0;
1334}
1335
1336static void read_signal_strength(struct dvb_frontend *fe)
1337{
cd21b334
DS		 1338 struct stv *state = fe->demodulator_priv;
1339 struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
19bb3b71
DS		 1340 u8 reg[2];
1341 u16 agc;
1342 s32 padc, power = 0;
1343 int i;
1344
1345 read_regs(state, RSTV0910_P2_AGCIQIN1 + state->regoff, reg, 2);
1346
ddb6a90d 1347 agc = (((u32)reg[0]) << 8) | reg[1];
19bb3b71
DS		 1348
1349 for (i = 0; i < 5; i += 1) {
1350 read_regs(state, RSTV0910_P2_POWERI + state->regoff, reg, 2);
ddb6a90d
DS		 1351 power += (u32)reg[0] * (u32)reg[0]
1352 + (u32)reg[1] * (u32)reg[1];
19bb3b71
DS		 1353 usleep_range(3000, 4000);
1354 }
1355 power /= 5;
1356
1357 padc = table_lookup(padc_lookup, ARRAY_SIZE(padc_lookup), power) + 352;
1358
19bb3b71 1359 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
399196ed 1360 p->strength.stat[0].svalue = (padc - agc);
cd21b334
DS		 1361}
1362
1363static int read_status(struct dvb_frontend *fe, enum fe_status *status)
1364{
1365 struct stv *state = fe->demodulator_priv;
1366 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1367 u8 dmd_state = 0;
1368 u8 dstatus = 0;
1369 enum receive_mode cur_receive_mode = RCVMODE_NONE;
1370 u32 feclock = 0;
1371
1372 *status = 0;
1373
1374 read_reg(state, RSTV0910_P2_DMDSTATE + state->regoff, &dmd_state);
1375
1376 if (dmd_state & 0x40) {
1377 read_reg(state, RSTV0910_P2_DSTATUS + state->regoff, &dstatus);
1378 if (dstatus & 0x08)
1379 cur_receive_mode = (dmd_state & 0x20) ?
1380 RCVMODE_DVBS : RCVMODE_DVBS2;
1381 }
1382 if (cur_receive_mode == RCVMODE_NONE) {
1383 set_vth(state);
1384
1385 /* reset signal statistics */
1386 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1387 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1388 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1389 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1390
1391 return 0;
1392 }
1393
1394 *status |= (FE_HAS_SIGNAL
1395 | FE_HAS_CARRIER
1396 | FE_HAS_VITERBI
1397 | FE_HAS_SYNC);
1398
1399 if (state->receive_mode == RCVMODE_NONE) {
1400 state->receive_mode = cur_receive_mode;
1401 state->demod_lock_time = jiffies;
1402 state->first_time_lock = 1;
1403
1404 get_signal_parameters(state);
1405 tracking_optimization(state);
1406
1407 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1408 state->tscfgh);
1409 usleep_range(3000, 4000);
1410 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1411 state->tscfgh | 0x01);
1412 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1413 state->tscfgh);
1414 }
1415 if (dmd_state & 0x40) {
1416 if (state->receive_mode == RCVMODE_DVBS2) {
1417 u8 pdelstatus;
1418
1419 read_reg(state,
1420 RSTV0910_P2_PDELSTATUS1 + state->regoff,
1421 &pdelstatus);
1422 feclock = (pdelstatus & 0x02) != 0;
1423 } else {
1424 u8 vstatus;
1425
1426 read_reg(state,
1427 RSTV0910_P2_VSTATUSVIT + state->regoff,
1428 &vstatus);
1429 feclock = (vstatus & 0x08) != 0;
1430 }
1431 }
1432
1433 if (feclock) {
1434 *status |= FE_HAS_LOCK;
1435
1436 if (state->first_time_lock) {
1437 u8 tmp;
1438
1439 state->first_time_lock = 0;
1440
1441 manage_matype_info(state);
1442
1443 if (state->receive_mode == RCVMODE_DVBS2) {
4f979d5c
DS		 1444 /*
1445 * FSTV0910_P2_MANUALSX_ROLLOFF,
cd21b334
DS		 1446 * FSTV0910_P2_MANUALS2_ROLLOFF = 0
1447 */
1448 state->demod_bits &= ~0x84;
1449 write_reg(state,
1450 RSTV0910_P2_DEMOD + state->regoff,
1451 state->demod_bits);
1452 read_reg(state,
1453 RSTV0910_P2_PDELCTRL2 + state->regoff,
1454 &tmp);
4f979d5c 1455 /* reset DVBS2 packet delinator error counter */
cd21b334
DS		 1456 tmp |= 0x40;
1457 write_reg(state,
1458 RSTV0910_P2_PDELCTRL2 + state->regoff,
1459 tmp);
4f979d5c 1460 /* reset DVBS2 packet delinator error counter */
cd21b334
DS		 1461 tmp &= ~0x40;
1462 write_reg(state,
1463 RSTV0910_P2_PDELCTRL2 + state->regoff,
1464 tmp);
1465
1466 state->berscale = 2;
1467 state->last_bernumerator = 0;
1468 state->last_berdenominator = 1;
1469 /* force to PRE BCH Rate */
1470 write_reg(state,
1471 RSTV0910_P2_ERRCTRL1 + state->regoff,
1472 BER_SRC_S2 | state->berscale);
1473 } else {
1474 state->berscale = 2;
1475 state->last_bernumerator = 0;
1476 state->last_berdenominator = 1;
1477 /* force to PRE RS Rate */
1478 write_reg(state,
1479 RSTV0910_P2_ERRCTRL1 + state->regoff,
1480 BER_SRC_S | state->berscale);
1481 }
4f979d5c 1482 /* Reset the Total packet counter */
cd21b334
DS		 1483 write_reg(state,
1484 RSTV0910_P2_FBERCPT4 + state->regoff, 0x00);
4f979d5c
DS		 1485 /*
1486 * Reset the packet Error counter2 (and Set it to
1487 * infinit error count mode)
cd21b334
DS		 1488 */
1489 write_reg(state,
1490 RSTV0910_P2_ERRCTRL2 + state->regoff, 0xc1);
1491
1492 set_vth_default(state);
1493 if (state->receive_mode == RCVMODE_DVBS)
1494 enable_puncture_rate(state,
1495 state->puncture_rate);
1496 }
9cc65447
DS		 1497
1498 /* Use highest signaled ModCod for quality */
1499 if (state->is_vcm) {
1500 u8 tmp;
1501 enum fe_stv0910_mod_cod mod_cod;
1502
1503 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff,
1504 &tmp);
1505 mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2);
1506
1507 if (mod_cod > state->mod_cod)
1508 state->mod_cod = mod_cod;
1509 }
cd21b334
DS		 1510 }
1511
1512 /* read signal statistics */
1513
1514 /* read signal strength */
1515 read_signal_strength(fe);
1516
1517 /* read carrier/noise on FE_HAS_CARRIER */
1518 if (*status & FE_HAS_CARRIER)
1519 read_snr(fe);
1520 else
1521 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1522
1523 /* read ber */
ddb6a90d 1524 if (*status & FE_HAS_VITERBI) {
cd21b334 1525 read_ber(fe);
ddb6a90d 1526 } else {
cd21b334
DS		 1527 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1528 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1529 }
1530
1531 return 0;
1532}
1533
1534static int get_frontend(struct dvb_frontend *fe,
1535 struct dtv_frontend_properties *p)
1536{
1537 struct stv *state = fe->demodulator_priv;
1538 u8 tmp;
0b885ded 1539 u32 symbolrate;
cd21b334
DS		 1540
1541 if (state->receive_mode == RCVMODE_DVBS2) {
1542 u32 mc;
20e671df 1543 const enum fe_modulation modcod2mod[0x20] = {
cd21b334
DS		 1544 QPSK, QPSK, QPSK, QPSK,
1545 QPSK, QPSK, QPSK, QPSK,
1546 QPSK, QPSK, QPSK, QPSK,
1547 PSK_8, PSK_8, PSK_8, PSK_8,
1548 PSK_8, PSK_8, APSK_16, APSK_16,
1549 APSK_16, APSK_16, APSK_16, APSK_16,
1550 APSK_32, APSK_32, APSK_32, APSK_32,
1551 APSK_32,
1552 };
20e671df 1553 const enum fe_code_rate modcod2fec[0x20] = {
cd21b334
DS		 1554 FEC_NONE, FEC_NONE, FEC_NONE, FEC_2_5,
1555 FEC_1_2, FEC_3_5, FEC_2_3, FEC_3_4,
1556 FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10,
1557 FEC_3_5, FEC_2_3, FEC_3_4, FEC_5_6,
1558 FEC_8_9, FEC_9_10, FEC_2_3, FEC_3_4,
1559 FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10,
1560 FEC_3_4, FEC_4_5, FEC_5_6, FEC_8_9,
1561 FEC_9_10
1562 };
1563 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp);
1564 mc = ((tmp & 0x7c) >> 2);
1565 p->pilot = (tmp & 0x01) ? PILOT_ON : PILOT_OFF;
1566 p->modulation = modcod2mod[mc];
1567 p->fec_inner = modcod2fec[mc];
1568 } else if (state->receive_mode == RCVMODE_DVBS) {
1569 read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp);
1570 switch (tmp & 0x1F) {
1571 case 0x0d:
1572 p->fec_inner = FEC_1_2;
1573 break;
1574 case 0x12:
1575 p->fec_inner = FEC_2_3;
1576 break;
1577 case 0x15:
1578 p->fec_inner = FEC_3_4;
1579 break;
1580 case 0x18:
1581 p->fec_inner = FEC_5_6;
1582 break;
1583 case 0x1a:
1584 p->fec_inner = FEC_7_8;
1585 break;
1586 default:
1587 p->fec_inner = FEC_NONE;
1588 break;
1589 }
1590 p->rolloff = ROLLOFF_35;
1591 }
1592
0b885ded
DS		 1593 if (state->receive_mode != RCVMODE_NONE) {
1594 get_cur_symbol_rate(state, &symbolrate);
1595 p->symbol_rate = symbolrate;
1596 }
cd21b334
DS		 1597 return 0;
1598}
1599
1600static int tune(struct dvb_frontend *fe, bool re_tune,
1601 unsigned int mode_flags,
1602 unsigned int *delay, enum fe_status *status)
1603{
1604 struct stv *state = fe->demodulator_priv;
1605 int r;
1606
1607 if (re_tune) {
1608 r = set_parameters(fe);
1609 if (r)
1610 return r;
1611 state->tune_time = jiffies;
1612 }
cd21b334
DS		 1613
1614 r = read_status(fe, status);
1615 if (r)
1616 return r;
f0e72c29
DS		 1617
1618 if (*status & FE_HAS_LOCK)
1619 return 0;
1620 *delay = HZ;
1621
cd21b334
DS		 1622 return 0;
1623}
1624
cd21b334
DS		 1625static int get_algo(struct dvb_frontend *fe)
1626{
1627 return DVBFE_ALGO_HW;
1628}
1629
1630static int set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
1631{
1632 struct stv *state = fe->demodulator_priv;
1633 u16 offs = state->nr ? 0x40 : 0;
1634
1635 switch (tone) {
1636 case SEC_TONE_ON:
1637 return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x38);
1638 case SEC_TONE_OFF:
1639 return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3a);
1640 default:
1641 break;
1642 }
1643 return -EINVAL;
1644}
1645
1646static int wait_dis(struct stv *state, u8 flag, u8 val)
1647{
1648 int i;
1649 u8 stat;
1650 u16 offs = state->nr ? 0x40 : 0;
1651
1652 for (i = 0; i < 10; i++) {
1653 read_reg(state, RSTV0910_P1_DISTXSTATUS + offs, &stat);
1654 if ((stat & flag) == val)
1655 return 0;
1656 usleep_range(10000, 11000);
1657 }
1658 return -ETIMEDOUT;
1659}
1660
1661static int send_master_cmd(struct dvb_frontend *fe,
1662 struct dvb_diseqc_master_cmd *cmd)
1663{
1664 struct stv *state = fe->demodulator_priv;
1665 u16 offs = state->nr ? 0x40 : 0;
1666 int i;
1667
1668 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3E);
1669 for (i = 0; i < cmd->msg_len; i++) {
1670 wait_dis(state, 0x40, 0x00);
1671 write_reg(state, RSTV0910_P1_DISTXFIFO + offs, cmd->msg[i]);
1672 }
1673 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A);
1674 wait_dis(state, 0x20, 0x20);
1675 return 0;
1676}
1677
448461af
DS		 1678static int send_burst(struct dvb_frontend *fe, enum fe_sec_mini_cmd burst)
1679{
1680 struct stv *state = fe->demodulator_priv;
1681 u16 offs = state->nr ? 0x40 : 0;
1682 u8 value;
1683
1684 if (burst == SEC_MINI_A) {
1685 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3F);
1686 value = 0x00;
1687 } else {
1688 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3E);
1689 value = 0xFF;
1690 }
1691 wait_dis(state, 0x40, 0x00);
1692 write_reg(state, RSTV0910_P1_DISTXFIFO + offs, value);
1693 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A);
1694 wait_dis(state, 0x20, 0x20);
1695
1696 return 0;
1697}
1698
cd21b334
DS		 1699static int sleep(struct dvb_frontend *fe)
1700{
1701 struct stv *state = fe->demodulator_priv;
1702
1703 stop(state);
1704 return 0;
1705}
1706
20e671df 1707static const struct dvb_frontend_ops stv0910_ops = {
cd21b334
DS		 1708 .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
1709 .info = {
20e671df 1710 .name = "ST STV0910",
cd21b334
DS		 1711 .frequency_min = 950000,
1712 .frequency_max = 2150000,
1713 .frequency_stepsize = 0,
1714 .frequency_tolerance = 0,
e5d9ce4d 1715 .symbol_rate_min = 100000,
cd21b334
DS		 1716 .symbol_rate_max = 70000000,
1717 .caps = FE_CAN_INVERSION_AUTO |
1718 FE_CAN_FEC_AUTO |
1719 FE_CAN_QPSK |
ea71c62b
DS		 1720 FE_CAN_2G_MODULATION |
1721 FE_CAN_MULTISTREAM
cd21b334
DS		 1722 },
1723 .sleep = sleep,
4f979d5c
DS		 1724 .release = release,
1725 .i2c_gate_ctrl = gate_ctrl,
2f4675c0 1726 .set_frontend = set_parameters,
4f979d5c
DS		 1727 .get_frontend_algo = get_algo,
1728 .get_frontend = get_frontend,
1729 .tune = tune,
cd21b334
DS		 1730 .read_status = read_status,
1731 .set_tone = set_tone,
1732
1733 .diseqc_send_master_cmd = send_master_cmd,
4f979d5c 1734 .diseqc_send_burst = send_burst,
cd21b334
DS		 1735};
1736
ddb6a90d 1737static struct stv_base *match_base(struct i2c_adapter *i2c, u8 adr)
cd21b334
DS		 1738{
1739 struct stv_base *p;
1740
1741 list_for_each_entry(p, &stvlist, stvlist)
1742 if (p->i2c == i2c && p->adr == adr)
1743 return p;
1744 return NULL;
1745}
1746
1747static void stv0910_init_stats(struct stv *state)
1748{
1749 struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
1750
1751 p->strength.len = 1;
1752 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1753 p->cnr.len = 1;
1754 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1755 p->pre_bit_error.len = 1;
1756 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1757 p->pre_bit_count.len = 1;
1758 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1759}
1760
1761struct dvb_frontend *stv0910_attach(struct i2c_adapter *i2c,
1762 struct stv0910_cfg *cfg,
1763 int nr)
1764{
1765 struct stv *state;
1766 struct stv_base *base;
1767
ddb6a90d 1768 state = kzalloc(sizeof(*state), GFP_KERNEL);
cd21b334
DS		 1769 if (!state)
1770 return NULL;
1771
1772 state->tscfgh = 0x20 | (cfg->parallel ? 0 : 0x40);
1773 state->tsgeneral = (cfg->parallel == 2) ? 0x02 : 0x00;
1774 state->i2crpt = 0x0A | ((cfg->rptlvl & 0x07) << 4);
1775 state->tsspeed = 0x28;
1776 state->nr = nr;
1777 state->regoff = state->nr ? 0 : 0x200;
1778 state->search_range = 16000000;
4f979d5c
DS		 1779 state->demod_bits = 0x10; /* Inversion : Auto with reset to 0 */
1780 state->receive_mode = RCVMODE_NONE;
ea71c62b 1781 state->cur_scrambling_code = (~0U);
cd21b334
DS		 1782 state->single = cfg->single ? 1 : 0;
1783
1784 base = match_base(i2c, cfg->adr);
1785 if (base) {
1786 base->count++;
1787 state->base = base;
1788 } else {
ddb6a90d 1789 base = kzalloc(sizeof(*base), GFP_KERNEL);
cd21b334
DS		 1790 if (!base)
1791 goto fail;
1792 base->i2c = i2c;
1793 base->adr = cfg->adr;
1794 base->count = 1;
1795 base->extclk = cfg->clk ? cfg->clk : 30000000;
1796
1797 mutex_init(&base->i2c_lock);
1798 mutex_init(&base->reg_lock);
1799 state->base = base;
1800 if (probe(state) < 0) {
1801 dev_info(&i2c->dev, "No demod found at adr %02X on %s\n",
ddb6a90d 1802 cfg->adr, dev_name(&i2c->dev));
cd21b334
DS		 1803 kfree(base);
1804 goto fail;
1805 }
1806 list_add(&base->stvlist, &stvlist);
1807 }
4f979d5c
DS		 1808 state->fe.ops = stv0910_ops;
1809 state->fe.demodulator_priv = state;
cd21b334
DS		 1810 state->nr = nr;
1811
1812 dev_info(&i2c->dev, "%s demod found at adr %02X on %s\n",
ddb6a90d 1813 state->fe.ops.info.name, cfg->adr, dev_name(&i2c->dev));
cd21b334
DS		 1814
1815 stv0910_init_stats(state);
1816
1817 return &state->fe;
1818
1819fail:
1820 kfree(state);
1821 return NULL;
1822}
1823EXPORT_SYMBOL_GPL(stv0910_attach);
1824
1825MODULE_DESCRIPTION("ST STV0910 multistandard frontend driver");
1826MODULE_AUTHOR("Ralph and Marcus Metzler, Manfred Voelkel");
1827MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)