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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
17cce932 IL |
2 | /* |
3 | * stv0367.c | |
4 | * | |
5 | * Driver for ST STV0367 DVB-T & DVB-C demodulator IC. | |
6 | * | |
7 | * Copyright (C) ST Microelectronics. | |
8 | * Copyright (C) 2010,2011 NetUP Inc. | |
9 | * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru> | |
17cce932 IL |
10 | */ |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/string.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/i2c.h> | |
17 | ||
fada1935 | 18 | #include <media/dvb_math.h> |
d394ad12 | 19 | |
17cce932 | 20 | #include "stv0367.h" |
8881ceb8 | 21 | #include "stv0367_defs.h" |
17cce932 IL |
22 | #include "stv0367_regs.h" |
23 | #include "stv0367_priv.h" | |
24 | ||
9aca4fb0 MCC |
25 | /* Max transfer size done by I2C transfer functions */ |
26 | #define MAX_XFER_SIZE 64 | |
27 | ||
17cce932 IL |
28 | static int stvdebug; |
29 | module_param_named(debug, stvdebug, int, 0644); | |
30 | ||
31 | static int i2cdebug; | |
32 | module_param_named(i2c_debug, i2cdebug, int, 0644); | |
33 | ||
34 | #define dprintk(args...) \ | |
35 | do { \ | |
36 | if (stvdebug) \ | |
37 | printk(KERN_DEBUG args); \ | |
38 | } while (0) | |
39 | /* DVB-C */ | |
40 | ||
dbbac11e DS |
41 | enum active_demod_state { demod_none, demod_ter, demod_cab }; |
42 | ||
17cce932 IL |
43 | struct stv0367cab_state { |
44 | enum stv0367_cab_signal_type state; | |
45 | u32 mclk; | |
46 | u32 adc_clk; | |
47 | s32 search_range; | |
48 | s32 derot_offset; | |
49 | /* results */ | |
50 | int locked; /* channel found */ | |
51 | u32 freq_khz; /* found frequency (in kHz) */ | |
52 | u32 symbol_rate; /* found symbol rate (in Bds) */ | |
0df289a2 | 53 | enum fe_spectral_inversion spect_inv; /* Spectrum Inversion */ |
cae7a901 | 54 | u32 qamfec_status_reg; /* status reg to poll for FEC Lock */ |
17cce932 IL |
55 | }; |
56 | ||
57 | struct stv0367ter_state { | |
58 | /* DVB-T */ | |
59 | enum stv0367_ter_signal_type state; | |
60 | enum stv0367_ter_if_iq_mode if_iq_mode; | |
61 | enum stv0367_ter_mode mode;/* mode 2K or 8K */ | |
0df289a2 | 62 | enum fe_guard_interval guard; |
17cce932 IL |
63 | enum stv0367_ter_hierarchy hierarchy; |
64 | u32 frequency; | |
0df289a2 | 65 | enum fe_spectral_inversion sense; /* current search spectrum */ |
17cce932 IL |
66 | u8 force; /* force mode/guard */ |
67 | u8 bw; /* channel width 6, 7 or 8 in MHz */ | |
68 | u8 pBW; /* channel width used during previous lock */ | |
69 | u32 pBER; | |
70 | u32 pPER; | |
71 | u32 ucblocks; | |
72 | s8 echo_pos; /* echo position */ | |
73 | u8 first_lock; | |
74 | u8 unlock_counter; | |
75 | u32 agc_val; | |
76 | }; | |
77 | ||
78 | struct stv0367_state { | |
79 | struct dvb_frontend fe; | |
80 | struct i2c_adapter *i2c; | |
81 | /* config settings */ | |
82 | const struct stv0367_config *config; | |
83 | u8 chip_id; | |
84 | /* DVB-C */ | |
85 | struct stv0367cab_state *cab_state; | |
86 | /* DVB-T */ | |
87 | struct stv0367ter_state *ter_state; | |
f61c2991 DS |
88 | /* flags for operation control */ |
89 | u8 use_i2c_gatectrl; | |
8881ceb8 | 90 | u8 deftabs; |
7718dcf0 | 91 | u8 reinit_on_setfrontend; |
b16338e3 | 92 | u8 auto_if_khz; |
dbbac11e | 93 | enum active_demod_state activedemod; |
17cce932 IL |
94 | }; |
95 | ||
96 | #define RF_LOOKUP_TABLE_SIZE 31 | |
97 | #define RF_LOOKUP_TABLE2_SIZE 16 | |
98 | /* RF Level (for RF AGC->AGC1) Lookup Table, depends on the board and tuner.*/ | |
817d2fd4 | 99 | static const s32 stv0367cab_RF_LookUp1[RF_LOOKUP_TABLE_SIZE][RF_LOOKUP_TABLE_SIZE] = { |
17cce932 IL |
100 | {/*AGC1*/ |
101 | 48, 50, 51, 53, 54, 56, 57, 58, 60, 61, 62, 63, | |
102 | 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, | |
103 | 76, 77, 78, 80, 83, 85, 88, | |
104 | }, {/*RF(dbm)*/ | |
105 | 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, | |
106 | 34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 46, 47, | |
107 | 49, 50, 52, 53, 54, 55, 56, | |
108 | } | |
109 | }; | |
110 | /* RF Level (for IF AGC->AGC2) Lookup Table, depends on the board and tuner.*/ | |
817d2fd4 | 111 | static const s32 stv0367cab_RF_LookUp2[RF_LOOKUP_TABLE2_SIZE][RF_LOOKUP_TABLE2_SIZE] = { |
17cce932 IL |
112 | {/*AGC2*/ |
113 | 28, 29, 31, 32, 34, 35, 36, 37, | |
114 | 38, 39, 40, 41, 42, 43, 44, 45, | |
115 | }, {/*RF(dbm)*/ | |
116 | 57, 58, 59, 60, 61, 62, 63, 64, | |
117 | 65, 66, 67, 68, 69, 70, 71, 72, | |
118 | } | |
119 | }; | |
120 | ||
17cce932 IL |
121 | static |
122 | int stv0367_writeregs(struct stv0367_state *state, u16 reg, u8 *data, int len) | |
123 | { | |
9aca4fb0 | 124 | u8 buf[MAX_XFER_SIZE]; |
17cce932 IL |
125 | struct i2c_msg msg = { |
126 | .addr = state->config->demod_address, | |
127 | .flags = 0, | |
128 | .buf = buf, | |
129 | .len = len + 2 | |
130 | }; | |
131 | int ret; | |
132 | ||
9aca4fb0 MCC |
133 | if (2 + len > sizeof(buf)) { |
134 | printk(KERN_WARNING | |
135 | "%s: i2c wr reg=%04x: len=%d is too big!\n", | |
136 | KBUILD_MODNAME, reg, len); | |
137 | return -EINVAL; | |
138 | } | |
139 | ||
140 | ||
17cce932 IL |
141 | buf[0] = MSB(reg); |
142 | buf[1] = LSB(reg); | |
143 | memcpy(buf + 2, data, len); | |
144 | ||
145 | if (i2cdebug) | |
86a10283 PG |
146 | printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__, |
147 | state->config->demod_address, reg, buf[2]); | |
17cce932 IL |
148 | |
149 | ret = i2c_transfer(state->i2c, &msg, 1); | |
150 | if (ret != 1) | |
86a10283 PG |
151 | printk(KERN_ERR "%s: i2c write error! ([%02x] %02x: %02x)\n", |
152 | __func__, state->config->demod_address, reg, buf[2]); | |
17cce932 IL |
153 | |
154 | return (ret != 1) ? -EREMOTEIO : 0; | |
155 | } | |
156 | ||
157 | static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data) | |
158 | { | |
3cd890db AB |
159 | u8 tmp = data; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ |
160 | ||
161 | return stv0367_writeregs(state, reg, &tmp, 1); | |
17cce932 IL |
162 | } |
163 | ||
164 | static u8 stv0367_readreg(struct stv0367_state *state, u16 reg) | |
165 | { | |
166 | u8 b0[] = { 0, 0 }; | |
167 | u8 b1[] = { 0 }; | |
168 | struct i2c_msg msg[] = { | |
169 | { | |
170 | .addr = state->config->demod_address, | |
171 | .flags = 0, | |
172 | .buf = b0, | |
173 | .len = 2 | |
174 | }, { | |
175 | .addr = state->config->demod_address, | |
176 | .flags = I2C_M_RD, | |
177 | .buf = b1, | |
178 | .len = 1 | |
179 | } | |
180 | }; | |
181 | int ret; | |
182 | ||
183 | b0[0] = MSB(reg); | |
184 | b0[1] = LSB(reg); | |
185 | ||
186 | ret = i2c_transfer(state->i2c, msg, 2); | |
187 | if (ret != 2) | |
86a10283 PG |
188 | printk(KERN_ERR "%s: i2c read error ([%02x] %02x: %02x)\n", |
189 | __func__, state->config->demod_address, reg, b1[0]); | |
17cce932 IL |
190 | |
191 | if (i2cdebug) | |
86a10283 PG |
192 | printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__, |
193 | state->config->demod_address, reg, b1[0]); | |
17cce932 IL |
194 | |
195 | return b1[0]; | |
196 | } | |
197 | ||
198 | static void extract_mask_pos(u32 label, u8 *mask, u8 *pos) | |
199 | { | |
200 | u8 position = 0, i = 0; | |
201 | ||
202 | (*mask) = label & 0xff; | |
203 | ||
204 | while ((position == 0) && (i < 8)) { | |
205 | position = ((*mask) >> i) & 0x01; | |
206 | i++; | |
207 | } | |
208 | ||
209 | (*pos) = (i - 1); | |
210 | } | |
211 | ||
212 | static void stv0367_writebits(struct stv0367_state *state, u32 label, u8 val) | |
213 | { | |
214 | u8 reg, mask, pos; | |
215 | ||
216 | reg = stv0367_readreg(state, (label >> 16) & 0xffff); | |
217 | extract_mask_pos(label, &mask, &pos); | |
218 | ||
219 | val = mask & (val << pos); | |
220 | ||
221 | reg = (reg & (~mask)) | val; | |
222 | stv0367_writereg(state, (label >> 16) & 0xffff, reg); | |
223 | ||
224 | } | |
225 | ||
226 | static void stv0367_setbits(u8 *reg, u32 label, u8 val) | |
227 | { | |
228 | u8 mask, pos; | |
229 | ||
230 | extract_mask_pos(label, &mask, &pos); | |
231 | ||
232 | val = mask & (val << pos); | |
233 | ||
234 | (*reg) = ((*reg) & (~mask)) | val; | |
235 | } | |
236 | ||
237 | static u8 stv0367_readbits(struct stv0367_state *state, u32 label) | |
238 | { | |
239 | u8 val = 0xff; | |
240 | u8 mask, pos; | |
241 | ||
242 | extract_mask_pos(label, &mask, &pos); | |
243 | ||
244 | val = stv0367_readreg(state, label >> 16); | |
245 | val = (val & mask) >> pos; | |
246 | ||
247 | return val; | |
248 | } | |
249 | ||
8c8ca1c7 MCC |
250 | #if 0 /* Currently, unused */ |
251 | static u8 stv0367_getbits(u8 reg, u32 label) | |
17cce932 IL |
252 | { |
253 | u8 mask, pos; | |
254 | ||
255 | extract_mask_pos(label, &mask, &pos); | |
256 | ||
257 | return (reg & mask) >> pos; | |
258 | } | |
8c8ca1c7 | 259 | #endif |
41727cbb DS |
260 | |
261 | static void stv0367_write_table(struct stv0367_state *state, | |
262 | const struct st_register *deftab) | |
263 | { | |
264 | int i = 0; | |
265 | ||
266 | while (1) { | |
267 | if (!deftab[i].addr) | |
268 | break; | |
269 | stv0367_writereg(state, deftab[i].addr, deftab[i].value); | |
270 | i++; | |
271 | } | |
272 | } | |
273 | ||
8a9c0735 DS |
274 | static void stv0367_pll_setup(struct stv0367_state *state, |
275 | u32 icspeed, u32 xtal) | |
276 | { | |
277 | /* note on regs: R367TER_* and R367CAB_* defines each point to | |
278 | * 0xf0d8, so just use R367TER_ for both cases | |
279 | */ | |
280 | ||
281 | switch (icspeed) { | |
282 | case STV0367_ICSPEED_58000: | |
283 | switch (xtal) { | |
284 | default: | |
285 | case 27000000: | |
286 | dprintk("STV0367 SetCLKgen for 58MHz IC and 27Mhz crystal\n"); | |
287 | /* PLLMDIV: 27, PLLNDIV: 232 */ | |
288 | stv0367_writereg(state, R367TER_PLLMDIV, 0x1b); | |
289 | stv0367_writereg(state, R367TER_PLLNDIV, 0xe8); | |
290 | break; | |
291 | } | |
292 | break; | |
293 | default: | |
294 | case STV0367_ICSPEED_53125: | |
295 | switch (xtal) { | |
296 | /* set internal freq to 53.125MHz */ | |
297 | case 16000000: | |
298 | stv0367_writereg(state, R367TER_PLLMDIV, 0x2); | |
299 | stv0367_writereg(state, R367TER_PLLNDIV, 0x1b); | |
300 | break; | |
301 | case 25000000: | |
302 | stv0367_writereg(state, R367TER_PLLMDIV, 0xa); | |
303 | stv0367_writereg(state, R367TER_PLLNDIV, 0x55); | |
304 | break; | |
305 | default: | |
306 | case 27000000: | |
307 | dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n"); | |
308 | stv0367_writereg(state, R367TER_PLLMDIV, 0x1); | |
309 | stv0367_writereg(state, R367TER_PLLNDIV, 0x8); | |
310 | break; | |
311 | case 30000000: | |
312 | stv0367_writereg(state, R367TER_PLLMDIV, 0xc); | |
313 | stv0367_writereg(state, R367TER_PLLNDIV, 0x55); | |
314 | break; | |
315 | } | |
316 | } | |
317 | ||
318 | stv0367_writereg(state, R367TER_PLLSETUP, 0x18); | |
319 | } | |
320 | ||
b16338e3 DS |
321 | static int stv0367_get_if_khz(struct stv0367_state *state, u32 *ifkhz) |
322 | { | |
323 | if (state->auto_if_khz && state->fe.ops.tuner_ops.get_if_frequency) { | |
324 | state->fe.ops.tuner_ops.get_if_frequency(&state->fe, ifkhz); | |
325 | *ifkhz = *ifkhz / 1000; /* hz -> khz */ | |
326 | } else | |
327 | *ifkhz = state->config->if_khz; | |
328 | ||
329 | return 0; | |
330 | } | |
331 | ||
17cce932 IL |
332 | static int stv0367ter_gate_ctrl(struct dvb_frontend *fe, int enable) |
333 | { | |
334 | struct stv0367_state *state = fe->demodulator_priv; | |
335 | u8 tmp = stv0367_readreg(state, R367TER_I2CRPT); | |
336 | ||
337 | dprintk("%s:\n", __func__); | |
338 | ||
339 | if (enable) { | |
340 | stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 0); | |
341 | stv0367_setbits(&tmp, F367TER_I2CT_ON, 1); | |
342 | } else { | |
343 | stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 1); | |
344 | stv0367_setbits(&tmp, F367TER_I2CT_ON, 0); | |
345 | } | |
346 | ||
347 | stv0367_writereg(state, R367TER_I2CRPT, tmp); | |
348 | ||
349 | return 0; | |
350 | } | |
351 | ||
352 | static u32 stv0367_get_tuner_freq(struct dvb_frontend *fe) | |
353 | { | |
20721185 EG |
354 | struct dvb_frontend_ops *frontend_ops = &fe->ops; |
355 | struct dvb_tuner_ops *tuner_ops = &frontend_ops->tuner_ops; | |
17cce932 | 356 | u32 freq = 0; |
bf512b2d | 357 | int err = 0; |
17cce932 IL |
358 | |
359 | dprintk("%s:\n", __func__); | |
360 | ||
17cce932 IL |
361 | if (tuner_ops->get_frequency) { |
362 | err = tuner_ops->get_frequency(fe, &freq); | |
363 | if (err < 0) { | |
364 | printk(KERN_ERR "%s: Invalid parameter\n", __func__); | |
365 | return err; | |
366 | } | |
367 | ||
368 | dprintk("%s: frequency=%d\n", __func__, freq); | |
369 | ||
370 | } else | |
371 | return -1; | |
372 | ||
373 | return freq; | |
374 | } | |
375 | ||
376 | static u16 CellsCoeffs_8MHz_367cofdm[3][6][5] = { | |
377 | { | |
378 | {0x10EF, 0xE205, 0x10EF, 0xCE49, 0x6DA7}, /* CELL 1 COEFFS 27M*/ | |
379 | {0x2151, 0xc557, 0x2151, 0xc705, 0x6f93}, /* CELL 2 COEFFS */ | |
380 | {0x2503, 0xc000, 0x2503, 0xc375, 0x7194}, /* CELL 3 COEFFS */ | |
381 | {0x20E9, 0xca94, 0x20e9, 0xc153, 0x7194}, /* CELL 4 COEFFS */ | |
382 | {0x06EF, 0xF852, 0x06EF, 0xC057, 0x7207}, /* CELL 5 COEFFS */ | |
383 | {0x0000, 0x0ECC, 0x0ECC, 0x0000, 0x3647} /* CELL 6 COEFFS */ | |
384 | }, { | |
385 | {0x10A0, 0xE2AF, 0x10A1, 0xCE76, 0x6D6D}, /* CELL 1 COEFFS 25M*/ | |
386 | {0x20DC, 0xC676, 0x20D9, 0xC80A, 0x6F29}, | |
387 | {0x2532, 0xC000, 0x251D, 0xC391, 0x706F}, | |
388 | {0x1F7A, 0xCD2B, 0x2032, 0xC15E, 0x711F}, | |
389 | {0x0698, 0xFA5E, 0x0568, 0xC059, 0x7193}, | |
390 | {0x0000, 0x0918, 0x149C, 0x0000, 0x3642} /* CELL 6 COEFFS */ | |
391 | }, { | |
392 | {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */ | |
393 | {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, | |
394 | {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, | |
395 | {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, | |
396 | {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, | |
397 | {0x0000, 0x0000, 0x0000, 0x0000, 0x0000} | |
398 | } | |
399 | }; | |
400 | ||
401 | static u16 CellsCoeffs_7MHz_367cofdm[3][6][5] = { | |
402 | { | |
403 | {0x12CA, 0xDDAF, 0x12CA, 0xCCEB, 0x6FB1}, /* CELL 1 COEFFS 27M*/ | |
404 | {0x2329, 0xC000, 0x2329, 0xC6B0, 0x725F}, /* CELL 2 COEFFS */ | |
405 | {0x2394, 0xC000, 0x2394, 0xC2C7, 0x7410}, /* CELL 3 COEFFS */ | |
406 | {0x251C, 0xC000, 0x251C, 0xC103, 0x74D9}, /* CELL 4 COEFFS */ | |
407 | {0x0804, 0xF546, 0x0804, 0xC040, 0x7544}, /* CELL 5 COEFFS */ | |
408 | {0x0000, 0x0CD9, 0x0CD9, 0x0000, 0x370A} /* CELL 6 COEFFS */ | |
409 | }, { | |
410 | {0x1285, 0xDE47, 0x1285, 0xCD17, 0x6F76}, /*25M*/ | |
411 | {0x234C, 0xC000, 0x2348, 0xC6DA, 0x7206}, | |
412 | {0x23B4, 0xC000, 0x23AC, 0xC2DB, 0x73B3}, | |
413 | {0x253D, 0xC000, 0x25B6, 0xC10B, 0x747F}, | |
414 | {0x0721, 0xF79C, 0x065F, 0xC041, 0x74EB}, | |
415 | {0x0000, 0x08FA, 0x1162, 0x0000, 0x36FF} | |
416 | }, { | |
417 | {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */ | |
418 | {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, | |
419 | {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, | |
420 | {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, | |
421 | {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, | |
422 | {0x0000, 0x0000, 0x0000, 0x0000, 0x0000} | |
423 | } | |
424 | }; | |
425 | ||
426 | static u16 CellsCoeffs_6MHz_367cofdm[3][6][5] = { | |
427 | { | |
428 | {0x1699, 0xD5B8, 0x1699, 0xCBC3, 0x713B}, /* CELL 1 COEFFS 27M*/ | |
429 | {0x2245, 0xC000, 0x2245, 0xC568, 0x74D5}, /* CELL 2 COEFFS */ | |
430 | {0x227F, 0xC000, 0x227F, 0xC1FC, 0x76C6}, /* CELL 3 COEFFS */ | |
431 | {0x235E, 0xC000, 0x235E, 0xC0A7, 0x778A}, /* CELL 4 COEFFS */ | |
432 | {0x0ECB, 0xEA0B, 0x0ECB, 0xC027, 0x77DD}, /* CELL 5 COEFFS */ | |
433 | {0x0000, 0x0B68, 0x0B68, 0x0000, 0xC89A}, /* CELL 6 COEFFS */ | |
434 | }, { | |
435 | {0x1655, 0xD64E, 0x1658, 0xCBEF, 0x70FE}, /*25M*/ | |
436 | {0x225E, 0xC000, 0x2256, 0xC589, 0x7489}, | |
437 | {0x2293, 0xC000, 0x2295, 0xC209, 0x767E}, | |
438 | {0x2377, 0xC000, 0x23AA, 0xC0AB, 0x7746}, | |
439 | {0x0DC7, 0xEBC8, 0x0D07, 0xC027, 0x7799}, | |
440 | {0x0000, 0x0888, 0x0E9C, 0x0000, 0x3757} | |
441 | ||
442 | }, { | |
443 | {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */ | |
444 | {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, | |
445 | {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, | |
446 | {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, | |
447 | {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, | |
448 | {0x0000, 0x0000, 0x0000, 0x0000, 0x0000} | |
449 | } | |
450 | }; | |
451 | ||
452 | static u32 stv0367ter_get_mclk(struct stv0367_state *state, u32 ExtClk_Hz) | |
453 | { | |
454 | u32 mclk_Hz = 0; /* master clock frequency (Hz) */ | |
455 | u32 m, n, p; | |
456 | ||
457 | dprintk("%s:\n", __func__); | |
458 | ||
459 | if (stv0367_readbits(state, F367TER_BYPASS_PLLXN) == 0) { | |
460 | n = (u32)stv0367_readbits(state, F367TER_PLL_NDIV); | |
461 | if (n == 0) | |
462 | n = n + 1; | |
463 | ||
464 | m = (u32)stv0367_readbits(state, F367TER_PLL_MDIV); | |
465 | if (m == 0) | |
466 | m = m + 1; | |
467 | ||
468 | p = (u32)stv0367_readbits(state, F367TER_PLL_PDIV); | |
469 | if (p > 5) | |
470 | p = 5; | |
471 | ||
472 | mclk_Hz = ((ExtClk_Hz / 2) * n) / (m * (1 << p)); | |
473 | ||
474 | dprintk("N=%d M=%d P=%d mclk_Hz=%d ExtClk_Hz=%d\n", | |
475 | n, m, p, mclk_Hz, ExtClk_Hz); | |
476 | } else | |
477 | mclk_Hz = ExtClk_Hz; | |
478 | ||
479 | dprintk("%s: mclk_Hz=%d\n", __func__, mclk_Hz); | |
480 | ||
481 | return mclk_Hz; | |
482 | } | |
483 | ||
484 | static int stv0367ter_filt_coeff_init(struct stv0367_state *state, | |
bc4b18c6 | 485 | u16 CellsCoeffs[3][6][5], u32 DemodXtal) |
17cce932 IL |
486 | { |
487 | int i, j, k, freq; | |
488 | ||
489 | dprintk("%s:\n", __func__); | |
490 | ||
491 | freq = stv0367ter_get_mclk(state, DemodXtal); | |
492 | ||
493 | if (freq == 53125000) | |
494 | k = 1; /* equivalent to Xtal 25M on 362*/ | |
495 | else if (freq == 54000000) | |
496 | k = 0; /* equivalent to Xtal 27M on 362*/ | |
497 | else if (freq == 52500000) | |
498 | k = 2; /* equivalent to Xtal 30M on 362*/ | |
499 | else | |
500 | return 0; | |
501 | ||
502 | for (i = 1; i <= 6; i++) { | |
503 | stv0367_writebits(state, F367TER_IIR_CELL_NB, i - 1); | |
504 | ||
505 | for (j = 1; j <= 5; j++) { | |
506 | stv0367_writereg(state, | |
507 | (R367TER_IIRCX_COEFF1_MSB + 2 * (j - 1)), | |
508 | MSB(CellsCoeffs[k][i-1][j-1])); | |
509 | stv0367_writereg(state, | |
510 | (R367TER_IIRCX_COEFF1_LSB + 2 * (j - 1)), | |
511 | LSB(CellsCoeffs[k][i-1][j-1])); | |
512 | } | |
513 | } | |
514 | ||
515 | return 1; | |
516 | ||
517 | } | |
518 | ||
519 | static void stv0367ter_agc_iir_lock_detect_set(struct stv0367_state *state) | |
520 | { | |
521 | dprintk("%s:\n", __func__); | |
522 | ||
523 | stv0367_writebits(state, F367TER_LOCK_DETECT_LSB, 0x00); | |
524 | ||
525 | /* Lock detect 1 */ | |
526 | stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x00); | |
527 | stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06); | |
528 | stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04); | |
529 | ||
530 | /* Lock detect 2 */ | |
531 | stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x01); | |
532 | stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06); | |
533 | stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04); | |
534 | ||
535 | /* Lock detect 3 */ | |
536 | stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x02); | |
537 | stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01); | |
538 | stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00); | |
539 | ||
540 | /* Lock detect 4 */ | |
541 | stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x03); | |
542 | stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01); | |
543 | stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00); | |
544 | ||
545 | } | |
546 | ||
547 | static int stv0367_iir_filt_init(struct stv0367_state *state, u8 Bandwidth, | |
548 | u32 DemodXtalValue) | |
549 | { | |
550 | dprintk("%s:\n", __func__); | |
551 | ||
552 | stv0367_writebits(state, F367TER_NRST_IIR, 0); | |
553 | ||
554 | switch (Bandwidth) { | |
555 | case 6: | |
556 | if (!stv0367ter_filt_coeff_init(state, | |
557 | CellsCoeffs_6MHz_367cofdm, | |
558 | DemodXtalValue)) | |
559 | return 0; | |
560 | break; | |
561 | case 7: | |
562 | if (!stv0367ter_filt_coeff_init(state, | |
563 | CellsCoeffs_7MHz_367cofdm, | |
564 | DemodXtalValue)) | |
565 | return 0; | |
566 | break; | |
567 | case 8: | |
568 | if (!stv0367ter_filt_coeff_init(state, | |
569 | CellsCoeffs_8MHz_367cofdm, | |
570 | DemodXtalValue)) | |
571 | return 0; | |
572 | break; | |
573 | default: | |
574 | return 0; | |
575 | } | |
576 | ||
577 | stv0367_writebits(state, F367TER_NRST_IIR, 1); | |
578 | ||
579 | return 1; | |
580 | } | |
581 | ||
582 | static void stv0367ter_agc_iir_rst(struct stv0367_state *state) | |
583 | { | |
584 | ||
585 | u8 com_n; | |
586 | ||
587 | dprintk("%s:\n", __func__); | |
588 | ||
589 | com_n = stv0367_readbits(state, F367TER_COM_N); | |
590 | ||
591 | stv0367_writebits(state, F367TER_COM_N, 0x07); | |
592 | ||
593 | stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x00); | |
594 | stv0367_writebits(state, F367TER_COM_AGC_ON, 0x00); | |
595 | ||
596 | stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x01); | |
597 | stv0367_writebits(state, F367TER_COM_AGC_ON, 0x01); | |
598 | ||
599 | stv0367_writebits(state, F367TER_COM_N, com_n); | |
600 | ||
601 | } | |
602 | ||
603 | static int stv0367ter_duration(s32 mode, int tempo1, int tempo2, int tempo3) | |
604 | { | |
605 | int local_tempo = 0; | |
606 | switch (mode) { | |
607 | case 0: | |
608 | local_tempo = tempo1; | |
609 | break; | |
610 | case 1: | |
611 | local_tempo = tempo2; | |
612 | break ; | |
613 | ||
614 | case 2: | |
615 | local_tempo = tempo3; | |
616 | break; | |
617 | ||
618 | default: | |
619 | break; | |
620 | } | |
621 | /* msleep(local_tempo); */ | |
622 | return local_tempo; | |
623 | } | |
624 | ||
625 | static enum | |
626 | stv0367_ter_signal_type stv0367ter_check_syr(struct stv0367_state *state) | |
627 | { | |
628 | int wd = 100; | |
629 | unsigned short int SYR_var; | |
630 | s32 SYRStatus; | |
631 | ||
632 | dprintk("%s:\n", __func__); | |
633 | ||
634 | SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK); | |
635 | ||
636 | while ((!SYR_var) && (wd > 0)) { | |
637 | usleep_range(2000, 3000); | |
638 | wd -= 2; | |
639 | SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK); | |
640 | } | |
641 | ||
642 | if (!SYR_var) | |
643 | SYRStatus = FE_TER_NOSYMBOL; | |
644 | else | |
645 | SYRStatus = FE_TER_SYMBOLOK; | |
646 | ||
647 | dprintk("stv0367ter_check_syr SYRStatus %s\n", | |
648 | SYR_var == 0 ? "No Symbol" : "OK"); | |
649 | ||
650 | return SYRStatus; | |
651 | } | |
652 | ||
653 | static enum | |
654 | stv0367_ter_signal_type stv0367ter_check_cpamp(struct stv0367_state *state, | |
655 | s32 FFTmode) | |
656 | { | |
657 | ||
658 | s32 CPAMPvalue = 0, CPAMPStatus, CPAMPMin; | |
659 | int wd = 0; | |
660 | ||
661 | dprintk("%s:\n", __func__); | |
662 | ||
663 | switch (FFTmode) { | |
664 | case 0: /*2k mode*/ | |
665 | CPAMPMin = 20; | |
666 | wd = 10; | |
667 | break; | |
668 | case 1: /*8k mode*/ | |
669 | CPAMPMin = 80; | |
670 | wd = 55; | |
671 | break; | |
672 | case 2: /*4k mode*/ | |
673 | CPAMPMin = 40; | |
674 | wd = 30; | |
675 | break; | |
676 | default: | |
677 | CPAMPMin = 0xffff; /*drives to NOCPAMP */ | |
678 | break; | |
679 | } | |
680 | ||
681 | dprintk("%s: CPAMPMin=%d wd=%d\n", __func__, CPAMPMin, wd); | |
682 | ||
683 | CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT); | |
684 | while ((CPAMPvalue < CPAMPMin) && (wd > 0)) { | |
685 | usleep_range(1000, 2000); | |
686 | wd -= 1; | |
687 | CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT); | |
688 | /*dprintk("CPAMPvalue= %d at wd=%d\n",CPAMPvalue,wd); */ | |
689 | } | |
690 | dprintk("******last CPAMPvalue= %d at wd=%d\n", CPAMPvalue, wd); | |
691 | if (CPAMPvalue < CPAMPMin) { | |
692 | CPAMPStatus = FE_TER_NOCPAMP; | |
df5a38e9 | 693 | dprintk("%s: CPAMP failed\n", __func__); |
17cce932 | 694 | } else { |
df5a38e9 | 695 | dprintk("%s: CPAMP OK !\n", __func__); |
17cce932 IL |
696 | CPAMPStatus = FE_TER_CPAMPOK; |
697 | } | |
698 | ||
699 | return CPAMPStatus; | |
700 | } | |
701 | ||
8c8ca1c7 MCC |
702 | static enum stv0367_ter_signal_type |
703 | stv0367ter_lock_algo(struct stv0367_state *state) | |
17cce932 IL |
704 | { |
705 | enum stv0367_ter_signal_type ret_flag; | |
706 | short int wd, tempo; | |
707 | u8 try, u_var1 = 0, u_var2 = 0, u_var3 = 0, u_var4 = 0, mode, guard; | |
708 | u8 tmp, tmp2; | |
709 | ||
710 | dprintk("%s:\n", __func__); | |
711 | ||
712 | if (state == NULL) | |
713 | return FE_TER_SWNOK; | |
714 | ||
715 | try = 0; | |
716 | do { | |
717 | ret_flag = FE_TER_LOCKOK; | |
718 | ||
719 | stv0367_writebits(state, F367TER_CORE_ACTIVE, 0); | |
720 | ||
721 | if (state->config->if_iq_mode != 0) | |
722 | stv0367_writebits(state, F367TER_COM_N, 0x07); | |
723 | ||
724 | stv0367_writebits(state, F367TER_GUARD, 3);/* suggest 2k 1/4 */ | |
725 | stv0367_writebits(state, F367TER_MODE, 0); | |
726 | stv0367_writebits(state, F367TER_SYR_TR_DIS, 0); | |
727 | usleep_range(5000, 10000); | |
728 | ||
729 | stv0367_writebits(state, F367TER_CORE_ACTIVE, 1); | |
730 | ||
731 | ||
732 | if (stv0367ter_check_syr(state) == FE_TER_NOSYMBOL) | |
733 | return FE_TER_NOSYMBOL; | |
734 | else { /* | |
735 | if chip locked on wrong mode first try, | |
736 | it must lock correctly second try */ | |
737 | mode = stv0367_readbits(state, F367TER_SYR_MODE); | |
738 | if (stv0367ter_check_cpamp(state, mode) == | |
739 | FE_TER_NOCPAMP) { | |
740 | if (try == 0) | |
741 | ret_flag = FE_TER_NOCPAMP; | |
742 | ||
743 | } | |
744 | } | |
745 | ||
746 | try++; | |
747 | } while ((try < 10) && (ret_flag != FE_TER_LOCKOK)); | |
748 | ||
749 | tmp = stv0367_readreg(state, R367TER_SYR_STAT); | |
750 | tmp2 = stv0367_readreg(state, R367TER_STATUS); | |
fb661a78 | 751 | dprintk("state=%p\n", state); |
17cce932 IL |
752 | dprintk("LOCK OK! mode=%d SYR_STAT=0x%x R367TER_STATUS=0x%x\n", |
753 | mode, tmp, tmp2); | |
754 | ||
755 | tmp = stv0367_readreg(state, R367TER_PRVIT); | |
756 | tmp2 = stv0367_readreg(state, R367TER_I2CRPT); | |
757 | dprintk("PRVIT=0x%x I2CRPT=0x%x\n", tmp, tmp2); | |
758 | ||
759 | tmp = stv0367_readreg(state, R367TER_GAIN_SRC1); | |
760 | dprintk("GAIN_SRC1=0x%x\n", tmp); | |
761 | ||
762 | if ((mode != 0) && (mode != 1) && (mode != 2)) | |
763 | return FE_TER_SWNOK; | |
764 | ||
765 | /*guard=stv0367_readbits(state,F367TER_SYR_GUARD); */ | |
766 | ||
25985edc | 767 | /*suppress EPQ auto for SYR_GARD 1/16 or 1/32 |
17cce932 IL |
768 | and set channel predictor in automatic */ |
769 | #if 0 | |
770 | switch (guard) { | |
771 | ||
772 | case 0: | |
773 | case 1: | |
774 | stv0367_writebits(state, F367TER_AUTO_LE_EN, 0); | |
775 | stv0367_writereg(state, R367TER_CHC_CTL, 0x01); | |
776 | break; | |
777 | case 2: | |
778 | case 3: | |
779 | stv0367_writebits(state, F367TER_AUTO_LE_EN, 1); | |
780 | stv0367_writereg(state, R367TER_CHC_CTL, 0x11); | |
781 | break; | |
782 | ||
783 | default: | |
784 | return FE_TER_SWNOK; | |
785 | } | |
786 | #endif | |
787 | ||
788 | /*reset fec an reedsolo FOR 367 only*/ | |
789 | stv0367_writebits(state, F367TER_RST_SFEC, 1); | |
790 | stv0367_writebits(state, F367TER_RST_REEDSOLO, 1); | |
791 | usleep_range(1000, 2000); | |
792 | stv0367_writebits(state, F367TER_RST_SFEC, 0); | |
793 | stv0367_writebits(state, F367TER_RST_REEDSOLO, 0); | |
794 | ||
795 | u_var1 = stv0367_readbits(state, F367TER_LK); | |
796 | u_var2 = stv0367_readbits(state, F367TER_PRF); | |
797 | u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK); | |
798 | /* u_var4=stv0367_readbits(state,F367TER_TSFIFO_LINEOK); */ | |
799 | ||
800 | wd = stv0367ter_duration(mode, 125, 500, 250); | |
801 | tempo = stv0367ter_duration(mode, 4, 16, 8); | |
802 | ||
803 | /*while ( ((!u_var1)||(!u_var2)||(!u_var3)||(!u_var4)) && (wd>=0)) */ | |
804 | while (((!u_var1) || (!u_var2) || (!u_var3)) && (wd >= 0)) { | |
805 | usleep_range(1000 * tempo, 1000 * (tempo + 1)); | |
806 | wd -= tempo; | |
807 | u_var1 = stv0367_readbits(state, F367TER_LK); | |
808 | u_var2 = stv0367_readbits(state, F367TER_PRF); | |
809 | u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK); | |
810 | /*u_var4=stv0367_readbits(state, F367TER_TSFIFO_LINEOK); */ | |
811 | } | |
812 | ||
813 | if (!u_var1) | |
814 | return FE_TER_NOLOCK; | |
815 | ||
816 | ||
817 | if (!u_var2) | |
818 | return FE_TER_NOPRFOUND; | |
819 | ||
820 | if (!u_var3) | |
821 | return FE_TER_NOTPS; | |
822 | ||
823 | guard = stv0367_readbits(state, F367TER_SYR_GUARD); | |
824 | stv0367_writereg(state, R367TER_CHC_CTL, 0x11); | |
825 | switch (guard) { | |
826 | case 0: | |
827 | case 1: | |
828 | stv0367_writebits(state, F367TER_AUTO_LE_EN, 0); | |
829 | /*stv0367_writereg(state,R367TER_CHC_CTL, 0x1);*/ | |
830 | stv0367_writebits(state, F367TER_SYR_FILTER, 0); | |
831 | break; | |
832 | case 2: | |
833 | case 3: | |
834 | stv0367_writebits(state, F367TER_AUTO_LE_EN, 1); | |
835 | /*stv0367_writereg(state,R367TER_CHC_CTL, 0x11);*/ | |
836 | stv0367_writebits(state, F367TER_SYR_FILTER, 1); | |
837 | break; | |
838 | ||
839 | default: | |
840 | return FE_TER_SWNOK; | |
841 | } | |
842 | ||
843 | /* apply Sfec workaround if 8K 64QAM CR!=1/2*/ | |
844 | if ((stv0367_readbits(state, F367TER_TPS_CONST) == 2) && | |
845 | (mode == 1) && | |
846 | (stv0367_readbits(state, F367TER_TPS_HPCODE) != 0)) { | |
847 | stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0); | |
848 | stv0367_writereg(state, R367TER_SFDLYSETM, 0x60); | |
849 | stv0367_writereg(state, R367TER_SFDLYSETL, 0x0); | |
850 | } else | |
851 | stv0367_writereg(state, R367TER_SFDLYSETH, 0x0); | |
852 | ||
853 | wd = stv0367ter_duration(mode, 125, 500, 250); | |
854 | u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK); | |
855 | ||
856 | while ((!u_var4) && (wd >= 0)) { | |
857 | usleep_range(1000 * tempo, 1000 * (tempo + 1)); | |
858 | wd -= tempo; | |
859 | u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK); | |
860 | } | |
861 | ||
862 | if (!u_var4) | |
863 | return FE_TER_NOLOCK; | |
864 | ||
865 | /* for 367 leave COM_N at 0x7 for IQ_mode*/ | |
866 | /*if(ter_state->if_iq_mode!=FE_TER_NORMAL_IF_TUNER) { | |
867 | tempo=0; | |
868 | while ((stv0367_readbits(state,F367TER_COM_USEGAINTRK)!=1) && | |
869 | (stv0367_readbits(state,F367TER_COM_AGCLOCK)!=1)&&(tempo<100)) { | |
870 | ChipWaitOrAbort(state,1); | |
871 | tempo+=1; | |
872 | } | |
873 | ||
874 | stv0367_writebits(state,F367TER_COM_N,0x17); | |
875 | } */ | |
876 | ||
877 | stv0367_writebits(state, F367TER_SYR_TR_DIS, 1); | |
878 | ||
879 | dprintk("FE_TER_LOCKOK !!!\n"); | |
880 | ||
881 | return FE_TER_LOCKOK; | |
882 | ||
883 | } | |
884 | ||
885 | static void stv0367ter_set_ts_mode(struct stv0367_state *state, | |
886 | enum stv0367_ts_mode PathTS) | |
887 | { | |
888 | ||
889 | dprintk("%s:\n", __func__); | |
890 | ||
891 | if (state == NULL) | |
892 | return; | |
893 | ||
894 | stv0367_writebits(state, F367TER_TS_DIS, 0); | |
895 | switch (PathTS) { | |
896 | default: | |
897 | /*for removing warning :default we can assume in parallel mode*/ | |
898 | case STV0367_PARALLEL_PUNCT_CLOCK: | |
899 | stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 0); | |
900 | stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 0); | |
901 | break; | |
902 | case STV0367_SERIAL_PUNCT_CLOCK: | |
903 | stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 1); | |
904 | stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 1); | |
905 | break; | |
906 | } | |
907 | } | |
908 | ||
909 | static void stv0367ter_set_clk_pol(struct stv0367_state *state, | |
910 | enum stv0367_clk_pol clock) | |
911 | { | |
912 | ||
913 | dprintk("%s:\n", __func__); | |
914 | ||
915 | if (state == NULL) | |
916 | return; | |
917 | ||
918 | switch (clock) { | |
919 | case STV0367_RISINGEDGE_CLOCK: | |
920 | stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 1); | |
921 | break; | |
922 | case STV0367_FALLINGEDGE_CLOCK: | |
923 | stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0); | |
924 | break; | |
925 | /*case FE_TER_CLOCK_POLARITY_DEFAULT:*/ | |
926 | default: | |
927 | stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0); | |
928 | break; | |
929 | } | |
930 | } | |
931 | ||
932 | #if 0 | |
933 | static void stv0367ter_core_sw(struct stv0367_state *state) | |
934 | { | |
935 | ||
936 | dprintk("%s:\n", __func__); | |
937 | ||
938 | stv0367_writebits(state, F367TER_CORE_ACTIVE, 0); | |
939 | stv0367_writebits(state, F367TER_CORE_ACTIVE, 1); | |
940 | msleep(350); | |
941 | } | |
942 | #endif | |
943 | static int stv0367ter_standby(struct dvb_frontend *fe, u8 standby_on) | |
944 | { | |
945 | struct stv0367_state *state = fe->demodulator_priv; | |
946 | ||
947 | dprintk("%s:\n", __func__); | |
948 | ||
949 | if (standby_on) { | |
950 | stv0367_writebits(state, F367TER_STDBY, 1); | |
951 | stv0367_writebits(state, F367TER_STDBY_FEC, 1); | |
952 | stv0367_writebits(state, F367TER_STDBY_CORE, 1); | |
953 | } else { | |
954 | stv0367_writebits(state, F367TER_STDBY, 0); | |
955 | stv0367_writebits(state, F367TER_STDBY_FEC, 0); | |
956 | stv0367_writebits(state, F367TER_STDBY_CORE, 0); | |
957 | } | |
958 | ||
959 | return 0; | |
960 | } | |
961 | ||
962 | static int stv0367ter_sleep(struct dvb_frontend *fe) | |
963 | { | |
964 | return stv0367ter_standby(fe, 1); | |
965 | } | |
966 | ||
8c8ca1c7 | 967 | static int stv0367ter_init(struct dvb_frontend *fe) |
17cce932 IL |
968 | { |
969 | struct stv0367_state *state = fe->demodulator_priv; | |
970 | struct stv0367ter_state *ter_state = state->ter_state; | |
17cce932 IL |
971 | |
972 | dprintk("%s:\n", __func__); | |
973 | ||
974 | ter_state->pBER = 0; | |
975 | ||
8881ceb8 DS |
976 | stv0367_write_table(state, |
977 | stv0367_deftabs[state->deftabs][STV0367_TAB_TER]); | |
17cce932 | 978 | |
8a9c0735 | 979 | stv0367_pll_setup(state, STV0367_ICSPEED_53125, state->config->xtal); |
17cce932 IL |
980 | |
981 | stv0367_writereg(state, R367TER_I2CRPT, 0xa0); | |
982 | stv0367_writereg(state, R367TER_ANACTRL, 0x00); | |
983 | ||
984 | /*Set TS1 and TS2 to serial or parallel mode */ | |
985 | stv0367ter_set_ts_mode(state, state->config->ts_mode); | |
986 | stv0367ter_set_clk_pol(state, state->config->clk_pol); | |
987 | ||
988 | state->chip_id = stv0367_readreg(state, R367TER_ID); | |
989 | ter_state->first_lock = 0; | |
990 | ter_state->unlock_counter = 2; | |
991 | ||
992 | return 0; | |
993 | } | |
994 | ||
285d55ad | 995 | static int stv0367ter_algo(struct dvb_frontend *fe) |
17cce932 | 996 | { |
285d55ad | 997 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
17cce932 IL |
998 | struct stv0367_state *state = fe->demodulator_priv; |
999 | struct stv0367ter_state *ter_state = state->ter_state; | |
1000 | int offset = 0, tempo = 0; | |
1001 | u8 u_var; | |
df1ec027 | 1002 | u8 /*constell,*/ counter; |
17cce932 IL |
1003 | s8 step; |
1004 | s32 timing_offset = 0; | |
b16338e3 | 1005 | u32 trl_nomrate = 0, InternalFreq = 0, temp = 0, ifkhz = 0; |
17cce932 IL |
1006 | |
1007 | dprintk("%s:\n", __func__); | |
1008 | ||
b16338e3 DS |
1009 | stv0367_get_if_khz(state, &ifkhz); |
1010 | ||
285d55ad | 1011 | ter_state->frequency = p->frequency; |
17cce932 IL |
1012 | ter_state->force = FE_TER_FORCENONE |
1013 | + stv0367_readbits(state, F367TER_FORCE) * 2; | |
1014 | ter_state->if_iq_mode = state->config->if_iq_mode; | |
1015 | switch (state->config->if_iq_mode) { | |
1016 | case FE_TER_NORMAL_IF_TUNER: /* Normal IF mode */ | |
1017 | dprintk("ALGO: FE_TER_NORMAL_IF_TUNER selected\n"); | |
1018 | stv0367_writebits(state, F367TER_TUNER_BB, 0); | |
1019 | stv0367_writebits(state, F367TER_LONGPATH_IF, 0); | |
1020 | stv0367_writebits(state, F367TER_DEMUX_SWAP, 0); | |
1021 | break; | |
1022 | case FE_TER_LONGPATH_IF_TUNER: /* Long IF mode */ | |
1023 | dprintk("ALGO: FE_TER_LONGPATH_IF_TUNER selected\n"); | |
1024 | stv0367_writebits(state, F367TER_TUNER_BB, 0); | |
1025 | stv0367_writebits(state, F367TER_LONGPATH_IF, 1); | |
1026 | stv0367_writebits(state, F367TER_DEMUX_SWAP, 1); | |
1027 | break; | |
1028 | case FE_TER_IQ_TUNER: /* IQ mode */ | |
1029 | dprintk("ALGO: FE_TER_IQ_TUNER selected\n"); | |
1030 | stv0367_writebits(state, F367TER_TUNER_BB, 1); | |
1031 | stv0367_writebits(state, F367TER_PPM_INVSEL, 0); | |
1032 | break; | |
1033 | default: | |
1034 | printk(KERN_ERR "ALGO: wrong TUNER type selected\n"); | |
1035 | return -EINVAL; | |
1036 | } | |
1037 | ||
1038 | usleep_range(5000, 7000); | |
1039 | ||
285d55ad | 1040 | switch (p->inversion) { |
17cce932 IL |
1041 | case INVERSION_AUTO: |
1042 | default: | |
1043 | dprintk("%s: inversion AUTO\n", __func__); | |
1044 | if (ter_state->if_iq_mode == FE_TER_IQ_TUNER) | |
1045 | stv0367_writebits(state, F367TER_IQ_INVERT, | |
1046 | ter_state->sense); | |
1047 | else | |
1048 | stv0367_writebits(state, F367TER_INV_SPECTR, | |
1049 | ter_state->sense); | |
1050 | ||
1051 | break; | |
1052 | case INVERSION_ON: | |
1053 | case INVERSION_OFF: | |
1054 | if (ter_state->if_iq_mode == FE_TER_IQ_TUNER) | |
1055 | stv0367_writebits(state, F367TER_IQ_INVERT, | |
285d55ad | 1056 | p->inversion); |
17cce932 IL |
1057 | else |
1058 | stv0367_writebits(state, F367TER_INV_SPECTR, | |
285d55ad | 1059 | p->inversion); |
17cce932 IL |
1060 | |
1061 | break; | |
1062 | } | |
1063 | ||
1064 | if ((ter_state->if_iq_mode != FE_TER_NORMAL_IF_TUNER) && | |
1065 | (ter_state->pBW != ter_state->bw)) { | |
1066 | stv0367ter_agc_iir_lock_detect_set(state); | |
1067 | ||
1068 | /*set fine agc target to 180 for LPIF or IQ mode*/ | |
1069 | /* set Q_AGCTarget */ | |
1070 | stv0367_writebits(state, F367TER_SEL_IQNTAR, 1); | |
1071 | stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB); | |
1072 | /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */ | |
1073 | ||
1074 | /* set Q_AGCTarget */ | |
1075 | stv0367_writebits(state, F367TER_SEL_IQNTAR, 0); | |
1076 | stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB); | |
1077 | /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */ | |
1078 | ||
1079 | if (!stv0367_iir_filt_init(state, ter_state->bw, | |
1080 | state->config->xtal)) | |
1081 | return -EINVAL; | |
1082 | /*set IIR filter once for 6,7 or 8MHz BW*/ | |
1083 | ter_state->pBW = ter_state->bw; | |
1084 | ||
1085 | stv0367ter_agc_iir_rst(state); | |
1086 | } | |
1087 | ||
1088 | if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO) | |
1089 | stv0367_writebits(state, F367TER_BDI_LPSEL, 0x01); | |
1090 | else | |
1091 | stv0367_writebits(state, F367TER_BDI_LPSEL, 0x00); | |
1092 | ||
1093 | InternalFreq = stv0367ter_get_mclk(state, state->config->xtal) / 1000; | |
1094 | temp = (int) | |
1095 | ((((ter_state->bw * 64 * (1 << 15) * 100) | |
1096 | / (InternalFreq)) * 10) / 7); | |
1097 | ||
1098 | stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, temp % 2); | |
1099 | temp = temp / 2; | |
1100 | stv0367_writebits(state, F367TER_TRL_NOMRATE_HI, temp / 256); | |
1101 | stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, temp % 256); | |
1102 | ||
1103 | temp = stv0367_readbits(state, F367TER_TRL_NOMRATE_HI) * 512 + | |
1104 | stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 + | |
1105 | stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB); | |
1106 | temp = (int)(((1 << 17) * ter_state->bw * 1000) / (7 * (InternalFreq))); | |
1107 | stv0367_writebits(state, F367TER_GAIN_SRC_HI, temp / 256); | |
1108 | stv0367_writebits(state, F367TER_GAIN_SRC_LO, temp % 256); | |
1109 | temp = stv0367_readbits(state, F367TER_GAIN_SRC_HI) * 256 + | |
1110 | stv0367_readbits(state, F367TER_GAIN_SRC_LO); | |
1111 | ||
1112 | temp = (int) | |
b16338e3 | 1113 | ((InternalFreq - ifkhz) * (1 << 16) / (InternalFreq)); |
17cce932 IL |
1114 | |
1115 | dprintk("DEROT temp=0x%x\n", temp); | |
1116 | stv0367_writebits(state, F367TER_INC_DEROT_HI, temp / 256); | |
1117 | stv0367_writebits(state, F367TER_INC_DEROT_LO, temp % 256); | |
1118 | ||
1119 | ter_state->echo_pos = 0; | |
1120 | ter_state->ucblocks = 0; /* liplianin */ | |
1121 | ter_state->pBER = 0; /* liplianin */ | |
1122 | stv0367_writebits(state, F367TER_LONG_ECHO, ter_state->echo_pos); | |
1123 | ||
1124 | if (stv0367ter_lock_algo(state) != FE_TER_LOCKOK) | |
1125 | return 0; | |
1126 | ||
1127 | ter_state->state = FE_TER_LOCKOK; | |
17cce932 IL |
1128 | |
1129 | ter_state->mode = stv0367_readbits(state, F367TER_SYR_MODE); | |
1130 | ter_state->guard = stv0367_readbits(state, F367TER_SYR_GUARD); | |
1131 | ||
1132 | ter_state->first_lock = 1; /* we know sense now :) */ | |
1133 | ||
1134 | ter_state->agc_val = | |
1135 | (stv0367_readbits(state, F367TER_AGC1_VAL_LO) << 16) + | |
1136 | (stv0367_readbits(state, F367TER_AGC1_VAL_HI) << 24) + | |
1137 | stv0367_readbits(state, F367TER_AGC2_VAL_LO) + | |
1138 | (stv0367_readbits(state, F367TER_AGC2_VAL_HI) << 8); | |
1139 | ||
1140 | /* Carrier offset calculation */ | |
1141 | stv0367_writebits(state, F367TER_FREEZE, 1); | |
1142 | offset = (stv0367_readbits(state, F367TER_CRL_FOFFSET_VHI) << 16) ; | |
1143 | offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_HI) << 8); | |
1144 | offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_LO)); | |
1145 | stv0367_writebits(state, F367TER_FREEZE, 0); | |
1146 | if (offset > 8388607) | |
1147 | offset -= 16777216; | |
1148 | ||
1149 | offset = offset * 2 / 16384; | |
1150 | ||
1151 | if (ter_state->mode == FE_TER_MODE_2K) | |
1152 | offset = (offset * 4464) / 1000;/*** 1 FFT BIN=4.464khz***/ | |
1153 | else if (ter_state->mode == FE_TER_MODE_4K) | |
1154 | offset = (offset * 223) / 100;/*** 1 FFT BIN=2.23khz***/ | |
1155 | else if (ter_state->mode == FE_TER_MODE_8K) | |
1156 | offset = (offset * 111) / 100;/*** 1 FFT BIN=1.1khz***/ | |
1157 | ||
1158 | if (stv0367_readbits(state, F367TER_PPM_INVSEL) == 1) { | |
1159 | if ((stv0367_readbits(state, F367TER_INV_SPECTR) == | |
1160 | (stv0367_readbits(state, | |
1161 | F367TER_STATUS_INV_SPECRUM) == 1))) | |
1162 | offset = offset * -1; | |
1163 | } | |
1164 | ||
1165 | if (ter_state->bw == 6) | |
1166 | offset = (offset * 6) / 8; | |
1167 | else if (ter_state->bw == 7) | |
1168 | offset = (offset * 7) / 8; | |
1169 | ||
1170 | ter_state->frequency += offset; | |
1171 | ||
1172 | tempo = 10; /* exit even if timing_offset stays null */ | |
1173 | while ((timing_offset == 0) && (tempo > 0)) { | |
1174 | usleep_range(10000, 20000); /*was 20ms */ | |
1175 | /* fine tuning of timing offset if required */ | |
1176 | timing_offset = stv0367_readbits(state, F367TER_TRL_TOFFSET_LO) | |
1177 | + 256 * stv0367_readbits(state, | |
1178 | F367TER_TRL_TOFFSET_HI); | |
1179 | if (timing_offset >= 32768) | |
1180 | timing_offset -= 65536; | |
1181 | trl_nomrate = (512 * stv0367_readbits(state, | |
1182 | F367TER_TRL_NOMRATE_HI) | |
1183 | + stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 | |
1184 | + stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB)); | |
1185 | ||
1186 | timing_offset = ((signed)(1000000 / trl_nomrate) * | |
1187 | timing_offset) / 2048; | |
1188 | tempo--; | |
1189 | } | |
1190 | ||
1191 | if (timing_offset <= 0) { | |
1192 | timing_offset = (timing_offset - 11) / 22; | |
1193 | step = -1; | |
1194 | } else { | |
1195 | timing_offset = (timing_offset + 11) / 22; | |
1196 | step = 1; | |
1197 | } | |
1198 | ||
1199 | for (counter = 0; counter < abs(timing_offset); counter++) { | |
1200 | trl_nomrate += step; | |
1201 | stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, | |
1202 | trl_nomrate % 2); | |
1203 | stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, | |
1204 | trl_nomrate / 2); | |
1205 | usleep_range(1000, 2000); | |
1206 | } | |
1207 | ||
1208 | usleep_range(5000, 6000); | |
1209 | /* unlocks could happen in case of trl centring big step, | |
1210 | then a core off/on restarts demod */ | |
1211 | u_var = stv0367_readbits(state, F367TER_LK); | |
1212 | ||
1213 | if (!u_var) { | |
1214 | stv0367_writebits(state, F367TER_CORE_ACTIVE, 0); | |
1215 | msleep(20); | |
1216 | stv0367_writebits(state, F367TER_CORE_ACTIVE, 1); | |
1217 | } | |
1218 | ||
1219 | return 0; | |
1220 | } | |
1221 | ||
285d55ad | 1222 | static int stv0367ter_set_frontend(struct dvb_frontend *fe) |
17cce932 | 1223 | { |
285d55ad | 1224 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
17cce932 IL |
1225 | struct stv0367_state *state = fe->demodulator_priv; |
1226 | struct stv0367ter_state *ter_state = state->ter_state; | |
1227 | ||
1228 | /*u8 trials[2]; */ | |
1229 | s8 num_trials, index; | |
1230 | u8 SenseTrials[] = { INVERSION_ON, INVERSION_OFF }; | |
1231 | ||
7718dcf0 DS |
1232 | if (state->reinit_on_setfrontend) |
1233 | stv0367ter_init(fe); | |
17cce932 IL |
1234 | |
1235 | if (fe->ops.tuner_ops.set_params) { | |
f61c2991 | 1236 | if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl) |
17cce932 | 1237 | fe->ops.i2c_gate_ctrl(fe, 1); |
14d24d14 | 1238 | fe->ops.tuner_ops.set_params(fe); |
f61c2991 | 1239 | if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl) |
17cce932 IL |
1240 | fe->ops.i2c_gate_ctrl(fe, 0); |
1241 | } | |
1242 | ||
285d55ad | 1243 | switch (p->transmission_mode) { |
17cce932 IL |
1244 | default: |
1245 | case TRANSMISSION_MODE_AUTO: | |
1246 | case TRANSMISSION_MODE_2K: | |
1247 | ter_state->mode = FE_TER_MODE_2K; | |
1248 | break; | |
1249 | /* case TRANSMISSION_MODE_4K: | |
1250 | pLook.mode = FE_TER_MODE_4K; | |
1251 | break;*/ | |
1252 | case TRANSMISSION_MODE_8K: | |
1253 | ter_state->mode = FE_TER_MODE_8K; | |
1254 | break; | |
1255 | } | |
1256 | ||
285d55ad | 1257 | switch (p->guard_interval) { |
17cce932 IL |
1258 | default: |
1259 | case GUARD_INTERVAL_1_32: | |
1260 | case GUARD_INTERVAL_1_16: | |
1261 | case GUARD_INTERVAL_1_8: | |
1262 | case GUARD_INTERVAL_1_4: | |
285d55ad | 1263 | ter_state->guard = p->guard_interval; |
17cce932 IL |
1264 | break; |
1265 | case GUARD_INTERVAL_AUTO: | |
1266 | ter_state->guard = GUARD_INTERVAL_1_32; | |
1267 | break; | |
1268 | } | |
1269 | ||
285d55ad MCC |
1270 | switch (p->bandwidth_hz) { |
1271 | case 6000000: | |
17cce932 IL |
1272 | ter_state->bw = FE_TER_CHAN_BW_6M; |
1273 | break; | |
285d55ad | 1274 | case 7000000: |
17cce932 IL |
1275 | ter_state->bw = FE_TER_CHAN_BW_7M; |
1276 | break; | |
285d55ad | 1277 | case 8000000: |
17cce932 IL |
1278 | default: |
1279 | ter_state->bw = FE_TER_CHAN_BW_8M; | |
1280 | } | |
1281 | ||
1282 | ter_state->hierarchy = FE_TER_HIER_NONE; | |
1283 | ||
285d55ad | 1284 | switch (p->inversion) { |
17cce932 IL |
1285 | case INVERSION_OFF: |
1286 | case INVERSION_ON: | |
1287 | num_trials = 1; | |
1288 | break; | |
1289 | default: | |
1290 | num_trials = 2; | |
1291 | if (ter_state->first_lock) | |
1292 | num_trials = 1; | |
1293 | break; | |
1294 | } | |
1295 | ||
1296 | ter_state->state = FE_TER_NOLOCK; | |
1297 | index = 0; | |
1298 | ||
1299 | while (((index) < num_trials) && (ter_state->state != FE_TER_LOCKOK)) { | |
1300 | if (!ter_state->first_lock) { | |
285d55ad | 1301 | if (p->inversion == INVERSION_AUTO) |
17cce932 IL |
1302 | ter_state->sense = SenseTrials[index]; |
1303 | ||
1304 | } | |
285d55ad | 1305 | stv0367ter_algo(fe); |
17cce932 IL |
1306 | |
1307 | if ((ter_state->state == FE_TER_LOCKOK) && | |
285d55ad | 1308 | (p->inversion == INVERSION_AUTO) && |
17cce932 IL |
1309 | (index == 1)) { |
1310 | /* invert spectrum sense */ | |
1311 | SenseTrials[index] = SenseTrials[0]; | |
1312 | SenseTrials[(index + 1) % 2] = (SenseTrials[1] + 1) % 2; | |
1313 | } | |
1314 | ||
1315 | index++; | |
1316 | } | |
1317 | ||
1318 | return 0; | |
1319 | } | |
1320 | ||
1321 | static int stv0367ter_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) | |
1322 | { | |
1323 | struct stv0367_state *state = fe->demodulator_priv; | |
1324 | struct stv0367ter_state *ter_state = state->ter_state; | |
1325 | u32 errs = 0; | |
1326 | ||
1327 | /*wait for counting completion*/ | |
1328 | if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) { | |
1329 | errs = | |
1330 | ((u32)stv0367_readbits(state, F367TER_ERR_CNT1) | |
1331 | * (1 << 16)) | |
1332 | + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI) | |
1333 | * (1 << 8)) | |
1334 | + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO)); | |
1335 | ter_state->ucblocks = errs; | |
1336 | } | |
1337 | ||
1338 | (*ucblocks) = ter_state->ucblocks; | |
1339 | ||
1340 | return 0; | |
1341 | } | |
1342 | ||
7e3e68bc MCC |
1343 | static int stv0367ter_get_frontend(struct dvb_frontend *fe, |
1344 | struct dtv_frontend_properties *p) | |
17cce932 IL |
1345 | { |
1346 | struct stv0367_state *state = fe->demodulator_priv; | |
1347 | struct stv0367ter_state *ter_state = state->ter_state; | |
17cce932 IL |
1348 | enum stv0367_ter_mode mode; |
1349 | int constell = 0,/* snr = 0,*/ Data = 0; | |
1350 | ||
285d55ad MCC |
1351 | p->frequency = stv0367_get_tuner_freq(fe); |
1352 | if ((int)p->frequency < 0) | |
1353 | p->frequency = -p->frequency; | |
17cce932 IL |
1354 | |
1355 | constell = stv0367_readbits(state, F367TER_TPS_CONST); | |
1356 | if (constell == 0) | |
285d55ad | 1357 | p->modulation = QPSK; |
17cce932 | 1358 | else if (constell == 1) |
285d55ad | 1359 | p->modulation = QAM_16; |
17cce932 | 1360 | else |
285d55ad | 1361 | p->modulation = QAM_64; |
17cce932 | 1362 | |
285d55ad | 1363 | p->inversion = stv0367_readbits(state, F367TER_INV_SPECTR); |
17cce932 IL |
1364 | |
1365 | /* Get the Hierarchical mode */ | |
1366 | Data = stv0367_readbits(state, F367TER_TPS_HIERMODE); | |
1367 | ||
1368 | switch (Data) { | |
1369 | case 0: | |
285d55ad | 1370 | p->hierarchy = HIERARCHY_NONE; |
17cce932 IL |
1371 | break; |
1372 | case 1: | |
285d55ad | 1373 | p->hierarchy = HIERARCHY_1; |
17cce932 IL |
1374 | break; |
1375 | case 2: | |
285d55ad | 1376 | p->hierarchy = HIERARCHY_2; |
17cce932 IL |
1377 | break; |
1378 | case 3: | |
285d55ad | 1379 | p->hierarchy = HIERARCHY_4; |
17cce932 IL |
1380 | break; |
1381 | default: | |
285d55ad | 1382 | p->hierarchy = HIERARCHY_AUTO; |
17cce932 IL |
1383 | break; /* error */ |
1384 | } | |
1385 | ||
1386 | /* Get the FEC Rate */ | |
1387 | if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO) | |
1388 | Data = stv0367_readbits(state, F367TER_TPS_LPCODE); | |
1389 | else | |
1390 | Data = stv0367_readbits(state, F367TER_TPS_HPCODE); | |
1391 | ||
1392 | switch (Data) { | |
1393 | case 0: | |
285d55ad | 1394 | p->code_rate_HP = FEC_1_2; |
17cce932 IL |
1395 | break; |
1396 | case 1: | |
285d55ad | 1397 | p->code_rate_HP = FEC_2_3; |
17cce932 IL |
1398 | break; |
1399 | case 2: | |
285d55ad | 1400 | p->code_rate_HP = FEC_3_4; |
17cce932 IL |
1401 | break; |
1402 | case 3: | |
285d55ad | 1403 | p->code_rate_HP = FEC_5_6; |
17cce932 IL |
1404 | break; |
1405 | case 4: | |
285d55ad | 1406 | p->code_rate_HP = FEC_7_8; |
17cce932 IL |
1407 | break; |
1408 | default: | |
285d55ad | 1409 | p->code_rate_HP = FEC_AUTO; |
17cce932 IL |
1410 | break; /* error */ |
1411 | } | |
1412 | ||
1413 | mode = stv0367_readbits(state, F367TER_SYR_MODE); | |
1414 | ||
1415 | switch (mode) { | |
1416 | case FE_TER_MODE_2K: | |
285d55ad | 1417 | p->transmission_mode = TRANSMISSION_MODE_2K; |
17cce932 IL |
1418 | break; |
1419 | /* case FE_TER_MODE_4K: | |
285d55ad | 1420 | p->transmission_mode = TRANSMISSION_MODE_4K; |
17cce932 IL |
1421 | break;*/ |
1422 | case FE_TER_MODE_8K: | |
285d55ad | 1423 | p->transmission_mode = TRANSMISSION_MODE_8K; |
17cce932 IL |
1424 | break; |
1425 | default: | |
285d55ad | 1426 | p->transmission_mode = TRANSMISSION_MODE_AUTO; |
17cce932 IL |
1427 | } |
1428 | ||
285d55ad | 1429 | p->guard_interval = stv0367_readbits(state, F367TER_SYR_GUARD); |
17cce932 | 1430 | |
7c995076 | 1431 | return 0; |
17cce932 IL |
1432 | } |
1433 | ||
b138afda | 1434 | static u32 stv0367ter_snr_readreg(struct dvb_frontend *fe) |
17cce932 IL |
1435 | { |
1436 | struct stv0367_state *state = fe->demodulator_priv; | |
1437 | u32 snru32 = 0; | |
1438 | int cpt = 0; | |
1439 | u8 cut = stv0367_readbits(state, F367TER_IDENTIFICATIONREG); | |
1440 | ||
1441 | while (cpt < 10) { | |
1442 | usleep_range(2000, 3000); | |
1443 | if (cut == 0x50) /*cut 1.0 cut 1.1*/ | |
1444 | snru32 += stv0367_readbits(state, F367TER_CHCSNR) / 4; | |
1445 | else /*cu2.0*/ | |
1446 | snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR); | |
1447 | ||
1448 | cpt++; | |
1449 | } | |
17cce932 IL |
1450 | snru32 /= 10;/*average on 10 values*/ |
1451 | ||
b138afda DS |
1452 | return snru32; |
1453 | } | |
1454 | ||
1455 | static int stv0367ter_read_snr(struct dvb_frontend *fe, u16 *snr) | |
1456 | { | |
1457 | u32 snrval = stv0367ter_snr_readreg(fe); | |
1458 | ||
1459 | *snr = snrval / 1000; | |
17cce932 IL |
1460 | |
1461 | return 0; | |
1462 | } | |
1463 | ||
1464 | #if 0 | |
1465 | static int stv0367ter_status(struct dvb_frontend *fe) | |
1466 | { | |
1467 | ||
1468 | struct stv0367_state *state = fe->demodulator_priv; | |
1469 | struct stv0367ter_state *ter_state = state->ter_state; | |
1470 | int locked = FALSE; | |
1471 | ||
1472 | locked = (stv0367_readbits(state, F367TER_LK)); | |
1473 | if (!locked) | |
1474 | ter_state->unlock_counter += 1; | |
1475 | else | |
1476 | ter_state->unlock_counter = 0; | |
1477 | ||
1478 | if (ter_state->unlock_counter > 2) { | |
1479 | if (!stv0367_readbits(state, F367TER_TPS_LOCK) || | |
1480 | (!stv0367_readbits(state, F367TER_LK))) { | |
1481 | stv0367_writebits(state, F367TER_CORE_ACTIVE, 0); | |
1482 | usleep_range(2000, 3000); | |
1483 | stv0367_writebits(state, F367TER_CORE_ACTIVE, 1); | |
1484 | msleep(350); | |
1485 | locked = (stv0367_readbits(state, F367TER_TPS_LOCK)) && | |
1486 | (stv0367_readbits(state, F367TER_LK)); | |
1487 | } | |
1488 | ||
1489 | } | |
1490 | ||
1491 | return locked; | |
1492 | } | |
1493 | #endif | |
0df289a2 MCC |
1494 | static int stv0367ter_read_status(struct dvb_frontend *fe, |
1495 | enum fe_status *status) | |
17cce932 IL |
1496 | { |
1497 | struct stv0367_state *state = fe->demodulator_priv; | |
1498 | ||
1499 | dprintk("%s:\n", __func__); | |
1500 | ||
1501 | *status = 0; | |
1502 | ||
1503 | if (stv0367_readbits(state, F367TER_LK)) { | |
430e29d9 MCC |
1504 | *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI |
1505 | | FE_HAS_SYNC | FE_HAS_LOCK; | |
17cce932 IL |
1506 | dprintk("%s: stv0367 has locked\n", __func__); |
1507 | } | |
1508 | ||
1509 | return 0; | |
1510 | } | |
1511 | ||
1512 | static int stv0367ter_read_ber(struct dvb_frontend *fe, u32 *ber) | |
1513 | { | |
1514 | struct stv0367_state *state = fe->demodulator_priv; | |
1515 | struct stv0367ter_state *ter_state = state->ter_state; | |
1516 | u32 Errors = 0, tber = 0, temporary = 0; | |
1517 | int abc = 0, def = 0; | |
1518 | ||
1519 | ||
1520 | /*wait for counting completion*/ | |
1521 | if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) | |
1522 | Errors = ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT) | |
1523 | * (1 << 16)) | |
1524 | + ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT_HI) | |
1525 | * (1 << 8)) | |
1526 | + ((u32)stv0367_readbits(state, | |
1527 | F367TER_SFEC_ERR_CNT_LO)); | |
1528 | /*measurement not completed, load previous value*/ | |
1529 | else { | |
1530 | tber = ter_state->pBER; | |
1531 | return 0; | |
1532 | } | |
1533 | ||
1534 | abc = stv0367_readbits(state, F367TER_SFEC_ERR_SOURCE); | |
1535 | def = stv0367_readbits(state, F367TER_SFEC_NUM_EVENT); | |
1536 | ||
1537 | if (Errors == 0) { | |
1538 | tber = 0; | |
1539 | } else if (abc == 0x7) { | |
1540 | if (Errors <= 4) { | |
1541 | temporary = (Errors * 1000000000) / (8 * (1 << 14)); | |
17cce932 IL |
1542 | } else if (Errors <= 42) { |
1543 | temporary = (Errors * 100000000) / (8 * (1 << 14)); | |
1544 | temporary = temporary * 10; | |
1545 | } else if (Errors <= 429) { | |
1546 | temporary = (Errors * 10000000) / (8 * (1 << 14)); | |
1547 | temporary = temporary * 100; | |
1548 | } else if (Errors <= 4294) { | |
1549 | temporary = (Errors * 1000000) / (8 * (1 << 14)); | |
1550 | temporary = temporary * 1000; | |
1551 | } else if (Errors <= 42949) { | |
1552 | temporary = (Errors * 100000) / (8 * (1 << 14)); | |
1553 | temporary = temporary * 10000; | |
1554 | } else if (Errors <= 429496) { | |
1555 | temporary = (Errors * 10000) / (8 * (1 << 14)); | |
1556 | temporary = temporary * 100000; | |
1557 | } else { /*if (Errors<4294967) 2^22 max error*/ | |
1558 | temporary = (Errors * 1000) / (8 * (1 << 14)); | |
1559 | temporary = temporary * 100000; /* still to *10 */ | |
1560 | } | |
1561 | ||
1562 | /* Byte error*/ | |
1563 | if (def == 2) | |
1564 | /*tber=Errors/(8*(1 <<14));*/ | |
1565 | tber = temporary; | |
1566 | else if (def == 3) | |
1567 | /*tber=Errors/(8*(1 <<16));*/ | |
1568 | tber = temporary / 4; | |
1569 | else if (def == 4) | |
1570 | /*tber=Errors/(8*(1 <<18));*/ | |
1571 | tber = temporary / 16; | |
1572 | else if (def == 5) | |
1573 | /*tber=Errors/(8*(1 <<20));*/ | |
1574 | tber = temporary / 64; | |
1575 | else if (def == 6) | |
1576 | /*tber=Errors/(8*(1 <<22));*/ | |
1577 | tber = temporary / 256; | |
1578 | else | |
1579 | /* should not pass here*/ | |
1580 | tber = 0; | |
1581 | ||
1582 | if ((Errors < 4294967) && (Errors > 429496)) | |
1583 | tber *= 10; | |
1584 | ||
1585 | } | |
1586 | ||
1587 | /* save actual value */ | |
1588 | ter_state->pBER = tber; | |
1589 | ||
1590 | (*ber) = tber; | |
1591 | ||
1592 | return 0; | |
1593 | } | |
1594 | #if 0 | |
1595 | static u32 stv0367ter_get_per(struct stv0367_state *state) | |
1596 | { | |
1597 | struct stv0367ter_state *ter_state = state->ter_state; | |
1598 | u32 Errors = 0, Per = 0, temporary = 0; | |
1599 | int abc = 0, def = 0, cpt = 0; | |
1600 | ||
1601 | while (((stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 1) && | |
1602 | (cpt < 400)) || ((Errors == 0) && (cpt < 400))) { | |
1603 | usleep_range(1000, 2000); | |
1604 | Errors = ((u32)stv0367_readbits(state, F367TER_ERR_CNT1) | |
1605 | * (1 << 16)) | |
1606 | + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI) | |
1607 | * (1 << 8)) | |
1608 | + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO)); | |
1609 | cpt++; | |
1610 | } | |
1611 | abc = stv0367_readbits(state, F367TER_ERR_SRC1); | |
1612 | def = stv0367_readbits(state, F367TER_NUM_EVT1); | |
1613 | ||
1614 | if (Errors == 0) | |
1615 | Per = 0; | |
1616 | else if (abc == 0x9) { | |
1617 | if (Errors <= 4) { | |
1618 | temporary = (Errors * 1000000000) / (8 * (1 << 8)); | |
17cce932 IL |
1619 | } else if (Errors <= 42) { |
1620 | temporary = (Errors * 100000000) / (8 * (1 << 8)); | |
1621 | temporary = temporary * 10; | |
1622 | } else if (Errors <= 429) { | |
1623 | temporary = (Errors * 10000000) / (8 * (1 << 8)); | |
1624 | temporary = temporary * 100; | |
1625 | } else if (Errors <= 4294) { | |
1626 | temporary = (Errors * 1000000) / (8 * (1 << 8)); | |
1627 | temporary = temporary * 1000; | |
1628 | } else if (Errors <= 42949) { | |
1629 | temporary = (Errors * 100000) / (8 * (1 << 8)); | |
1630 | temporary = temporary * 10000; | |
1631 | } else { /*if(Errors<=429496) 2^16 errors max*/ | |
1632 | temporary = (Errors * 10000) / (8 * (1 << 8)); | |
1633 | temporary = temporary * 100000; | |
1634 | } | |
1635 | ||
1636 | /* pkt error*/ | |
1637 | if (def == 2) | |
1638 | /*Per=Errors/(1 << 8);*/ | |
1639 | Per = temporary; | |
1640 | else if (def == 3) | |
1641 | /*Per=Errors/(1 << 10);*/ | |
1642 | Per = temporary / 4; | |
1643 | else if (def == 4) | |
1644 | /*Per=Errors/(1 << 12);*/ | |
1645 | Per = temporary / 16; | |
1646 | else if (def == 5) | |
1647 | /*Per=Errors/(1 << 14);*/ | |
1648 | Per = temporary / 64; | |
1649 | else if (def == 6) | |
1650 | /*Per=Errors/(1 << 16);*/ | |
1651 | Per = temporary / 256; | |
1652 | else | |
1653 | Per = 0; | |
1654 | ||
1655 | } | |
1656 | /* save actual value */ | |
1657 | ter_state->pPER = Per; | |
1658 | ||
1659 | return Per; | |
1660 | } | |
1661 | #endif | |
1662 | static int stv0367_get_tune_settings(struct dvb_frontend *fe, | |
1663 | struct dvb_frontend_tune_settings | |
1664 | *fe_tune_settings) | |
1665 | { | |
1666 | fe_tune_settings->min_delay_ms = 1000; | |
1667 | fe_tune_settings->step_size = 0; | |
1668 | fe_tune_settings->max_drift = 0; | |
1669 | ||
1670 | return 0; | |
1671 | } | |
1672 | ||
1673 | static void stv0367_release(struct dvb_frontend *fe) | |
1674 | { | |
1675 | struct stv0367_state *state = fe->demodulator_priv; | |
1676 | ||
1677 | kfree(state->ter_state); | |
1678 | kfree(state->cab_state); | |
1679 | kfree(state); | |
1680 | } | |
1681 | ||
bd336e63 | 1682 | static const struct dvb_frontend_ops stv0367ter_ops = { |
285d55ad | 1683 | .delsys = { SYS_DVBT }, |
17cce932 IL |
1684 | .info = { |
1685 | .name = "ST STV0367 DVB-T", | |
f1b1eabf MCC |
1686 | .frequency_min_hz = 47 * MHz, |
1687 | .frequency_max_hz = 862 * MHz, | |
1688 | .frequency_stepsize_hz = 15625, | |
17cce932 IL |
1689 | .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | |
1690 | FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | | |
1691 | FE_CAN_FEC_AUTO | | |
1692 | FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | | |
1693 | FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO | | |
1694 | FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER | | |
1695 | FE_CAN_INVERSION_AUTO | | |
1696 | FE_CAN_MUTE_TS | |
1697 | }, | |
1698 | .release = stv0367_release, | |
1699 | .init = stv0367ter_init, | |
1700 | .sleep = stv0367ter_sleep, | |
1701 | .i2c_gate_ctrl = stv0367ter_gate_ctrl, | |
285d55ad MCC |
1702 | .set_frontend = stv0367ter_set_frontend, |
1703 | .get_frontend = stv0367ter_get_frontend, | |
17cce932 IL |
1704 | .get_tune_settings = stv0367_get_tune_settings, |
1705 | .read_status = stv0367ter_read_status, | |
1706 | .read_ber = stv0367ter_read_ber,/* too slow */ | |
1707 | /* .read_signal_strength = stv0367_read_signal_strength,*/ | |
1708 | .read_snr = stv0367ter_read_snr, | |
1709 | .read_ucblocks = stv0367ter_read_ucblocks, | |
1710 | }; | |
1711 | ||
1712 | struct dvb_frontend *stv0367ter_attach(const struct stv0367_config *config, | |
1713 | struct i2c_adapter *i2c) | |
1714 | { | |
1715 | struct stv0367_state *state = NULL; | |
1716 | struct stv0367ter_state *ter_state = NULL; | |
1717 | ||
1718 | /* allocate memory for the internal state */ | |
1719 | state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL); | |
1720 | if (state == NULL) | |
1721 | goto error; | |
1722 | ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL); | |
1723 | if (ter_state == NULL) | |
1724 | goto error; | |
1725 | ||
1726 | /* setup the state */ | |
1727 | state->i2c = i2c; | |
1728 | state->config = config; | |
1729 | state->ter_state = ter_state; | |
1730 | state->fe.ops = stv0367ter_ops; | |
1731 | state->fe.demodulator_priv = state; | |
1732 | state->chip_id = stv0367_readreg(state, 0xf000); | |
1733 | ||
f61c2991 DS |
1734 | /* demod operation options */ |
1735 | state->use_i2c_gatectrl = 1; | |
8881ceb8 | 1736 | state->deftabs = STV0367_DEFTAB_GENERIC; |
7718dcf0 | 1737 | state->reinit_on_setfrontend = 1; |
b16338e3 | 1738 | state->auto_if_khz = 0; |
f61c2991 | 1739 | |
17cce932 IL |
1740 | dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id); |
1741 | ||
1742 | /* check if the demod is there */ | |
1743 | if ((state->chip_id != 0x50) && (state->chip_id != 0x60)) | |
1744 | goto error; | |
1745 | ||
1746 | return &state->fe; | |
1747 | ||
1748 | error: | |
1749 | kfree(ter_state); | |
1750 | kfree(state); | |
1751 | return NULL; | |
1752 | } | |
1753 | EXPORT_SYMBOL(stv0367ter_attach); | |
1754 | ||
1755 | static int stv0367cab_gate_ctrl(struct dvb_frontend *fe, int enable) | |
1756 | { | |
1757 | struct stv0367_state *state = fe->demodulator_priv; | |
1758 | ||
1759 | dprintk("%s:\n", __func__); | |
1760 | ||
1761 | stv0367_writebits(state, F367CAB_I2CT_ON, (enable > 0) ? 1 : 0); | |
1762 | ||
1763 | return 0; | |
1764 | } | |
1765 | ||
1766 | static u32 stv0367cab_get_mclk(struct dvb_frontend *fe, u32 ExtClk_Hz) | |
1767 | { | |
1768 | struct stv0367_state *state = fe->demodulator_priv; | |
1769 | u32 mclk_Hz = 0;/* master clock frequency (Hz) */ | |
1770 | u32 M, N, P; | |
1771 | ||
1772 | ||
1773 | if (stv0367_readbits(state, F367CAB_BYPASS_PLLXN) == 0) { | |
1774 | N = (u32)stv0367_readbits(state, F367CAB_PLL_NDIV); | |
1775 | if (N == 0) | |
1776 | N = N + 1; | |
1777 | ||
1778 | M = (u32)stv0367_readbits(state, F367CAB_PLL_MDIV); | |
1779 | if (M == 0) | |
1780 | M = M + 1; | |
1781 | ||
1782 | P = (u32)stv0367_readbits(state, F367CAB_PLL_PDIV); | |
1783 | ||
1784 | if (P > 5) | |
1785 | P = 5; | |
1786 | ||
1787 | mclk_Hz = ((ExtClk_Hz / 2) * N) / (M * (1 << P)); | |
1788 | dprintk("stv0367cab_get_mclk BYPASS_PLLXN mclk_Hz=%d\n", | |
1789 | mclk_Hz); | |
1790 | } else | |
1791 | mclk_Hz = ExtClk_Hz; | |
1792 | ||
1793 | dprintk("stv0367cab_get_mclk final mclk_Hz=%d\n", mclk_Hz); | |
1794 | ||
1795 | return mclk_Hz; | |
1796 | } | |
1797 | ||
1798 | static u32 stv0367cab_get_adc_freq(struct dvb_frontend *fe, u32 ExtClk_Hz) | |
1799 | { | |
1800 | u32 ADCClk_Hz = ExtClk_Hz; | |
1801 | ||
1802 | ADCClk_Hz = stv0367cab_get_mclk(fe, ExtClk_Hz); | |
1803 | ||
1804 | return ADCClk_Hz; | |
1805 | } | |
1806 | ||
8c8ca1c7 MCC |
1807 | static enum stv0367cab_mod stv0367cab_SetQamSize(struct stv0367_state *state, |
1808 | u32 SymbolRate, | |
1809 | enum stv0367cab_mod QAMSize) | |
17cce932 IL |
1810 | { |
1811 | /* Set QAM size */ | |
1812 | stv0367_writebits(state, F367CAB_QAM_MODE, QAMSize); | |
1813 | ||
1814 | /* Set Registers settings specific to the QAM size */ | |
1815 | switch (QAMSize) { | |
1816 | case FE_CAB_MOD_QAM4: | |
1817 | stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); | |
1818 | break; | |
1819 | case FE_CAB_MOD_QAM16: | |
1820 | stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64); | |
1821 | stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); | |
1822 | stv0367_writereg(state, R367CAB_FSM_STATE, 0x90); | |
1823 | stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); | |
1824 | stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7); | |
1825 | stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95); | |
1826 | stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40); | |
1827 | stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a); | |
1828 | break; | |
1829 | case FE_CAB_MOD_QAM32: | |
1830 | stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); | |
1831 | stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e); | |
1832 | stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0); | |
1833 | stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); | |
1834 | stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7); | |
1835 | stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d); | |
1836 | stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f); | |
1837 | stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7); | |
1838 | break; | |
1839 | case FE_CAB_MOD_QAM64: | |
1840 | stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82); | |
1841 | stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a); | |
8b39f076 | 1842 | if (SymbolRate > 4500000) { |
17cce932 IL |
1843 | stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0); |
1844 | stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); | |
1845 | stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5); | |
8b39f076 | 1846 | } else if (SymbolRate > 2500000) { |
17cce932 IL |
1847 | stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0); |
1848 | stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); | |
1849 | stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6); | |
1850 | } else { | |
1851 | stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0); | |
1852 | stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1); | |
1853 | stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7); | |
1854 | } | |
1855 | stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95); | |
1856 | stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40); | |
1857 | stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99); | |
1858 | break; | |
1859 | case FE_CAB_MOD_QAM128: | |
1860 | stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); | |
1861 | stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76); | |
1862 | stv0367_writereg(state, R367CAB_FSM_STATE, 0x90); | |
1863 | stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1); | |
8b39f076 | 1864 | if (SymbolRate > 4500000) |
17cce932 | 1865 | stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7); |
8b39f076 | 1866 | else if (SymbolRate > 2500000) |
17cce932 IL |
1867 | stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6); |
1868 | else | |
1869 | stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97); | |
1870 | ||
1871 | stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e); | |
1872 | stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f); | |
1873 | stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7); | |
1874 | break; | |
1875 | case FE_CAB_MOD_QAM256: | |
1876 | stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94); | |
1877 | stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a); | |
1878 | stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0); | |
8b39f076 | 1879 | if (SymbolRate > 4500000) |
17cce932 | 1880 | stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); |
8b39f076 | 1881 | else if (SymbolRate > 2500000) |
17cce932 IL |
1882 | stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); |
1883 | else | |
1884 | stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1); | |
1885 | ||
1886 | stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7); | |
1887 | stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85); | |
1888 | stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40); | |
1889 | stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7); | |
1890 | break; | |
1891 | case FE_CAB_MOD_QAM512: | |
1892 | stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); | |
1893 | break; | |
1894 | case FE_CAB_MOD_QAM1024: | |
1895 | stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); | |
1896 | break; | |
1897 | default: | |
1898 | break; | |
1899 | } | |
1900 | ||
1901 | return QAMSize; | |
1902 | } | |
1903 | ||
1904 | static u32 stv0367cab_set_derot_freq(struct stv0367_state *state, | |
1905 | u32 adc_hz, s32 derot_hz) | |
1906 | { | |
1907 | u32 sampled_if = 0; | |
1908 | u32 adc_khz; | |
1909 | ||
1910 | adc_khz = adc_hz / 1000; | |
1911 | ||
1912 | dprintk("%s: adc_hz=%d derot_hz=%d\n", __func__, adc_hz, derot_hz); | |
1913 | ||
1914 | if (adc_khz != 0) { | |
1915 | if (derot_hz < 1000000) | |
1916 | derot_hz = adc_hz / 4; /* ZIF operation */ | |
1917 | if (derot_hz > adc_hz) | |
1918 | derot_hz = derot_hz - adc_hz; | |
1919 | sampled_if = (u32)derot_hz / 1000; | |
1920 | sampled_if *= 32768; | |
1921 | sampled_if /= adc_khz; | |
1922 | sampled_if *= 256; | |
1923 | } | |
1924 | ||
1925 | if (sampled_if > 8388607) | |
1926 | sampled_if = 8388607; | |
1927 | ||
1928 | dprintk("%s: sampled_if=0x%x\n", __func__, sampled_if); | |
1929 | ||
1930 | stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if); | |
1931 | stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8)); | |
1932 | stv0367_writebits(state, F367CAB_MIX_NCO_INC_HH, (sampled_if >> 16)); | |
1933 | ||
1934 | return derot_hz; | |
1935 | } | |
1936 | ||
1937 | static u32 stv0367cab_get_derot_freq(struct stv0367_state *state, u32 adc_hz) | |
1938 | { | |
1939 | u32 sampled_if; | |
1940 | ||
1941 | sampled_if = stv0367_readbits(state, F367CAB_MIX_NCO_INC_LL) + | |
1942 | (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HL) << 8) + | |
1943 | (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HH) << 16); | |
1944 | ||
1945 | sampled_if /= 256; | |
1946 | sampled_if *= (adc_hz / 1000); | |
1947 | sampled_if += 1; | |
1948 | sampled_if /= 32768; | |
1949 | ||
1950 | return sampled_if; | |
1951 | } | |
1952 | ||
1953 | static u32 stv0367cab_set_srate(struct stv0367_state *state, u32 adc_hz, | |
1954 | u32 mclk_hz, u32 SymbolRate, | |
1955 | enum stv0367cab_mod QAMSize) | |
1956 | { | |
1957 | u32 QamSizeCorr = 0; | |
1958 | u32 u32_tmp = 0, u32_tmp1 = 0; | |
1959 | u32 adp_khz; | |
1960 | ||
1961 | dprintk("%s:\n", __func__); | |
1962 | ||
1963 | /* Set Correction factor of SRC gain */ | |
1964 | switch (QAMSize) { | |
1965 | case FE_CAB_MOD_QAM4: | |
1966 | QamSizeCorr = 1110; | |
1967 | break; | |
1968 | case FE_CAB_MOD_QAM16: | |
1969 | QamSizeCorr = 1032; | |
1970 | break; | |
1971 | case FE_CAB_MOD_QAM32: | |
1972 | QamSizeCorr = 954; | |
1973 | break; | |
1974 | case FE_CAB_MOD_QAM64: | |
1975 | QamSizeCorr = 983; | |
1976 | break; | |
1977 | case FE_CAB_MOD_QAM128: | |
1978 | QamSizeCorr = 957; | |
1979 | break; | |
1980 | case FE_CAB_MOD_QAM256: | |
1981 | QamSizeCorr = 948; | |
1982 | break; | |
1983 | case FE_CAB_MOD_QAM512: | |
1984 | QamSizeCorr = 0; | |
1985 | break; | |
1986 | case FE_CAB_MOD_QAM1024: | |
1987 | QamSizeCorr = 944; | |
1988 | break; | |
1989 | default: | |
1990 | break; | |
1991 | } | |
1992 | ||
1993 | /* Transfer ratio calculation */ | |
1994 | if (adc_hz != 0) { | |
1995 | u32_tmp = 256 * SymbolRate; | |
1996 | u32_tmp = u32_tmp / adc_hz; | |
1997 | } | |
1998 | stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp); | |
1999 | ||
2000 | /* Symbol rate and SRC gain calculation */ | |
2001 | adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */ | |
2002 | if (adp_khz != 0) { | |
2003 | u32_tmp = SymbolRate; | |
2004 | u32_tmp1 = SymbolRate; | |
2005 | ||
2006 | if (u32_tmp < 2097152) { /* 2097152 = 2^21 */ | |
2007 | /* Symbol rate calculation */ | |
2008 | u32_tmp *= 2048; /* 2048 = 2^11 */ | |
2009 | u32_tmp = u32_tmp / adp_khz; | |
2010 | u32_tmp = u32_tmp * 16384; /* 16384 = 2^14 */ | |
2011 | u32_tmp /= 125 ; /* 125 = 1000/2^3 */ | |
2012 | u32_tmp = u32_tmp * 8; /* 8 = 2^3 */ | |
2013 | ||
2014 | /* SRC Gain Calculation */ | |
2015 | u32_tmp1 *= 2048; /* *2*2^10 */ | |
2016 | u32_tmp1 /= 439; /* *2/878 */ | |
2017 | u32_tmp1 *= 256; /* *2^8 */ | |
2018 | u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */ | |
2019 | u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */ | |
2020 | u32_tmp1 = u32_tmp1 / 10000000; | |
2021 | ||
2022 | } else if (u32_tmp < 4194304) { /* 4194304 = 2**22 */ | |
2023 | /* Symbol rate calculation */ | |
2024 | u32_tmp *= 1024 ; /* 1024 = 2**10 */ | |
2025 | u32_tmp = u32_tmp / adp_khz; | |
2026 | u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */ | |
2027 | u32_tmp /= 125 ; /* 125 = 1000/2**3 */ | |
2028 | u32_tmp = u32_tmp * 16; /* 16 = 2**4 */ | |
2029 | ||
2030 | /* SRC Gain Calculation */ | |
2031 | u32_tmp1 *= 1024; /* *2*2^9 */ | |
2032 | u32_tmp1 /= 439; /* *2/878 */ | |
2033 | u32_tmp1 *= 256; /* *2^8 */ | |
2034 | u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz)*/ | |
2035 | u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */ | |
2036 | u32_tmp1 = u32_tmp1 / 5000000; | |
2037 | } else if (u32_tmp < 8388607) { /* 8388607 = 2**23 */ | |
2038 | /* Symbol rate calculation */ | |
2039 | u32_tmp *= 512 ; /* 512 = 2**9 */ | |
2040 | u32_tmp = u32_tmp / adp_khz; | |
2041 | u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */ | |
2042 | u32_tmp /= 125 ; /* 125 = 1000/2**3 */ | |
2043 | u32_tmp = u32_tmp * 32; /* 32 = 2**5 */ | |
2044 | ||
2045 | /* SRC Gain Calculation */ | |
2046 | u32_tmp1 *= 512; /* *2*2^8 */ | |
2047 | u32_tmp1 /= 439; /* *2/878 */ | |
2048 | u32_tmp1 *= 256; /* *2^8 */ | |
2049 | u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */ | |
2050 | u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */ | |
2051 | u32_tmp1 = u32_tmp1 / 2500000; | |
2052 | } else { | |
2053 | /* Symbol rate calculation */ | |
2054 | u32_tmp *= 256 ; /* 256 = 2**8 */ | |
2055 | u32_tmp = u32_tmp / adp_khz; | |
2056 | u32_tmp = u32_tmp * 16384; /* 16384 = 2**13 */ | |
2057 | u32_tmp /= 125 ; /* 125 = 1000/2**3 */ | |
2058 | u32_tmp = u32_tmp * 64; /* 64 = 2**6 */ | |
2059 | ||
2060 | /* SRC Gain Calculation */ | |
2061 | u32_tmp1 *= 256; /* 2*2^7 */ | |
2062 | u32_tmp1 /= 439; /* *2/878 */ | |
2063 | u32_tmp1 *= 256; /* *2^8 */ | |
2064 | u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */ | |
2065 | u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */ | |
2066 | u32_tmp1 = u32_tmp1 / 1250000; | |
2067 | } | |
2068 | } | |
2069 | #if 0 | |
2070 | /* Filters' coefficients are calculated and written | |
2071 | into registers only if the filters are enabled */ | |
2072 | if (stv0367_readbits(state, F367CAB_ADJ_EN)) { | |
2073 | stv0367cab_SetIirAdjacentcoefficient(state, mclk_hz, | |
2074 | SymbolRate); | |
2075 | /* AllPass filter must be enabled | |
2076 | when the adjacents filter is used */ | |
2077 | stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 1); | |
2078 | stv0367cab_SetAllPasscoefficient(state, mclk_hz, SymbolRate); | |
2079 | } else | |
2080 | /* AllPass filter must be disabled | |
2081 | when the adjacents filter is not used */ | |
2082 | #endif | |
2083 | stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0); | |
2084 | ||
2085 | stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp); | |
2086 | stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8)); | |
2087 | stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16)); | |
2088 | stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24)); | |
2089 | ||
2090 | stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff); | |
2091 | stv0367_writebits(state, F367CAB_GAIN_SRC_HI, (u32_tmp1 >> 8) & 0x00ff); | |
2092 | ||
2093 | return SymbolRate ; | |
2094 | } | |
2095 | ||
2096 | static u32 stv0367cab_GetSymbolRate(struct stv0367_state *state, u32 mclk_hz) | |
2097 | { | |
2098 | u32 regsym; | |
2099 | u32 adp_khz; | |
2100 | ||
2101 | regsym = stv0367_readreg(state, R367CAB_SRC_NCO_LL) + | |
2102 | (stv0367_readreg(state, R367CAB_SRC_NCO_LH) << 8) + | |
2103 | (stv0367_readreg(state, R367CAB_SRC_NCO_HL) << 16) + | |
2104 | (stv0367_readreg(state, R367CAB_SRC_NCO_HH) << 24); | |
2105 | ||
2106 | adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */ | |
2107 | ||
2108 | if (regsym < 134217728) { /* 134217728L = 2**27*/ | |
2109 | regsym = regsym * 32; /* 32 = 2**5 */ | |
2110 | regsym = regsym / 32768; /* 32768L = 2**15 */ | |
2111 | regsym = adp_khz * regsym; /* AdpClk in kHz */ | |
2112 | regsym = regsym / 128; /* 128 = 2**7 */ | |
2113 | regsym *= 125 ; /* 125 = 1000/2**3 */ | |
2114 | regsym /= 2048 ; /* 2048 = 2**11 */ | |
2115 | } else if (regsym < 268435456) { /* 268435456L = 2**28 */ | |
2116 | regsym = regsym * 16; /* 16 = 2**4 */ | |
2117 | regsym = regsym / 32768; /* 32768L = 2**15 */ | |
2118 | regsym = adp_khz * regsym; /* AdpClk in kHz */ | |
2119 | regsym = regsym / 128; /* 128 = 2**7 */ | |
2120 | regsym *= 125 ; /* 125 = 1000/2**3*/ | |
2121 | regsym /= 1024 ; /* 256 = 2**10*/ | |
2122 | } else if (regsym < 536870912) { /* 536870912L = 2**29*/ | |
2123 | regsym = regsym * 8; /* 8 = 2**3 */ | |
2124 | regsym = regsym / 32768; /* 32768L = 2**15 */ | |
2125 | regsym = adp_khz * regsym; /* AdpClk in kHz */ | |
2126 | regsym = regsym / 128; /* 128 = 2**7 */ | |
2127 | regsym *= 125 ; /* 125 = 1000/2**3 */ | |
2128 | regsym /= 512 ; /* 128 = 2**9 */ | |
2129 | } else { | |
2130 | regsym = regsym * 4; /* 4 = 2**2 */ | |
2131 | regsym = regsym / 32768; /* 32768L = 2**15 */ | |
2132 | regsym = adp_khz * regsym; /* AdpClk in kHz */ | |
2133 | regsym = regsym / 128; /* 128 = 2**7 */ | |
2134 | regsym *= 125 ; /* 125 = 1000/2**3 */ | |
2135 | regsym /= 256 ; /* 64 = 2**8 */ | |
2136 | } | |
2137 | ||
2138 | return regsym; | |
2139 | } | |
2140 | ||
d105d083 DS |
2141 | static u32 stv0367cab_fsm_status(struct stv0367_state *state) |
2142 | { | |
2143 | return stv0367_readbits(state, F367CAB_FSM_STATUS); | |
2144 | } | |
2145 | ||
2146 | static u32 stv0367cab_qamfec_lock(struct stv0367_state *state) | |
2147 | { | |
2148 | return stv0367_readbits(state, | |
2149 | (state->cab_state->qamfec_status_reg ? | |
2150 | state->cab_state->qamfec_status_reg : | |
2151 | F367CAB_QAMFEC_LOCK)); | |
2152 | } | |
2153 | ||
2154 | static | |
2155 | enum stv0367_cab_signal_type stv0367cab_fsm_signaltype(u32 qam_fsm_status) | |
2156 | { | |
2157 | enum stv0367_cab_signal_type signaltype = FE_CAB_NOAGC; | |
2158 | ||
2159 | switch (qam_fsm_status) { | |
2160 | case 1: | |
2161 | signaltype = FE_CAB_NOAGC; | |
2162 | break; | |
2163 | case 2: | |
2164 | signaltype = FE_CAB_NOTIMING; | |
2165 | break; | |
2166 | case 3: | |
2167 | signaltype = FE_CAB_TIMINGOK; | |
2168 | break; | |
2169 | case 4: | |
2170 | signaltype = FE_CAB_NOCARRIER; | |
2171 | break; | |
2172 | case 5: | |
2173 | signaltype = FE_CAB_CARRIEROK; | |
2174 | break; | |
2175 | case 7: | |
2176 | signaltype = FE_CAB_NOBLIND; | |
2177 | break; | |
2178 | case 8: | |
2179 | signaltype = FE_CAB_BLINDOK; | |
2180 | break; | |
2181 | case 10: | |
2182 | signaltype = FE_CAB_NODEMOD; | |
2183 | break; | |
2184 | case 11: | |
2185 | signaltype = FE_CAB_DEMODOK; | |
2186 | break; | |
2187 | case 12: | |
2188 | signaltype = FE_CAB_DEMODOK; | |
2189 | break; | |
2190 | case 13: | |
2191 | signaltype = FE_CAB_NODEMOD; | |
2192 | break; | |
2193 | case 14: | |
2194 | signaltype = FE_CAB_NOBLIND; | |
2195 | break; | |
2196 | case 15: | |
2197 | signaltype = FE_CAB_NOSIGNAL; | |
2198 | break; | |
2199 | default: | |
2200 | break; | |
2201 | } | |
2202 | ||
2203 | return signaltype; | |
2204 | } | |
2205 | ||
0df289a2 MCC |
2206 | static int stv0367cab_read_status(struct dvb_frontend *fe, |
2207 | enum fe_status *status) | |
17cce932 IL |
2208 | { |
2209 | struct stv0367_state *state = fe->demodulator_priv; | |
2210 | ||
2211 | dprintk("%s:\n", __func__); | |
2212 | ||
2213 | *status = 0; | |
2214 | ||
d105d083 DS |
2215 | /* update cab_state->state from QAM_FSM_STATUS */ |
2216 | state->cab_state->state = stv0367cab_fsm_signaltype( | |
2217 | stv0367cab_fsm_status(state)); | |
430e29d9 | 2218 | |
d105d083 DS |
2219 | if (stv0367cab_qamfec_lock(state)) { |
2220 | *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | |
2221 | | FE_HAS_SYNC | FE_HAS_LOCK; | |
2222 | dprintk("%s: stv0367 has locked\n", __func__); | |
2223 | } else { | |
2224 | if (state->cab_state->state > FE_CAB_NOSIGNAL) | |
2225 | *status |= FE_HAS_SIGNAL; | |
430e29d9 | 2226 | |
d105d083 DS |
2227 | if (state->cab_state->state > FE_CAB_NOCARRIER) |
2228 | *status |= FE_HAS_CARRIER; | |
430e29d9 | 2229 | |
d105d083 DS |
2230 | if (state->cab_state->state >= FE_CAB_DEMODOK) |
2231 | *status |= FE_HAS_VITERBI; | |
430e29d9 | 2232 | |
d105d083 DS |
2233 | if (state->cab_state->state >= FE_CAB_DATAOK) |
2234 | *status |= FE_HAS_SYNC; | |
17cce932 IL |
2235 | } |
2236 | ||
2237 | return 0; | |
2238 | } | |
2239 | ||
2240 | static int stv0367cab_standby(struct dvb_frontend *fe, u8 standby_on) | |
2241 | { | |
2242 | struct stv0367_state *state = fe->demodulator_priv; | |
2243 | ||
2244 | dprintk("%s:\n", __func__); | |
2245 | ||
2246 | if (standby_on) { | |
2247 | stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x03); | |
2248 | stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x01); | |
2249 | stv0367_writebits(state, F367CAB_STDBY, 1); | |
2250 | stv0367_writebits(state, F367CAB_STDBY_CORE, 1); | |
2251 | stv0367_writebits(state, F367CAB_EN_BUFFER_I, 0); | |
2252 | stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 0); | |
2253 | stv0367_writebits(state, F367CAB_POFFQ, 1); | |
2254 | stv0367_writebits(state, F367CAB_POFFI, 1); | |
2255 | } else { | |
2256 | stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x00); | |
2257 | stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x00); | |
2258 | stv0367_writebits(state, F367CAB_STDBY, 0); | |
2259 | stv0367_writebits(state, F367CAB_STDBY_CORE, 0); | |
2260 | stv0367_writebits(state, F367CAB_EN_BUFFER_I, 1); | |
2261 | stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 1); | |
2262 | stv0367_writebits(state, F367CAB_POFFQ, 0); | |
2263 | stv0367_writebits(state, F367CAB_POFFI, 0); | |
2264 | } | |
2265 | ||
2266 | return 0; | |
2267 | } | |
2268 | ||
2269 | static int stv0367cab_sleep(struct dvb_frontend *fe) | |
2270 | { | |
2271 | return stv0367cab_standby(fe, 1); | |
2272 | } | |
2273 | ||
8c8ca1c7 | 2274 | static int stv0367cab_init(struct dvb_frontend *fe) |
17cce932 IL |
2275 | { |
2276 | struct stv0367_state *state = fe->demodulator_priv; | |
2277 | struct stv0367cab_state *cab_state = state->cab_state; | |
17cce932 IL |
2278 | |
2279 | dprintk("%s:\n", __func__); | |
2280 | ||
8881ceb8 DS |
2281 | stv0367_write_table(state, |
2282 | stv0367_deftabs[state->deftabs][STV0367_TAB_CAB]); | |
17cce932 IL |
2283 | |
2284 | switch (state->config->ts_mode) { | |
2285 | case STV0367_DVBCI_CLOCK: | |
2286 | dprintk("Setting TSMode = STV0367_DVBCI_CLOCK\n"); | |
2287 | stv0367_writebits(state, F367CAB_OUTFORMAT, 0x03); | |
2288 | break; | |
2289 | case STV0367_SERIAL_PUNCT_CLOCK: | |
2290 | case STV0367_SERIAL_CONT_CLOCK: | |
2291 | stv0367_writebits(state, F367CAB_OUTFORMAT, 0x01); | |
2292 | break; | |
2293 | case STV0367_PARALLEL_PUNCT_CLOCK: | |
2294 | case STV0367_OUTPUTMODE_DEFAULT: | |
2295 | stv0367_writebits(state, F367CAB_OUTFORMAT, 0x00); | |
2296 | break; | |
2297 | } | |
2298 | ||
2299 | switch (state->config->clk_pol) { | |
2300 | case STV0367_RISINGEDGE_CLOCK: | |
2301 | stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x00); | |
2302 | break; | |
2303 | case STV0367_FALLINGEDGE_CLOCK: | |
2304 | case STV0367_CLOCKPOLARITY_DEFAULT: | |
2305 | stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x01); | |
2306 | break; | |
2307 | } | |
2308 | ||
2309 | stv0367_writebits(state, F367CAB_SYNC_STRIP, 0x00); | |
2310 | ||
2311 | stv0367_writebits(state, F367CAB_CT_NBST, 0x01); | |
2312 | ||
2313 | stv0367_writebits(state, F367CAB_TS_SWAP, 0x01); | |
2314 | ||
2315 | stv0367_writebits(state, F367CAB_FIFO_BYPASS, 0x00); | |
2316 | ||
2317 | stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */ | |
2318 | ||
2319 | cab_state->mclk = stv0367cab_get_mclk(fe, state->config->xtal); | |
2320 | cab_state->adc_clk = stv0367cab_get_adc_freq(fe, state->config->xtal); | |
2321 | ||
2322 | return 0; | |
2323 | } | |
2324 | static | |
2325 | enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state, | |
285d55ad | 2326 | struct dtv_frontend_properties *p) |
17cce932 | 2327 | { |
17cce932 IL |
2328 | struct stv0367cab_state *cab_state = state->cab_state; |
2329 | enum stv0367_cab_signal_type signalType = FE_CAB_NOAGC; | |
b16338e3 | 2330 | u32 QAMFEC_Lock, QAM_Lock, u32_tmp, ifkhz, |
17cce932 IL |
2331 | LockTime, TRLTimeOut, AGCTimeOut, CRLSymbols, |
2332 | CRLTimeOut, EQLTimeOut, DemodTimeOut, FECTimeOut; | |
2333 | u8 TrackAGCAccum; | |
2334 | s32 tmp; | |
2335 | ||
2336 | dprintk("%s:\n", __func__); | |
2337 | ||
b16338e3 DS |
2338 | stv0367_get_if_khz(state, &ifkhz); |
2339 | ||
17cce932 IL |
2340 | /* Timeouts calculation */ |
2341 | /* A max lock time of 25 ms is allowed for delayed AGC */ | |
2342 | AGCTimeOut = 25; | |
2343 | /* 100000 symbols needed by the TRL as a maximum value */ | |
285d55ad | 2344 | TRLTimeOut = 100000000 / p->symbol_rate; |
17cce932 IL |
2345 | /* CRLSymbols is the needed number of symbols to achieve a lock |
2346 | within [-4%, +4%] of the symbol rate. | |
2347 | CRL timeout is calculated | |
2348 | for a lock within [-search_range, +search_range]. | |
2349 | EQL timeout can be changed depending on | |
2350 | the micro-reflections we want to handle. | |
2351 | A characterization must be performed | |
2352 | with these echoes to get new timeout values. | |
2353 | */ | |
285d55ad | 2354 | switch (p->modulation) { |
17cce932 IL |
2355 | case QAM_16: |
2356 | CRLSymbols = 150000; | |
2357 | EQLTimeOut = 100; | |
2358 | break; | |
2359 | case QAM_32: | |
2360 | CRLSymbols = 250000; | |
2361 | EQLTimeOut = 100; | |
2362 | break; | |
2363 | case QAM_64: | |
2364 | CRLSymbols = 200000; | |
2365 | EQLTimeOut = 100; | |
2366 | break; | |
2367 | case QAM_128: | |
2368 | CRLSymbols = 250000; | |
2369 | EQLTimeOut = 100; | |
2370 | break; | |
2371 | case QAM_256: | |
2372 | CRLSymbols = 250000; | |
2373 | EQLTimeOut = 100; | |
2374 | break; | |
2375 | default: | |
2376 | CRLSymbols = 200000; | |
2377 | EQLTimeOut = 100; | |
2378 | break; | |
2379 | } | |
2380 | #if 0 | |
2381 | if (pIntParams->search_range < 0) { | |
2382 | CRLTimeOut = (25 * CRLSymbols * | |
2383 | (-pIntParams->search_range / 1000)) / | |
2384 | (pIntParams->symbol_rate / 1000); | |
2385 | } else | |
2386 | #endif | |
2387 | CRLTimeOut = (25 * CRLSymbols * (cab_state->search_range / 1000)) / | |
285d55ad | 2388 | (p->symbol_rate / 1000); |
17cce932 | 2389 | |
285d55ad | 2390 | CRLTimeOut = (1000 * CRLTimeOut) / p->symbol_rate; |
17cce932 IL |
2391 | /* Timeouts below 50ms are coerced */ |
2392 | if (CRLTimeOut < 50) | |
2393 | CRLTimeOut = 50; | |
2394 | /* A maximum of 100 TS packets is needed to get FEC lock even in case | |
2395 | the spectrum inversion needs to be changed. | |
2396 | This is equal to 20 ms in case of the lowest symbol rate of 0.87Msps | |
2397 | */ | |
2398 | FECTimeOut = 20; | |
2399 | DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut; | |
2400 | ||
2401 | dprintk("%s: DemodTimeOut=%d\n", __func__, DemodTimeOut); | |
2402 | ||
2403 | /* Reset the TRL to ensure nothing starts until the | |
2404 | AGC is stable which ensures a better lock time | |
2405 | */ | |
2406 | stv0367_writereg(state, R367CAB_CTRL_1, 0x04); | |
2407 | /* Set AGC accumulation time to minimum and lock threshold to maximum | |
2408 | in order to speed up the AGC lock */ | |
2409 | TrackAGCAccum = stv0367_readbits(state, F367CAB_AGC_ACCUMRSTSEL); | |
2410 | stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, 0x0); | |
2411 | /* Modulus Mapper is disabled */ | |
2412 | stv0367_writebits(state, F367CAB_MODULUSMAP_EN, 0); | |
2413 | /* Disable the sweep function */ | |
2414 | stv0367_writebits(state, F367CAB_SWEEP_EN, 0); | |
2415 | /* The sweep function is never used, Sweep rate must be set to 0 */ | |
2416 | /* Set the derotator frequency in Hz */ | |
2417 | stv0367cab_set_derot_freq(state, cab_state->adc_clk, | |
b16338e3 | 2418 | (1000 * (s32)ifkhz + cab_state->derot_offset)); |
17cce932 | 2419 | /* Disable the Allpass Filter when the symbol rate is out of range */ |
285d55ad | 2420 | if ((p->symbol_rate > 10800000) | (p->symbol_rate < 1800000)) { |
17cce932 IL |
2421 | stv0367_writebits(state, F367CAB_ADJ_EN, 0); |
2422 | stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0); | |
2423 | } | |
2424 | #if 0 | |
2425 | /* Check if the tuner is locked */ | |
2426 | tuner_lock = stv0367cab_tuner_get_status(fe); | |
2427 | if (tuner_lock == 0) | |
2428 | return FE_367CAB_NOTUNER; | |
2429 | #endif | |
83a35e36 | 2430 | /* Release the TRL to start demodulator acquisition */ |
17cce932 IL |
2431 | /* Wait for QAM lock */ |
2432 | LockTime = 0; | |
2433 | stv0367_writereg(state, R367CAB_CTRL_1, 0x00); | |
2434 | do { | |
d105d083 | 2435 | QAM_Lock = stv0367cab_fsm_status(state); |
17cce932 IL |
2436 | if ((LockTime >= (DemodTimeOut - EQLTimeOut)) && |
2437 | (QAM_Lock == 0x04)) | |
2438 | /* | |
2439 | * We don't wait longer, the frequency/phase offset | |
2440 | * must be too big | |
2441 | */ | |
2442 | LockTime = DemodTimeOut; | |
2443 | else if ((LockTime >= (AGCTimeOut + TRLTimeOut)) && | |
2444 | (QAM_Lock == 0x02)) | |
2445 | /* | |
2446 | * We don't wait longer, either there is no signal or | |
2447 | * it is not the right symbol rate or it is an analog | |
2448 | * carrier | |
2449 | */ | |
2450 | { | |
2451 | LockTime = DemodTimeOut; | |
2452 | u32_tmp = stv0367_readbits(state, | |
2453 | F367CAB_AGC_PWR_WORD_LO) + | |
2454 | (stv0367_readbits(state, | |
2455 | F367CAB_AGC_PWR_WORD_ME) << 8) + | |
2456 | (stv0367_readbits(state, | |
2457 | F367CAB_AGC_PWR_WORD_HI) << 16); | |
2458 | if (u32_tmp >= 131072) | |
2459 | u32_tmp = 262144 - u32_tmp; | |
2460 | u32_tmp = u32_tmp / (1 << (11 - stv0367_readbits(state, | |
2461 | F367CAB_AGC_IF_BWSEL))); | |
2462 | ||
2463 | if (u32_tmp < stv0367_readbits(state, | |
2464 | F367CAB_AGC_PWRREF_LO) + | |
2465 | 256 * stv0367_readbits(state, | |
2466 | F367CAB_AGC_PWRREF_HI) - 10) | |
2467 | QAM_Lock = 0x0f; | |
2468 | } else { | |
2469 | usleep_range(10000, 20000); | |
2470 | LockTime += 10; | |
2471 | } | |
2472 | dprintk("QAM_Lock=0x%x LockTime=%d\n", QAM_Lock, LockTime); | |
2473 | tmp = stv0367_readreg(state, R367CAB_IT_STATUS1); | |
2474 | ||
2475 | dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp); | |
2476 | ||
2477 | } while (((QAM_Lock != 0x0c) && (QAM_Lock != 0x0b)) && | |
2478 | (LockTime < DemodTimeOut)); | |
2479 | ||
2480 | dprintk("QAM_Lock=0x%x\n", QAM_Lock); | |
2481 | ||
2482 | tmp = stv0367_readreg(state, R367CAB_IT_STATUS1); | |
2483 | dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp); | |
2484 | tmp = stv0367_readreg(state, R367CAB_IT_STATUS2); | |
2485 | dprintk("R367CAB_IT_STATUS2=0x%x\n", tmp); | |
2486 | ||
2487 | tmp = stv0367cab_get_derot_freq(state, cab_state->adc_clk); | |
2488 | dprintk("stv0367cab_get_derot_freq=0x%x\n", tmp); | |
2489 | ||
2490 | if ((QAM_Lock == 0x0c) || (QAM_Lock == 0x0b)) { | |
2491 | /* Wait for FEC lock */ | |
2492 | LockTime = 0; | |
2493 | do { | |
2494 | usleep_range(5000, 7000); | |
2495 | LockTime += 5; | |
d105d083 | 2496 | QAMFEC_Lock = stv0367cab_qamfec_lock(state); |
17cce932 IL |
2497 | } while (!QAMFEC_Lock && (LockTime < FECTimeOut)); |
2498 | } else | |
2499 | QAMFEC_Lock = 0; | |
2500 | ||
2501 | if (QAMFEC_Lock) { | |
2502 | signalType = FE_CAB_DATAOK; | |
17cce932 IL |
2503 | cab_state->spect_inv = stv0367_readbits(state, |
2504 | F367CAB_QUAD_INV); | |
2505 | #if 0 | |
2506 | /* not clear for me */ | |
b16338e3 DS |
2507 | if (ifkhz != 0) { |
2508 | if (ifkhz > cab_state->adc_clk / 1000) { | |
17cce932 IL |
2509 | cab_state->freq_khz = |
2510 | FE_Cab_TunerGetFrequency(pIntParams->hTuner) | |
2511 | - stv0367cab_get_derot_freq(state, cab_state->adc_clk) | |
b16338e3 | 2512 | - cab_state->adc_clk / 1000 + ifkhz; |
17cce932 IL |
2513 | } else { |
2514 | cab_state->freq_khz = | |
2515 | FE_Cab_TunerGetFrequency(pIntParams->hTuner) | |
2516 | - stv0367cab_get_derot_freq(state, cab_state->adc_clk) | |
b16338e3 | 2517 | + ifkhz; |
17cce932 IL |
2518 | } |
2519 | } else { | |
2520 | cab_state->freq_khz = | |
2521 | FE_Cab_TunerGetFrequency(pIntParams->hTuner) + | |
2522 | stv0367cab_get_derot_freq(state, | |
2523 | cab_state->adc_clk) - | |
2524 | cab_state->adc_clk / 4000; | |
2525 | } | |
2526 | #endif | |
2527 | cab_state->symbol_rate = stv0367cab_GetSymbolRate(state, | |
2528 | cab_state->mclk); | |
2529 | cab_state->locked = 1; | |
2530 | ||
2531 | /* stv0367_setbits(state, F367CAB_AGC_ACCUMRSTSEL,7);*/ | |
d105d083 DS |
2532 | } else |
2533 | signalType = stv0367cab_fsm_signaltype(QAM_Lock); | |
17cce932 IL |
2534 | |
2535 | /* Set the AGC control values to tracking values */ | |
2536 | stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, TrackAGCAccum); | |
2537 | return signalType; | |
2538 | } | |
2539 | ||
285d55ad | 2540 | static int stv0367cab_set_frontend(struct dvb_frontend *fe) |
17cce932 | 2541 | { |
285d55ad | 2542 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
17cce932 IL |
2543 | struct stv0367_state *state = fe->demodulator_priv; |
2544 | struct stv0367cab_state *cab_state = state->cab_state; | |
17cce932 IL |
2545 | enum stv0367cab_mod QAMSize = 0; |
2546 | ||
2547 | dprintk("%s: freq = %d, srate = %d\n", __func__, | |
285d55ad | 2548 | p->frequency, p->symbol_rate); |
17cce932 IL |
2549 | |
2550 | cab_state->derot_offset = 0; | |
2551 | ||
285d55ad | 2552 | switch (p->modulation) { |
17cce932 IL |
2553 | case QAM_16: |
2554 | QAMSize = FE_CAB_MOD_QAM16; | |
2555 | break; | |
2556 | case QAM_32: | |
2557 | QAMSize = FE_CAB_MOD_QAM32; | |
2558 | break; | |
2559 | case QAM_64: | |
2560 | QAMSize = FE_CAB_MOD_QAM64; | |
2561 | break; | |
2562 | case QAM_128: | |
2563 | QAMSize = FE_CAB_MOD_QAM128; | |
2564 | break; | |
2565 | case QAM_256: | |
2566 | QAMSize = FE_CAB_MOD_QAM256; | |
2567 | break; | |
2568 | default: | |
2569 | break; | |
2570 | } | |
2571 | ||
7718dcf0 DS |
2572 | if (state->reinit_on_setfrontend) |
2573 | stv0367cab_init(fe); | |
17cce932 IL |
2574 | |
2575 | /* Tuner Frequency Setting */ | |
2576 | if (fe->ops.tuner_ops.set_params) { | |
f61c2991 | 2577 | if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl) |
17cce932 | 2578 | fe->ops.i2c_gate_ctrl(fe, 1); |
14d24d14 | 2579 | fe->ops.tuner_ops.set_params(fe); |
f61c2991 | 2580 | if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl) |
17cce932 IL |
2581 | fe->ops.i2c_gate_ctrl(fe, 0); |
2582 | } | |
2583 | ||
2584 | stv0367cab_SetQamSize( | |
2585 | state, | |
285d55ad | 2586 | p->symbol_rate, |
17cce932 IL |
2587 | QAMSize); |
2588 | ||
2589 | stv0367cab_set_srate(state, | |
2590 | cab_state->adc_clk, | |
2591 | cab_state->mclk, | |
285d55ad | 2592 | p->symbol_rate, |
17cce932 IL |
2593 | QAMSize); |
2594 | /* Search algorithm launch, [-1.1*RangeOffset, +1.1*RangeOffset] scan */ | |
285d55ad | 2595 | cab_state->state = stv0367cab_algo(state, p); |
17cce932 IL |
2596 | return 0; |
2597 | } | |
2598 | ||
7e3e68bc MCC |
2599 | static int stv0367cab_get_frontend(struct dvb_frontend *fe, |
2600 | struct dtv_frontend_properties *p) | |
17cce932 IL |
2601 | { |
2602 | struct stv0367_state *state = fe->demodulator_priv; | |
2603 | struct stv0367cab_state *cab_state = state->cab_state; | |
b16338e3 | 2604 | u32 ifkhz = 0; |
17cce932 IL |
2605 | |
2606 | enum stv0367cab_mod QAMSize; | |
2607 | ||
2608 | dprintk("%s:\n", __func__); | |
2609 | ||
b16338e3 | 2610 | stv0367_get_if_khz(state, &ifkhz); |
285d55ad | 2611 | p->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk); |
17cce932 IL |
2612 | |
2613 | QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE); | |
2614 | switch (QAMSize) { | |
2615 | case FE_CAB_MOD_QAM16: | |
285d55ad | 2616 | p->modulation = QAM_16; |
17cce932 IL |
2617 | break; |
2618 | case FE_CAB_MOD_QAM32: | |
285d55ad | 2619 | p->modulation = QAM_32; |
17cce932 IL |
2620 | break; |
2621 | case FE_CAB_MOD_QAM64: | |
285d55ad | 2622 | p->modulation = QAM_64; |
17cce932 IL |
2623 | break; |
2624 | case FE_CAB_MOD_QAM128: | |
285d55ad | 2625 | p->modulation = QAM_128; |
17cce932 | 2626 | break; |
eafeda96 | 2627 | case FE_CAB_MOD_QAM256: |
285d55ad | 2628 | p->modulation = QAM_256; |
17cce932 IL |
2629 | break; |
2630 | default: | |
2631 | break; | |
2632 | } | |
2633 | ||
285d55ad | 2634 | p->frequency = stv0367_get_tuner_freq(fe); |
17cce932 | 2635 | |
285d55ad | 2636 | dprintk("%s: tuner frequency = %d\n", __func__, p->frequency); |
17cce932 | 2637 | |
b16338e3 | 2638 | if (ifkhz == 0) { |
285d55ad | 2639 | p->frequency += |
17cce932 IL |
2640 | (stv0367cab_get_derot_freq(state, cab_state->adc_clk) - |
2641 | cab_state->adc_clk / 4000); | |
2642 | return 0; | |
2643 | } | |
2644 | ||
b16338e3 DS |
2645 | if (ifkhz > cab_state->adc_clk / 1000) |
2646 | p->frequency += (ifkhz | |
17cce932 IL |
2647 | - stv0367cab_get_derot_freq(state, cab_state->adc_clk) |
2648 | - cab_state->adc_clk / 1000); | |
2649 | else | |
b16338e3 | 2650 | p->frequency += (ifkhz |
17cce932 IL |
2651 | - stv0367cab_get_derot_freq(state, cab_state->adc_clk)); |
2652 | ||
2653 | return 0; | |
2654 | } | |
2655 | ||
2656 | #if 0 | |
2657 | void stv0367cab_GetErrorCount(state, enum stv0367cab_mod QAMSize, | |
2658 | u32 symbol_rate, FE_367qam_Monitor *Monitor_results) | |
2659 | { | |
2660 | stv0367cab_OptimiseNByteAndGetBER(state, QAMSize, symbol_rate, Monitor_results); | |
2661 | stv0367cab_GetPacketsCount(state, Monitor_results); | |
2662 | ||
2663 | return; | |
2664 | } | |
2665 | ||
2666 | static int stv0367cab_read_ber(struct dvb_frontend *fe, u32 *ber) | |
2667 | { | |
2668 | struct stv0367_state *state = fe->demodulator_priv; | |
2669 | ||
2670 | return 0; | |
2671 | } | |
2672 | #endif | |
2673 | static s32 stv0367cab_get_rf_lvl(struct stv0367_state *state) | |
2674 | { | |
2675 | s32 rfLevel = 0; | |
2676 | s32 RfAgcPwm = 0, IfAgcPwm = 0; | |
2677 | u8 i; | |
2678 | ||
2679 | stv0367_writebits(state, F367CAB_STDBY_ADCGP, 0x0); | |
2680 | ||
2681 | RfAgcPwm = | |
2682 | (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_LO) & 0x03) + | |
2683 | (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_HI) << 2); | |
2684 | RfAgcPwm = 100 * RfAgcPwm / 1023; | |
2685 | ||
2686 | IfAgcPwm = | |
2687 | stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_LO) + | |
2688 | (stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_HI) << 8); | |
2689 | if (IfAgcPwm >= 2048) | |
2690 | IfAgcPwm -= 2048; | |
2691 | else | |
2692 | IfAgcPwm += 2048; | |
2693 | ||
2694 | IfAgcPwm = 100 * IfAgcPwm / 4095; | |
2695 | ||
2696 | /* For DTT75467 on NIM */ | |
2697 | if (RfAgcPwm < 90 && IfAgcPwm < 28) { | |
2698 | for (i = 0; i < RF_LOOKUP_TABLE_SIZE; i++) { | |
2699 | if (RfAgcPwm <= stv0367cab_RF_LookUp1[0][i]) { | |
2700 | rfLevel = (-1) * stv0367cab_RF_LookUp1[1][i]; | |
2701 | break; | |
2702 | } | |
2703 | } | |
2704 | if (i == RF_LOOKUP_TABLE_SIZE) | |
2705 | rfLevel = -56; | |
2706 | } else { /*if IF AGC>10*/ | |
2707 | for (i = 0; i < RF_LOOKUP_TABLE2_SIZE; i++) { | |
2708 | if (IfAgcPwm <= stv0367cab_RF_LookUp2[0][i]) { | |
2709 | rfLevel = (-1) * stv0367cab_RF_LookUp2[1][i]; | |
2710 | break; | |
2711 | } | |
2712 | } | |
2713 | if (i == RF_LOOKUP_TABLE2_SIZE) | |
2714 | rfLevel = -72; | |
2715 | } | |
2716 | return rfLevel; | |
2717 | } | |
2718 | ||
2719 | static int stv0367cab_read_strength(struct dvb_frontend *fe, u16 *strength) | |
2720 | { | |
2721 | struct stv0367_state *state = fe->demodulator_priv; | |
2722 | ||
2723 | s32 signal = stv0367cab_get_rf_lvl(state); | |
2724 | ||
2725 | dprintk("%s: signal=%d dBm\n", __func__, signal); | |
2726 | ||
2727 | if (signal <= -72) | |
2728 | *strength = 65535; | |
2729 | else | |
2730 | *strength = (22 + signal) * (-1311); | |
2731 | ||
2732 | dprintk("%s: strength=%d\n", __func__, (*strength)); | |
2733 | ||
2734 | return 0; | |
2735 | } | |
2736 | ||
b138afda | 2737 | static int stv0367cab_snr_power(struct dvb_frontend *fe) |
17cce932 IL |
2738 | { |
2739 | struct stv0367_state *state = fe->demodulator_priv; | |
17cce932 | 2740 | enum stv0367cab_mod QAMSize; |
17cce932 IL |
2741 | |
2742 | QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE); | |
2743 | switch (QAMSize) { | |
2744 | case FE_CAB_MOD_QAM4: | |
b138afda | 2745 | return 21904; |
17cce932 | 2746 | case FE_CAB_MOD_QAM16: |
b138afda | 2747 | return 20480; |
17cce932 | 2748 | case FE_CAB_MOD_QAM32: |
b138afda | 2749 | return 23040; |
17cce932 | 2750 | case FE_CAB_MOD_QAM64: |
b138afda | 2751 | return 21504; |
17cce932 | 2752 | case FE_CAB_MOD_QAM128: |
b138afda | 2753 | return 23616; |
17cce932 | 2754 | case FE_CAB_MOD_QAM256: |
b138afda | 2755 | return 21760; |
17cce932 | 2756 | case FE_CAB_MOD_QAM1024: |
b138afda | 2757 | return 21280; |
17cce932 | 2758 | default: |
17cce932 IL |
2759 | break; |
2760 | } | |
2761 | ||
b138afda DS |
2762 | return 1; |
2763 | } | |
2764 | ||
2765 | static int stv0367cab_snr_readreg(struct dvb_frontend *fe, int avgdiv) | |
2766 | { | |
2767 | struct stv0367_state *state = fe->demodulator_priv; | |
2768 | u32 regval = 0; | |
2769 | int i; | |
2770 | ||
17cce932 IL |
2771 | for (i = 0; i < 10; i++) { |
2772 | regval += (stv0367_readbits(state, F367CAB_SNR_LO) | |
2773 | + 256 * stv0367_readbits(state, F367CAB_SNR_HI)); | |
2774 | } | |
2775 | ||
b138afda DS |
2776 | if (avgdiv) |
2777 | regval /= 10; | |
2778 | ||
2779 | return regval; | |
2780 | } | |
2781 | ||
2782 | static int stv0367cab_read_snr(struct dvb_frontend *fe, u16 *snr) | |
2783 | { | |
2784 | struct stv0367_state *state = fe->demodulator_priv; | |
2785 | u32 noisepercentage; | |
2786 | u32 regval = 0, temp = 0; | |
2787 | int power; | |
2788 | ||
2789 | power = stv0367cab_snr_power(fe); | |
2790 | regval = stv0367cab_snr_readreg(fe, 1); | |
2791 | ||
17cce932 IL |
2792 | if (regval != 0) { |
2793 | temp = power | |
2794 | * (1 << (3 + stv0367_readbits(state, F367CAB_SNR_PER))); | |
2795 | temp /= regval; | |
2796 | } | |
2797 | ||
2798 | /* table values, not needed to calculate logarithms */ | |
2799 | if (temp >= 5012) | |
2800 | noisepercentage = 100; | |
2801 | else if (temp >= 3981) | |
2802 | noisepercentage = 93; | |
2803 | else if (temp >= 3162) | |
2804 | noisepercentage = 86; | |
2805 | else if (temp >= 2512) | |
2806 | noisepercentage = 79; | |
2807 | else if (temp >= 1995) | |
2808 | noisepercentage = 72; | |
2809 | else if (temp >= 1585) | |
2810 | noisepercentage = 65; | |
2811 | else if (temp >= 1259) | |
2812 | noisepercentage = 58; | |
2813 | else if (temp >= 1000) | |
2814 | noisepercentage = 50; | |
2815 | else if (temp >= 794) | |
2816 | noisepercentage = 43; | |
2817 | else if (temp >= 501) | |
2818 | noisepercentage = 36; | |
2819 | else if (temp >= 316) | |
2820 | noisepercentage = 29; | |
2821 | else if (temp >= 200) | |
2822 | noisepercentage = 22; | |
2823 | else if (temp >= 158) | |
2824 | noisepercentage = 14; | |
2825 | else if (temp >= 126) | |
2826 | noisepercentage = 7; | |
2827 | else | |
2828 | noisepercentage = 0; | |
2829 | ||
2830 | dprintk("%s: noisepercentage=%d\n", __func__, noisepercentage); | |
2831 | ||
2832 | *snr = (noisepercentage * 65535) / 100; | |
2833 | ||
2834 | return 0; | |
2835 | } | |
2836 | ||
78db66e5 AO |
2837 | static int stv0367cab_read_ucblcks(struct dvb_frontend *fe, u32 *ucblocks) |
2838 | { | |
2839 | struct stv0367_state *state = fe->demodulator_priv; | |
2840 | int corrected, tscount; | |
2841 | ||
2842 | *ucblocks = (stv0367_readreg(state, R367CAB_RS_COUNTER_5) << 8) | |
2843 | | stv0367_readreg(state, R367CAB_RS_COUNTER_4); | |
2844 | corrected = (stv0367_readreg(state, R367CAB_RS_COUNTER_3) << 8) | |
2845 | | stv0367_readreg(state, R367CAB_RS_COUNTER_2); | |
2846 | tscount = (stv0367_readreg(state, R367CAB_RS_COUNTER_2) << 8) | |
2847 | | stv0367_readreg(state, R367CAB_RS_COUNTER_1); | |
2848 | ||
2849 | dprintk("%s: uncorrected blocks=%d corrected blocks=%d tscount=%d\n", | |
2850 | __func__, *ucblocks, corrected, tscount); | |
2851 | ||
2852 | return 0; | |
2853 | }; | |
2854 | ||
bd336e63 | 2855 | static const struct dvb_frontend_ops stv0367cab_ops = { |
285d55ad | 2856 | .delsys = { SYS_DVBC_ANNEX_A }, |
17cce932 IL |
2857 | .info = { |
2858 | .name = "ST STV0367 DVB-C", | |
f1b1eabf MCC |
2859 | .frequency_min_hz = 47 * MHz, |
2860 | .frequency_max_hz = 862 * MHz, | |
2861 | .frequency_stepsize_hz = 62500, | |
17cce932 IL |
2862 | .symbol_rate_min = 870000, |
2863 | .symbol_rate_max = 11700000, | |
2864 | .caps = 0x400 |/* FE_CAN_QAM_4 */ | |
2865 | FE_CAN_QAM_16 | FE_CAN_QAM_32 | | |
2866 | FE_CAN_QAM_64 | FE_CAN_QAM_128 | | |
2867 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO | |
2868 | }, | |
2869 | .release = stv0367_release, | |
2870 | .init = stv0367cab_init, | |
2871 | .sleep = stv0367cab_sleep, | |
2872 | .i2c_gate_ctrl = stv0367cab_gate_ctrl, | |
285d55ad MCC |
2873 | .set_frontend = stv0367cab_set_frontend, |
2874 | .get_frontend = stv0367cab_get_frontend, | |
17cce932 IL |
2875 | .read_status = stv0367cab_read_status, |
2876 | /* .read_ber = stv0367cab_read_ber, */ | |
2877 | .read_signal_strength = stv0367cab_read_strength, | |
2878 | .read_snr = stv0367cab_read_snr, | |
78db66e5 | 2879 | .read_ucblocks = stv0367cab_read_ucblcks, |
17cce932 IL |
2880 | .get_tune_settings = stv0367_get_tune_settings, |
2881 | }; | |
2882 | ||
2883 | struct dvb_frontend *stv0367cab_attach(const struct stv0367_config *config, | |
2884 | struct i2c_adapter *i2c) | |
2885 | { | |
2886 | struct stv0367_state *state = NULL; | |
2887 | struct stv0367cab_state *cab_state = NULL; | |
2888 | ||
2889 | /* allocate memory for the internal state */ | |
2890 | state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL); | |
2891 | if (state == NULL) | |
2892 | goto error; | |
2893 | cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL); | |
2894 | if (cab_state == NULL) | |
2895 | goto error; | |
2896 | ||
2897 | /* setup the state */ | |
2898 | state->i2c = i2c; | |
2899 | state->config = config; | |
2900 | cab_state->search_range = 280000; | |
cae7a901 | 2901 | cab_state->qamfec_status_reg = F367CAB_QAMFEC_LOCK; |
17cce932 IL |
2902 | state->cab_state = cab_state; |
2903 | state->fe.ops = stv0367cab_ops; | |
2904 | state->fe.demodulator_priv = state; | |
2905 | state->chip_id = stv0367_readreg(state, 0xf000); | |
2906 | ||
f61c2991 DS |
2907 | /* demod operation options */ |
2908 | state->use_i2c_gatectrl = 1; | |
8881ceb8 | 2909 | state->deftabs = STV0367_DEFTAB_GENERIC; |
7718dcf0 | 2910 | state->reinit_on_setfrontend = 1; |
b16338e3 | 2911 | state->auto_if_khz = 0; |
f61c2991 | 2912 | |
17cce932 IL |
2913 | dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id); |
2914 | ||
2915 | /* check if the demod is there */ | |
2916 | if ((state->chip_id != 0x50) && (state->chip_id != 0x60)) | |
2917 | goto error; | |
2918 | ||
2919 | return &state->fe; | |
2920 | ||
2921 | error: | |
2922 | kfree(cab_state); | |
2923 | kfree(state); | |
2924 | return NULL; | |
2925 | } | |
2926 | EXPORT_SYMBOL(stv0367cab_attach); | |
2927 | ||
dbbac11e DS |
2928 | /* |
2929 | * Functions for operation on Digital Devices hardware | |
2930 | */ | |
2931 | ||
2932 | static void stv0367ddb_setup_ter(struct stv0367_state *state) | |
2933 | { | |
2934 | stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00); | |
2935 | stv0367_writereg(state, R367TER_DEBUG_LT5, 0x00); | |
2936 | stv0367_writereg(state, R367TER_DEBUG_LT6, 0x00); /* R367CAB_CTRL_1 */ | |
2937 | stv0367_writereg(state, R367TER_DEBUG_LT7, 0x00); /* R367CAB_CTRL_2 */ | |
2938 | stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00); | |
2939 | stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00); | |
2940 | ||
2941 | /* Tuner Setup */ | |
2942 | /* Buffer Q disabled, I Enabled, unsigned ADC */ | |
2943 | stv0367_writereg(state, R367TER_ANADIGCTRL, 0x89); | |
2944 | stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */ | |
2945 | ||
2946 | /* Clock setup */ | |
2947 | /* PLL bypassed and disabled */ | |
2948 | stv0367_writereg(state, R367TER_ANACTRL, 0x0D); | |
2949 | stv0367_writereg(state, R367TER_TOPCTRL, 0x00); /* Set OFDM */ | |
2950 | ||
2951 | /* IC runs at 54 MHz with a 27 MHz crystal */ | |
2952 | stv0367_pll_setup(state, STV0367_ICSPEED_53125, state->config->xtal); | |
2953 | ||
2954 | msleep(50); | |
2955 | /* PLL enabled and used */ | |
2956 | stv0367_writereg(state, R367TER_ANACTRL, 0x00); | |
2957 | ||
2958 | state->activedemod = demod_ter; | |
2959 | } | |
2960 | ||
2961 | static void stv0367ddb_setup_cab(struct stv0367_state *state) | |
2962 | { | |
2963 | stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00); | |
2964 | stv0367_writereg(state, R367TER_DEBUG_LT5, 0x01); | |
2965 | stv0367_writereg(state, R367TER_DEBUG_LT6, 0x06); /* R367CAB_CTRL_1 */ | |
2966 | stv0367_writereg(state, R367TER_DEBUG_LT7, 0x03); /* R367CAB_CTRL_2 */ | |
2967 | stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00); | |
2968 | stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00); | |
2969 | ||
2970 | /* Tuner Setup */ | |
2971 | /* Buffer Q disabled, I Enabled, signed ADC */ | |
2972 | stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8B); | |
2973 | /* ADCQ disabled */ | |
2974 | stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); | |
2975 | ||
2976 | /* Clock setup */ | |
2977 | /* PLL bypassed and disabled */ | |
2978 | stv0367_writereg(state, R367TER_ANACTRL, 0x0D); | |
2979 | /* Set QAM */ | |
2980 | stv0367_writereg(state, R367TER_TOPCTRL, 0x10); | |
2981 | ||
2982 | /* IC runs at 58 MHz with a 27 MHz crystal */ | |
2983 | stv0367_pll_setup(state, STV0367_ICSPEED_58000, state->config->xtal); | |
2984 | ||
2985 | msleep(50); | |
2986 | /* PLL enabled and used */ | |
2987 | stv0367_writereg(state, R367TER_ANACTRL, 0x00); | |
2988 | ||
2989 | state->cab_state->mclk = stv0367cab_get_mclk(&state->fe, | |
2990 | state->config->xtal); | |
2991 | state->cab_state->adc_clk = stv0367cab_get_adc_freq(&state->fe, | |
2992 | state->config->xtal); | |
2993 | ||
2994 | state->activedemod = demod_cab; | |
2995 | } | |
2996 | ||
2997 | static int stv0367ddb_set_frontend(struct dvb_frontend *fe) | |
2998 | { | |
2999 | struct stv0367_state *state = fe->demodulator_priv; | |
3000 | ||
3001 | switch (fe->dtv_property_cache.delivery_system) { | |
3002 | case SYS_DVBT: | |
3003 | if (state->activedemod != demod_ter) | |
3004 | stv0367ddb_setup_ter(state); | |
3005 | ||
3006 | return stv0367ter_set_frontend(fe); | |
3007 | case SYS_DVBC_ANNEX_A: | |
3008 | if (state->activedemod != demod_cab) | |
3009 | stv0367ddb_setup_cab(state); | |
3010 | ||
3011 | /* protect against division error oopses */ | |
3012 | if (fe->dtv_property_cache.symbol_rate == 0) { | |
3013 | printk(KERN_ERR "Invalid symbol rate\n"); | |
3014 | return -EINVAL; | |
3015 | } | |
3016 | ||
3017 | return stv0367cab_set_frontend(fe); | |
3018 | default: | |
3019 | break; | |
3020 | } | |
3021 | ||
3022 | return -EINVAL; | |
3023 | } | |
3024 | ||
006fe8ee DS |
3025 | static void stv0367ddb_read_signal_strength(struct dvb_frontend *fe) |
3026 | { | |
3027 | struct stv0367_state *state = fe->demodulator_priv; | |
3028 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; | |
3029 | s32 signalstrength; | |
3030 | ||
3031 | switch (state->activedemod) { | |
3032 | case demod_cab: | |
3033 | signalstrength = stv0367cab_get_rf_lvl(state) * 1000; | |
3034 | break; | |
3035 | default: | |
3036 | p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
3037 | return; | |
3038 | } | |
3039 | ||
3040 | p->strength.stat[0].scale = FE_SCALE_DECIBEL; | |
3041 | p->strength.stat[0].uvalue = signalstrength; | |
3042 | } | |
3043 | ||
d394ad12 DS |
3044 | static void stv0367ddb_read_snr(struct dvb_frontend *fe) |
3045 | { | |
3046 | struct stv0367_state *state = fe->demodulator_priv; | |
3047 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; | |
3048 | int cab_pwr; | |
3049 | u32 regval, tmpval, snrval = 0; | |
3050 | ||
3051 | switch (state->activedemod) { | |
3052 | case demod_ter: | |
3053 | snrval = stv0367ter_snr_readreg(fe); | |
3054 | break; | |
3055 | case demod_cab: | |
3056 | cab_pwr = stv0367cab_snr_power(fe); | |
3057 | regval = stv0367cab_snr_readreg(fe, 0); | |
3058 | ||
3059 | /* prevent division by zero */ | |
f5a1ba83 | 3060 | if (!regval) { |
d394ad12 | 3061 | snrval = 0; |
f5a1ba83 MCC |
3062 | break; |
3063 | } | |
d394ad12 DS |
3064 | |
3065 | tmpval = (cab_pwr * 320) / regval; | |
3066 | snrval = ((tmpval != 0) ? (intlog2(tmpval) / 5581) : 0); | |
3067 | break; | |
3068 | default: | |
3069 | p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
3070 | return; | |
3071 | } | |
3072 | ||
3073 | p->cnr.stat[0].scale = FE_SCALE_DECIBEL; | |
3074 | p->cnr.stat[0].uvalue = snrval; | |
3075 | } | |
3076 | ||
4043eb23 DS |
3077 | static void stv0367ddb_read_ucblocks(struct dvb_frontend *fe) |
3078 | { | |
3079 | struct stv0367_state *state = fe->demodulator_priv; | |
3080 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; | |
3081 | u32 ucblocks = 0; | |
3082 | ||
3083 | switch (state->activedemod) { | |
3084 | case demod_ter: | |
3085 | stv0367ter_read_ucblocks(fe, &ucblocks); | |
3086 | break; | |
3087 | case demod_cab: | |
3088 | stv0367cab_read_ucblcks(fe, &ucblocks); | |
3089 | break; | |
3090 | default: | |
3091 | p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
3092 | return; | |
3093 | } | |
3094 | ||
3095 | p->block_error.stat[0].scale = FE_SCALE_COUNTER; | |
3096 | p->block_error.stat[0].uvalue = ucblocks; | |
3097 | } | |
3098 | ||
dbbac11e DS |
3099 | static int stv0367ddb_read_status(struct dvb_frontend *fe, |
3100 | enum fe_status *status) | |
3101 | { | |
3102 | struct stv0367_state *state = fe->demodulator_priv; | |
4043eb23 | 3103 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
3658ea39 | 3104 | int ret = 0; |
dbbac11e DS |
3105 | |
3106 | switch (state->activedemod) { | |
3107 | case demod_ter: | |
4043eb23 DS |
3108 | ret = stv0367ter_read_status(fe, status); |
3109 | break; | |
dbbac11e | 3110 | case demod_cab: |
4043eb23 | 3111 | ret = stv0367cab_read_status(fe, status); |
dbbac11e | 3112 | break; |
4043eb23 | 3113 | default: |
3658ea39 | 3114 | break; |
dbbac11e DS |
3115 | } |
3116 | ||
4043eb23 DS |
3117 | /* stop and report on *_read_status failure */ |
3118 | if (ret) | |
3119 | return ret; | |
3120 | ||
006fe8ee DS |
3121 | stv0367ddb_read_signal_strength(fe); |
3122 | ||
d394ad12 DS |
3123 | /* read carrier/noise when a carrier is detected */ |
3124 | if (*status & FE_HAS_CARRIER) | |
3125 | stv0367ddb_read_snr(fe); | |
3126 | else | |
3127 | p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
3128 | ||
87b46710 DS |
3129 | /* read uncorrected blocks on FE_HAS_LOCK */ |
3130 | if (*status & FE_HAS_LOCK) | |
3131 | stv0367ddb_read_ucblocks(fe); | |
3132 | else | |
4043eb23 | 3133 | p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; |
4043eb23 DS |
3134 | |
3135 | return 0; | |
dbbac11e DS |
3136 | } |
3137 | ||
3138 | static int stv0367ddb_get_frontend(struct dvb_frontend *fe, | |
3139 | struct dtv_frontend_properties *p) | |
3140 | { | |
3141 | struct stv0367_state *state = fe->demodulator_priv; | |
3142 | ||
3143 | switch (state->activedemod) { | |
3144 | case demod_ter: | |
3145 | return stv0367ter_get_frontend(fe, p); | |
3146 | case demod_cab: | |
3147 | return stv0367cab_get_frontend(fe, p); | |
3148 | default: | |
3149 | break; | |
3150 | } | |
3151 | ||
3658ea39 | 3152 | return 0; |
dbbac11e DS |
3153 | } |
3154 | ||
3155 | static int stv0367ddb_sleep(struct dvb_frontend *fe) | |
3156 | { | |
3157 | struct stv0367_state *state = fe->demodulator_priv; | |
3158 | ||
3159 | switch (state->activedemod) { | |
3160 | case demod_ter: | |
3161 | state->activedemod = demod_none; | |
3162 | return stv0367ter_sleep(fe); | |
3163 | case demod_cab: | |
3164 | state->activedemod = demod_none; | |
3165 | return stv0367cab_sleep(fe); | |
3166 | default: | |
3167 | break; | |
3168 | } | |
3169 | ||
3170 | return -EINVAL; | |
3171 | } | |
3172 | ||
3173 | static int stv0367ddb_init(struct stv0367_state *state) | |
3174 | { | |
3175 | struct stv0367ter_state *ter_state = state->ter_state; | |
4043eb23 | 3176 | struct dtv_frontend_properties *p = &state->fe.dtv_property_cache; |
dbbac11e DS |
3177 | |
3178 | stv0367_writereg(state, R367TER_TOPCTRL, 0x10); | |
3179 | ||
3180 | if (stv0367_deftabs[state->deftabs][STV0367_TAB_BASE]) | |
3181 | stv0367_write_table(state, | |
3182 | stv0367_deftabs[state->deftabs][STV0367_TAB_BASE]); | |
3183 | ||
3184 | stv0367_write_table(state, | |
3185 | stv0367_deftabs[state->deftabs][STV0367_TAB_CAB]); | |
3186 | ||
3187 | stv0367_writereg(state, R367TER_TOPCTRL, 0x00); | |
3188 | stv0367_write_table(state, | |
3189 | stv0367_deftabs[state->deftabs][STV0367_TAB_TER]); | |
3190 | ||
3191 | stv0367_writereg(state, R367TER_GAIN_SRC1, 0x2A); | |
3192 | stv0367_writereg(state, R367TER_GAIN_SRC2, 0xD6); | |
3193 | stv0367_writereg(state, R367TER_INC_DEROT1, 0x55); | |
3194 | stv0367_writereg(state, R367TER_INC_DEROT2, 0x55); | |
3195 | stv0367_writereg(state, R367TER_TRL_CTL, 0x14); | |
3196 | stv0367_writereg(state, R367TER_TRL_NOMRATE1, 0xAE); | |
3197 | stv0367_writereg(state, R367TER_TRL_NOMRATE2, 0x56); | |
3198 | stv0367_writereg(state, R367TER_FEPATH_CFG, 0x0); | |
3199 | ||
3200 | /* OFDM TS Setup */ | |
3201 | ||
3202 | stv0367_writereg(state, R367TER_TSCFGH, 0x70); | |
3203 | stv0367_writereg(state, R367TER_TSCFGM, 0xC0); | |
3204 | stv0367_writereg(state, R367TER_TSCFGL, 0x20); | |
3205 | stv0367_writereg(state, R367TER_TSSPEED, 0x40); /* Fixed at 54 MHz */ | |
3206 | ||
3207 | stv0367_writereg(state, R367TER_TSCFGH, 0x71); | |
3208 | stv0367_writereg(state, R367TER_TSCFGH, 0x70); | |
3209 | ||
3210 | stv0367_writereg(state, R367TER_TOPCTRL, 0x10); | |
3211 | ||
3212 | /* Also needed for QAM */ | |
3213 | stv0367_writereg(state, R367TER_AGC12C, 0x01); /* AGC Pin setup */ | |
3214 | ||
3215 | stv0367_writereg(state, R367TER_AGCCTRL1, 0x8A); | |
3216 | ||
3217 | /* QAM TS setup, note exact format also depends on descrambler */ | |
3218 | /* settings */ | |
3219 | /* Inverted Clock, Swap, serial */ | |
3220 | stv0367_writereg(state, R367CAB_OUTFORMAT_0, 0x85); | |
3221 | ||
3222 | /* Clock setup (PLL bypassed and disabled) */ | |
3223 | stv0367_writereg(state, R367TER_ANACTRL, 0x0D); | |
3224 | ||
3225 | /* IC runs at 58 MHz with a 27 MHz crystal */ | |
3226 | stv0367_pll_setup(state, STV0367_ICSPEED_58000, state->config->xtal); | |
3227 | ||
3228 | /* Tuner setup */ | |
3229 | /* Buffer Q disabled, I Enabled, signed ADC */ | |
3230 | stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8b); | |
3231 | stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */ | |
3232 | ||
3233 | /* Improves the C/N lock limit */ | |
3234 | stv0367_writereg(state, R367CAB_FSM_SNR2_HTH, 0x23); | |
3235 | /* ZIF/IF Automatic mode */ | |
3236 | stv0367_writereg(state, R367CAB_IQ_QAM, 0x01); | |
3237 | /* Improving burst noise performances */ | |
3238 | stv0367_writereg(state, R367CAB_EQU_FFE_LEAKAGE, 0x83); | |
3239 | /* Improving ACI performances */ | |
3240 | stv0367_writereg(state, R367CAB_IQDEM_ADJ_EN, 0x05); | |
3241 | ||
3242 | /* PLL enabled and used */ | |
3243 | stv0367_writereg(state, R367TER_ANACTRL, 0x00); | |
3244 | ||
3245 | stv0367_writereg(state, R367TER_I2CRPT, (0x08 | ((5 & 0x07) << 4))); | |
3246 | ||
3247 | ter_state->pBER = 0; | |
3248 | ter_state->first_lock = 0; | |
3249 | ter_state->unlock_counter = 2; | |
3250 | ||
4043eb23 DS |
3251 | p->strength.len = 1; |
3252 | p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
3253 | p->cnr.len = 1; | |
3254 | p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
3255 | p->block_error.len = 1; | |
3256 | p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
3257 | ||
dbbac11e DS |
3258 | return 0; |
3259 | } | |
3260 | ||
3261 | static const struct dvb_frontend_ops stv0367ddb_ops = { | |
3262 | .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT }, | |
3263 | .info = { | |
3264 | .name = "ST STV0367 DDB DVB-C/T", | |
f1b1eabf MCC |
3265 | .frequency_min_hz = 47 * MHz, |
3266 | .frequency_max_hz = 865 * MHz, | |
3267 | .frequency_stepsize_hz = 166667, | |
dbbac11e DS |
3268 | .symbol_rate_min = 870000, |
3269 | .symbol_rate_max = 11700000, | |
3270 | .caps = /* DVB-C */ | |
3271 | 0x400 |/* FE_CAN_QAM_4 */ | |
3272 | FE_CAN_QAM_16 | FE_CAN_QAM_32 | | |
3273 | FE_CAN_QAM_64 | FE_CAN_QAM_128 | | |
c6721526 | 3274 | FE_CAN_QAM_256 | |
dbbac11e | 3275 | /* DVB-T */ |
f9c1e254 DS |
3276 | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | |
3277 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | | |
3278 | FE_CAN_QPSK | FE_CAN_TRANSMISSION_MODE_AUTO | | |
3279 | FE_CAN_RECOVER | FE_CAN_INVERSION_AUTO | | |
dbbac11e DS |
3280 | FE_CAN_MUTE_TS |
3281 | }, | |
3282 | .release = stv0367_release, | |
3283 | .sleep = stv0367ddb_sleep, | |
3284 | .i2c_gate_ctrl = stv0367cab_gate_ctrl, /* valid for TER and CAB */ | |
3285 | .set_frontend = stv0367ddb_set_frontend, | |
3286 | .get_frontend = stv0367ddb_get_frontend, | |
3287 | .get_tune_settings = stv0367_get_tune_settings, | |
3288 | .read_status = stv0367ddb_read_status, | |
3289 | }; | |
3290 | ||
3291 | struct dvb_frontend *stv0367ddb_attach(const struct stv0367_config *config, | |
3292 | struct i2c_adapter *i2c) | |
3293 | { | |
3294 | struct stv0367_state *state = NULL; | |
3295 | struct stv0367ter_state *ter_state = NULL; | |
3296 | struct stv0367cab_state *cab_state = NULL; | |
3297 | ||
3298 | /* allocate memory for the internal state */ | |
3299 | state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL); | |
3300 | if (state == NULL) | |
3301 | goto error; | |
3302 | ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL); | |
3303 | if (ter_state == NULL) | |
3304 | goto error; | |
3305 | cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL); | |
3306 | if (cab_state == NULL) | |
3307 | goto error; | |
3308 | ||
3309 | /* setup the state */ | |
3310 | state->i2c = i2c; | |
3311 | state->config = config; | |
3312 | state->ter_state = ter_state; | |
3313 | cab_state->search_range = 280000; | |
3314 | cab_state->qamfec_status_reg = F367CAB_DESCR_SYNCSTATE; | |
3315 | state->cab_state = cab_state; | |
3316 | state->fe.ops = stv0367ddb_ops; | |
3317 | state->fe.demodulator_priv = state; | |
3318 | state->chip_id = stv0367_readreg(state, R367TER_ID); | |
3319 | ||
3320 | /* demod operation options */ | |
3321 | state->use_i2c_gatectrl = 0; | |
3322 | state->deftabs = STV0367_DEFTAB_DDB; | |
3323 | state->reinit_on_setfrontend = 0; | |
3324 | state->auto_if_khz = 1; | |
3325 | state->activedemod = demod_none; | |
3326 | ||
3327 | dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id); | |
3328 | ||
3329 | /* check if the demod is there */ | |
3330 | if ((state->chip_id != 0x50) && (state->chip_id != 0x60)) | |
3331 | goto error; | |
3332 | ||
3333 | dev_info(&i2c->dev, "Found %s with ChipID %02X at adr %02X\n", | |
3334 | state->fe.ops.info.name, state->chip_id, | |
3335 | config->demod_address); | |
3336 | ||
3337 | stv0367ddb_init(state); | |
3338 | ||
3339 | return &state->fe; | |
3340 | ||
3341 | error: | |
3342 | kfree(cab_state); | |
3343 | kfree(ter_state); | |
3344 | kfree(state); | |
3345 | return NULL; | |
3346 | } | |
3347 | EXPORT_SYMBOL(stv0367ddb_attach); | |
3348 | ||
17cce932 IL |
3349 | MODULE_PARM_DESC(debug, "Set debug"); |
3350 | MODULE_PARM_DESC(i2c_debug, "Set i2c debug"); | |
3351 | ||
3352 | MODULE_AUTHOR("Igor M. Liplianin"); | |
3353 | MODULE_DESCRIPTION("ST STV0367 DVB-C/T demodulator driver"); | |
3354 | MODULE_LICENSE("GPL"); |