Commit | Line | Data |
---|---|---|
3e54a169 | 1 | /* |
18349f40 MS |
2 | * Driver for Silicon Labs Si2161 DVB-T and Si2165 DVB-C/-T Demodulator |
3 | * | |
77f887cd | 4 | * Copyright (C) 2013-2017 Matthias Schwarzott <zzam@gentoo.org> |
18349f40 MS |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * References: | |
17 | * http://www.silabs.com/Support%20Documents/TechnicalDocs/Si2165-short.pdf | |
18 | */ | |
3e54a169 MS |
19 | |
20 | #include <linux/delay.h> | |
21 | #include <linux/errno.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/string.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/firmware.h> | |
e3ea5e94 | 28 | #include <linux/regmap.h> |
3e54a169 | 29 | |
fada1935 MCC |
30 | #include <media/dvb_frontend.h> |
31 | #include <media/dvb_math.h> | |
3e54a169 MS |
32 | #include "si2165_priv.h" |
33 | #include "si2165.h" | |
34 | ||
18349f40 MS |
35 | /* |
36 | * Hauppauge WinTV-HVR-930C-HD B130 / PCTV QuatroStick 521e 1113xx | |
37 | * uses 16 MHz xtal | |
38 | * | |
39 | * Hauppauge WinTV-HVR-930C-HD B131 / PCTV QuatroStick 522e 1114xx | |
40 | * uses 24 MHz clock provided by tuner | |
41 | */ | |
3e54a169 MS |
42 | |
43 | struct si2165_state { | |
7cd785ad MS |
44 | struct i2c_client *client; |
45 | ||
e3ea5e94 | 46 | struct regmap *regmap; |
3e54a169 | 47 | |
d9a201df | 48 | struct dvb_frontend fe; |
3e54a169 MS |
49 | |
50 | struct si2165_config config; | |
51 | ||
55bea400 | 52 | u8 chip_revcode; |
3e54a169 MS |
53 | u8 chip_type; |
54 | ||
55 | /* calculated by xtal and div settings */ | |
56 | u32 fvco_hz; | |
57 | u32 sys_clk; | |
58 | u32 adc_clk; | |
59 | ||
e9c7d19a MS |
60 | /* DVBv3 stats */ |
61 | u64 ber_prev; | |
62 | ||
3e54a169 MS |
63 | bool has_dvbc; |
64 | bool has_dvbt; | |
65 | bool firmware_loaded; | |
66 | }; | |
67 | ||
3e54a169 | 68 | static int si2165_write(struct si2165_state *state, const u16 reg, |
7dbbb4bf | 69 | const u8 *src, const int count) |
3e54a169 MS |
70 | { |
71 | int ret; | |
3e54a169 | 72 | |
7dbbb4bf MS |
73 | dev_dbg(&state->client->dev, "i2c write: reg: 0x%04x, data: %*ph\n", |
74 | reg, count, src); | |
3e54a169 | 75 | |
e3ea5e94 | 76 | ret = regmap_bulk_write(state->regmap, reg, src, count); |
3e54a169 | 77 | |
e3ea5e94 | 78 | if (ret) |
aa155449 | 79 | dev_err(&state->client->dev, "%s: ret == %d\n", __func__, ret); |
3e54a169 | 80 | |
e3ea5e94 | 81 | return ret; |
3e54a169 MS |
82 | } |
83 | ||
84 | static int si2165_read(struct si2165_state *state, | |
85 | const u16 reg, u8 *val, const int count) | |
86 | { | |
e3ea5e94 | 87 | int ret = regmap_bulk_read(state->regmap, reg, val, count); |
3e54a169 | 88 | |
e3ea5e94 | 89 | if (ret) { |
aa155449 | 90 | dev_err(&state->client->dev, "%s: error (addr %02x reg %04x error (ret == %i)\n", |
3e54a169 | 91 | __func__, state->config.i2c_addr, reg, ret); |
e3ea5e94 | 92 | return ret; |
3e54a169 MS |
93 | } |
94 | ||
7dbbb4bf MS |
95 | dev_dbg(&state->client->dev, "i2c read: reg: 0x%04x, data: %*ph\n", |
96 | reg, count, val); | |
3e54a169 MS |
97 | |
98 | return 0; | |
99 | } | |
100 | ||
101 | static int si2165_readreg8(struct si2165_state *state, | |
7dbbb4bf | 102 | const u16 reg, u8 *val) |
3e54a169 | 103 | { |
e3ea5e94 MS |
104 | unsigned int val_tmp; |
105 | int ret = regmap_read(state->regmap, reg, &val_tmp); | |
106 | *val = (u8)val_tmp; | |
1b54da77 | 107 | dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%02x\n", reg, *val); |
3e54a169 MS |
108 | return ret; |
109 | } | |
110 | ||
111 | static int si2165_readreg16(struct si2165_state *state, | |
7dbbb4bf | 112 | const u16 reg, u16 *val) |
3e54a169 MS |
113 | { |
114 | u8 buf[2]; | |
115 | ||
116 | int ret = si2165_read(state, reg, buf, 2); | |
117 | *val = buf[0] | buf[1] << 8; | |
1b54da77 | 118 | dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%04x\n", reg, *val); |
3e54a169 MS |
119 | return ret; |
120 | } | |
121 | ||
c0675d0b MS |
122 | static int si2165_readreg24(struct si2165_state *state, |
123 | const u16 reg, u32 *val) | |
124 | { | |
125 | u8 buf[3]; | |
126 | ||
127 | int ret = si2165_read(state, reg, buf, 3); | |
128 | *val = buf[0] | buf[1] << 8 | buf[2] << 16; | |
129 | dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%06x\n", reg, *val); | |
130 | return ret; | |
131 | } | |
132 | ||
3e54a169 MS |
133 | static int si2165_writereg8(struct si2165_state *state, const u16 reg, u8 val) |
134 | { | |
e3ea5e94 | 135 | return regmap_write(state->regmap, reg, val); |
3e54a169 MS |
136 | } |
137 | ||
138 | static int si2165_writereg16(struct si2165_state *state, const u16 reg, u16 val) | |
139 | { | |
140 | u8 buf[2] = { val & 0xff, (val >> 8) & 0xff }; | |
141 | ||
142 | return si2165_write(state, reg, buf, 2); | |
143 | } | |
144 | ||
145 | static int si2165_writereg24(struct si2165_state *state, const u16 reg, u32 val) | |
146 | { | |
147 | u8 buf[3] = { val & 0xff, (val >> 8) & 0xff, (val >> 16) & 0xff }; | |
148 | ||
149 | return si2165_write(state, reg, buf, 3); | |
150 | } | |
151 | ||
152 | static int si2165_writereg32(struct si2165_state *state, const u16 reg, u32 val) | |
153 | { | |
154 | u8 buf[4] = { | |
155 | val & 0xff, | |
156 | (val >> 8) & 0xff, | |
157 | (val >> 16) & 0xff, | |
158 | (val >> 24) & 0xff | |
159 | }; | |
160 | return si2165_write(state, reg, buf, 4); | |
161 | } | |
162 | ||
163 | static int si2165_writereg_mask8(struct si2165_state *state, const u16 reg, | |
164 | u8 val, u8 mask) | |
165 | { | |
3e54a169 | 166 | if (mask != 0xff) { |
c2e5c951 ME |
167 | u8 tmp; |
168 | int ret = si2165_readreg8(state, reg, &tmp); | |
169 | ||
3e54a169 | 170 | if (ret < 0) |
c2e5c951 | 171 | return ret; |
3e54a169 MS |
172 | |
173 | val &= mask; | |
174 | tmp &= ~mask; | |
175 | val |= tmp; | |
176 | } | |
c2e5c951 | 177 | return si2165_writereg8(state, reg, val); |
3e54a169 MS |
178 | } |
179 | ||
7dbbb4bf MS |
180 | #define REG16(reg, val) \ |
181 | { (reg), (val) & 0xff }, \ | |
182 | { (reg) + 1, (val) >> 8 & 0xff } | |
a5293dbd MS |
183 | struct si2165_reg_value_pair { |
184 | u16 reg; | |
185 | u8 val; | |
186 | }; | |
187 | ||
188 | static int si2165_write_reg_list(struct si2165_state *state, | |
189 | const struct si2165_reg_value_pair *regs, | |
190 | int count) | |
191 | { | |
192 | int i; | |
193 | int ret; | |
194 | ||
195 | for (i = 0; i < count; i++) { | |
196 | ret = si2165_writereg8(state, regs[i].reg, regs[i].val); | |
197 | if (ret < 0) | |
198 | return ret; | |
199 | } | |
200 | return 0; | |
201 | } | |
202 | ||
3e54a169 MS |
203 | static int si2165_get_tune_settings(struct dvb_frontend *fe, |
204 | struct dvb_frontend_tune_settings *s) | |
205 | { | |
206 | s->min_delay_ms = 1000; | |
207 | return 0; | |
208 | } | |
209 | ||
210 | static int si2165_init_pll(struct si2165_state *state) | |
211 | { | |
7dbbb4bf | 212 | u32 ref_freq_hz = state->config.ref_freq_hz; |
3e54a169 MS |
213 | u8 divr = 1; /* 1..7 */ |
214 | u8 divp = 1; /* only 1 or 4 */ | |
215 | u8 divn = 56; /* 1..63 */ | |
216 | u8 divm = 8; | |
217 | u8 divl = 12; | |
218 | u8 buf[4]; | |
219 | ||
18349f40 MS |
220 | /* |
221 | * hardcoded values can be deleted if calculation is verified | |
222 | * or it yields the same values as the windows driver | |
223 | */ | |
7dbbb4bf | 224 | switch (ref_freq_hz) { |
3e54a169 MS |
225 | case 16000000u: |
226 | divn = 56; | |
227 | break; | |
228 | case 24000000u: | |
229 | divr = 2; | |
230 | divp = 4; | |
231 | divn = 19; | |
232 | break; | |
233 | default: | |
234 | /* ref_freq / divr must be between 4 and 16 MHz */ | |
7dbbb4bf | 235 | if (ref_freq_hz > 16000000u) |
3e54a169 MS |
236 | divr = 2; |
237 | ||
18349f40 MS |
238 | /* |
239 | * now select divn and divp such that | |
240 | * fvco is in 1624..1824 MHz | |
241 | */ | |
7dbbb4bf | 242 | if (1624000000u * divr > ref_freq_hz * 2u * 63u) |
3e54a169 MS |
243 | divp = 4; |
244 | ||
245 | /* is this already correct regarding rounding? */ | |
7dbbb4bf | 246 | divn = 1624000000u * divr / (ref_freq_hz * 2u * divp); |
3e54a169 MS |
247 | break; |
248 | } | |
249 | ||
250 | /* adc_clk and sys_clk depend on xtal and pll settings */ | |
7dbbb4bf | 251 | state->fvco_hz = ref_freq_hz / divr |
3e54a169 MS |
252 | * 2u * divn * divp; |
253 | state->adc_clk = state->fvco_hz / (divm * 4u); | |
254 | state->sys_clk = state->fvco_hz / (divl * 2u); | |
255 | ||
814f86c9 | 256 | /* write all 4 pll registers 0x00a0..0x00a3 at once */ |
3e54a169 MS |
257 | buf[0] = divl; |
258 | buf[1] = divm; | |
259 | buf[2] = (divn & 0x3f) | ((divp == 1) ? 0x40 : 0x00) | 0x80; | |
260 | buf[3] = divr; | |
814f86c9 | 261 | return si2165_write(state, REG_PLL_DIVL, buf, 4); |
3e54a169 MS |
262 | } |
263 | ||
264 | static int si2165_adjust_pll_divl(struct si2165_state *state, u8 divl) | |
265 | { | |
266 | state->sys_clk = state->fvco_hz / (divl * 2u); | |
814f86c9 | 267 | return si2165_writereg8(state, REG_PLL_DIVL, divl); |
3e54a169 MS |
268 | } |
269 | ||
270 | static u32 si2165_get_fe_clk(struct si2165_state *state) | |
271 | { | |
272 | /* assume Oversampling mode Ovr4 is used */ | |
273 | return state->adc_clk; | |
274 | } | |
275 | ||
e73c7bfe | 276 | static int si2165_wait_init_done(struct si2165_state *state) |
3e54a169 MS |
277 | { |
278 | int ret = -EINVAL; | |
279 | u8 val = 0; | |
280 | int i; | |
281 | ||
282 | for (i = 0; i < 3; ++i) { | |
814f86c9 | 283 | si2165_readreg8(state, REG_INIT_DONE, &val); |
3e54a169 MS |
284 | if (val == 0x01) |
285 | return 0; | |
286 | usleep_range(1000, 50000); | |
287 | } | |
77f887cd | 288 | dev_err(&state->client->dev, "init_done was not set\n"); |
3e54a169 MS |
289 | return ret; |
290 | } | |
291 | ||
292 | static int si2165_upload_firmware_block(struct si2165_state *state, | |
7dbbb4bf MS |
293 | const u8 *data, u32 len, u32 *poffset, |
294 | u32 block_count) | |
3e54a169 MS |
295 | { |
296 | int ret; | |
297 | u8 buf_ctrl[4] = { 0x00, 0x00, 0x00, 0xc0 }; | |
298 | u8 wordcount; | |
299 | u32 cur_block = 0; | |
300 | u32 offset = poffset ? *poffset : 0; | |
301 | ||
302 | if (len < 4) | |
303 | return -EINVAL; | |
304 | if (len % 4 != 0) | |
305 | return -EINVAL; | |
306 | ||
1b54da77 | 307 | dev_dbg(&state->client->dev, |
7dbbb4bf MS |
308 | "fw load: %s: called with len=0x%x offset=0x%x blockcount=0x%x\n", |
309 | __func__, len, offset, block_count); | |
310 | while (offset + 12 <= len && cur_block < block_count) { | |
1b54da77 | 311 | dev_dbg(&state->client->dev, |
7dbbb4bf MS |
312 | "fw load: %s: in while len=0x%x offset=0x%x cur_block=0x%x blockcount=0x%x\n", |
313 | __func__, len, offset, cur_block, block_count); | |
3e54a169 | 314 | wordcount = data[offset]; |
7dbbb4bf MS |
315 | if (wordcount < 1 || data[offset + 1] || |
316 | data[offset + 2] || data[offset + 3]) { | |
aa155449 | 317 | dev_warn(&state->client->dev, |
77f887cd MS |
318 | "bad fw data[0..3] = %*ph\n", |
319 | 4, data); | |
3e54a169 MS |
320 | return -EINVAL; |
321 | } | |
322 | ||
323 | if (offset + 8 + wordcount * 4 > len) { | |
aa155449 | 324 | dev_warn(&state->client->dev, |
77f887cd MS |
325 | "len is too small for block len=%d, wordcount=%d\n", |
326 | len, wordcount); | |
3e54a169 MS |
327 | return -EINVAL; |
328 | } | |
329 | ||
330 | buf_ctrl[0] = wordcount - 1; | |
331 | ||
814f86c9 | 332 | ret = si2165_write(state, REG_DCOM_CONTROL_BYTE, buf_ctrl, 4); |
3e54a169 MS |
333 | if (ret < 0) |
334 | goto error; | |
814f86c9 | 335 | ret = si2165_write(state, REG_DCOM_ADDR, data + offset + 4, 4); |
3e54a169 MS |
336 | if (ret < 0) |
337 | goto error; | |
338 | ||
339 | offset += 8; | |
340 | ||
341 | while (wordcount > 0) { | |
814f86c9 MS |
342 | ret = si2165_write(state, REG_DCOM_DATA, |
343 | data + offset, 4); | |
3e54a169 MS |
344 | if (ret < 0) |
345 | goto error; | |
346 | wordcount--; | |
347 | offset += 4; | |
348 | } | |
349 | cur_block++; | |
350 | } | |
351 | ||
1b54da77 | 352 | dev_dbg(&state->client->dev, |
7dbbb4bf MS |
353 | "fw load: %s: after while len=0x%x offset=0x%x cur_block=0x%x blockcount=0x%x\n", |
354 | __func__, len, offset, cur_block, block_count); | |
3e54a169 MS |
355 | |
356 | if (poffset) | |
357 | *poffset = offset; | |
358 | ||
1b54da77 | 359 | dev_dbg(&state->client->dev, |
7dbbb4bf MS |
360 | "fw load: %s: returned offset=0x%x\n", |
361 | __func__, offset); | |
3e54a169 MS |
362 | |
363 | return 0; | |
364 | error: | |
365 | return ret; | |
366 | } | |
367 | ||
368 | static int si2165_upload_firmware(struct si2165_state *state) | |
369 | { | |
370 | /* int ret; */ | |
371 | u8 val[3]; | |
372 | u16 val16; | |
373 | int ret; | |
374 | ||
375 | const struct firmware *fw = NULL; | |
55bea400 | 376 | u8 *fw_file; |
3e54a169 MS |
377 | const u8 *data; |
378 | u32 len; | |
379 | u32 offset; | |
380 | u8 patch_version; | |
381 | u8 block_count; | |
382 | u16 crc_expected; | |
383 | ||
55bea400 MS |
384 | switch (state->chip_revcode) { |
385 | case 0x03: /* revision D */ | |
386 | fw_file = SI2165_FIRMWARE_REV_D; | |
387 | break; | |
388 | default: | |
77f887cd | 389 | dev_info(&state->client->dev, "no firmware file for revision=%d\n", |
7dbbb4bf | 390 | state->chip_revcode); |
55bea400 MS |
391 | return 0; |
392 | } | |
393 | ||
3e54a169 | 394 | /* request the firmware, this will block and timeout */ |
aa155449 | 395 | ret = request_firmware(&fw, fw_file, &state->client->dev); |
3e54a169 | 396 | if (ret) { |
77f887cd | 397 | dev_warn(&state->client->dev, "firmware file '%s' not found\n", |
7dbbb4bf | 398 | fw_file); |
3e54a169 MS |
399 | goto error; |
400 | } | |
401 | ||
402 | data = fw->data; | |
403 | len = fw->size; | |
404 | ||
77f887cd | 405 | dev_info(&state->client->dev, "downloading firmware from file '%s' size=%d\n", |
7dbbb4bf | 406 | fw_file, len); |
3e54a169 MS |
407 | |
408 | if (len % 4 != 0) { | |
77f887cd | 409 | dev_warn(&state->client->dev, "firmware size is not multiple of 4\n"); |
3e54a169 MS |
410 | ret = -EINVAL; |
411 | goto error; | |
412 | } | |
413 | ||
414 | /* check header (8 bytes) */ | |
415 | if (len < 8) { | |
77f887cd | 416 | dev_warn(&state->client->dev, "firmware header is missing\n"); |
3e54a169 MS |
417 | ret = -EINVAL; |
418 | goto error; | |
419 | } | |
420 | ||
421 | if (data[0] != 1 || data[1] != 0) { | |
77f887cd | 422 | dev_warn(&state->client->dev, "firmware file version is wrong\n"); |
3e54a169 MS |
423 | ret = -EINVAL; |
424 | goto error; | |
425 | } | |
426 | ||
427 | patch_version = data[2]; | |
428 | block_count = data[4]; | |
429 | crc_expected = data[7] << 8 | data[6]; | |
430 | ||
431 | /* start uploading fw */ | |
432 | /* boot/wdog status */ | |
814f86c9 | 433 | ret = si2165_writereg8(state, REG_WDOG_AND_BOOT, 0x00); |
3e54a169 MS |
434 | if (ret < 0) |
435 | goto error; | |
436 | /* reset */ | |
814f86c9 | 437 | ret = si2165_writereg8(state, REG_RST_ALL, 0x00); |
3e54a169 MS |
438 | if (ret < 0) |
439 | goto error; | |
440 | /* boot/wdog status */ | |
814f86c9 | 441 | ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val); |
3e54a169 MS |
442 | if (ret < 0) |
443 | goto error; | |
444 | ||
445 | /* enable reset on error */ | |
814f86c9 | 446 | ret = si2165_readreg8(state, REG_EN_RST_ERROR, val); |
3e54a169 MS |
447 | if (ret < 0) |
448 | goto error; | |
814f86c9 | 449 | ret = si2165_readreg8(state, REG_EN_RST_ERROR, val); |
3e54a169 MS |
450 | if (ret < 0) |
451 | goto error; | |
814f86c9 | 452 | ret = si2165_writereg8(state, REG_EN_RST_ERROR, 0x02); |
3e54a169 MS |
453 | if (ret < 0) |
454 | goto error; | |
455 | ||
456 | /* start right after the header */ | |
457 | offset = 8; | |
458 | ||
7dbbb4bf MS |
459 | dev_info(&state->client->dev, "%s: extracted patch_version=0x%02x, block_count=0x%02x, crc_expected=0x%04x\n", |
460 | __func__, patch_version, block_count, crc_expected); | |
3e54a169 MS |
461 | |
462 | ret = si2165_upload_firmware_block(state, data, len, &offset, 1); | |
463 | if (ret < 0) | |
464 | goto error; | |
465 | ||
814f86c9 | 466 | ret = si2165_writereg8(state, REG_PATCH_VERSION, patch_version); |
3e54a169 MS |
467 | if (ret < 0) |
468 | goto error; | |
469 | ||
470 | /* reset crc */ | |
814f86c9 | 471 | ret = si2165_writereg8(state, REG_RST_CRC, 0x01); |
3e54a169 | 472 | if (ret) |
ec73b9fd | 473 | goto error; |
3e54a169 MS |
474 | |
475 | ret = si2165_upload_firmware_block(state, data, len, | |
476 | &offset, block_count); | |
477 | if (ret < 0) { | |
aa155449 | 478 | dev_err(&state->client->dev, |
77f887cd | 479 | "firmware could not be uploaded\n"); |
3e54a169 MS |
480 | goto error; |
481 | } | |
482 | ||
483 | /* read crc */ | |
814f86c9 | 484 | ret = si2165_readreg16(state, REG_CRC, &val16); |
3e54a169 MS |
485 | if (ret) |
486 | goto error; | |
487 | ||
488 | if (val16 != crc_expected) { | |
aa155449 | 489 | dev_err(&state->client->dev, |
77f887cd MS |
490 | "firmware crc mismatch %04x != %04x\n", |
491 | val16, crc_expected); | |
3e54a169 MS |
492 | ret = -EINVAL; |
493 | goto error; | |
494 | } | |
495 | ||
496 | ret = si2165_upload_firmware_block(state, data, len, &offset, 5); | |
497 | if (ret) | |
498 | goto error; | |
499 | ||
500 | if (len != offset) { | |
aa155449 | 501 | dev_err(&state->client->dev, |
77f887cd MS |
502 | "firmware len mismatch %04x != %04x\n", |
503 | len, offset); | |
3e54a169 MS |
504 | ret = -EINVAL; |
505 | goto error; | |
506 | } | |
507 | ||
508 | /* reset watchdog error register */ | |
814f86c9 | 509 | ret = si2165_writereg_mask8(state, REG_WDOG_AND_BOOT, 0x02, 0x02); |
3e54a169 MS |
510 | if (ret < 0) |
511 | goto error; | |
512 | ||
513 | /* enable reset on error */ | |
814f86c9 | 514 | ret = si2165_writereg_mask8(state, REG_EN_RST_ERROR, 0x01, 0x01); |
3e54a169 MS |
515 | if (ret < 0) |
516 | goto error; | |
517 | ||
77f887cd | 518 | dev_info(&state->client->dev, "fw load finished\n"); |
3e54a169 MS |
519 | |
520 | ret = 0; | |
521 | state->firmware_loaded = true; | |
522 | error: | |
523 | if (fw) { | |
524 | release_firmware(fw); | |
525 | fw = NULL; | |
526 | } | |
527 | ||
528 | return ret; | |
529 | } | |
530 | ||
531 | static int si2165_init(struct dvb_frontend *fe) | |
532 | { | |
533 | int ret = 0; | |
534 | struct si2165_state *state = fe->demodulator_priv; | |
c0675d0b | 535 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
3e54a169 MS |
536 | u8 val; |
537 | u8 patch_version = 0x00; | |
538 | ||
1b54da77 | 539 | dev_dbg(&state->client->dev, "%s: called\n", __func__); |
3e54a169 MS |
540 | |
541 | /* powerup */ | |
814f86c9 | 542 | ret = si2165_writereg8(state, REG_CHIP_MODE, state->config.chip_mode); |
3e54a169 MS |
543 | if (ret < 0) |
544 | goto error; | |
545 | /* dsp_clock_enable */ | |
814f86c9 | 546 | ret = si2165_writereg8(state, REG_DSP_CLOCK, 0x01); |
3e54a169 MS |
547 | if (ret < 0) |
548 | goto error; | |
814f86c9 MS |
549 | /* verify chip_mode */ |
550 | ret = si2165_readreg8(state, REG_CHIP_MODE, &val); | |
3e54a169 MS |
551 | if (ret < 0) |
552 | goto error; | |
553 | if (val != state->config.chip_mode) { | |
77f887cd | 554 | dev_err(&state->client->dev, "could not set chip_mode\n"); |
3e54a169 MS |
555 | return -EINVAL; |
556 | } | |
557 | ||
558 | /* agc */ | |
814f86c9 | 559 | ret = si2165_writereg8(state, REG_AGC_IF_TRI, 0x00); |
3e54a169 MS |
560 | if (ret < 0) |
561 | goto error; | |
814f86c9 | 562 | ret = si2165_writereg8(state, REG_AGC_IF_SLR, 0x01); |
3e54a169 MS |
563 | if (ret < 0) |
564 | goto error; | |
814f86c9 | 565 | ret = si2165_writereg8(state, REG_AGC2_OUTPUT, 0x00); |
3e54a169 MS |
566 | if (ret < 0) |
567 | goto error; | |
814f86c9 | 568 | ret = si2165_writereg8(state, REG_AGC2_CLKDIV, 0x07); |
3e54a169 MS |
569 | if (ret < 0) |
570 | goto error; | |
571 | /* rssi pad */ | |
814f86c9 | 572 | ret = si2165_writereg8(state, REG_RSSI_PAD_CTRL, 0x00); |
3e54a169 MS |
573 | if (ret < 0) |
574 | goto error; | |
814f86c9 | 575 | ret = si2165_writereg8(state, REG_RSSI_ENABLE, 0x00); |
3e54a169 MS |
576 | if (ret < 0) |
577 | goto error; | |
578 | ||
579 | ret = si2165_init_pll(state); | |
580 | if (ret < 0) | |
581 | goto error; | |
582 | ||
583 | /* enable chip_init */ | |
814f86c9 | 584 | ret = si2165_writereg8(state, REG_CHIP_INIT, 0x01); |
3e54a169 MS |
585 | if (ret < 0) |
586 | goto error; | |
587 | /* set start_init */ | |
814f86c9 | 588 | ret = si2165_writereg8(state, REG_START_INIT, 0x01); |
3e54a169 MS |
589 | if (ret < 0) |
590 | goto error; | |
591 | ret = si2165_wait_init_done(state); | |
592 | if (ret < 0) | |
593 | goto error; | |
594 | ||
595 | /* disable chip_init */ | |
814f86c9 | 596 | ret = si2165_writereg8(state, REG_CHIP_INIT, 0x00); |
3e54a169 MS |
597 | if (ret < 0) |
598 | goto error; | |
599 | ||
964b3727 MS |
600 | /* ber_pkt - default 65535 */ |
601 | ret = si2165_writereg16(state, REG_BER_PKT, | |
602 | STATISTICS_PERIOD_PKT_COUNT); | |
3e54a169 MS |
603 | if (ret < 0) |
604 | goto error; | |
605 | ||
814f86c9 | 606 | ret = si2165_readreg8(state, REG_PATCH_VERSION, &patch_version); |
3e54a169 MS |
607 | if (ret < 0) |
608 | goto error; | |
609 | ||
814f86c9 | 610 | ret = si2165_writereg8(state, REG_AUTO_RESET, 0x00); |
3e54a169 MS |
611 | if (ret < 0) |
612 | goto error; | |
613 | ||
614 | /* dsp_addr_jump */ | |
814f86c9 | 615 | ret = si2165_writereg32(state, REG_ADDR_JUMP, 0xf4000000); |
3e54a169 MS |
616 | if (ret < 0) |
617 | goto error; | |
618 | /* boot/wdog status */ | |
814f86c9 | 619 | ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, &val); |
3e54a169 MS |
620 | if (ret < 0) |
621 | goto error; | |
622 | ||
623 | if (patch_version == 0x00) { | |
624 | ret = si2165_upload_firmware(state); | |
625 | if (ret < 0) | |
626 | goto error; | |
627 | } | |
628 | ||
75d62fc0 | 629 | /* ts output config */ |
814f86c9 | 630 | ret = si2165_writereg8(state, REG_TS_DATA_MODE, 0x20); |
75d62fc0 MS |
631 | if (ret < 0) |
632 | return ret; | |
814f86c9 | 633 | ret = si2165_writereg16(state, REG_TS_TRI, 0x00fe); |
75d62fc0 MS |
634 | if (ret < 0) |
635 | return ret; | |
814f86c9 | 636 | ret = si2165_writereg24(state, REG_TS_SLR, 0x555555); |
75d62fc0 MS |
637 | if (ret < 0) |
638 | return ret; | |
814f86c9 | 639 | ret = si2165_writereg8(state, REG_TS_CLK_MODE, 0x01); |
ec278f87 MS |
640 | if (ret < 0) |
641 | return ret; | |
642 | ret = si2165_writereg8(state, REG_TS_PARALLEL_MODE, 0x00); | |
75d62fc0 MS |
643 | if (ret < 0) |
644 | return ret; | |
645 | ||
c0675d0b MS |
646 | c = &state->fe.dtv_property_cache; |
647 | c->cnr.len = 1; | |
648 | c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
964b3727 MS |
649 | c->post_bit_error.len = 1; |
650 | c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
651 | c->post_bit_count.len = 1; | |
652 | c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
c0675d0b | 653 | |
3e54a169 MS |
654 | return 0; |
655 | error: | |
656 | return ret; | |
657 | } | |
658 | ||
659 | static int si2165_sleep(struct dvb_frontend *fe) | |
660 | { | |
661 | int ret; | |
662 | struct si2165_state *state = fe->demodulator_priv; | |
663 | ||
664 | /* dsp clock disable */ | |
814f86c9 | 665 | ret = si2165_writereg8(state, REG_DSP_CLOCK, 0x00); |
3e54a169 MS |
666 | if (ret < 0) |
667 | return ret; | |
668 | /* chip mode */ | |
814f86c9 | 669 | ret = si2165_writereg8(state, REG_CHIP_MODE, SI2165_MODE_OFF); |
3e54a169 MS |
670 | if (ret < 0) |
671 | return ret; | |
672 | return 0; | |
673 | } | |
674 | ||
0df289a2 | 675 | static int si2165_read_status(struct dvb_frontend *fe, enum fe_status *status) |
3e54a169 MS |
676 | { |
677 | int ret; | |
1e5fde1b | 678 | u8 u8tmp; |
c0675d0b | 679 | u32 u32tmp; |
3e54a169 | 680 | struct si2165_state *state = fe->demodulator_priv; |
c0675d0b MS |
681 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
682 | u32 delsys = c->delivery_system; | |
3e54a169 | 683 | |
1e5fde1b MS |
684 | *status = 0; |
685 | ||
686 | switch (delsys) { | |
687 | case SYS_DVBT: | |
688 | /* check fast signal type */ | |
689 | ret = si2165_readreg8(state, REG_CHECK_SIGNAL, &u8tmp); | |
690 | if (ret < 0) | |
691 | return ret; | |
692 | switch (u8tmp & 0x3) { | |
693 | case 0: /* searching */ | |
694 | case 1: /* nothing */ | |
695 | break; | |
696 | case 2: /* digital signal */ | |
697 | *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER; | |
698 | break; | |
699 | } | |
700 | break; | |
701 | case SYS_DVBC_ANNEX_A: | |
702 | /* check packet sync lock */ | |
703 | ret = si2165_readreg8(state, REG_PS_LOCK, &u8tmp); | |
704 | if (ret < 0) | |
705 | return ret; | |
706 | if (u8tmp & 0x01) { | |
707 | *status |= FE_HAS_SIGNAL; | |
708 | *status |= FE_HAS_CARRIER; | |
709 | *status |= FE_HAS_VITERBI; | |
710 | *status |= FE_HAS_SYNC; | |
711 | } | |
712 | break; | |
713 | } | |
3e54a169 MS |
714 | |
715 | /* check fec_lock */ | |
1e5fde1b | 716 | ret = si2165_readreg8(state, REG_FEC_LOCK, &u8tmp); |
3e54a169 MS |
717 | if (ret < 0) |
718 | return ret; | |
1e5fde1b | 719 | if (u8tmp & 0x01) { |
3e54a169 MS |
720 | *status |= FE_HAS_SIGNAL; |
721 | *status |= FE_HAS_CARRIER; | |
722 | *status |= FE_HAS_VITERBI; | |
723 | *status |= FE_HAS_SYNC; | |
724 | *status |= FE_HAS_LOCK; | |
725 | } | |
726 | ||
c0675d0b MS |
727 | /* CNR */ |
728 | if (delsys == SYS_DVBC_ANNEX_A && *status & FE_HAS_VITERBI) { | |
729 | ret = si2165_readreg24(state, REG_C_N, &u32tmp); | |
730 | if (ret < 0) | |
731 | return ret; | |
732 | /* | |
733 | * svalue = | |
734 | * 1000 * c_n/dB = | |
735 | * 1000 * 10 * log10(2^24 / regval) = | |
736 | * 1000 * 10 * (log10(2^24) - log10(regval)) = | |
737 | * 1000 * 10 * (intlog10(2^24) - intlog10(regval)) / 2^24 | |
738 | * | |
739 | * intlog10(x) = log10(x) * 2^24 | |
740 | * intlog10(2^24) = log10(2^24) * 2^24 = 121210686 | |
741 | */ | |
742 | u32tmp = (1000 * 10 * (121210686 - (u64)intlog10(u32tmp))) | |
743 | >> 24; | |
744 | c->cnr.stat[0].scale = FE_SCALE_DECIBEL; | |
745 | c->cnr.stat[0].svalue = u32tmp; | |
746 | } else | |
747 | c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
748 | ||
964b3727 MS |
749 | /* BER */ |
750 | if (*status & FE_HAS_VITERBI) { | |
751 | if (c->post_bit_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) { | |
752 | /* start new sampling period to get rid of old data*/ | |
753 | ret = si2165_writereg8(state, REG_BER_RST, 0x01); | |
754 | if (ret < 0) | |
755 | return ret; | |
756 | ||
757 | /* set scale to enter read code on next call */ | |
758 | c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; | |
759 | c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; | |
760 | c->post_bit_error.stat[0].uvalue = 0; | |
761 | c->post_bit_count.stat[0].uvalue = 0; | |
762 | ||
e9c7d19a MS |
763 | /* |
764 | * reset DVBv3 value to deliver a good result | |
765 | * for the first call | |
766 | */ | |
767 | state->ber_prev = 0; | |
768 | ||
964b3727 MS |
769 | } else { |
770 | ret = si2165_readreg8(state, REG_BER_AVAIL, &u8tmp); | |
771 | if (ret < 0) | |
772 | return ret; | |
773 | ||
774 | if (u8tmp & 1) { | |
775 | u32 biterrcnt; | |
776 | ||
777 | ret = si2165_readreg24(state, REG_BER_BIT, | |
778 | &biterrcnt); | |
779 | if (ret < 0) | |
780 | return ret; | |
781 | ||
782 | c->post_bit_error.stat[0].uvalue += | |
783 | biterrcnt; | |
784 | c->post_bit_count.stat[0].uvalue += | |
785 | STATISTICS_PERIOD_BIT_COUNT; | |
786 | ||
787 | /* start new sampling period */ | |
788 | ret = si2165_writereg8(state, | |
789 | REG_BER_RST, 0x01); | |
790 | if (ret < 0) | |
791 | return ret; | |
792 | ||
793 | dev_dbg(&state->client->dev, | |
794 | "post_bit_error=%u post_bit_count=%u\n", | |
795 | biterrcnt, STATISTICS_PERIOD_BIT_COUNT); | |
796 | } | |
797 | } | |
798 | } else { | |
799 | c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
800 | c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
801 | } | |
802 | ||
3e54a169 MS |
803 | return 0; |
804 | } | |
805 | ||
2e687a6d MS |
806 | static int si2165_read_snr(struct dvb_frontend *fe, u16 *snr) |
807 | { | |
808 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; | |
809 | ||
810 | if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL) | |
811 | *snr = div_s64(c->cnr.stat[0].svalue, 100); | |
812 | else | |
813 | *snr = 0; | |
814 | return 0; | |
815 | } | |
816 | ||
e9c7d19a MS |
817 | static int si2165_read_ber(struct dvb_frontend *fe, u32 *ber) |
818 | { | |
819 | struct si2165_state *state = fe->demodulator_priv; | |
820 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; | |
821 | ||
822 | if (c->post_bit_error.stat[0].scale != FE_SCALE_COUNTER) { | |
823 | *ber = 0; | |
824 | return 0; | |
825 | } | |
826 | ||
827 | *ber = c->post_bit_error.stat[0].uvalue - state->ber_prev; | |
828 | state->ber_prev = c->post_bit_error.stat[0].uvalue; | |
829 | ||
830 | return 0; | |
831 | } | |
832 | ||
3e54a169 MS |
833 | static int si2165_set_oversamp(struct si2165_state *state, u32 dvb_rate) |
834 | { | |
835 | u64 oversamp; | |
836 | u32 reg_value; | |
837 | ||
2df9dda0 MS |
838 | if (!dvb_rate) |
839 | return -EINVAL; | |
840 | ||
3e54a169 MS |
841 | oversamp = si2165_get_fe_clk(state); |
842 | oversamp <<= 23; | |
843 | do_div(oversamp, dvb_rate); | |
844 | reg_value = oversamp & 0x3fffffff; | |
845 | ||
1b54da77 | 846 | dev_dbg(&state->client->dev, "Write oversamp=%#x\n", reg_value); |
814f86c9 | 847 | return si2165_writereg32(state, REG_OVERSAMP, reg_value); |
3e54a169 MS |
848 | } |
849 | ||
542fb3c5 | 850 | static int si2165_set_if_freq_shift(struct si2165_state *state) |
3e54a169 | 851 | { |
542fb3c5 | 852 | struct dvb_frontend *fe = &state->fe; |
3e54a169 MS |
853 | u64 if_freq_shift; |
854 | s32 reg_value = 0; | |
855 | u32 fe_clk = si2165_get_fe_clk(state); | |
542fb3c5 | 856 | u32 IF = 0; |
3e54a169 | 857 | |
542fb3c5 | 858 | if (!fe->ops.tuner_ops.get_if_frequency) { |
aa155449 | 859 | dev_err(&state->client->dev, |
77f887cd | 860 | "Error: get_if_frequency() not defined at tuner. Can't work without it!\n"); |
542fb3c5 MS |
861 | return -EINVAL; |
862 | } | |
863 | ||
2df9dda0 MS |
864 | if (!fe_clk) |
865 | return -EINVAL; | |
866 | ||
542fb3c5 | 867 | fe->ops.tuner_ops.get_if_frequency(fe, &IF); |
3e54a169 MS |
868 | if_freq_shift = IF; |
869 | if_freq_shift <<= 29; | |
870 | ||
871 | do_div(if_freq_shift, fe_clk); | |
872 | reg_value = (s32)if_freq_shift; | |
873 | ||
874 | if (state->config.inversion) | |
875 | reg_value = -reg_value; | |
876 | ||
877 | reg_value = reg_value & 0x1fffffff; | |
878 | ||
879 | /* if_freq_shift, usbdump contained 0x023ee08f; */ | |
814f86c9 | 880 | return si2165_writereg32(state, REG_IF_FREQ_SHIFT, reg_value); |
3e54a169 MS |
881 | } |
882 | ||
25e73753 MS |
883 | static const struct si2165_reg_value_pair dvbt_regs[] = { |
884 | /* standard = DVB-T */ | |
814f86c9 | 885 | { REG_DVB_STANDARD, 0x01 }, |
25e73753 | 886 | /* impulsive_noise_remover */ |
814f86c9 MS |
887 | { REG_IMPULSIVE_NOISE_REM, 0x01 }, |
888 | { REG_AUTO_RESET, 0x00 }, | |
25e73753 | 889 | /* agc2 */ |
814f86c9 MS |
890 | { REG_AGC2_MIN, 0x41 }, |
891 | { REG_AGC2_KACQ, 0x0e }, | |
892 | { REG_AGC2_KLOC, 0x10 }, | |
25e73753 | 893 | /* agc */ |
814f86c9 MS |
894 | { REG_AGC_UNFREEZE_THR, 0x03 }, |
895 | { REG_AGC_CRESTF_DBX8, 0x78 }, | |
25e73753 | 896 | /* agc */ |
814f86c9 MS |
897 | { REG_AAF_CRESTF_DBX8, 0x78 }, |
898 | { REG_ACI_CRESTF_DBX8, 0x68 }, | |
25e73753 | 899 | /* freq_sync_range */ |
814f86c9 | 900 | REG16(REG_FREQ_SYNC_RANGE, 0x0064), |
25e73753 | 901 | /* gp_reg0 */ |
814f86c9 | 902 | { REG_GP_REG0_MSB, 0x00 } |
25e73753 MS |
903 | }; |
904 | ||
3b0c9807 | 905 | static int si2165_set_frontend_dvbt(struct dvb_frontend *fe) |
3e54a169 MS |
906 | { |
907 | int ret; | |
908 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; | |
909 | struct si2165_state *state = fe->demodulator_priv; | |
3e54a169 MS |
910 | u32 dvb_rate = 0; |
911 | u16 bw10k; | |
7655a3ae | 912 | u32 bw_hz = p->bandwidth_hz; |
3e54a169 | 913 | |
1b54da77 | 914 | dev_dbg(&state->client->dev, "%s: called\n", __func__); |
3e54a169 | 915 | |
3e54a169 MS |
916 | if (!state->has_dvbt) |
917 | return -EINVAL; | |
918 | ||
7655a3ae MS |
919 | /* no bandwidth auto-detection */ |
920 | if (bw_hz == 0) | |
921 | return -EINVAL; | |
922 | ||
923 | dvb_rate = bw_hz * 8 / 7; | |
924 | bw10k = bw_hz / 10000; | |
3e54a169 | 925 | |
3e54a169 MS |
926 | ret = si2165_adjust_pll_divl(state, 12); |
927 | if (ret < 0) | |
928 | return ret; | |
929 | ||
3e54a169 | 930 | /* bandwidth in 10KHz steps */ |
814f86c9 | 931 | ret = si2165_writereg16(state, REG_T_BANDWIDTH, bw10k); |
3e54a169 MS |
932 | if (ret < 0) |
933 | return ret; | |
934 | ret = si2165_set_oversamp(state, dvb_rate); | |
935 | if (ret < 0) | |
936 | return ret; | |
25e73753 MS |
937 | |
938 | ret = si2165_write_reg_list(state, dvbt_regs, ARRAY_SIZE(dvbt_regs)); | |
3e54a169 MS |
939 | if (ret < 0) |
940 | return ret; | |
25e73753 | 941 | |
3b0c9807 MS |
942 | return 0; |
943 | } | |
944 | ||
94c17334 MS |
945 | static const struct si2165_reg_value_pair dvbc_regs[] = { |
946 | /* standard = DVB-C */ | |
814f86c9 | 947 | { REG_DVB_STANDARD, 0x05 }, |
94c17334 MS |
948 | |
949 | /* agc2 */ | |
814f86c9 MS |
950 | { REG_AGC2_MIN, 0x50 }, |
951 | { REG_AGC2_KACQ, 0x0e }, | |
952 | { REG_AGC2_KLOC, 0x10 }, | |
94c17334 | 953 | /* agc */ |
814f86c9 MS |
954 | { REG_AGC_UNFREEZE_THR, 0x03 }, |
955 | { REG_AGC_CRESTF_DBX8, 0x68 }, | |
94c17334 | 956 | /* agc */ |
814f86c9 MS |
957 | { REG_AAF_CRESTF_DBX8, 0x68 }, |
958 | { REG_ACI_CRESTF_DBX8, 0x50 }, | |
959 | ||
960 | { REG_EQ_AUTO_CONTROL, 0x0d }, | |
961 | ||
962 | { REG_KP_LOCK, 0x05 }, | |
963 | { REG_CENTRAL_TAP, 0x09 }, | |
964 | REG16(REG_UNKNOWN_350, 0x3e80), | |
814f86c9 MS |
965 | |
966 | { REG_AUTO_RESET, 0x01 }, | |
967 | REG16(REG_UNKNOWN_24C, 0x0000), | |
968 | REG16(REG_UNKNOWN_27C, 0x0000), | |
969 | { REG_SWEEP_STEP, 0x03 }, | |
814f86c9 | 970 | { REG_AGC_IF_TRI, 0x00 }, |
94c17334 MS |
971 | }; |
972 | ||
973 | static int si2165_set_frontend_dvbc(struct dvb_frontend *fe) | |
974 | { | |
975 | struct si2165_state *state = fe->demodulator_priv; | |
976 | int ret; | |
977 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; | |
978 | const u32 dvb_rate = p->symbol_rate; | |
548b1f94 | 979 | u8 u8tmp; |
94c17334 MS |
980 | |
981 | if (!state->has_dvbc) | |
982 | return -EINVAL; | |
983 | ||
984 | if (dvb_rate == 0) | |
985 | return -EINVAL; | |
986 | ||
987 | ret = si2165_adjust_pll_divl(state, 14); | |
988 | if (ret < 0) | |
989 | return ret; | |
990 | ||
991 | /* Oversampling */ | |
992 | ret = si2165_set_oversamp(state, dvb_rate); | |
993 | if (ret < 0) | |
994 | return ret; | |
995 | ||
548b1f94 MS |
996 | switch (p->modulation) { |
997 | case QPSK: | |
998 | u8tmp = 0x3; | |
999 | break; | |
1000 | case QAM_16: | |
1001 | u8tmp = 0x7; | |
1002 | break; | |
1003 | case QAM_32: | |
1004 | u8tmp = 0x8; | |
1005 | break; | |
1006 | case QAM_64: | |
1007 | u8tmp = 0x9; | |
1008 | break; | |
1009 | case QAM_128: | |
1010 | u8tmp = 0xa; | |
1011 | break; | |
1012 | case QAM_256: | |
1013 | default: | |
1014 | u8tmp = 0xb; | |
1015 | break; | |
1016 | } | |
1017 | ret = si2165_writereg8(state, REG_REQ_CONSTELLATION, u8tmp); | |
1018 | if (ret < 0) | |
1019 | return ret; | |
1020 | ||
f4d90518 | 1021 | ret = si2165_writereg32(state, REG_LOCK_TIMEOUT, 0x007a1200); |
94c17334 MS |
1022 | if (ret < 0) |
1023 | return ret; | |
1024 | ||
1025 | ret = si2165_write_reg_list(state, dvbc_regs, ARRAY_SIZE(dvbc_regs)); | |
1026 | if (ret < 0) | |
1027 | return ret; | |
1028 | ||
1029 | return 0; | |
1030 | } | |
1031 | ||
814f86c9 MS |
1032 | static const struct si2165_reg_value_pair adc_rewrite[] = { |
1033 | { REG_ADC_RI1, 0x46 }, | |
1034 | { REG_ADC_RI3, 0x00 }, | |
1035 | { REG_ADC_RI5, 0x0a }, | |
1036 | { REG_ADC_RI6, 0xff }, | |
1037 | { REG_ADC_RI8, 0x70 } | |
3b0c9807 MS |
1038 | }; |
1039 | ||
1040 | static int si2165_set_frontend(struct dvb_frontend *fe) | |
1041 | { | |
1042 | struct si2165_state *state = fe->demodulator_priv; | |
1043 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; | |
1044 | u32 delsys = p->delivery_system; | |
1045 | int ret; | |
1046 | u8 val[3]; | |
1047 | ||
1048 | /* initial setting of if freq shift */ | |
1049 | ret = si2165_set_if_freq_shift(state); | |
1050 | if (ret < 0) | |
1051 | return ret; | |
1052 | ||
1053 | switch (delsys) { | |
1054 | case SYS_DVBT: | |
1055 | ret = si2165_set_frontend_dvbt(fe); | |
1056 | if (ret < 0) | |
1057 | return ret; | |
1058 | break; | |
94c17334 MS |
1059 | case SYS_DVBC_ANNEX_A: |
1060 | ret = si2165_set_frontend_dvbc(fe); | |
1061 | if (ret < 0) | |
1062 | return ret; | |
1063 | break; | |
3b0c9807 MS |
1064 | default: |
1065 | return -EINVAL; | |
1066 | } | |
1067 | ||
3e54a169 | 1068 | /* dsp_addr_jump */ |
814f86c9 | 1069 | ret = si2165_writereg32(state, REG_ADDR_JUMP, 0xf4000000); |
3e54a169 MS |
1070 | if (ret < 0) |
1071 | return ret; | |
1072 | ||
1073 | if (fe->ops.tuner_ops.set_params) | |
1074 | fe->ops.tuner_ops.set_params(fe); | |
1075 | ||
1076 | /* recalc if_freq_shift if IF might has changed */ | |
542fb3c5 | 1077 | ret = si2165_set_if_freq_shift(state); |
3e54a169 MS |
1078 | if (ret < 0) |
1079 | return ret; | |
1080 | ||
1081 | /* boot/wdog status */ | |
814f86c9 | 1082 | ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val); |
3e54a169 MS |
1083 | if (ret < 0) |
1084 | return ret; | |
814f86c9 | 1085 | ret = si2165_writereg8(state, REG_WDOG_AND_BOOT, 0x00); |
3e54a169 MS |
1086 | if (ret < 0) |
1087 | return ret; | |
3b0c9807 | 1088 | |
3e54a169 | 1089 | /* reset all */ |
814f86c9 | 1090 | ret = si2165_writereg8(state, REG_RST_ALL, 0x00); |
3e54a169 MS |
1091 | if (ret < 0) |
1092 | return ret; | |
1093 | /* gp_reg0 */ | |
814f86c9 | 1094 | ret = si2165_writereg32(state, REG_GP_REG0_LSB, 0x00000000); |
3e54a169 MS |
1095 | if (ret < 0) |
1096 | return ret; | |
eae56684 MS |
1097 | |
1098 | /* write adc values after each reset*/ | |
814f86c9 MS |
1099 | ret = si2165_write_reg_list(state, adc_rewrite, |
1100 | ARRAY_SIZE(adc_rewrite)); | |
eae56684 MS |
1101 | if (ret < 0) |
1102 | return ret; | |
1103 | ||
3e54a169 | 1104 | /* start_synchro */ |
814f86c9 | 1105 | ret = si2165_writereg8(state, REG_START_SYNCHRO, 0x01); |
3e54a169 MS |
1106 | if (ret < 0) |
1107 | return ret; | |
1108 | /* boot/wdog status */ | |
814f86c9 | 1109 | ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val); |
3e54a169 MS |
1110 | if (ret < 0) |
1111 | return ret; | |
1112 | ||
1113 | return 0; | |
1114 | } | |
1115 | ||
bd336e63 | 1116 | static const struct dvb_frontend_ops si2165_ops = { |
3e54a169 | 1117 | .info = { |
119bd82e | 1118 | .name = "Silicon Labs ", |
94c17334 MS |
1119 | /* For DVB-C */ |
1120 | .symbol_rate_min = 1000000, | |
1121 | .symbol_rate_max = 7200000, | |
1122 | /* For DVB-T */ | |
f1b1eabf | 1123 | .frequency_stepsize_hz = 166667, |
94c17334 | 1124 | .caps = FE_CAN_FEC_1_2 | |
3e54a169 MS |
1125 | FE_CAN_FEC_2_3 | |
1126 | FE_CAN_FEC_3_4 | | |
1127 | FE_CAN_FEC_5_6 | | |
1128 | FE_CAN_FEC_7_8 | | |
1129 | FE_CAN_FEC_AUTO | | |
1130 | FE_CAN_QPSK | | |
1131 | FE_CAN_QAM_16 | | |
1132 | FE_CAN_QAM_32 | | |
1133 | FE_CAN_QAM_64 | | |
1134 | FE_CAN_QAM_128 | | |
1135 | FE_CAN_QAM_256 | | |
3e54a169 MS |
1136 | FE_CAN_GUARD_INTERVAL_AUTO | |
1137 | FE_CAN_HIERARCHY_AUTO | | |
1138 | FE_CAN_MUTE_TS | | |
1139 | FE_CAN_TRANSMISSION_MODE_AUTO | | |
1140 | FE_CAN_RECOVER | |
1141 | }, | |
1142 | ||
1143 | .get_tune_settings = si2165_get_tune_settings, | |
1144 | ||
1145 | .init = si2165_init, | |
1146 | .sleep = si2165_sleep, | |
1147 | ||
c1c49674 | 1148 | .set_frontend = si2165_set_frontend, |
3e54a169 | 1149 | .read_status = si2165_read_status, |
2e687a6d | 1150 | .read_snr = si2165_read_snr, |
e9c7d19a | 1151 | .read_ber = si2165_read_ber, |
3e54a169 MS |
1152 | }; |
1153 | ||
7cd785ad | 1154 | static int si2165_probe(struct i2c_client *client, |
7dbbb4bf | 1155 | const struct i2c_device_id *id) |
7cd785ad MS |
1156 | { |
1157 | struct si2165_state *state = NULL; | |
1158 | struct si2165_platform_data *pdata = client->dev.platform_data; | |
1159 | int n; | |
1160 | int ret = 0; | |
1161 | u8 val; | |
1162 | char rev_char; | |
1163 | const char *chip_name; | |
e3ea5e94 MS |
1164 | static const struct regmap_config regmap_config = { |
1165 | .reg_bits = 16, | |
1166 | .val_bits = 8, | |
1167 | .max_register = 0x08ff, | |
1168 | }; | |
7cd785ad MS |
1169 | |
1170 | /* allocate memory for the internal state */ | |
7dbbb4bf MS |
1171 | state = kzalloc(sizeof(*state), GFP_KERNEL); |
1172 | if (!state) { | |
7cd785ad MS |
1173 | ret = -ENOMEM; |
1174 | goto error; | |
1175 | } | |
1176 | ||
e3ea5e94 MS |
1177 | /* create regmap */ |
1178 | state->regmap = devm_regmap_init_i2c(client, ®map_config); | |
1179 | if (IS_ERR(state->regmap)) { | |
1180 | ret = PTR_ERR(state->regmap); | |
1181 | goto error; | |
1182 | } | |
1183 | ||
7cd785ad MS |
1184 | /* setup the state */ |
1185 | state->client = client; | |
7cd785ad MS |
1186 | state->config.i2c_addr = client->addr; |
1187 | state->config.chip_mode = pdata->chip_mode; | |
7dbbb4bf | 1188 | state->config.ref_freq_hz = pdata->ref_freq_hz; |
7cd785ad MS |
1189 | state->config.inversion = pdata->inversion; |
1190 | ||
7dbbb4bf MS |
1191 | if (state->config.ref_freq_hz < 4000000 || |
1192 | state->config.ref_freq_hz > 27000000) { | |
77f887cd | 1193 | dev_err(&state->client->dev, "ref_freq of %d Hz not supported by this driver\n", |
7dbbb4bf | 1194 | state->config.ref_freq_hz); |
7cd785ad MS |
1195 | ret = -EINVAL; |
1196 | goto error; | |
1197 | } | |
1198 | ||
1199 | /* create dvb_frontend */ | |
1200 | memcpy(&state->fe.ops, &si2165_ops, | |
7dbbb4bf | 1201 | sizeof(struct dvb_frontend_ops)); |
7cd785ad MS |
1202 | state->fe.ops.release = NULL; |
1203 | state->fe.demodulator_priv = state; | |
1204 | i2c_set_clientdata(client, state); | |
1205 | ||
1206 | /* powerup */ | |
814f86c9 | 1207 | ret = si2165_writereg8(state, REG_CHIP_MODE, state->config.chip_mode); |
7cd785ad MS |
1208 | if (ret < 0) |
1209 | goto nodev_error; | |
1210 | ||
814f86c9 | 1211 | ret = si2165_readreg8(state, REG_CHIP_MODE, &val); |
7cd785ad MS |
1212 | if (ret < 0) |
1213 | goto nodev_error; | |
1214 | if (val != state->config.chip_mode) | |
1215 | goto nodev_error; | |
1216 | ||
814f86c9 | 1217 | ret = si2165_readreg8(state, REG_CHIP_REVCODE, &state->chip_revcode); |
7cd785ad MS |
1218 | if (ret < 0) |
1219 | goto nodev_error; | |
1220 | ||
814f86c9 | 1221 | ret = si2165_readreg8(state, REV_CHIP_TYPE, &state->chip_type); |
7cd785ad MS |
1222 | if (ret < 0) |
1223 | goto nodev_error; | |
1224 | ||
1225 | /* powerdown */ | |
814f86c9 | 1226 | ret = si2165_writereg8(state, REG_CHIP_MODE, SI2165_MODE_OFF); |
7cd785ad MS |
1227 | if (ret < 0) |
1228 | goto nodev_error; | |
1229 | ||
1230 | if (state->chip_revcode < 26) | |
1231 | rev_char = 'A' + state->chip_revcode; | |
1232 | else | |
1233 | rev_char = '?'; | |
1234 | ||
1235 | switch (state->chip_type) { | |
1236 | case 0x06: | |
1237 | chip_name = "Si2161"; | |
1238 | state->has_dvbt = true; | |
1239 | break; | |
1240 | case 0x07: | |
1241 | chip_name = "Si2165"; | |
1242 | state->has_dvbt = true; | |
1243 | state->has_dvbc = true; | |
1244 | break; | |
1245 | default: | |
77f887cd MS |
1246 | dev_err(&state->client->dev, "Unsupported Silicon Labs chip (type %d, rev %d)\n", |
1247 | state->chip_type, state->chip_revcode); | |
7cd785ad MS |
1248 | goto nodev_error; |
1249 | } | |
1250 | ||
aa155449 | 1251 | dev_info(&state->client->dev, |
7dbbb4bf | 1252 | "Detected Silicon Labs %s-%c (type %d, rev %d)\n", |
77f887cd | 1253 | chip_name, rev_char, state->chip_type, |
7cd785ad MS |
1254 | state->chip_revcode); |
1255 | ||
1256 | strlcat(state->fe.ops.info.name, chip_name, | |
7dbbb4bf | 1257 | sizeof(state->fe.ops.info.name)); |
7cd785ad MS |
1258 | |
1259 | n = 0; | |
1260 | if (state->has_dvbt) { | |
1261 | state->fe.ops.delsys[n++] = SYS_DVBT; | |
1262 | strlcat(state->fe.ops.info.name, " DVB-T", | |
1263 | sizeof(state->fe.ops.info.name)); | |
1264 | } | |
1265 | if (state->has_dvbc) { | |
1266 | state->fe.ops.delsys[n++] = SYS_DVBC_ANNEX_A; | |
1267 | strlcat(state->fe.ops.info.name, " DVB-C", | |
1268 | sizeof(state->fe.ops.info.name)); | |
1269 | } | |
1270 | ||
1271 | /* return fe pointer */ | |
1272 | *pdata->fe = &state->fe; | |
1273 | ||
1274 | return 0; | |
1275 | ||
1276 | nodev_error: | |
1277 | ret = -ENODEV; | |
1278 | error: | |
1279 | kfree(state); | |
1280 | dev_dbg(&client->dev, "failed=%d\n", ret); | |
1281 | return ret; | |
1282 | } | |
1283 | ||
1284 | static int si2165_remove(struct i2c_client *client) | |
1285 | { | |
1286 | struct si2165_state *state = i2c_get_clientdata(client); | |
1287 | ||
1288 | dev_dbg(&client->dev, "\n"); | |
1289 | ||
1290 | kfree(state); | |
1291 | return 0; | |
1292 | } | |
1293 | ||
1294 | static const struct i2c_device_id si2165_id_table[] = { | |
1295 | {"si2165", 0}, | |
1296 | {} | |
1297 | }; | |
1298 | MODULE_DEVICE_TABLE(i2c, si2165_id_table); | |
1299 | ||
1300 | static struct i2c_driver si2165_driver = { | |
1301 | .driver = { | |
1302 | .owner = THIS_MODULE, | |
1303 | .name = "si2165", | |
1304 | }, | |
1305 | .probe = si2165_probe, | |
1306 | .remove = si2165_remove, | |
1307 | .id_table = si2165_id_table, | |
1308 | }; | |
1309 | ||
1310 | module_i2c_driver(si2165_driver); | |
1311 | ||
3e54a169 MS |
1312 | MODULE_DESCRIPTION("Silicon Labs Si2165 DVB-C/-T Demodulator driver"); |
1313 | MODULE_AUTHOR("Matthias Schwarzott <zzam@gentoo.org>"); | |
1314 | MODULE_LICENSE("GPL"); | |
55bea400 | 1315 | MODULE_FIRMWARE(SI2165_FIRMWARE_REV_D); |