Commit | Line | Data |
---|---|---|
3e54a169 | 1 | /* |
18349f40 MS |
2 | * Driver for Silicon Labs Si2161 DVB-T and Si2165 DVB-C/-T Demodulator |
3 | * | |
77f887cd | 4 | * Copyright (C) 2013-2017 Matthias Schwarzott <zzam@gentoo.org> |
18349f40 MS |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * References: | |
17 | * http://www.silabs.com/Support%20Documents/TechnicalDocs/Si2165-short.pdf | |
18 | */ | |
3e54a169 MS |
19 | |
20 | #include <linux/delay.h> | |
21 | #include <linux/errno.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/string.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/firmware.h> | |
e3ea5e94 | 28 | #include <linux/regmap.h> |
3e54a169 MS |
29 | |
30 | #include "dvb_frontend.h" | |
31 | #include "dvb_math.h" | |
32 | #include "si2165_priv.h" | |
33 | #include "si2165.h" | |
34 | ||
18349f40 MS |
35 | /* |
36 | * Hauppauge WinTV-HVR-930C-HD B130 / PCTV QuatroStick 521e 1113xx | |
37 | * uses 16 MHz xtal | |
38 | * | |
39 | * Hauppauge WinTV-HVR-930C-HD B131 / PCTV QuatroStick 522e 1114xx | |
40 | * uses 24 MHz clock provided by tuner | |
41 | */ | |
3e54a169 MS |
42 | |
43 | struct si2165_state { | |
7cd785ad MS |
44 | struct i2c_client *client; |
45 | ||
e3ea5e94 | 46 | struct regmap *regmap; |
3e54a169 | 47 | |
d9a201df | 48 | struct dvb_frontend fe; |
3e54a169 MS |
49 | |
50 | struct si2165_config config; | |
51 | ||
55bea400 | 52 | u8 chip_revcode; |
3e54a169 MS |
53 | u8 chip_type; |
54 | ||
55 | /* calculated by xtal and div settings */ | |
56 | u32 fvco_hz; | |
57 | u32 sys_clk; | |
58 | u32 adc_clk; | |
59 | ||
60 | bool has_dvbc; | |
61 | bool has_dvbt; | |
62 | bool firmware_loaded; | |
63 | }; | |
64 | ||
3e54a169 MS |
65 | static int si2165_write(struct si2165_state *state, const u16 reg, |
66 | const u8 *src, const int count) | |
67 | { | |
68 | int ret; | |
3e54a169 | 69 | |
1b54da77 | 70 | dev_dbg(&state->client->dev, "i2c write: reg: 0x%04x, data: %*ph\n", reg, count, src); |
3e54a169 | 71 | |
e3ea5e94 | 72 | ret = regmap_bulk_write(state->regmap, reg, src, count); |
3e54a169 | 73 | |
e3ea5e94 | 74 | if (ret) |
aa155449 | 75 | dev_err(&state->client->dev, "%s: ret == %d\n", __func__, ret); |
3e54a169 | 76 | |
e3ea5e94 | 77 | return ret; |
3e54a169 MS |
78 | } |
79 | ||
80 | static int si2165_read(struct si2165_state *state, | |
81 | const u16 reg, u8 *val, const int count) | |
82 | { | |
e3ea5e94 | 83 | int ret = regmap_bulk_read(state->regmap, reg, val, count); |
3e54a169 | 84 | |
e3ea5e94 | 85 | if (ret) { |
aa155449 | 86 | dev_err(&state->client->dev, "%s: error (addr %02x reg %04x error (ret == %i)\n", |
3e54a169 | 87 | __func__, state->config.i2c_addr, reg, ret); |
e3ea5e94 | 88 | return ret; |
3e54a169 MS |
89 | } |
90 | ||
1b54da77 | 91 | dev_dbg(&state->client->dev, "i2c read: reg: 0x%04x, data: %*ph\n", reg, count, val); |
3e54a169 MS |
92 | |
93 | return 0; | |
94 | } | |
95 | ||
96 | static int si2165_readreg8(struct si2165_state *state, | |
97 | const u16 reg, u8 *val) | |
98 | { | |
e3ea5e94 MS |
99 | unsigned int val_tmp; |
100 | int ret = regmap_read(state->regmap, reg, &val_tmp); | |
101 | *val = (u8)val_tmp; | |
1b54da77 | 102 | dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%02x\n", reg, *val); |
3e54a169 MS |
103 | return ret; |
104 | } | |
105 | ||
106 | static int si2165_readreg16(struct si2165_state *state, | |
107 | const u16 reg, u16 *val) | |
108 | { | |
109 | u8 buf[2]; | |
110 | ||
111 | int ret = si2165_read(state, reg, buf, 2); | |
112 | *val = buf[0] | buf[1] << 8; | |
1b54da77 | 113 | dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%04x\n", reg, *val); |
3e54a169 MS |
114 | return ret; |
115 | } | |
116 | ||
117 | static int si2165_writereg8(struct si2165_state *state, const u16 reg, u8 val) | |
118 | { | |
e3ea5e94 | 119 | return regmap_write(state->regmap, reg, val); |
3e54a169 MS |
120 | } |
121 | ||
122 | static int si2165_writereg16(struct si2165_state *state, const u16 reg, u16 val) | |
123 | { | |
124 | u8 buf[2] = { val & 0xff, (val >> 8) & 0xff }; | |
125 | ||
126 | return si2165_write(state, reg, buf, 2); | |
127 | } | |
128 | ||
129 | static int si2165_writereg24(struct si2165_state *state, const u16 reg, u32 val) | |
130 | { | |
131 | u8 buf[3] = { val & 0xff, (val >> 8) & 0xff, (val >> 16) & 0xff }; | |
132 | ||
133 | return si2165_write(state, reg, buf, 3); | |
134 | } | |
135 | ||
136 | static int si2165_writereg32(struct si2165_state *state, const u16 reg, u32 val) | |
137 | { | |
138 | u8 buf[4] = { | |
139 | val & 0xff, | |
140 | (val >> 8) & 0xff, | |
141 | (val >> 16) & 0xff, | |
142 | (val >> 24) & 0xff | |
143 | }; | |
144 | return si2165_write(state, reg, buf, 4); | |
145 | } | |
146 | ||
147 | static int si2165_writereg_mask8(struct si2165_state *state, const u16 reg, | |
148 | u8 val, u8 mask) | |
149 | { | |
3e54a169 | 150 | if (mask != 0xff) { |
c2e5c951 ME |
151 | u8 tmp; |
152 | int ret = si2165_readreg8(state, reg, &tmp); | |
153 | ||
3e54a169 | 154 | if (ret < 0) |
c2e5c951 | 155 | return ret; |
3e54a169 MS |
156 | |
157 | val &= mask; | |
158 | tmp &= ~mask; | |
159 | val |= tmp; | |
160 | } | |
c2e5c951 | 161 | return si2165_writereg8(state, reg, val); |
3e54a169 MS |
162 | } |
163 | ||
a5293dbd MS |
164 | #define REG16(reg, val) { (reg), (val) & 0xff }, { (reg)+1, (val)>>8 & 0xff } |
165 | struct si2165_reg_value_pair { | |
166 | u16 reg; | |
167 | u8 val; | |
168 | }; | |
169 | ||
170 | static int si2165_write_reg_list(struct si2165_state *state, | |
171 | const struct si2165_reg_value_pair *regs, | |
172 | int count) | |
173 | { | |
174 | int i; | |
175 | int ret; | |
176 | ||
177 | for (i = 0; i < count; i++) { | |
178 | ret = si2165_writereg8(state, regs[i].reg, regs[i].val); | |
179 | if (ret < 0) | |
180 | return ret; | |
181 | } | |
182 | return 0; | |
183 | } | |
184 | ||
3e54a169 MS |
185 | static int si2165_get_tune_settings(struct dvb_frontend *fe, |
186 | struct dvb_frontend_tune_settings *s) | |
187 | { | |
188 | s->min_delay_ms = 1000; | |
189 | return 0; | |
190 | } | |
191 | ||
192 | static int si2165_init_pll(struct si2165_state *state) | |
193 | { | |
194 | u32 ref_freq_Hz = state->config.ref_freq_Hz; | |
195 | u8 divr = 1; /* 1..7 */ | |
196 | u8 divp = 1; /* only 1 or 4 */ | |
197 | u8 divn = 56; /* 1..63 */ | |
198 | u8 divm = 8; | |
199 | u8 divl = 12; | |
200 | u8 buf[4]; | |
201 | ||
18349f40 MS |
202 | /* |
203 | * hardcoded values can be deleted if calculation is verified | |
204 | * or it yields the same values as the windows driver | |
205 | */ | |
3e54a169 MS |
206 | switch (ref_freq_Hz) { |
207 | case 16000000u: | |
208 | divn = 56; | |
209 | break; | |
210 | case 24000000u: | |
211 | divr = 2; | |
212 | divp = 4; | |
213 | divn = 19; | |
214 | break; | |
215 | default: | |
216 | /* ref_freq / divr must be between 4 and 16 MHz */ | |
217 | if (ref_freq_Hz > 16000000u) | |
218 | divr = 2; | |
219 | ||
18349f40 MS |
220 | /* |
221 | * now select divn and divp such that | |
222 | * fvco is in 1624..1824 MHz | |
223 | */ | |
3e54a169 MS |
224 | if (1624000000u * divr > ref_freq_Hz * 2u * 63u) |
225 | divp = 4; | |
226 | ||
227 | /* is this already correct regarding rounding? */ | |
228 | divn = 1624000000u * divr / (ref_freq_Hz * 2u * divp); | |
229 | break; | |
230 | } | |
231 | ||
232 | /* adc_clk and sys_clk depend on xtal and pll settings */ | |
233 | state->fvco_hz = ref_freq_Hz / divr | |
234 | * 2u * divn * divp; | |
235 | state->adc_clk = state->fvco_hz / (divm * 4u); | |
236 | state->sys_clk = state->fvco_hz / (divl * 2u); | |
237 | ||
238 | /* write pll registers 0x00a0..0x00a3 at once */ | |
239 | buf[0] = divl; | |
240 | buf[1] = divm; | |
241 | buf[2] = (divn & 0x3f) | ((divp == 1) ? 0x40 : 0x00) | 0x80; | |
242 | buf[3] = divr; | |
243 | return si2165_write(state, 0x00a0, buf, 4); | |
244 | } | |
245 | ||
246 | static int si2165_adjust_pll_divl(struct si2165_state *state, u8 divl) | |
247 | { | |
248 | state->sys_clk = state->fvco_hz / (divl * 2u); | |
249 | return si2165_writereg8(state, 0x00a0, divl); /* pll_divl */ | |
250 | } | |
251 | ||
252 | static u32 si2165_get_fe_clk(struct si2165_state *state) | |
253 | { | |
254 | /* assume Oversampling mode Ovr4 is used */ | |
255 | return state->adc_clk; | |
256 | } | |
257 | ||
e73c7bfe | 258 | static int si2165_wait_init_done(struct si2165_state *state) |
3e54a169 MS |
259 | { |
260 | int ret = -EINVAL; | |
261 | u8 val = 0; | |
262 | int i; | |
263 | ||
264 | for (i = 0; i < 3; ++i) { | |
265 | si2165_readreg8(state, 0x0054, &val); | |
266 | if (val == 0x01) | |
267 | return 0; | |
268 | usleep_range(1000, 50000); | |
269 | } | |
77f887cd | 270 | dev_err(&state->client->dev, "init_done was not set\n"); |
3e54a169 MS |
271 | return ret; |
272 | } | |
273 | ||
274 | static int si2165_upload_firmware_block(struct si2165_state *state, | |
275 | const u8 *data, u32 len, u32 *poffset, u32 block_count) | |
276 | { | |
277 | int ret; | |
278 | u8 buf_ctrl[4] = { 0x00, 0x00, 0x00, 0xc0 }; | |
279 | u8 wordcount; | |
280 | u32 cur_block = 0; | |
281 | u32 offset = poffset ? *poffset : 0; | |
282 | ||
283 | if (len < 4) | |
284 | return -EINVAL; | |
285 | if (len % 4 != 0) | |
286 | return -EINVAL; | |
287 | ||
1b54da77 MS |
288 | dev_dbg(&state->client->dev, |
289 | "fw load: si2165_upload_firmware_block called with len=0x%x offset=0x%x blockcount=0x%x\n", | |
3e54a169 MS |
290 | len, offset, block_count); |
291 | while (offset+12 <= len && cur_block < block_count) { | |
1b54da77 MS |
292 | dev_dbg(&state->client->dev, |
293 | "fw load: si2165_upload_firmware_block in while len=0x%x offset=0x%x cur_block=0x%x blockcount=0x%x\n", | |
3e54a169 MS |
294 | len, offset, cur_block, block_count); |
295 | wordcount = data[offset]; | |
296 | if (wordcount < 1 || data[offset+1] || | |
297 | data[offset+2] || data[offset+3]) { | |
aa155449 | 298 | dev_warn(&state->client->dev, |
77f887cd MS |
299 | "bad fw data[0..3] = %*ph\n", |
300 | 4, data); | |
3e54a169 MS |
301 | return -EINVAL; |
302 | } | |
303 | ||
304 | if (offset + 8 + wordcount * 4 > len) { | |
aa155449 | 305 | dev_warn(&state->client->dev, |
77f887cd MS |
306 | "len is too small for block len=%d, wordcount=%d\n", |
307 | len, wordcount); | |
3e54a169 MS |
308 | return -EINVAL; |
309 | } | |
310 | ||
311 | buf_ctrl[0] = wordcount - 1; | |
312 | ||
313 | ret = si2165_write(state, 0x0364, buf_ctrl, 4); | |
314 | if (ret < 0) | |
315 | goto error; | |
316 | ret = si2165_write(state, 0x0368, data+offset+4, 4); | |
317 | if (ret < 0) | |
318 | goto error; | |
319 | ||
320 | offset += 8; | |
321 | ||
322 | while (wordcount > 0) { | |
323 | ret = si2165_write(state, 0x36c, data+offset, 4); | |
324 | if (ret < 0) | |
325 | goto error; | |
326 | wordcount--; | |
327 | offset += 4; | |
328 | } | |
329 | cur_block++; | |
330 | } | |
331 | ||
1b54da77 MS |
332 | dev_dbg(&state->client->dev, |
333 | "fw load: si2165_upload_firmware_block after while len=0x%x offset=0x%x cur_block=0x%x blockcount=0x%x\n", | |
3e54a169 MS |
334 | len, offset, cur_block, block_count); |
335 | ||
336 | if (poffset) | |
337 | *poffset = offset; | |
338 | ||
1b54da77 MS |
339 | dev_dbg(&state->client->dev, |
340 | "fw load: si2165_upload_firmware_block returned offset=0x%x\n", | |
3e54a169 MS |
341 | offset); |
342 | ||
343 | return 0; | |
344 | error: | |
345 | return ret; | |
346 | } | |
347 | ||
348 | static int si2165_upload_firmware(struct si2165_state *state) | |
349 | { | |
350 | /* int ret; */ | |
351 | u8 val[3]; | |
352 | u16 val16; | |
353 | int ret; | |
354 | ||
355 | const struct firmware *fw = NULL; | |
55bea400 | 356 | u8 *fw_file; |
3e54a169 MS |
357 | const u8 *data; |
358 | u32 len; | |
359 | u32 offset; | |
360 | u8 patch_version; | |
361 | u8 block_count; | |
362 | u16 crc_expected; | |
363 | ||
55bea400 MS |
364 | switch (state->chip_revcode) { |
365 | case 0x03: /* revision D */ | |
366 | fw_file = SI2165_FIRMWARE_REV_D; | |
367 | break; | |
368 | default: | |
77f887cd MS |
369 | dev_info(&state->client->dev, "no firmware file for revision=%d\n", |
370 | state->chip_revcode); | |
55bea400 MS |
371 | return 0; |
372 | } | |
373 | ||
3e54a169 | 374 | /* request the firmware, this will block and timeout */ |
aa155449 | 375 | ret = request_firmware(&fw, fw_file, &state->client->dev); |
3e54a169 | 376 | if (ret) { |
77f887cd MS |
377 | dev_warn(&state->client->dev, "firmware file '%s' not found\n", |
378 | fw_file); | |
3e54a169 MS |
379 | goto error; |
380 | } | |
381 | ||
382 | data = fw->data; | |
383 | len = fw->size; | |
384 | ||
77f887cd MS |
385 | dev_info(&state->client->dev, "downloading firmware from file '%s' size=%d\n", |
386 | fw_file, len); | |
3e54a169 MS |
387 | |
388 | if (len % 4 != 0) { | |
77f887cd | 389 | dev_warn(&state->client->dev, "firmware size is not multiple of 4\n"); |
3e54a169 MS |
390 | ret = -EINVAL; |
391 | goto error; | |
392 | } | |
393 | ||
394 | /* check header (8 bytes) */ | |
395 | if (len < 8) { | |
77f887cd | 396 | dev_warn(&state->client->dev, "firmware header is missing\n"); |
3e54a169 MS |
397 | ret = -EINVAL; |
398 | goto error; | |
399 | } | |
400 | ||
401 | if (data[0] != 1 || data[1] != 0) { | |
77f887cd | 402 | dev_warn(&state->client->dev, "firmware file version is wrong\n"); |
3e54a169 MS |
403 | ret = -EINVAL; |
404 | goto error; | |
405 | } | |
406 | ||
407 | patch_version = data[2]; | |
408 | block_count = data[4]; | |
409 | crc_expected = data[7] << 8 | data[6]; | |
410 | ||
411 | /* start uploading fw */ | |
412 | /* boot/wdog status */ | |
413 | ret = si2165_writereg8(state, 0x0341, 0x00); | |
414 | if (ret < 0) | |
415 | goto error; | |
416 | /* reset */ | |
417 | ret = si2165_writereg8(state, 0x00c0, 0x00); | |
418 | if (ret < 0) | |
419 | goto error; | |
420 | /* boot/wdog status */ | |
421 | ret = si2165_readreg8(state, 0x0341, val); | |
422 | if (ret < 0) | |
423 | goto error; | |
424 | ||
425 | /* enable reset on error */ | |
426 | ret = si2165_readreg8(state, 0x035c, val); | |
427 | if (ret < 0) | |
428 | goto error; | |
429 | ret = si2165_readreg8(state, 0x035c, val); | |
430 | if (ret < 0) | |
431 | goto error; | |
432 | ret = si2165_writereg8(state, 0x035c, 0x02); | |
433 | if (ret < 0) | |
434 | goto error; | |
435 | ||
436 | /* start right after the header */ | |
437 | offset = 8; | |
438 | ||
77f887cd MS |
439 | dev_info(&state->client->dev, "si2165_upload_firmware extracted patch_version=0x%02x, block_count=0x%02x, crc_expected=0x%04x\n", |
440 | patch_version, block_count, crc_expected); | |
3e54a169 MS |
441 | |
442 | ret = si2165_upload_firmware_block(state, data, len, &offset, 1); | |
443 | if (ret < 0) | |
444 | goto error; | |
445 | ||
446 | ret = si2165_writereg8(state, 0x0344, patch_version); | |
447 | if (ret < 0) | |
448 | goto error; | |
449 | ||
450 | /* reset crc */ | |
451 | ret = si2165_writereg8(state, 0x0379, 0x01); | |
452 | if (ret) | |
ec73b9fd | 453 | goto error; |
3e54a169 MS |
454 | |
455 | ret = si2165_upload_firmware_block(state, data, len, | |
456 | &offset, block_count); | |
457 | if (ret < 0) { | |
aa155449 | 458 | dev_err(&state->client->dev, |
77f887cd | 459 | "firmware could not be uploaded\n"); |
3e54a169 MS |
460 | goto error; |
461 | } | |
462 | ||
463 | /* read crc */ | |
464 | ret = si2165_readreg16(state, 0x037a, &val16); | |
465 | if (ret) | |
466 | goto error; | |
467 | ||
468 | if (val16 != crc_expected) { | |
aa155449 | 469 | dev_err(&state->client->dev, |
77f887cd MS |
470 | "firmware crc mismatch %04x != %04x\n", |
471 | val16, crc_expected); | |
3e54a169 MS |
472 | ret = -EINVAL; |
473 | goto error; | |
474 | } | |
475 | ||
476 | ret = si2165_upload_firmware_block(state, data, len, &offset, 5); | |
477 | if (ret) | |
478 | goto error; | |
479 | ||
480 | if (len != offset) { | |
aa155449 | 481 | dev_err(&state->client->dev, |
77f887cd MS |
482 | "firmware len mismatch %04x != %04x\n", |
483 | len, offset); | |
3e54a169 MS |
484 | ret = -EINVAL; |
485 | goto error; | |
486 | } | |
487 | ||
488 | /* reset watchdog error register */ | |
489 | ret = si2165_writereg_mask8(state, 0x0341, 0x02, 0x02); | |
490 | if (ret < 0) | |
491 | goto error; | |
492 | ||
493 | /* enable reset on error */ | |
494 | ret = si2165_writereg_mask8(state, 0x035c, 0x01, 0x01); | |
495 | if (ret < 0) | |
496 | goto error; | |
497 | ||
77f887cd | 498 | dev_info(&state->client->dev, "fw load finished\n"); |
3e54a169 MS |
499 | |
500 | ret = 0; | |
501 | state->firmware_loaded = true; | |
502 | error: | |
503 | if (fw) { | |
504 | release_firmware(fw); | |
505 | fw = NULL; | |
506 | } | |
507 | ||
508 | return ret; | |
509 | } | |
510 | ||
511 | static int si2165_init(struct dvb_frontend *fe) | |
512 | { | |
513 | int ret = 0; | |
514 | struct si2165_state *state = fe->demodulator_priv; | |
515 | u8 val; | |
516 | u8 patch_version = 0x00; | |
517 | ||
1b54da77 | 518 | dev_dbg(&state->client->dev, "%s: called\n", __func__); |
3e54a169 MS |
519 | |
520 | /* powerup */ | |
521 | ret = si2165_writereg8(state, 0x0000, state->config.chip_mode); | |
522 | if (ret < 0) | |
523 | goto error; | |
524 | /* dsp_clock_enable */ | |
525 | ret = si2165_writereg8(state, 0x0104, 0x01); | |
526 | if (ret < 0) | |
527 | goto error; | |
528 | ret = si2165_readreg8(state, 0x0000, &val); /* verify chip_mode */ | |
529 | if (ret < 0) | |
530 | goto error; | |
531 | if (val != state->config.chip_mode) { | |
77f887cd | 532 | dev_err(&state->client->dev, "could not set chip_mode\n"); |
3e54a169 MS |
533 | return -EINVAL; |
534 | } | |
535 | ||
536 | /* agc */ | |
537 | ret = si2165_writereg8(state, 0x018b, 0x00); | |
538 | if (ret < 0) | |
539 | goto error; | |
540 | ret = si2165_writereg8(state, 0x0190, 0x01); | |
541 | if (ret < 0) | |
542 | goto error; | |
543 | ret = si2165_writereg8(state, 0x0170, 0x00); | |
544 | if (ret < 0) | |
545 | goto error; | |
546 | ret = si2165_writereg8(state, 0x0171, 0x07); | |
547 | if (ret < 0) | |
548 | goto error; | |
549 | /* rssi pad */ | |
550 | ret = si2165_writereg8(state, 0x0646, 0x00); | |
551 | if (ret < 0) | |
552 | goto error; | |
553 | ret = si2165_writereg8(state, 0x0641, 0x00); | |
554 | if (ret < 0) | |
555 | goto error; | |
556 | ||
557 | ret = si2165_init_pll(state); | |
558 | if (ret < 0) | |
559 | goto error; | |
560 | ||
561 | /* enable chip_init */ | |
562 | ret = si2165_writereg8(state, 0x0050, 0x01); | |
563 | if (ret < 0) | |
564 | goto error; | |
565 | /* set start_init */ | |
566 | ret = si2165_writereg8(state, 0x0096, 0x01); | |
567 | if (ret < 0) | |
568 | goto error; | |
569 | ret = si2165_wait_init_done(state); | |
570 | if (ret < 0) | |
571 | goto error; | |
572 | ||
573 | /* disable chip_init */ | |
574 | ret = si2165_writereg8(state, 0x0050, 0x00); | |
575 | if (ret < 0) | |
576 | goto error; | |
577 | ||
578 | /* ber_pkt */ | |
18349f40 | 579 | ret = si2165_writereg16(state, 0x0470, 0x7530); |
3e54a169 MS |
580 | if (ret < 0) |
581 | goto error; | |
582 | ||
583 | ret = si2165_readreg8(state, 0x0344, &patch_version); | |
584 | if (ret < 0) | |
585 | goto error; | |
586 | ||
587 | ret = si2165_writereg8(state, 0x00cb, 0x00); | |
588 | if (ret < 0) | |
589 | goto error; | |
590 | ||
591 | /* dsp_addr_jump */ | |
592 | ret = si2165_writereg32(state, 0x0348, 0xf4000000); | |
593 | if (ret < 0) | |
594 | goto error; | |
595 | /* boot/wdog status */ | |
596 | ret = si2165_readreg8(state, 0x0341, &val); | |
597 | if (ret < 0) | |
598 | goto error; | |
599 | ||
600 | if (patch_version == 0x00) { | |
601 | ret = si2165_upload_firmware(state); | |
602 | if (ret < 0) | |
603 | goto error; | |
604 | } | |
605 | ||
75d62fc0 MS |
606 | /* ts output config */ |
607 | ret = si2165_writereg8(state, 0x04e4, 0x20); | |
608 | if (ret < 0) | |
609 | return ret; | |
610 | ret = si2165_writereg16(state, 0x04ef, 0x00fe); | |
611 | if (ret < 0) | |
612 | return ret; | |
613 | ret = si2165_writereg24(state, 0x04f4, 0x555555); | |
614 | if (ret < 0) | |
615 | return ret; | |
616 | ret = si2165_writereg8(state, 0x04e5, 0x01); | |
617 | if (ret < 0) | |
618 | return ret; | |
619 | ||
3e54a169 MS |
620 | return 0; |
621 | error: | |
622 | return ret; | |
623 | } | |
624 | ||
625 | static int si2165_sleep(struct dvb_frontend *fe) | |
626 | { | |
627 | int ret; | |
628 | struct si2165_state *state = fe->demodulator_priv; | |
629 | ||
630 | /* dsp clock disable */ | |
631 | ret = si2165_writereg8(state, 0x0104, 0x00); | |
632 | if (ret < 0) | |
633 | return ret; | |
634 | /* chip mode */ | |
635 | ret = si2165_writereg8(state, 0x0000, SI2165_MODE_OFF); | |
636 | if (ret < 0) | |
637 | return ret; | |
638 | return 0; | |
639 | } | |
640 | ||
0df289a2 | 641 | static int si2165_read_status(struct dvb_frontend *fe, enum fe_status *status) |
3e54a169 MS |
642 | { |
643 | int ret; | |
644 | u8 fec_lock = 0; | |
645 | struct si2165_state *state = fe->demodulator_priv; | |
646 | ||
647 | if (!state->has_dvbt) | |
648 | return -EINVAL; | |
649 | ||
650 | /* check fec_lock */ | |
651 | ret = si2165_readreg8(state, 0x4e0, &fec_lock); | |
652 | if (ret < 0) | |
653 | return ret; | |
654 | *status = 0; | |
655 | if (fec_lock & 0x01) { | |
656 | *status |= FE_HAS_SIGNAL; | |
657 | *status |= FE_HAS_CARRIER; | |
658 | *status |= FE_HAS_VITERBI; | |
659 | *status |= FE_HAS_SYNC; | |
660 | *status |= FE_HAS_LOCK; | |
661 | } | |
662 | ||
663 | return 0; | |
664 | } | |
665 | ||
666 | static int si2165_set_oversamp(struct si2165_state *state, u32 dvb_rate) | |
667 | { | |
668 | u64 oversamp; | |
669 | u32 reg_value; | |
670 | ||
2df9dda0 MS |
671 | if (!dvb_rate) |
672 | return -EINVAL; | |
673 | ||
3e54a169 MS |
674 | oversamp = si2165_get_fe_clk(state); |
675 | oversamp <<= 23; | |
676 | do_div(oversamp, dvb_rate); | |
677 | reg_value = oversamp & 0x3fffffff; | |
678 | ||
1b54da77 | 679 | dev_dbg(&state->client->dev, "Write oversamp=%#x\n", reg_value); |
3e54a169 MS |
680 | return si2165_writereg32(state, 0x00e4, reg_value); |
681 | } | |
682 | ||
542fb3c5 | 683 | static int si2165_set_if_freq_shift(struct si2165_state *state) |
3e54a169 | 684 | { |
542fb3c5 | 685 | struct dvb_frontend *fe = &state->fe; |
3e54a169 MS |
686 | u64 if_freq_shift; |
687 | s32 reg_value = 0; | |
688 | u32 fe_clk = si2165_get_fe_clk(state); | |
542fb3c5 | 689 | u32 IF = 0; |
3e54a169 | 690 | |
542fb3c5 | 691 | if (!fe->ops.tuner_ops.get_if_frequency) { |
aa155449 | 692 | dev_err(&state->client->dev, |
77f887cd | 693 | "Error: get_if_frequency() not defined at tuner. Can't work without it!\n"); |
542fb3c5 MS |
694 | return -EINVAL; |
695 | } | |
696 | ||
2df9dda0 MS |
697 | if (!fe_clk) |
698 | return -EINVAL; | |
699 | ||
542fb3c5 | 700 | fe->ops.tuner_ops.get_if_frequency(fe, &IF); |
3e54a169 MS |
701 | if_freq_shift = IF; |
702 | if_freq_shift <<= 29; | |
703 | ||
704 | do_div(if_freq_shift, fe_clk); | |
705 | reg_value = (s32)if_freq_shift; | |
706 | ||
707 | if (state->config.inversion) | |
708 | reg_value = -reg_value; | |
709 | ||
710 | reg_value = reg_value & 0x1fffffff; | |
711 | ||
712 | /* if_freq_shift, usbdump contained 0x023ee08f; */ | |
713 | return si2165_writereg32(state, 0x00e8, reg_value); | |
714 | } | |
715 | ||
25e73753 MS |
716 | static const struct si2165_reg_value_pair dvbt_regs[] = { |
717 | /* standard = DVB-T */ | |
718 | { 0x00ec, 0x01 }, | |
719 | { 0x08f8, 0x00 }, | |
720 | /* impulsive_noise_remover */ | |
721 | { 0x031c, 0x01 }, | |
722 | { 0x00cb, 0x00 }, | |
723 | /* agc2 */ | |
724 | { 0x016e, 0x41 }, | |
725 | { 0x016c, 0x0e }, | |
726 | { 0x016d, 0x10 }, | |
727 | /* agc */ | |
728 | { 0x015b, 0x03 }, | |
729 | { 0x0150, 0x78 }, | |
730 | /* agc */ | |
731 | { 0x01a0, 0x78 }, | |
732 | { 0x01c8, 0x68 }, | |
733 | /* freq_sync_range */ | |
734 | REG16(0x030c, 0x0064), | |
735 | /* gp_reg0 */ | |
736 | { 0x0387, 0x00 } | |
737 | }; | |
738 | ||
3b0c9807 | 739 | static int si2165_set_frontend_dvbt(struct dvb_frontend *fe) |
3e54a169 MS |
740 | { |
741 | int ret; | |
742 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; | |
743 | struct si2165_state *state = fe->demodulator_priv; | |
3e54a169 MS |
744 | u32 dvb_rate = 0; |
745 | u16 bw10k; | |
7655a3ae | 746 | u32 bw_hz = p->bandwidth_hz; |
3e54a169 | 747 | |
1b54da77 | 748 | dev_dbg(&state->client->dev, "%s: called\n", __func__); |
3e54a169 | 749 | |
3e54a169 MS |
750 | if (!state->has_dvbt) |
751 | return -EINVAL; | |
752 | ||
7655a3ae MS |
753 | /* no bandwidth auto-detection */ |
754 | if (bw_hz == 0) | |
755 | return -EINVAL; | |
756 | ||
757 | dvb_rate = bw_hz * 8 / 7; | |
758 | bw10k = bw_hz / 10000; | |
3e54a169 | 759 | |
3e54a169 MS |
760 | ret = si2165_adjust_pll_divl(state, 12); |
761 | if (ret < 0) | |
762 | return ret; | |
763 | ||
3e54a169 MS |
764 | /* bandwidth in 10KHz steps */ |
765 | ret = si2165_writereg16(state, 0x0308, bw10k); | |
766 | if (ret < 0) | |
767 | return ret; | |
768 | ret = si2165_set_oversamp(state, dvb_rate); | |
769 | if (ret < 0) | |
770 | return ret; | |
25e73753 MS |
771 | |
772 | ret = si2165_write_reg_list(state, dvbt_regs, ARRAY_SIZE(dvbt_regs)); | |
3e54a169 MS |
773 | if (ret < 0) |
774 | return ret; | |
25e73753 | 775 | |
3b0c9807 MS |
776 | return 0; |
777 | } | |
778 | ||
94c17334 MS |
779 | static const struct si2165_reg_value_pair dvbc_regs[] = { |
780 | /* standard = DVB-C */ | |
781 | { 0x00ec, 0x05 }, | |
782 | { 0x08f8, 0x00 }, | |
783 | ||
784 | /* agc2 */ | |
785 | { 0x016e, 0x50 }, | |
786 | { 0x016c, 0x0e }, | |
787 | { 0x016d, 0x10 }, | |
788 | /* agc */ | |
789 | { 0x015b, 0x03 }, | |
790 | { 0x0150, 0x68 }, | |
791 | /* agc */ | |
792 | { 0x01a0, 0x68 }, | |
793 | { 0x01c8, 0x50 }, | |
794 | ||
795 | { 0x0278, 0x0d }, | |
796 | ||
797 | { 0x023a, 0x05 }, | |
798 | { 0x0261, 0x09 }, | |
799 | REG16(0x0350, 0x3e80), | |
800 | { 0x02f4, 0x00 }, | |
801 | ||
802 | { 0x00cb, 0x01 }, | |
803 | REG16(0x024c, 0x0000), | |
804 | REG16(0x027c, 0x0000), | |
805 | { 0x0232, 0x03 }, | |
806 | { 0x02f4, 0x0b }, | |
807 | { 0x018b, 0x00 }, | |
808 | }; | |
809 | ||
810 | static int si2165_set_frontend_dvbc(struct dvb_frontend *fe) | |
811 | { | |
812 | struct si2165_state *state = fe->demodulator_priv; | |
813 | int ret; | |
814 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; | |
815 | const u32 dvb_rate = p->symbol_rate; | |
816 | const u32 bw_hz = p->bandwidth_hz; | |
817 | ||
818 | if (!state->has_dvbc) | |
819 | return -EINVAL; | |
820 | ||
821 | if (dvb_rate == 0) | |
822 | return -EINVAL; | |
823 | ||
824 | ret = si2165_adjust_pll_divl(state, 14); | |
825 | if (ret < 0) | |
826 | return ret; | |
827 | ||
828 | /* Oversampling */ | |
829 | ret = si2165_set_oversamp(state, dvb_rate); | |
830 | if (ret < 0) | |
831 | return ret; | |
832 | ||
833 | ret = si2165_writereg32(state, 0x00c4, bw_hz); | |
834 | if (ret < 0) | |
835 | return ret; | |
836 | ||
837 | ret = si2165_write_reg_list(state, dvbc_regs, ARRAY_SIZE(dvbc_regs)); | |
838 | if (ret < 0) | |
839 | return ret; | |
840 | ||
841 | return 0; | |
842 | } | |
843 | ||
3b0c9807 MS |
844 | static const struct si2165_reg_value_pair agc_rewrite[] = { |
845 | { 0x012a, 0x46 }, | |
846 | { 0x012c, 0x00 }, | |
847 | { 0x012e, 0x0a }, | |
848 | { 0x012f, 0xff }, | |
849 | { 0x0123, 0x70 } | |
850 | }; | |
851 | ||
852 | static int si2165_set_frontend(struct dvb_frontend *fe) | |
853 | { | |
854 | struct si2165_state *state = fe->demodulator_priv; | |
855 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; | |
856 | u32 delsys = p->delivery_system; | |
857 | int ret; | |
858 | u8 val[3]; | |
859 | ||
860 | /* initial setting of if freq shift */ | |
861 | ret = si2165_set_if_freq_shift(state); | |
862 | if (ret < 0) | |
863 | return ret; | |
864 | ||
865 | switch (delsys) { | |
866 | case SYS_DVBT: | |
867 | ret = si2165_set_frontend_dvbt(fe); | |
868 | if (ret < 0) | |
869 | return ret; | |
870 | break; | |
94c17334 MS |
871 | case SYS_DVBC_ANNEX_A: |
872 | ret = si2165_set_frontend_dvbc(fe); | |
873 | if (ret < 0) | |
874 | return ret; | |
875 | break; | |
3b0c9807 MS |
876 | default: |
877 | return -EINVAL; | |
878 | } | |
879 | ||
3e54a169 MS |
880 | /* dsp_addr_jump */ |
881 | ret = si2165_writereg32(state, 0x0348, 0xf4000000); | |
882 | if (ret < 0) | |
883 | return ret; | |
884 | ||
885 | if (fe->ops.tuner_ops.set_params) | |
886 | fe->ops.tuner_ops.set_params(fe); | |
887 | ||
888 | /* recalc if_freq_shift if IF might has changed */ | |
542fb3c5 | 889 | ret = si2165_set_if_freq_shift(state); |
3e54a169 MS |
890 | if (ret < 0) |
891 | return ret; | |
892 | ||
893 | /* boot/wdog status */ | |
894 | ret = si2165_readreg8(state, 0x0341, val); | |
895 | if (ret < 0) | |
896 | return ret; | |
897 | ret = si2165_writereg8(state, 0x0341, 0x00); | |
898 | if (ret < 0) | |
899 | return ret; | |
3b0c9807 | 900 | |
3e54a169 MS |
901 | /* reset all */ |
902 | ret = si2165_writereg8(state, 0x00c0, 0x00); | |
903 | if (ret < 0) | |
904 | return ret; | |
905 | /* gp_reg0 */ | |
906 | ret = si2165_writereg32(state, 0x0384, 0x00000000); | |
907 | if (ret < 0) | |
908 | return ret; | |
eae56684 MS |
909 | |
910 | /* write adc values after each reset*/ | |
911 | ret = si2165_write_reg_list(state, agc_rewrite, | |
912 | ARRAY_SIZE(agc_rewrite)); | |
913 | if (ret < 0) | |
914 | return ret; | |
915 | ||
3e54a169 MS |
916 | /* start_synchro */ |
917 | ret = si2165_writereg8(state, 0x02e0, 0x01); | |
918 | if (ret < 0) | |
919 | return ret; | |
920 | /* boot/wdog status */ | |
921 | ret = si2165_readreg8(state, 0x0341, val); | |
922 | if (ret < 0) | |
923 | return ret; | |
924 | ||
925 | return 0; | |
926 | } | |
927 | ||
bd336e63 | 928 | static const struct dvb_frontend_ops si2165_ops = { |
3e54a169 | 929 | .info = { |
119bd82e | 930 | .name = "Silicon Labs ", |
94c17334 MS |
931 | /* For DVB-C */ |
932 | .symbol_rate_min = 1000000, | |
933 | .symbol_rate_max = 7200000, | |
934 | /* For DVB-T */ | |
935 | .frequency_stepsize = 166667, | |
936 | .caps = FE_CAN_FEC_1_2 | | |
3e54a169 MS |
937 | FE_CAN_FEC_2_3 | |
938 | FE_CAN_FEC_3_4 | | |
939 | FE_CAN_FEC_5_6 | | |
940 | FE_CAN_FEC_7_8 | | |
941 | FE_CAN_FEC_AUTO | | |
942 | FE_CAN_QPSK | | |
943 | FE_CAN_QAM_16 | | |
944 | FE_CAN_QAM_32 | | |
945 | FE_CAN_QAM_64 | | |
946 | FE_CAN_QAM_128 | | |
947 | FE_CAN_QAM_256 | | |
948 | FE_CAN_QAM_AUTO | | |
3e54a169 MS |
949 | FE_CAN_GUARD_INTERVAL_AUTO | |
950 | FE_CAN_HIERARCHY_AUTO | | |
951 | FE_CAN_MUTE_TS | | |
952 | FE_CAN_TRANSMISSION_MODE_AUTO | | |
953 | FE_CAN_RECOVER | |
954 | }, | |
955 | ||
956 | .get_tune_settings = si2165_get_tune_settings, | |
957 | ||
958 | .init = si2165_init, | |
959 | .sleep = si2165_sleep, | |
960 | ||
c1c49674 | 961 | .set_frontend = si2165_set_frontend, |
3e54a169 | 962 | .read_status = si2165_read_status, |
3e54a169 MS |
963 | }; |
964 | ||
7cd785ad MS |
965 | static int si2165_probe(struct i2c_client *client, |
966 | const struct i2c_device_id *id) | |
967 | { | |
968 | struct si2165_state *state = NULL; | |
969 | struct si2165_platform_data *pdata = client->dev.platform_data; | |
970 | int n; | |
971 | int ret = 0; | |
972 | u8 val; | |
973 | char rev_char; | |
974 | const char *chip_name; | |
e3ea5e94 MS |
975 | static const struct regmap_config regmap_config = { |
976 | .reg_bits = 16, | |
977 | .val_bits = 8, | |
978 | .max_register = 0x08ff, | |
979 | }; | |
7cd785ad MS |
980 | |
981 | /* allocate memory for the internal state */ | |
982 | state = kzalloc(sizeof(struct si2165_state), GFP_KERNEL); | |
983 | if (state == NULL) { | |
984 | ret = -ENOMEM; | |
985 | goto error; | |
986 | } | |
987 | ||
e3ea5e94 MS |
988 | /* create regmap */ |
989 | state->regmap = devm_regmap_init_i2c(client, ®map_config); | |
990 | if (IS_ERR(state->regmap)) { | |
991 | ret = PTR_ERR(state->regmap); | |
992 | goto error; | |
993 | } | |
994 | ||
7cd785ad MS |
995 | /* setup the state */ |
996 | state->client = client; | |
7cd785ad MS |
997 | state->config.i2c_addr = client->addr; |
998 | state->config.chip_mode = pdata->chip_mode; | |
999 | state->config.ref_freq_Hz = pdata->ref_freq_Hz; | |
1000 | state->config.inversion = pdata->inversion; | |
1001 | ||
1002 | if (state->config.ref_freq_Hz < 4000000 | |
1003 | || state->config.ref_freq_Hz > 27000000) { | |
77f887cd MS |
1004 | dev_err(&state->client->dev, "ref_freq of %d Hz not supported by this driver\n", |
1005 | state->config.ref_freq_Hz); | |
7cd785ad MS |
1006 | ret = -EINVAL; |
1007 | goto error; | |
1008 | } | |
1009 | ||
1010 | /* create dvb_frontend */ | |
1011 | memcpy(&state->fe.ops, &si2165_ops, | |
1012 | sizeof(struct dvb_frontend_ops)); | |
1013 | state->fe.ops.release = NULL; | |
1014 | state->fe.demodulator_priv = state; | |
1015 | i2c_set_clientdata(client, state); | |
1016 | ||
1017 | /* powerup */ | |
1018 | ret = si2165_writereg8(state, 0x0000, state->config.chip_mode); | |
1019 | if (ret < 0) | |
1020 | goto nodev_error; | |
1021 | ||
1022 | ret = si2165_readreg8(state, 0x0000, &val); | |
1023 | if (ret < 0) | |
1024 | goto nodev_error; | |
1025 | if (val != state->config.chip_mode) | |
1026 | goto nodev_error; | |
1027 | ||
1028 | ret = si2165_readreg8(state, 0x0023, &state->chip_revcode); | |
1029 | if (ret < 0) | |
1030 | goto nodev_error; | |
1031 | ||
1032 | ret = si2165_readreg8(state, 0x0118, &state->chip_type); | |
1033 | if (ret < 0) | |
1034 | goto nodev_error; | |
1035 | ||
1036 | /* powerdown */ | |
1037 | ret = si2165_writereg8(state, 0x0000, SI2165_MODE_OFF); | |
1038 | if (ret < 0) | |
1039 | goto nodev_error; | |
1040 | ||
1041 | if (state->chip_revcode < 26) | |
1042 | rev_char = 'A' + state->chip_revcode; | |
1043 | else | |
1044 | rev_char = '?'; | |
1045 | ||
1046 | switch (state->chip_type) { | |
1047 | case 0x06: | |
1048 | chip_name = "Si2161"; | |
1049 | state->has_dvbt = true; | |
1050 | break; | |
1051 | case 0x07: | |
1052 | chip_name = "Si2165"; | |
1053 | state->has_dvbt = true; | |
1054 | state->has_dvbc = true; | |
1055 | break; | |
1056 | default: | |
77f887cd MS |
1057 | dev_err(&state->client->dev, "Unsupported Silicon Labs chip (type %d, rev %d)\n", |
1058 | state->chip_type, state->chip_revcode); | |
7cd785ad MS |
1059 | goto nodev_error; |
1060 | } | |
1061 | ||
aa155449 | 1062 | dev_info(&state->client->dev, |
77f887cd MS |
1063 | "Detected Silicon Labs %s-%c (type %d, rev %d)\n", |
1064 | chip_name, rev_char, state->chip_type, | |
7cd785ad MS |
1065 | state->chip_revcode); |
1066 | ||
1067 | strlcat(state->fe.ops.info.name, chip_name, | |
1068 | sizeof(state->fe.ops.info.name)); | |
1069 | ||
1070 | n = 0; | |
1071 | if (state->has_dvbt) { | |
1072 | state->fe.ops.delsys[n++] = SYS_DVBT; | |
1073 | strlcat(state->fe.ops.info.name, " DVB-T", | |
1074 | sizeof(state->fe.ops.info.name)); | |
1075 | } | |
1076 | if (state->has_dvbc) { | |
1077 | state->fe.ops.delsys[n++] = SYS_DVBC_ANNEX_A; | |
1078 | strlcat(state->fe.ops.info.name, " DVB-C", | |
1079 | sizeof(state->fe.ops.info.name)); | |
1080 | } | |
1081 | ||
1082 | /* return fe pointer */ | |
1083 | *pdata->fe = &state->fe; | |
1084 | ||
1085 | return 0; | |
1086 | ||
1087 | nodev_error: | |
1088 | ret = -ENODEV; | |
1089 | error: | |
1090 | kfree(state); | |
1091 | dev_dbg(&client->dev, "failed=%d\n", ret); | |
1092 | return ret; | |
1093 | } | |
1094 | ||
1095 | static int si2165_remove(struct i2c_client *client) | |
1096 | { | |
1097 | struct si2165_state *state = i2c_get_clientdata(client); | |
1098 | ||
1099 | dev_dbg(&client->dev, "\n"); | |
1100 | ||
1101 | kfree(state); | |
1102 | return 0; | |
1103 | } | |
1104 | ||
1105 | static const struct i2c_device_id si2165_id_table[] = { | |
1106 | {"si2165", 0}, | |
1107 | {} | |
1108 | }; | |
1109 | MODULE_DEVICE_TABLE(i2c, si2165_id_table); | |
1110 | ||
1111 | static struct i2c_driver si2165_driver = { | |
1112 | .driver = { | |
1113 | .owner = THIS_MODULE, | |
1114 | .name = "si2165", | |
1115 | }, | |
1116 | .probe = si2165_probe, | |
1117 | .remove = si2165_remove, | |
1118 | .id_table = si2165_id_table, | |
1119 | }; | |
1120 | ||
1121 | module_i2c_driver(si2165_driver); | |
1122 | ||
3e54a169 MS |
1123 | MODULE_DESCRIPTION("Silicon Labs Si2165 DVB-C/-T Demodulator driver"); |
1124 | MODULE_AUTHOR("Matthias Schwarzott <zzam@gentoo.org>"); | |
1125 | MODULE_LICENSE("GPL"); | |
55bea400 | 1126 | MODULE_FIRMWARE(SI2165_FIRMWARE_REV_D); |