projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[media] rtl2832: convert to regmap API
[linux-2.6-block.git] / drivers / media / dvb-frontends / rtl2832.c
CommitLineData
82041c0a
TM		 1/*
2 * Realtek RTL2832 DVB-T demodulator driver
3 *
4 * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include "rtl2832_priv.h"
73983497 22#include "dvb_math.h"
298f18a3 23#include <linux/bitops.h>
82041c0a 24
298f18a3 25#define REG_MASK(b) (BIT(b + 1) - 1)
82041c0a
TM		 26
27static const struct rtl2832_reg_entry registers[] = {
28 [DVBT_SOFT_RST] = {0x1, 0x1, 2, 2},
29 [DVBT_IIC_REPEAT] = {0x1, 0x1, 3, 3},
30 [DVBT_TR_WAIT_MIN_8K] = {0x1, 0x88, 11, 2},
31 [DVBT_RSD_BER_FAIL_VAL] = {0x1, 0x8f, 15, 0},
32 [DVBT_EN_BK_TRK] = {0x1, 0xa6, 7, 7},
33 [DVBT_AD_EN_REG] = {0x0, 0x8, 7, 7},
34 [DVBT_AD_EN_REG1] = {0x0, 0x8, 6, 6},
35 [DVBT_EN_BBIN] = {0x1, 0xb1, 0, 0},
36 [DVBT_MGD_THD0] = {0x1, 0x95, 7, 0},
37 [DVBT_MGD_THD1] = {0x1, 0x96, 7, 0},
38 [DVBT_MGD_THD2] = {0x1, 0x97, 7, 0},
39 [DVBT_MGD_THD3] = {0x1, 0x98, 7, 0},
40 [DVBT_MGD_THD4] = {0x1, 0x99, 7, 0},
41 [DVBT_MGD_THD5] = {0x1, 0x9a, 7, 0},
42 [DVBT_MGD_THD6] = {0x1, 0x9b, 7, 0},
43 [DVBT_MGD_THD7] = {0x1, 0x9c, 7, 0},
44 [DVBT_EN_CACQ_NOTCH] = {0x1, 0x61, 4, 4},
45 [DVBT_AD_AV_REF] = {0x0, 0x9, 6, 0},
46 [DVBT_REG_PI] = {0x0, 0xa, 2, 0},
47 [DVBT_PIP_ON] = {0x0, 0x21, 3, 3},
48 [DVBT_SCALE1_B92] = {0x2, 0x92, 7, 0},
49 [DVBT_SCALE1_B93] = {0x2, 0x93, 7, 0},
50 [DVBT_SCALE1_BA7] = {0x2, 0xa7, 7, 0},
51 [DVBT_SCALE1_BA9] = {0x2, 0xa9, 7, 0},
52 [DVBT_SCALE1_BAA] = {0x2, 0xaa, 7, 0},
53 [DVBT_SCALE1_BAB] = {0x2, 0xab, 7, 0},
54 [DVBT_SCALE1_BAC] = {0x2, 0xac, 7, 0},
55 [DVBT_SCALE1_BB0] = {0x2, 0xb0, 7, 0},
56 [DVBT_SCALE1_BB1] = {0x2, 0xb1, 7, 0},
57 [DVBT_KB_P1] = {0x1, 0x64, 3, 1},
58 [DVBT_KB_P2] = {0x1, 0x64, 6, 4},
59 [DVBT_KB_P3] = {0x1, 0x65, 2, 0},
60 [DVBT_OPT_ADC_IQ] = {0x0, 0x6, 5, 4},
61 [DVBT_AD_AVI] = {0x0, 0x9, 1, 0},
62 [DVBT_AD_AVQ] = {0x0, 0x9, 3, 2},
63 [DVBT_K1_CR_STEP12] = {0x2, 0xad, 9, 4},
64 [DVBT_TRK_KS_P2] = {0x1, 0x6f, 2, 0},
65 [DVBT_TRK_KS_I2] = {0x1, 0x70, 5, 3},
66 [DVBT_TR_THD_SET2] = {0x1, 0x72, 3, 0},
67 [DVBT_TRK_KC_P2] = {0x1, 0x73, 5, 3},
68 [DVBT_TRK_KC_I2] = {0x1, 0x75, 2, 0},
69 [DVBT_CR_THD_SET2] = {0x1, 0x76, 7, 6},
70 [DVBT_PSET_IFFREQ] = {0x1, 0x19, 21, 0},
71 [DVBT_SPEC_INV] = {0x1, 0x15, 0, 0},
72 [DVBT_RSAMP_RATIO] = {0x1, 0x9f, 27, 2},
73 [DVBT_CFREQ_OFF_RATIO] = {0x1, 0x9d, 23, 4},
74 [DVBT_FSM_STAGE] = {0x3, 0x51, 6, 3},
75 [DVBT_RX_CONSTEL] = {0x3, 0x3c, 3, 2},
76 [DVBT_RX_HIER] = {0x3, 0x3c, 6, 4},
77 [DVBT_RX_C_RATE_LP] = {0x3, 0x3d, 2, 0},
78 [DVBT_RX_C_RATE_HP] = {0x3, 0x3d, 5, 3},
79 [DVBT_GI_IDX] = {0x3, 0x51, 1, 0},
80 [DVBT_FFT_MODE_IDX] = {0x3, 0x51, 2, 2},
81 [DVBT_RSD_BER_EST] = {0x3, 0x4e, 15, 0},
82 [DVBT_CE_EST_EVM] = {0x4, 0xc, 15, 0},
83 [DVBT_RF_AGC_VAL] = {0x3, 0x5b, 13, 0},
84 [DVBT_IF_AGC_VAL] = {0x3, 0x59, 13, 0},
85 [DVBT_DAGC_VAL] = {0x3, 0x5, 7, 0},
86 [DVBT_SFREQ_OFF] = {0x3, 0x18, 13, 0},
87 [DVBT_CFREQ_OFF] = {0x3, 0x5f, 17, 0},
88 [DVBT_POLAR_RF_AGC] = {0x0, 0xe, 1, 1},
89 [DVBT_POLAR_IF_AGC] = {0x0, 0xe, 0, 0},
90 [DVBT_AAGC_HOLD] = {0x1, 0x4, 5, 5},
91 [DVBT_EN_RF_AGC] = {0x1, 0x4, 6, 6},
92 [DVBT_EN_IF_AGC] = {0x1, 0x4, 7, 7},
93 [DVBT_IF_AGC_MIN] = {0x1, 0x8, 7, 0},
94 [DVBT_IF_AGC_MAX] = {0x1, 0x9, 7, 0},
95 [DVBT_RF_AGC_MIN] = {0x1, 0xa, 7, 0},
96 [DVBT_RF_AGC_MAX] = {0x1, 0xb, 7, 0},
97 [DVBT_IF_AGC_MAN] = {0x1, 0xc, 6, 6},
98 [DVBT_IF_AGC_MAN_VAL] = {0x1, 0xc, 13, 0},
99 [DVBT_RF_AGC_MAN] = {0x1, 0xe, 6, 6},
100 [DVBT_RF_AGC_MAN_VAL] = {0x1, 0xe, 13, 0},
101 [DVBT_DAGC_TRG_VAL] = {0x1, 0x12, 7, 0},
102 [DVBT_AGC_TARG_VAL_0] = {0x1, 0x2, 0, 0},
103 [DVBT_AGC_TARG_VAL_8_1] = {0x1, 0x3, 7, 0},
104 [DVBT_AAGC_LOOP_GAIN] = {0x1, 0xc7, 5, 1},
105 [DVBT_LOOP_GAIN2_3_0] = {0x1, 0x4, 4, 1},
106 [DVBT_LOOP_GAIN2_4] = {0x1, 0x5, 7, 7},
107 [DVBT_LOOP_GAIN3] = {0x1, 0xc8, 4, 0},
108 [DVBT_VTOP1] = {0x1, 0x6, 5, 0},
109 [DVBT_VTOP2] = {0x1, 0xc9, 5, 0},
110 [DVBT_VTOP3] = {0x1, 0xca, 5, 0},
111 [DVBT_KRF1] = {0x1, 0xcb, 7, 0},
112 [DVBT_KRF2] = {0x1, 0x7, 7, 0},
113 [DVBT_KRF3] = {0x1, 0xcd, 7, 0},
114 [DVBT_KRF4] = {0x1, 0xce, 7, 0},
115 [DVBT_EN_GI_PGA] = {0x1, 0xe5, 0, 0},
116 [DVBT_THD_LOCK_UP] = {0x1, 0xd9, 8, 0},
117 [DVBT_THD_LOCK_DW] = {0x1, 0xdb, 8, 0},
118 [DVBT_THD_UP1] = {0x1, 0xdd, 7, 0},
119 [DVBT_THD_DW1] = {0x1, 0xde, 7, 0},
120 [DVBT_INTER_CNT_LEN] = {0x1, 0xd8, 3, 0},
121 [DVBT_GI_PGA_STATE] = {0x1, 0xe6, 3, 3},
122 [DVBT_EN_AGC_PGA] = {0x1, 0xd7, 0, 0},
123 [DVBT_CKOUTPAR] = {0x1, 0x7b, 5, 5},
124 [DVBT_CKOUT_PWR] = {0x1, 0x7b, 6, 6},
125 [DVBT_SYNC_DUR] = {0x1, 0x7b, 7, 7},
126 [DVBT_ERR_DUR] = {0x1, 0x7c, 0, 0},
127 [DVBT_SYNC_LVL] = {0x1, 0x7c, 1, 1},
128 [DVBT_ERR_LVL] = {0x1, 0x7c, 2, 2},
129 [DVBT_VAL_LVL] = {0x1, 0x7c, 3, 3},
130 [DVBT_SERIAL] = {0x1, 0x7c, 4, 4},
131 [DVBT_SER_LSB] = {0x1, 0x7c, 5, 5},
132 [DVBT_CDIV_PH0] = {0x1, 0x7d, 3, 0},
133 [DVBT_CDIV_PH1] = {0x1, 0x7d, 7, 4},
134 [DVBT_MPEG_IO_OPT_2_2] = {0x0, 0x6, 7, 7},
135 [DVBT_MPEG_IO_OPT_1_0] = {0x0, 0x7, 7, 6},
136 [DVBT_CKOUTPAR_PIP] = {0x0, 0xb7, 4, 4},
137 [DVBT_CKOUT_PWR_PIP] = {0x0, 0xb7, 3, 3},
138 [DVBT_SYNC_LVL_PIP] = {0x0, 0xb7, 2, 2},
139 [DVBT_ERR_LVL_PIP] = {0x0, 0xb7, 1, 1},
140 [DVBT_VAL_LVL_PIP] = {0x0, 0xb7, 0, 0},
141 [DVBT_CKOUTPAR_PID] = {0x0, 0xb9, 4, 4},
142 [DVBT_CKOUT_PWR_PID] = {0x0, 0xb9, 3, 3},
143 [DVBT_SYNC_LVL_PID] = {0x0, 0xb9, 2, 2},
144 [DVBT_ERR_LVL_PID] = {0x0, 0xb9, 1, 1},
145 [DVBT_VAL_LVL_PID] = {0x0, 0xb9, 0, 0},
146 [DVBT_SM_PASS] = {0x1, 0x93, 11, 0},
147 [DVBT_AD7_SETTING] = {0x0, 0x11, 15, 0},
148 [DVBT_RSSI_R] = {0x3, 0x1, 6, 0},
149 [DVBT_ACI_DET_IND] = {0x3, 0x12, 0, 0},
150 [DVBT_REG_MON] = {0x0, 0xd, 1, 0},
151 [DVBT_REG_MONSEL] = {0x0, 0xd, 2, 2},
152 [DVBT_REG_GPE] = {0x0, 0xd, 7, 7},
153 [DVBT_REG_GPO] = {0x0, 0x10, 0, 0},
154 [DVBT_REG_4MSEL] = {0x0, 0x13, 0, 0},
155};
156
d1016581
AP		 157/* Our regmap is bypassing I2C adapter lock, thus we do it! */
158int rtl2832_bulk_write(struct i2c_client *client, unsigned int reg,
159 const void *val, size_t val_count)
82041c0a 160{
d1016581 161 struct rtl2832_dev *dev = i2c_get_clientdata(client);
82041c0a 162 int ret;
82041c0a 163
d1016581
AP		 164 i2c_lock_adapter(client->adapter);
165 ret = regmap_bulk_write(dev->regmap, reg, val, val_count);
166 i2c_unlock_adapter(client->adapter);
82041c0a
TM		 167 return ret;
168}
169
d1016581
AP		 170int rtl2832_update_bits(struct i2c_client *client, unsigned int reg,
171 unsigned int mask, unsigned int val)
82041c0a 172{
d1016581 173 struct rtl2832_dev *dev = i2c_get_clientdata(client);
82041c0a 174 int ret;
82041c0a 175
d1016581
AP		 176 i2c_lock_adapter(client->adapter);
177 ret = regmap_update_bits(dev->regmap, reg, mask, val);
178 i2c_unlock_adapter(client->adapter);
298efdd3 179 return ret;
82041c0a
TM		 180}
181
d1016581
AP		 182int rtl2832_bulk_read(struct i2c_client *client, unsigned int reg, void *val,
183 size_t val_count)
82041c0a 184{
d1016581 185 struct rtl2832_dev *dev = i2c_get_clientdata(client);
82041c0a
TM		 186 int ret;
187
d1016581
AP		 188 i2c_lock_adapter(client->adapter);
189 ret = regmap_bulk_read(dev->regmap, reg, val, val_count);
190 i2c_unlock_adapter(client->adapter);
191 return ret;
192}
82041c0a 193
d1016581
AP		 194/* write multiple registers */
195static int rtl2832_wr_regs(struct rtl2832_dev *dev, u8 reg, u8 page, u8 *val, int len)
196{
197 return rtl2832_bulk_write(dev->client, page << 8 | reg, val, len);
82041c0a
TM		 198}
199
200/* read multiple registers */
d1016581 201static int rtl2832_rd_regs(struct rtl2832_dev *dev, u8 reg, u8 page, u8 *val, int len)
82041c0a 202{
d1016581 203 return rtl2832_bulk_read(dev->client, page << 8 | reg, val, len);
82041c0a
TM		 204}
205
82041c0a 206/* write single register */
038c6f24 207static int rtl2832_wr_reg(struct rtl2832_dev *dev, u8 reg, u8 page, u8 val)
82041c0a 208{
038c6f24 209 return rtl2832_wr_regs(dev, reg, page, &val, 1);
82041c0a 210}
82041c0a
TM		 211
212/* read single register */
038c6f24 213static int rtl2832_rd_reg(struct rtl2832_dev *dev, u8 reg, u8 page, u8 *val)
82041c0a 214{
038c6f24 215 return rtl2832_rd_regs(dev, reg, page, val, 1);
82041c0a
TM		 216}
217
038c6f24 218static int rtl2832_rd_demod_reg(struct rtl2832_dev *dev, int reg, u32 *val)
82041c0a 219{
6e6aac65 220 struct i2c_client *client = dev->client;
82041c0a
TM		 221 int ret;
222
223 u8 reg_start_addr;
224 u8 msb, lsb;
225 u8 page;
226 u8 reading[4];
227 u32 reading_tmp;
228 int i;
229
230 u8 len;
231 u32 mask;
232
233 reg_start_addr = registers[reg].start_address;
234 msb = registers[reg].msb;
235 lsb = registers[reg].lsb;
236 page = registers[reg].page;
237
238 len = (msb >> 3) + 1;
298f18a3 239 mask = REG_MASK(msb - lsb);
82041c0a 240
038c6f24 241 ret = rtl2832_rd_regs(dev, reg_start_addr, page, &reading[0], len);
82041c0a
TM		 242 if (ret)
243 goto err;
244
245 reading_tmp = 0;
246 for (i = 0; i < len; i++)
247 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
248
249 *val = (reading_tmp >> lsb) & mask;
250
251 return ret;
252
253err:
6e6aac65 254 dev_dbg(&client->dev, "failed=%d\n", ret);
82041c0a
TM		 255 return ret;
256
257}
258
038c6f24 259static int rtl2832_wr_demod_reg(struct rtl2832_dev *dev, int reg, u32 val)
82041c0a 260{
6e6aac65 261 struct i2c_client *client = dev->client;
82041c0a
TM		 262 int ret, i;
263 u8 len;
264 u8 reg_start_addr;
265 u8 msb, lsb;
266 u8 page;
267 u32 mask;
268
269
270 u8 reading[4];
271 u8 writing[4];
272 u32 reading_tmp;
273 u32 writing_tmp;
274
275
276 reg_start_addr = registers[reg].start_address;
277 msb = registers[reg].msb;
278 lsb = registers[reg].lsb;
279 page = registers[reg].page;
280
281 len = (msb >> 3) + 1;
298f18a3 282 mask = REG_MASK(msb - lsb);
82041c0a
TM		 283
284
038c6f24 285 ret = rtl2832_rd_regs(dev, reg_start_addr, page, &reading[0], len);
82041c0a
TM		 286 if (ret)
287 goto err;
288
289 reading_tmp = 0;
290 for (i = 0; i < len; i++)
291 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
292
293 writing_tmp = reading_tmp & ~(mask << lsb);
294 writing_tmp |= ((val & mask) << lsb);
295
296
297 for (i = 0; i < len; i++)
298 writing[i] = (writing_tmp >> ((len - 1 - i) * 8)) & 0xff;
299
038c6f24 300 ret = rtl2832_wr_regs(dev, reg_start_addr, page, &writing[0], len);
82041c0a
TM		 301 if (ret)
302 goto err;
303
304 return ret;
305
306err:
6e6aac65 307 dev_dbg(&client->dev, "failed=%d\n", ret);
82041c0a
TM		 308 return ret;
309
310}
311
82041c0a
TM		 312static int rtl2832_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
313{
038c6f24 314 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65
AP		 315 struct i2c_client *client = dev->client;
316 int ret;
82041c0a 317
6e6aac65 318 dev_dbg(&client->dev, "enable=%d\n", enable);
82041c0a
TM		 319
320 /* gate already open or close */
038c6f24 321 if (dev->i2c_gate_state == enable)
82041c0a
TM		 322 return 0;
323
038c6f24 324 ret = rtl2832_wr_demod_reg(dev, DVBT_IIC_REPEAT, (enable ? 0x1 : 0x0));
82041c0a
TM		 325 if (ret)
326 goto err;
327
038c6f24 328 dev->i2c_gate_state = enable;
82041c0a
TM		 329
330 return ret;
331err:
6e6aac65 332 dev_dbg(&client->dev, "failed=%d\n", ret);
82041c0a
TM		 333 return ret;
334}
335
884655ad 336static int rtl2832_set_if(struct dvb_frontend *fe, u32 if_freq)
82041c0a 337{
038c6f24 338 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 339 struct i2c_client *client = dev->client;
884655ad 340 int ret;
82041c0a 341 u64 pset_iffreq;
884655ad
MCC		 342 u8 en_bbin = (if_freq == 0 ? 0x1 : 0x0);
343
344 /*
345 * PSET_IFFREQ = - floor((IfFreqHz % CrystalFreqHz) * pow(2, 22)
346 * / CrystalFreqHz)
347 */
348
e1174d78 349 pset_iffreq = if_freq % dev->pdata->clk;
884655ad 350 pset_iffreq *= 0x400000;
e1174d78 351 pset_iffreq = div_u64(pset_iffreq, dev->pdata->clk);
c8832e8f 352 pset_iffreq = -pset_iffreq;
884655ad 353 pset_iffreq = pset_iffreq & 0x3fffff;
6e6aac65
AP		 354 dev_dbg(&client->dev, "if_frequency=%d pset_iffreq=%08x\n",
355 if_freq, (unsigned)pset_iffreq);
c8832e8f 356
038c6f24 357 ret = rtl2832_wr_demod_reg(dev, DVBT_EN_BBIN, en_bbin);
884655ad
MCC		 358 if (ret)
359 return ret;
360
038c6f24 361 ret = rtl2832_wr_demod_reg(dev, DVBT_PSET_IFFREQ, pset_iffreq);
884655ad 362
3ca2418d 363 return ret;
884655ad
MCC		 364}
365
366static int rtl2832_init(struct dvb_frontend *fe)
367{
038c6f24 368 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 369 struct i2c_client *client = dev->client;
832cc7cd 370 const struct rtl2832_reg_value *init;
884655ad 371 int i, ret, len;
82041c0a
TM		 372 /* initialization values for the demodulator registers */
373 struct rtl2832_reg_value rtl2832_initial_regs[] = {
374 {DVBT_AD_EN_REG, 0x1},
375 {DVBT_AD_EN_REG1, 0x1},
376 {DVBT_RSD_BER_FAIL_VAL, 0x2800},
377 {DVBT_MGD_THD0, 0x10},
378 {DVBT_MGD_THD1, 0x20},
379 {DVBT_MGD_THD2, 0x20},
380 {DVBT_MGD_THD3, 0x40},
381 {DVBT_MGD_THD4, 0x22},
382 {DVBT_MGD_THD5, 0x32},
383 {DVBT_MGD_THD6, 0x37},
384 {DVBT_MGD_THD7, 0x39},
385 {DVBT_EN_BK_TRK, 0x0},
386 {DVBT_EN_CACQ_NOTCH, 0x0},
387 {DVBT_AD_AV_REF, 0x2a},
388 {DVBT_REG_PI, 0x6},
389 {DVBT_PIP_ON, 0x0},
390 {DVBT_CDIV_PH0, 0x8},
391 {DVBT_CDIV_PH1, 0x8},
392 {DVBT_SCALE1_B92, 0x4},
393 {DVBT_SCALE1_B93, 0xb0},
394 {DVBT_SCALE1_BA7, 0x78},
395 {DVBT_SCALE1_BA9, 0x28},
396 {DVBT_SCALE1_BAA, 0x59},
397 {DVBT_SCALE1_BAB, 0x83},
398 {DVBT_SCALE1_BAC, 0xd4},
399 {DVBT_SCALE1_BB0, 0x65},
400 {DVBT_SCALE1_BB1, 0x43},
401 {DVBT_KB_P1, 0x1},
402 {DVBT_KB_P2, 0x4},
403 {DVBT_KB_P3, 0x7},
404 {DVBT_K1_CR_STEP12, 0xa},
405 {DVBT_REG_GPE, 0x1},
406 {DVBT_SERIAL, 0x0},
407 {DVBT_CDIV_PH0, 0x9},
408 {DVBT_CDIV_PH1, 0x9},
409 {DVBT_MPEG_IO_OPT_2_2, 0x0},
410 {DVBT_MPEG_IO_OPT_1_0, 0x0},
411 {DVBT_TRK_KS_P2, 0x4},
412 {DVBT_TRK_KS_I2, 0x7},
413 {DVBT_TR_THD_SET2, 0x6},
414 {DVBT_TRK_KC_I2, 0x5},
415 {DVBT_CR_THD_SET2, 0x1},
82041c0a
TM		 416 };
417
6e6aac65 418 dev_dbg(&client->dev, "\n");
82041c0a 419
82041c0a 420 for (i = 0; i < ARRAY_SIZE(rtl2832_initial_regs); i++) {
038c6f24 421 ret = rtl2832_wr_demod_reg(dev, rtl2832_initial_regs[i].reg,
82041c0a
TM		 422 rtl2832_initial_regs[i].value);
423 if (ret)
424 goto err;
425 }
426
832cc7cd 427 /* load tuner specific settings */
e1174d78
AP		 428 dev_dbg(&client->dev, "load settings for tuner=%02x\n",
429 dev->pdata->tuner);
430 switch (dev->pdata->tuner) {
832cc7cd
AP		 431 case RTL2832_TUNER_FC0012:
432 case RTL2832_TUNER_FC0013:
433 len = ARRAY_SIZE(rtl2832_tuner_init_fc0012);
434 init = rtl2832_tuner_init_fc0012;
435 break;
5db4187a
AP		 436 case RTL2832_TUNER_TUA9001:
437 len = ARRAY_SIZE(rtl2832_tuner_init_tua9001);
438 init = rtl2832_tuner_init_tua9001;
439 break;
7e688de0
AP		 440 case RTL2832_TUNER_E4000:
441 len = ARRAY_SIZE(rtl2832_tuner_init_e4000);
442 init = rtl2832_tuner_init_e4000;
443 break;
fa4bfd2b 444 case RTL2832_TUNER_R820T:
a26758ed 445 case RTL2832_TUNER_R828D:
fa4bfd2b
MCC		 446 len = ARRAY_SIZE(rtl2832_tuner_init_r820t);
447 init = rtl2832_tuner_init_r820t;
448 break;
832cc7cd
AP		 449 default:
450 ret = -EINVAL;
451 goto err;
452 }
453
454 for (i = 0; i < len; i++) {
038c6f24 455 ret = rtl2832_wr_demod_reg(dev, init[i].reg, init[i].value);
832cc7cd
AP		 456 if (ret)
457 goto err;
458 }
459
fa4bfd2b
MCC		 460 /*
461 * r820t NIM code does a software reset here at the demod -
3ca2418d
AP		 462 * may not be needed, as there's already a software reset at
463 * set_params()
fa4bfd2b
MCC		 464 */
465#if 1
466 /* soft reset */
038c6f24 467 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
fa4bfd2b
MCC		 468 if (ret)
469 goto err;
470
038c6f24 471 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
fa4bfd2b
MCC		 472 if (ret)
473 goto err;
474#endif
82041c0a 475
038c6f24 476 dev->sleeping = false;
82041c0a
TM		 477
478 return ret;
479
480err:
6e6aac65 481 dev_dbg(&client->dev, "failed=%d\n", ret);
82041c0a
TM		 482 return ret;
483}
484
485static int rtl2832_sleep(struct dvb_frontend *fe)
486{
038c6f24 487 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 488 struct i2c_client *client = dev->client;
82041c0a 489
6e6aac65 490 dev_dbg(&client->dev, "\n");
038c6f24 491 dev->sleeping = true;
82041c0a
TM		 492 return 0;
493}
494
b0944ea2 495static int rtl2832_get_tune_settings(struct dvb_frontend *fe,
82041c0a
TM		 496 struct dvb_frontend_tune_settings *s)
497{
038c6f24 498 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 499 struct i2c_client *client = dev->client;
298efdd3 500
6e6aac65 501 dev_dbg(&client->dev, "\n");
82041c0a
TM		 502 s->min_delay_ms = 1000;
503 s->step_size = fe->ops.info.frequency_stepsize * 2;
504 s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
505 return 0;
506}
507
508static int rtl2832_set_frontend(struct dvb_frontend *fe)
509{
038c6f24 510 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 511 struct i2c_client *client = dev->client;
82041c0a
TM		 512 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
513 int ret, i, j;
514 u64 bw_mode, num, num2;
515 u32 resamp_ratio, cfreq_off_ratio;
82041c0a
TM		 516 static u8 bw_params[3][32] = {
517 /* 6 MHz bandwidth */
518 {
519 0xf5, 0xff, 0x15, 0x38, 0x5d, 0x6d, 0x52, 0x07, 0xfa, 0x2f,
520 0x53, 0xf5, 0x3f, 0xca, 0x0b, 0x91, 0xea, 0x30, 0x63, 0xb2,
521 0x13, 0xda, 0x0b, 0xc4, 0x18, 0x7e, 0x16, 0x66, 0x08, 0x67,
522 0x19, 0xe0,
523 },
524
525 /* 7 MHz bandwidth */
526 {
527 0xe7, 0xcc, 0xb5, 0xba, 0xe8, 0x2f, 0x67, 0x61, 0x00, 0xaf,
528 0x86, 0xf2, 0xbf, 0x59, 0x04, 0x11, 0xb6, 0x33, 0xa4, 0x30,
529 0x15, 0x10, 0x0a, 0x42, 0x18, 0xf8, 0x17, 0xd9, 0x07, 0x22,
530 0x19, 0x10,
531 },
532
533 /* 8 MHz bandwidth */
534 {
535 0x09, 0xf6, 0xd2, 0xa7, 0x9a, 0xc9, 0x27, 0x77, 0x06, 0xbf,
536 0xec, 0xf4, 0x4f, 0x0b, 0xfc, 0x01, 0x63, 0x35, 0x54, 0xa7,
537 0x16, 0x66, 0x08, 0xb4, 0x19, 0x6e, 0x19, 0x65, 0x05, 0xc8,
538 0x19, 0xe0,
539 },
540 };
541
542
6e6aac65
AP		 543 dev_dbg(&client->dev, "frequency=%u bandwidth_hz=%u inversion=%u\n",
544 c->frequency, c->bandwidth_hz, c->inversion);
82041c0a
TM		 545
546 /* program tuner */
547 if (fe->ops.tuner_ops.set_params)
548 fe->ops.tuner_ops.set_params(fe);
549
fe37b38b 550 /* PIP mode related */
038c6f24 551 ret = rtl2832_wr_regs(dev, 0x92, 1, "\x00\x0f\xff", 3);
fe37b38b
AP		 552 if (ret)
553 goto err;
554
fa4bfd2b
MCC		 555 /* If the frontend has get_if_frequency(), use it */
556 if (fe->ops.tuner_ops.get_if_frequency) {
557 u32 if_freq;
fa4bfd2b
MCC		 558
559 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
560 if (ret)
561 goto err;
562
884655ad 563 ret = rtl2832_set_if(fe, if_freq);
fa4bfd2b
MCC		 564 if (ret)
565 goto err;
566 }
567
82041c0a
TM		 568 switch (c->bandwidth_hz) {
569 case 6000000:
570 i = 0;
571 bw_mode = 48000000;
572 break;
573 case 7000000:
574 i = 1;
575 bw_mode = 56000000;
576 break;
577 case 8000000:
578 i = 2;
579 bw_mode = 64000000;
580 break;
581 default:
6e6aac65
AP		 582 dev_err(&client->dev, "invalid bandwidth_hz %u\n",
583 c->bandwidth_hz);
584 ret = -EINVAL;
585 goto err;
82041c0a
TM		 586 }
587
fc4b3fa7 588 for (j = 0; j < sizeof(bw_params[0]); j++) {
038c6f24 589 ret = rtl2832_wr_regs(dev, 0x1c+j, 1, &bw_params[i][j], 1);
82041c0a
TM		 590 if (ret)
591 goto err;
592 }
593
594 /* calculate and set resample ratio
595 * RSAMP_RATIO = floor(CrystalFreqHz * 7 * pow(2, 22)
596 * / ConstWithBandwidthMode)
597 */
e1174d78 598 num = dev->pdata->clk * 7;
82041c0a
TM		 599 num *= 0x400000;
600 num = div_u64(num, bw_mode);
601 resamp_ratio = num & 0x3ffffff;
038c6f24 602 ret = rtl2832_wr_demod_reg(dev, DVBT_RSAMP_RATIO, resamp_ratio);
82041c0a
TM		 603 if (ret)
604 goto err;
605
606 /* calculate and set cfreq off ratio
607 * CFREQ_OFF_RATIO = - floor(ConstWithBandwidthMode * pow(2, 20)
608 * / (CrystalFreqHz * 7))
609 */
610 num = bw_mode << 20;
e1174d78 611 num2 = dev->pdata->clk * 7;
82041c0a
TM		 612 num = div_u64(num, num2);
613 num = -num;
614 cfreq_off_ratio = num & 0xfffff;
038c6f24 615 ret = rtl2832_wr_demod_reg(dev, DVBT_CFREQ_OFF_RATIO, cfreq_off_ratio);
82041c0a
TM		 616 if (ret)
617 goto err;
618
82041c0a 619 /* soft reset */
038c6f24 620 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
82041c0a
TM		 621 if (ret)
622 goto err;
623
038c6f24 624 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
82041c0a
TM		 625 if (ret)
626 goto err;
627
628 return ret;
629err:
6e6aac65 630 dev_dbg(&client->dev, "failed=%d\n", ret);
82041c0a
TM		 631 return ret;
632}
633
0ce67a2a
AP		 634static int rtl2832_get_frontend(struct dvb_frontend *fe)
635{
038c6f24 636 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 637 struct i2c_client *client = dev->client;
0ce67a2a
AP		 638 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
639 int ret;
640 u8 buf[3];
641
038c6f24 642 if (dev->sleeping)
0ce67a2a
AP		 643 return 0;
644
038c6f24 645 ret = rtl2832_rd_regs(dev, 0x3c, 3, buf, 2);
0ce67a2a
AP		 646 if (ret)
647 goto err;
648
038c6f24 649 ret = rtl2832_rd_reg(dev, 0x51, 3, &buf[2]);
0ce67a2a
AP		 650 if (ret)
651 goto err;
652
6e6aac65 653 dev_dbg(&client->dev, "TPS=%*ph\n", 3, buf);
0ce67a2a
AP		 654
655 switch ((buf[0] >> 2) & 3) {
656 case 0:
657 c->modulation = QPSK;
658 break;
659 case 1:
660 c->modulation = QAM_16;
661 break;
662 case 2:
663 c->modulation = QAM_64;
664 break;
665 }
666
667 switch ((buf[2] >> 2) & 1) {
668 case 0:
669 c->transmission_mode = TRANSMISSION_MODE_2K;
670 break;
671 case 1:
672 c->transmission_mode = TRANSMISSION_MODE_8K;
673 }
674
675 switch ((buf[2] >> 0) & 3) {
676 case 0:
677 c->guard_interval = GUARD_INTERVAL_1_32;
678 break;
679 case 1:
680 c->guard_interval = GUARD_INTERVAL_1_16;
681 break;
682 case 2:
683 c->guard_interval = GUARD_INTERVAL_1_8;
684 break;
685 case 3:
686 c->guard_interval = GUARD_INTERVAL_1_4;
687 break;
688 }
689
690 switch ((buf[0] >> 4) & 7) {
691 case 0:
692 c->hierarchy = HIERARCHY_NONE;
693 break;
694 case 1:
695 c->hierarchy = HIERARCHY_1;
696 break;
697 case 2:
698 c->hierarchy = HIERARCHY_2;
699 break;
700 case 3:
701 c->hierarchy = HIERARCHY_4;
702 break;
703 }
704
705 switch ((buf[1] >> 3) & 7) {
706 case 0:
707 c->code_rate_HP = FEC_1_2;
708 break;
709 case 1:
710 c->code_rate_HP = FEC_2_3;
711 break;
712 case 2:
713 c->code_rate_HP = FEC_3_4;
714 break;
715 case 3:
716 c->code_rate_HP = FEC_5_6;
717 break;
718 case 4:
719 c->code_rate_HP = FEC_7_8;
720 break;
721 }
722
723 switch ((buf[1] >> 0) & 7) {
724 case 0:
725 c->code_rate_LP = FEC_1_2;
726 break;
727 case 1:
728 c->code_rate_LP = FEC_2_3;
729 break;
730 case 2:
731 c->code_rate_LP = FEC_3_4;
732 break;
733 case 3:
734 c->code_rate_LP = FEC_5_6;
735 break;
736 case 4:
737 c->code_rate_LP = FEC_7_8;
738 break;
739 }
740
741 return 0;
742err:
6e6aac65 743 dev_dbg(&client->dev, "failed=%d\n", ret);
0ce67a2a
AP		 744 return ret;
745}
746
82041c0a
TM		 747static int rtl2832_read_status(struct dvb_frontend *fe, fe_status_t *status)
748{
038c6f24 749 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 750 struct i2c_client *client = dev->client;
82041c0a
TM		 751 int ret;
752 u32 tmp;
82041c0a 753
6e6aac65
AP		 754 dev_dbg(&client->dev, "\n");
755
756 *status = 0;
038c6f24 757 if (dev->sleeping)
82041c0a
TM		 758 return 0;
759
038c6f24 760 ret = rtl2832_rd_demod_reg(dev, DVBT_FSM_STAGE, &tmp);
82041c0a
TM		 761 if (ret)
762 goto err;
763
764 if (tmp == 11) {
765 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
766 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
767 }
768 /* TODO find out if this is also true for rtl2832? */
769 /*else if (tmp == 10) {
770 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
771 FE_HAS_VITERBI;
772 }*/
773
774 return ret;
775err:
6e6aac65 776 dev_dbg(&client->dev, "failed=%d\n", ret);
82041c0a
TM		 777 return ret;
778}
779
73983497
AP		 780static int rtl2832_read_snr(struct dvb_frontend *fe, u16 *snr)
781{
038c6f24 782 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 783 struct i2c_client *client = dev->client;
73983497
AP		 784 int ret, hierarchy, constellation;
785 u8 buf[2], tmp;
786 u16 tmp16;
787#define CONSTELLATION_NUM 3
788#define HIERARCHY_NUM 4
789 static const u32 snr_constant[CONSTELLATION_NUM][HIERARCHY_NUM] = {
790 { 85387325, 85387325, 85387325, 85387325 },
791 { 86676178, 86676178, 87167949, 87795660 },
792 { 87659938, 87659938, 87885178, 88241743 },
793 };
794
795 /* reports SNR in resolution of 0.1 dB */
796
038c6f24 797 ret = rtl2832_rd_reg(dev, 0x3c, 3, &tmp);
73983497
AP		 798 if (ret)
799 goto err;
800
801 constellation = (tmp >> 2) & 0x03; /* [3:2] */
802 if (constellation > CONSTELLATION_NUM - 1)
803 goto err;
804
805 hierarchy = (tmp >> 4) & 0x07; /* [6:4] */
806 if (hierarchy > HIERARCHY_NUM - 1)
807 goto err;
808
038c6f24 809 ret = rtl2832_rd_regs(dev, 0x0c, 4, buf, 2);
73983497
AP		 810 if (ret)
811 goto err;
812
813 tmp16 = buf[0] << 8 | buf[1];
814
815 if (tmp16)
816 *snr = (snr_constant[constellation][hierarchy] -
817 intlog10(tmp16)) / ((1 << 24) / 100);
818 else
819 *snr = 0;
820
821 return 0;
822err:
6e6aac65 823 dev_dbg(&client->dev, "failed=%d\n", ret);
73983497
AP		 824 return ret;
825}
826
db32d74a
AP		 827static int rtl2832_read_ber(struct dvb_frontend *fe, u32 *ber)
828{
038c6f24 829 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 830 struct i2c_client *client = dev->client;
db32d74a
AP		 831 int ret;
832 u8 buf[2];
833
038c6f24 834 ret = rtl2832_rd_regs(dev, 0x4e, 3, buf, 2);
db32d74a
AP		 835 if (ret)
836 goto err;
837
838 *ber = buf[0] << 8 | buf[1];
839
840 return 0;
841err:
6e6aac65 842 dev_dbg(&client->dev, "failed=%d\n", ret);
db32d74a
AP		 843 return ret;
844}
845
92d20d9f 846/*
d1016581
AP		 847 * I2C gate/mux/repeater logic
848 * We must use unlocked __i2c_transfer() here (through regmap) because of I2C
849 * adapter lock is already taken by tuner driver.
850 * There is delay mechanism to avoid unneeded I2C gate open / close. Gate close
851 * is delayed here a little bit in order to see if there is sequence of I2C
92d20d9f 852 * messages sent to same I2C bus.
92d20d9f
AP		 853 */
854static void rtl2832_i2c_gate_work(struct work_struct *work)
855{
d1016581 856 struct rtl2832_dev *dev = container_of(work, struct rtl2832_dev, i2c_gate_work.work);
6e6aac65 857 struct i2c_client *client = dev->client;
92d20d9f 858 int ret;
6e6aac65 859
d1016581
AP		 860 /* close gate */
861 ret = rtl2832_update_bits(dev->client, 0x101, 0x08, 0x00);
862 if (ret)
92d20d9f
AP		 863 goto err;
864
038c6f24 865 dev->i2c_gate_state = false;
92d20d9f
AP		 866
867 return;
868err:
6e6aac65 869 dev_dbg(&client->dev, "failed=%d\n", ret);
92d20d9f
AP		 870 return;
871}
872
0ea872d4 873static int rtl2832_select(struct i2c_adapter *adap, void *mux_priv, u32 chan_id)
8823f028 874{
038c6f24 875 struct rtl2832_dev *dev = mux_priv;
6e6aac65 876 struct i2c_client *client = dev->client;
0ea872d4 877 int ret;
92d20d9f
AP		 878
879 /* terminate possible gate closing */
d1016581 880 cancel_delayed_work(&dev->i2c_gate_work);
8823f028 881
038c6f24 882 if (dev->i2c_gate_state == chan_id)
0ea872d4
AP		 883 return 0;
884
d1016581
AP		 885 /*
886 * chan_id 1 is muxed adapter demod provides and chan_id 0 is demod
887 * itself. We need open gate when request is for chan_id 1. On that case
888 * I2C adapter lock is already taken and due to that we will use
889 * regmap_update_bits() which does not lock again I2C adapter.
890 */
0ea872d4 891 if (chan_id == 1)
d1016581 892 ret = regmap_update_bits(dev->regmap, 0x101, 0x08, 0x08);
0ea872d4 893 else
d1016581
AP		 894 ret = rtl2832_update_bits(dev->client, 0x101, 0x08, 0x00);
895 if (ret)
0ea872d4
AP		 896 goto err;
897
038c6f24 898 dev->i2c_gate_state = chan_id;
0ea872d4
AP		 899
900 return 0;
901err:
6e6aac65 902 dev_dbg(&client->dev, "failed=%d\n", ret);
d1016581 903 return ret;
8823f028
AP		 904}
905
92d20d9f 906static int rtl2832_deselect(struct i2c_adapter *adap, void *mux_priv,
d1016581 907 u32 chan_id)
92d20d9f 908{
038c6f24 909 struct rtl2832_dev *dev = mux_priv;
6e6aac65 910
038c6f24 911 schedule_delayed_work(&dev->i2c_gate_work, usecs_to_jiffies(100));
92d20d9f
AP		 912 return 0;
913}
914
82041c0a
TM		 915static struct dvb_frontend_ops rtl2832_ops = {
916 .delsys = { SYS_DVBT },
917 .info = {
918 .name = "Realtek RTL2832 (DVB-T)",
919 .frequency_min = 174000000,
920 .frequency_max = 862000000,
921 .frequency_stepsize = 166667,
922 .caps = FE_CAN_FEC_1_2 |
923 FE_CAN_FEC_2_3 |
924 FE_CAN_FEC_3_4 |
925 FE_CAN_FEC_5_6 |
926 FE_CAN_FEC_7_8 |
927 FE_CAN_FEC_AUTO |
928 FE_CAN_QPSK |
929 FE_CAN_QAM_16 |
930 FE_CAN_QAM_64 |
931 FE_CAN_QAM_AUTO |
932 FE_CAN_TRANSMISSION_MODE_AUTO |
933 FE_CAN_GUARD_INTERVAL_AUTO |
934 FE_CAN_HIERARCHY_AUTO |
935 FE_CAN_RECOVER |
936 FE_CAN_MUTE_TS
937 },
938
82041c0a
TM		 939 .init = rtl2832_init,
940 .sleep = rtl2832_sleep,
941
942 .get_tune_settings = rtl2832_get_tune_settings,
943
944 .set_frontend = rtl2832_set_frontend,
0ce67a2a 945 .get_frontend = rtl2832_get_frontend,
82041c0a
TM		 946
947 .read_status = rtl2832_read_status,
73983497 948 .read_snr = rtl2832_read_snr,
db32d74a 949 .read_ber = rtl2832_read_ber,
73983497 950
82041c0a
TM		 951 .i2c_gate_ctrl = rtl2832_i2c_gate_ctrl,
952};
953
d1016581
AP		 954/*
955 * We implement own I2C access routines for regmap in order to get manual access
956 * to I2C adapter lock, which is needed for I2C mux adapter.
957 */
958static int rtl2832_regmap_read(void *context, const void *reg_buf,
959 size_t reg_size, void *val_buf, size_t val_size)
960{
961 struct i2c_client *client = context;
962 int ret;
963 struct i2c_msg msg[2] = {
964 {
965 .addr = client->addr,
966 .flags = 0,
967 .len = reg_size,
968 .buf = (u8 *)reg_buf,
969 }, {
970 .addr = client->addr,
971 .flags = I2C_M_RD,
972 .len = val_size,
973 .buf = val_buf,
974 }
975 };
976
977 ret = __i2c_transfer(client->adapter, msg, 2);
978 if (ret != 2) {
979 dev_warn(&client->dev, "i2c reg read failed %d\n", ret);
980 if (ret >= 0)
981 ret = -EREMOTEIO;
982 return ret;
983 }
984 return 0;
985}
986
987static int rtl2832_regmap_write(void *context, const void *data, size_t count)
988{
989 struct i2c_client *client = context;
990 int ret;
991 struct i2c_msg msg[1] = {
992 {
993 .addr = client->addr,
994 .flags = 0,
995 .len = count,
996 .buf = (u8 *)data,
997 }
998 };
999
1000 ret = __i2c_transfer(client->adapter, msg, 1);
1001 if (ret != 1) {
1002 dev_warn(&client->dev, "i2c reg write failed %d\n", ret);
1003 if (ret >= 0)
1004 ret = -EREMOTEIO;
1005 return ret;
1006 }
1007 return 0;
1008}
1009
1010static int rtl2832_regmap_gather_write(void *context, const void *reg,
1011 size_t reg_len, const void *val,
1012 size_t val_len)
1013{
1014 struct i2c_client *client = context;
1015 int ret;
1016 u8 buf[256];
1017 struct i2c_msg msg[1] = {
1018 {
1019 .addr = client->addr,
1020 .flags = 0,
1021 .len = 1 + val_len,
1022 .buf = buf,
1023 }
1024 };
1025
1026 buf[0] = *(u8 const *)reg;
1027 memcpy(&buf[1], val, val_len);
1028
1029 ret = __i2c_transfer(client->adapter, msg, 1);
1030 if (ret != 1) {
1031 dev_warn(&client->dev, "i2c reg write failed %d\n", ret);
1032 if (ret >= 0)
1033 ret = -EREMOTEIO;
1034 return ret;
1035 }
1036 return 0;
1037}
1038
6f5f6ee2
AP		 1039static struct dvb_frontend *rtl2832_get_dvb_frontend(struct i2c_client *client)
1040{
038c6f24 1041 struct rtl2832_dev *dev = i2c_get_clientdata(client);
6f5f6ee2
AP		 1042
1043 dev_dbg(&client->dev, "\n");
1044 return &dev->fe;
1045}
1046
1047static struct i2c_adapter *rtl2832_get_i2c_adapter_(struct i2c_client *client)
1048{
038c6f24 1049 struct rtl2832_dev *dev = i2c_get_clientdata(client);
6f5f6ee2
AP		 1050
1051 dev_dbg(&client->dev, "\n");
1052 return dev->i2c_adapter_tuner;
1053}
1054
1055static struct i2c_adapter *rtl2832_get_private_i2c_adapter_(struct i2c_client *client)
1056{
038c6f24 1057 struct rtl2832_dev *dev = i2c_get_clientdata(client);
6f5f6ee2
AP		 1058
1059 dev_dbg(&client->dev, "\n");
1060 return dev->i2c_adapter;
1061}
1062
1063static int rtl2832_enable_slave_ts(struct i2c_client *client)
1064{
038c6f24 1065 struct rtl2832_dev *dev = i2c_get_clientdata(client);
6f5f6ee2
AP		 1066 int ret;
1067
6e6aac65 1068 dev_dbg(&client->dev, "\n");
6f5f6ee2
AP		 1069
1070 ret = rtl2832_wr_regs(dev, 0x0c, 1, "\x5f\xff", 2);
1071 if (ret)
1072 goto err;
1073
1074 ret = rtl2832_wr_demod_reg(dev, DVBT_PIP_ON, 0x1);
1075 if (ret)
1076 goto err;
1077
1078 ret = rtl2832_wr_reg(dev, 0xbc, 0, 0x18);
1079 if (ret)
1080 goto err;
1081
1082 ret = rtl2832_wr_reg(dev, 0x22, 0, 0x01);
1083 if (ret)
1084 goto err;
1085
1086 ret = rtl2832_wr_reg(dev, 0x26, 0, 0x1f);
1087 if (ret)
1088 goto err;
1089
1090 ret = rtl2832_wr_reg(dev, 0x27, 0, 0xff);
1091 if (ret)
1092 goto err;
1093
1094 ret = rtl2832_wr_regs(dev, 0x92, 1, "\x7f\xf7\xff", 3);
1095 if (ret)
1096 goto err;
1097
1098 /* soft reset */
1099 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
1100 if (ret)
1101 goto err;
1102
1103 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
1104 if (ret)
1105 goto err;
1106
1107 return 0;
1108err:
1109 dev_dbg(&client->dev, "failed=%d\n", ret);
1110 return ret;
1111}
1112
c2c8386f
AP		 1113static int rtl2832_probe(struct i2c_client *client,
1114 const struct i2c_device_id *id)
1115{
1116 struct rtl2832_platform_data *pdata = client->dev.platform_data;
c2c8386f 1117 struct i2c_adapter *i2c = client->adapter;
038c6f24 1118 struct rtl2832_dev *dev;
c2c8386f
AP		 1119 int ret;
1120 u8 tmp;
d1016581
AP		 1121 static const struct regmap_bus regmap_bus = {
1122 .read = rtl2832_regmap_read,
1123 .write = rtl2832_regmap_write,
1124 .gather_write = rtl2832_regmap_gather_write,
1125 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
1126 };
1127 static const struct regmap_range_cfg regmap_range_cfg[] = {
1128 {
1129 .selector_reg = 0x00,
1130 .selector_mask = 0xff,
1131 .selector_shift = 0,
1132 .window_start = 0,
1133 .window_len = 0x100,
1134 .range_min = 0 * 0x100,
1135 .range_max = 5 * 0x100,
1136 },
1137 };
1138 static const struct regmap_config regmap_config = {
1139 .reg_bits = 8,
1140 .val_bits = 8,
1141 .max_register = 5 * 0x100,
1142 .ranges = regmap_range_cfg,
1143 .num_ranges = ARRAY_SIZE(regmap_range_cfg),
1144 };
c2c8386f
AP		 1145
1146 dev_dbg(&client->dev, "\n");
1147
c2c8386f 1148 /* allocate memory for the internal state */
038c6f24
AP		 1149 dev = kzalloc(sizeof(struct rtl2832_dev), GFP_KERNEL);
1150 if (dev == NULL) {
c2c8386f
AP		 1151 ret = -ENOMEM;
1152 goto err;
1153 }
1154
038c6f24 1155 /* setup the state */
d1016581 1156 i2c_set_clientdata(client, dev);
038c6f24 1157 dev->client = client;
e1174d78
AP		 1158 dev->pdata = client->dev.platform_data;
1159 if (pdata->config) {
1160 dev->pdata->clk = pdata->config->xtal;
1161 dev->pdata->tuner = pdata->config->tuner;
1162 }
038c6f24 1163 dev->sleeping = true;
038c6f24 1164 INIT_DELAYED_WORK(&dev->i2c_gate_work, rtl2832_i2c_gate_work);
d1016581
AP		 1165 /* create regmap */
1166 dev->regmap = regmap_init(&client->dev, &regmap_bus, client,
1167 &regmap_config);
1168 if (IS_ERR(dev->regmap)) {
1169 ret = PTR_ERR(dev->regmap);
1170 goto err_kfree;
1171 }
c2c8386f 1172 /* create muxed i2c adapter for demod itself */
038c6f24 1173 dev->i2c_adapter = i2c_add_mux_adapter(i2c, &i2c->dev, dev, 0, 0, 0,
c2c8386f 1174 rtl2832_select, NULL);
038c6f24 1175 if (dev->i2c_adapter == NULL) {
c2c8386f 1176 ret = -ENODEV;
d1016581 1177 goto err_regmap_exit;
c2c8386f
AP		 1178 }
1179
1180 /* check if the demod is there */
038c6f24 1181 ret = rtl2832_rd_reg(dev, 0x00, 0x0, &tmp);
c2c8386f
AP		 1182 if (ret)
1183 goto err_i2c_del_mux_adapter;
1184
1185 /* create muxed i2c adapter for demod tuner bus */
038c6f24 1186 dev->i2c_adapter_tuner = i2c_add_mux_adapter(i2c, &i2c->dev, dev,
c2c8386f 1187 0, 1, 0, rtl2832_select, rtl2832_deselect);
038c6f24 1188 if (dev->i2c_adapter_tuner == NULL) {
c2c8386f
AP		 1189 ret = -ENODEV;
1190 goto err_i2c_del_mux_adapter;
1191 }
1192
1193 /* create dvb_frontend */
038c6f24
AP		 1194 memcpy(&dev->fe.ops, &rtl2832_ops, sizeof(struct dvb_frontend_ops));
1195 dev->fe.demodulator_priv = dev;
6f5f6ee2
AP		 1196
1197 /* setup callbacks */
1198 pdata->get_dvb_frontend = rtl2832_get_dvb_frontend;
1199 pdata->get_i2c_adapter = rtl2832_get_i2c_adapter_;
1200 pdata->get_private_i2c_adapter = rtl2832_get_private_i2c_adapter_;
1201 pdata->enable_slave_ts = rtl2832_enable_slave_ts;
c2c8386f
AP		 1202
1203 dev_info(&client->dev, "Realtek RTL2832 successfully attached\n");
1204 return 0;
1205err_i2c_del_mux_adapter:
038c6f24 1206 i2c_del_mux_adapter(dev->i2c_adapter);
d1016581
AP		 1207err_regmap_exit:
1208 regmap_exit(dev->regmap);
c2c8386f 1209err_kfree:
038c6f24 1210 kfree(dev);
c2c8386f
AP		 1211err:
1212 dev_dbg(&client->dev, "failed=%d\n", ret);
1213 return ret;
1214}
1215
1216static int rtl2832_remove(struct i2c_client *client)
1217{
038c6f24 1218 struct rtl2832_dev *dev = i2c_get_clientdata(client);
c2c8386f
AP		 1219
1220 dev_dbg(&client->dev, "\n");
1221
038c6f24 1222 cancel_delayed_work_sync(&dev->i2c_gate_work);
c2c8386f 1223
038c6f24 1224 i2c_del_mux_adapter(dev->i2c_adapter_tuner);
c2c8386f 1225
038c6f24 1226 i2c_del_mux_adapter(dev->i2c_adapter);
c2c8386f 1227
d1016581
AP		 1228 regmap_exit(dev->regmap);
1229
038c6f24 1230 kfree(dev);
c2c8386f
AP		 1231
1232 return 0;
1233}
1234
1235static const struct i2c_device_id rtl2832_id_table[] = {
1236 {"rtl2832", 0},
1237 {}
1238};
1239MODULE_DEVICE_TABLE(i2c, rtl2832_id_table);
1240
1241static struct i2c_driver rtl2832_driver = {
1242 .driver = {
1243 .owner = THIS_MODULE,
1244 .name = "rtl2832",
1245 },
1246 .probe = rtl2832_probe,
1247 .remove = rtl2832_remove,
1248 .id_table = rtl2832_id_table,
1249};
1250
1251module_i2c_driver(rtl2832_driver);
1252
82041c0a
TM		 1253MODULE_AUTHOR("Thomas Mair <mair.thomas86@gmail.com>");
1254MODULE_DESCRIPTION("Realtek RTL2832 DVB-T demodulator driver");
1255MODULE_LICENSE("GPL");
1256MODULE_VERSION("0.5");
Linux 6.x block layer and io_uring tree(s)