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[media] vb2: Fix dma_dir setting for dma-contig mem type
[linux-2.6-block.git] / drivers / media / dvb-frontends / rtl2832.c
CommitLineData
82041c0a
TM		 1/*
2 * Realtek RTL2832 DVB-T demodulator driver
3 *
4 * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
75c24005 5 * Copyright (C) 2012-2014 Antti Palosaari <crope@iki.fi>
82041c0a
TM		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21
22#include "rtl2832_priv.h"
82041c0a 23
298f18a3 24#define REG_MASK(b) (BIT(b + 1) - 1)
82041c0a
TM		 25
26static const struct rtl2832_reg_entry registers[] = {
eec21beb
AP		 27 [DVBT_SOFT_RST] = {0x101, 2, 2},
28 [DVBT_IIC_REPEAT] = {0x101, 3, 3},
29 [DVBT_TR_WAIT_MIN_8K] = {0x188, 11, 2},
30 [DVBT_RSD_BER_FAIL_VAL] = {0x18f, 15, 0},
31 [DVBT_EN_BK_TRK] = {0x1a6, 7, 7},
32 [DVBT_AD_EN_REG] = {0x008, 7, 7},
33 [DVBT_AD_EN_REG1] = {0x008, 6, 6},
34 [DVBT_EN_BBIN] = {0x1b1, 0, 0},
35 [DVBT_MGD_THD0] = {0x195, 7, 0},
36 [DVBT_MGD_THD1] = {0x196, 7, 0},
37 [DVBT_MGD_THD2] = {0x197, 7, 0},
38 [DVBT_MGD_THD3] = {0x198, 7, 0},
39 [DVBT_MGD_THD4] = {0x199, 7, 0},
40 [DVBT_MGD_THD5] = {0x19a, 7, 0},
41 [DVBT_MGD_THD6] = {0x19b, 7, 0},
42 [DVBT_MGD_THD7] = {0x19c, 7, 0},
43 [DVBT_EN_CACQ_NOTCH] = {0x161, 4, 4},
44 [DVBT_AD_AV_REF] = {0x009, 6, 0},
45 [DVBT_REG_PI] = {0x00a, 2, 0},
46 [DVBT_PIP_ON] = {0x021, 3, 3},
47 [DVBT_SCALE1_B92] = {0x292, 7, 0},
48 [DVBT_SCALE1_B93] = {0x293, 7, 0},
49 [DVBT_SCALE1_BA7] = {0x2a7, 7, 0},
50 [DVBT_SCALE1_BA9] = {0x2a9, 7, 0},
51 [DVBT_SCALE1_BAA] = {0x2aa, 7, 0},
52 [DVBT_SCALE1_BAB] = {0x2ab, 7, 0},
53 [DVBT_SCALE1_BAC] = {0x2ac, 7, 0},
54 [DVBT_SCALE1_BB0] = {0x2b0, 7, 0},
55 [DVBT_SCALE1_BB1] = {0x2b1, 7, 0},
56 [DVBT_KB_P1] = {0x164, 3, 1},
57 [DVBT_KB_P2] = {0x164, 6, 4},
58 [DVBT_KB_P3] = {0x165, 2, 0},
59 [DVBT_OPT_ADC_IQ] = {0x006, 5, 4},
60 [DVBT_AD_AVI] = {0x009, 1, 0},
61 [DVBT_AD_AVQ] = {0x009, 3, 2},
62 [DVBT_K1_CR_STEP12] = {0x2ad, 9, 4},
63 [DVBT_TRK_KS_P2] = {0x16f, 2, 0},
64 [DVBT_TRK_KS_I2] = {0x170, 5, 3},
65 [DVBT_TR_THD_SET2] = {0x172, 3, 0},
66 [DVBT_TRK_KC_P2] = {0x173, 5, 3},
67 [DVBT_TRK_KC_I2] = {0x175, 2, 0},
68 [DVBT_CR_THD_SET2] = {0x176, 7, 6},
69 [DVBT_PSET_IFFREQ] = {0x119, 21, 0},
70 [DVBT_SPEC_INV] = {0x115, 0, 0},
71 [DVBT_RSAMP_RATIO] = {0x19f, 27, 2},
72 [DVBT_CFREQ_OFF_RATIO] = {0x19d, 23, 4},
73 [DVBT_FSM_STAGE] = {0x351, 6, 3},
74 [DVBT_RX_CONSTEL] = {0x33c, 3, 2},
75 [DVBT_RX_HIER] = {0x33c, 6, 4},
76 [DVBT_RX_C_RATE_LP] = {0x33d, 2, 0},
77 [DVBT_RX_C_RATE_HP] = {0x33d, 5, 3},
78 [DVBT_GI_IDX] = {0x351, 1, 0},
79 [DVBT_FFT_MODE_IDX] = {0x351, 2, 2},
80 [DVBT_RSD_BER_EST] = {0x34e, 15, 0},
81 [DVBT_CE_EST_EVM] = {0x40c, 15, 0},
82 [DVBT_RF_AGC_VAL] = {0x35b, 13, 0},
83 [DVBT_IF_AGC_VAL] = {0x359, 13, 0},
84 [DVBT_DAGC_VAL] = {0x305, 7, 0},
85 [DVBT_SFREQ_OFF] = {0x318, 13, 0},
86 [DVBT_CFREQ_OFF] = {0x35f, 17, 0},
87 [DVBT_POLAR_RF_AGC] = {0x00e, 1, 1},
88 [DVBT_POLAR_IF_AGC] = {0x00e, 0, 0},
89 [DVBT_AAGC_HOLD] = {0x104, 5, 5},
90 [DVBT_EN_RF_AGC] = {0x104, 6, 6},
91 [DVBT_EN_IF_AGC] = {0x104, 7, 7},
92 [DVBT_IF_AGC_MIN] = {0x108, 7, 0},
93 [DVBT_IF_AGC_MAX] = {0x109, 7, 0},
94 [DVBT_RF_AGC_MIN] = {0x10a, 7, 0},
95 [DVBT_RF_AGC_MAX] = {0x10b, 7, 0},
96 [DVBT_IF_AGC_MAN] = {0x10c, 6, 6},
97 [DVBT_IF_AGC_MAN_VAL] = {0x10c, 13, 0},
98 [DVBT_RF_AGC_MAN] = {0x10e, 6, 6},
99 [DVBT_RF_AGC_MAN_VAL] = {0x10e, 13, 0},
100 [DVBT_DAGC_TRG_VAL] = {0x112, 7, 0},
101 [DVBT_AGC_TARG_VAL_0] = {0x102, 0, 0},
102 [DVBT_AGC_TARG_VAL_8_1] = {0x103, 7, 0},
103 [DVBT_AAGC_LOOP_GAIN] = {0x1c7, 5, 1},
104 [DVBT_LOOP_GAIN2_3_0] = {0x104, 4, 1},
105 [DVBT_LOOP_GAIN2_4] = {0x105, 7, 7},
106 [DVBT_LOOP_GAIN3] = {0x1c8, 4, 0},
107 [DVBT_VTOP1] = {0x106, 5, 0},
108 [DVBT_VTOP2] = {0x1c9, 5, 0},
109 [DVBT_VTOP3] = {0x1ca, 5, 0},
110 [DVBT_KRF1] = {0x1cb, 7, 0},
111 [DVBT_KRF2] = {0x107, 7, 0},
112 [DVBT_KRF3] = {0x1cd, 7, 0},
113 [DVBT_KRF4] = {0x1ce, 7, 0},
114 [DVBT_EN_GI_PGA] = {0x1e5, 0, 0},
115 [DVBT_THD_LOCK_UP] = {0x1d9, 8, 0},
116 [DVBT_THD_LOCK_DW] = {0x1db, 8, 0},
117 [DVBT_THD_UP1] = {0x1dd, 7, 0},
118 [DVBT_THD_DW1] = {0x1de, 7, 0},
119 [DVBT_INTER_CNT_LEN] = {0x1d8, 3, 0},
120 [DVBT_GI_PGA_STATE] = {0x1e6, 3, 3},
121 [DVBT_EN_AGC_PGA] = {0x1d7, 0, 0},
122 [DVBT_CKOUTPAR] = {0x17b, 5, 5},
123 [DVBT_CKOUT_PWR] = {0x17b, 6, 6},
124 [DVBT_SYNC_DUR] = {0x17b, 7, 7},
125 [DVBT_ERR_DUR] = {0x17c, 0, 0},
126 [DVBT_SYNC_LVL] = {0x17c, 1, 1},
127 [DVBT_ERR_LVL] = {0x17c, 2, 2},
128 [DVBT_VAL_LVL] = {0x17c, 3, 3},
129 [DVBT_SERIAL] = {0x17c, 4, 4},
130 [DVBT_SER_LSB] = {0x17c, 5, 5},
131 [DVBT_CDIV_PH0] = {0x17d, 3, 0},
132 [DVBT_CDIV_PH1] = {0x17d, 7, 4},
133 [DVBT_MPEG_IO_OPT_2_2] = {0x006, 7, 7},
134 [DVBT_MPEG_IO_OPT_1_0] = {0x007, 7, 6},
135 [DVBT_CKOUTPAR_PIP] = {0x0b7, 4, 4},
136 [DVBT_CKOUT_PWR_PIP] = {0x0b7, 3, 3},
137 [DVBT_SYNC_LVL_PIP] = {0x0b7, 2, 2},
138 [DVBT_ERR_LVL_PIP] = {0x0b7, 1, 1},
139 [DVBT_VAL_LVL_PIP] = {0x0b7, 0, 0},
140 [DVBT_CKOUTPAR_PID] = {0x0b9, 4, 4},
141 [DVBT_CKOUT_PWR_PID] = {0x0b9, 3, 3},
142 [DVBT_SYNC_LVL_PID] = {0x0b9, 2, 2},
143 [DVBT_ERR_LVL_PID] = {0x0b9, 1, 1},
144 [DVBT_VAL_LVL_PID] = {0x0b9, 0, 0},
145 [DVBT_SM_PASS] = {0x193, 11, 0},
146 [DVBT_AD7_SETTING] = {0x011, 15, 0},
147 [DVBT_RSSI_R] = {0x301, 6, 0},
148 [DVBT_ACI_DET_IND] = {0x312, 0, 0},
149 [DVBT_REG_MON] = {0x00d, 1, 0},
150 [DVBT_REG_MONSEL] = {0x00d, 2, 2},
151 [DVBT_REG_GPE] = {0x00d, 7, 7},
152 [DVBT_REG_GPO] = {0x010, 0, 0},
153 [DVBT_REG_4MSEL] = {0x013, 0, 0},
82041c0a
TM		 154};
155
d1016581 156/* Our regmap is bypassing I2C adapter lock, thus we do it! */
bda977b7
MCC		 157static int rtl2832_bulk_write(struct i2c_client *client, unsigned int reg,
158 const void *val, size_t val_count)
82041c0a 159{
d1016581 160 struct rtl2832_dev *dev = i2c_get_clientdata(client);
82041c0a 161 int ret;
82041c0a 162
d1016581
AP		 163 i2c_lock_adapter(client->adapter);
164 ret = regmap_bulk_write(dev->regmap, reg, val, val_count);
165 i2c_unlock_adapter(client->adapter);
82041c0a
TM		 166 return ret;
167}
168
bda977b7
MCC		 169static int rtl2832_update_bits(struct i2c_client *client, unsigned int reg,
170 unsigned int mask, unsigned int val)
82041c0a 171{
d1016581 172 struct rtl2832_dev *dev = i2c_get_clientdata(client);
82041c0a 173 int ret;
82041c0a 174
d1016581
AP		 175 i2c_lock_adapter(client->adapter);
176 ret = regmap_update_bits(dev->regmap, reg, mask, val);
177 i2c_unlock_adapter(client->adapter);
298efdd3 178 return ret;
82041c0a
TM		 179}
180
bda977b7
MCC		 181static int rtl2832_bulk_read(struct i2c_client *client, unsigned int reg,
182 void *val, size_t val_count)
82041c0a 183{
d1016581 184 struct rtl2832_dev *dev = i2c_get_clientdata(client);
82041c0a
TM		 185 int ret;
186
d1016581
AP		 187 i2c_lock_adapter(client->adapter);
188 ret = regmap_bulk_read(dev->regmap, reg, val, val_count);
189 i2c_unlock_adapter(client->adapter);
190 return ret;
191}
82041c0a 192
038c6f24 193static int rtl2832_rd_demod_reg(struct rtl2832_dev *dev, int reg, u32 *val)
82041c0a 194{
6e6aac65 195 struct i2c_client *client = dev->client;
cd559e0b 196 int ret, i;
eec21beb 197 u16 reg_start_addr;
cd559e0b
AP		 198 u8 msb, lsb, reading[4], len;
199 u32 reading_tmp, mask;
82041c0a
TM		 200
201 reg_start_addr = registers[reg].start_address;
202 msb = registers[reg].msb;
203 lsb = registers[reg].lsb;
82041c0a 204 len = (msb >> 3) + 1;
298f18a3 205 mask = REG_MASK(msb - lsb);
82041c0a 206
eec21beb 207 ret = rtl2832_bulk_read(client, reg_start_addr, reading, len);
82041c0a
TM		 208 if (ret)
209 goto err;
210
211 reading_tmp = 0;
212 for (i = 0; i < len; i++)
213 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
214
215 *val = (reading_tmp >> lsb) & mask;
216
cd559e0b 217 return 0;
82041c0a 218err:
6e6aac65 219 dev_dbg(&client->dev, "failed=%d\n", ret);
82041c0a 220 return ret;
82041c0a
TM		 221}
222
038c6f24 223static int rtl2832_wr_demod_reg(struct rtl2832_dev *dev, int reg, u32 val)
82041c0a 224{
6e6aac65 225 struct i2c_client *client = dev->client;
82041c0a 226 int ret, i;
eec21beb 227 u16 reg_start_addr;
cd559e0b
AP		 228 u8 msb, lsb, reading[4], writing[4], len;
229 u32 reading_tmp, writing_tmp, mask;
82041c0a
TM		 230
231 reg_start_addr = registers[reg].start_address;
232 msb = registers[reg].msb;
233 lsb = registers[reg].lsb;
82041c0a 234 len = (msb >> 3) + 1;
298f18a3 235 mask = REG_MASK(msb - lsb);
82041c0a 236
eec21beb 237 ret = rtl2832_bulk_read(client, reg_start_addr, reading, len);
82041c0a
TM		 238 if (ret)
239 goto err;
240
241 reading_tmp = 0;
242 for (i = 0; i < len; i++)
243 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
244
245 writing_tmp = reading_tmp & ~(mask << lsb);
246 writing_tmp |= ((val & mask) << lsb);
247
82041c0a
TM		 248 for (i = 0; i < len; i++)
249 writing[i] = (writing_tmp >> ((len - 1 - i) * 8)) & 0xff;
250
eec21beb 251 ret = rtl2832_bulk_write(client, reg_start_addr, writing, len);
82041c0a
TM		 252 if (ret)
253 goto err;
254
cd559e0b 255 return 0;
82041c0a 256err:
6e6aac65 257 dev_dbg(&client->dev, "failed=%d\n", ret);
82041c0a 258 return ret;
82041c0a
TM		 259}
260
884655ad 261static int rtl2832_set_if(struct dvb_frontend *fe, u32 if_freq)
82041c0a 262{
038c6f24 263 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 264 struct i2c_client *client = dev->client;
884655ad 265 int ret;
82041c0a 266 u64 pset_iffreq;
884655ad
MCC		 267 u8 en_bbin = (if_freq == 0 ? 0x1 : 0x0);
268
269 /*
270 * PSET_IFFREQ = - floor((IfFreqHz % CrystalFreqHz) * pow(2, 22)
271 * / CrystalFreqHz)
272 */
e1174d78 273 pset_iffreq = if_freq % dev->pdata->clk;
884655ad 274 pset_iffreq *= 0x400000;
e1174d78 275 pset_iffreq = div_u64(pset_iffreq, dev->pdata->clk);
c8832e8f 276 pset_iffreq = -pset_iffreq;
884655ad 277 pset_iffreq = pset_iffreq & 0x3fffff;
6e6aac65
AP		 278 dev_dbg(&client->dev, "if_frequency=%d pset_iffreq=%08x\n",
279 if_freq, (unsigned)pset_iffreq);
c8832e8f 280
038c6f24 281 ret = rtl2832_wr_demod_reg(dev, DVBT_EN_BBIN, en_bbin);
884655ad 282 if (ret)
cd559e0b 283 goto err;
884655ad 284
038c6f24 285 ret = rtl2832_wr_demod_reg(dev, DVBT_PSET_IFFREQ, pset_iffreq);
cd559e0b
AP		 286 if (ret)
287 goto err;
884655ad 288
cd559e0b
AP		 289 return 0;
290err:
291 dev_dbg(&client->dev, "failed=%d\n", ret);
3ca2418d 292 return ret;
884655ad
MCC		 293}
294
295static int rtl2832_init(struct dvb_frontend *fe)
296{
038c6f24 297 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 298 struct i2c_client *client = dev->client;
19d273d6 299 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
832cc7cd 300 const struct rtl2832_reg_value *init;
884655ad 301 int i, ret, len;
82041c0a
TM		 302 /* initialization values for the demodulator registers */
303 struct rtl2832_reg_value rtl2832_initial_regs[] = {
304 {DVBT_AD_EN_REG, 0x1},
305 {DVBT_AD_EN_REG1, 0x1},
306 {DVBT_RSD_BER_FAIL_VAL, 0x2800},
307 {DVBT_MGD_THD0, 0x10},
308 {DVBT_MGD_THD1, 0x20},
309 {DVBT_MGD_THD2, 0x20},
310 {DVBT_MGD_THD3, 0x40},
311 {DVBT_MGD_THD4, 0x22},
312 {DVBT_MGD_THD5, 0x32},
313 {DVBT_MGD_THD6, 0x37},
314 {DVBT_MGD_THD7, 0x39},
315 {DVBT_EN_BK_TRK, 0x0},
316 {DVBT_EN_CACQ_NOTCH, 0x0},
317 {DVBT_AD_AV_REF, 0x2a},
318 {DVBT_REG_PI, 0x6},
319 {DVBT_PIP_ON, 0x0},
320 {DVBT_CDIV_PH0, 0x8},
321 {DVBT_CDIV_PH1, 0x8},
322 {DVBT_SCALE1_B92, 0x4},
323 {DVBT_SCALE1_B93, 0xb0},
324 {DVBT_SCALE1_BA7, 0x78},
325 {DVBT_SCALE1_BA9, 0x28},
326 {DVBT_SCALE1_BAA, 0x59},
327 {DVBT_SCALE1_BAB, 0x83},
328 {DVBT_SCALE1_BAC, 0xd4},
329 {DVBT_SCALE1_BB0, 0x65},
330 {DVBT_SCALE1_BB1, 0x43},
331 {DVBT_KB_P1, 0x1},
332 {DVBT_KB_P2, 0x4},
333 {DVBT_KB_P3, 0x7},
334 {DVBT_K1_CR_STEP12, 0xa},
335 {DVBT_REG_GPE, 0x1},
336 {DVBT_SERIAL, 0x0},
337 {DVBT_CDIV_PH0, 0x9},
338 {DVBT_CDIV_PH1, 0x9},
339 {DVBT_MPEG_IO_OPT_2_2, 0x0},
340 {DVBT_MPEG_IO_OPT_1_0, 0x0},
341 {DVBT_TRK_KS_P2, 0x4},
342 {DVBT_TRK_KS_I2, 0x7},
343 {DVBT_TR_THD_SET2, 0x6},
344 {DVBT_TRK_KC_I2, 0x5},
345 {DVBT_CR_THD_SET2, 0x1},
82041c0a
TM		 346 };
347
6e6aac65 348 dev_dbg(&client->dev, "\n");
82041c0a 349
82041c0a 350 for (i = 0; i < ARRAY_SIZE(rtl2832_initial_regs); i++) {
038c6f24 351 ret = rtl2832_wr_demod_reg(dev, rtl2832_initial_regs[i].reg,
82041c0a
TM		 352 rtl2832_initial_regs[i].value);
353 if (ret)
354 goto err;
355 }
356
832cc7cd 357 /* load tuner specific settings */
e1174d78
AP		 358 dev_dbg(&client->dev, "load settings for tuner=%02x\n",
359 dev->pdata->tuner);
360 switch (dev->pdata->tuner) {
832cc7cd
AP		 361 case RTL2832_TUNER_FC0012:
362 case RTL2832_TUNER_FC0013:
363 len = ARRAY_SIZE(rtl2832_tuner_init_fc0012);
364 init = rtl2832_tuner_init_fc0012;
365 break;
5db4187a
AP		 366 case RTL2832_TUNER_TUA9001:
367 len = ARRAY_SIZE(rtl2832_tuner_init_tua9001);
368 init = rtl2832_tuner_init_tua9001;
369 break;
7e688de0
AP		 370 case RTL2832_TUNER_E4000:
371 len = ARRAY_SIZE(rtl2832_tuner_init_e4000);
372 init = rtl2832_tuner_init_e4000;
373 break;
fa4bfd2b 374 case RTL2832_TUNER_R820T:
a26758ed 375 case RTL2832_TUNER_R828D:
fa4bfd2b
MCC		 376 len = ARRAY_SIZE(rtl2832_tuner_init_r820t);
377 init = rtl2832_tuner_init_r820t;
378 break;
832cc7cd
AP		 379 default:
380 ret = -EINVAL;
381 goto err;
382 }
383
384 for (i = 0; i < len; i++) {
038c6f24 385 ret = rtl2832_wr_demod_reg(dev, init[i].reg, init[i].value);
832cc7cd
AP		 386 if (ret)
387 goto err;
388 }
389
19d273d6 390 /* init stats here in order signal app which stats are supported */
25ef9f55
AP		 391 c->strength.len = 1;
392 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
19d273d6
AP		 393 c->cnr.len = 1;
394 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6b4fd018
AP		 395 c->post_bit_error.len = 1;
396 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
397 c->post_bit_count.len = 1;
398 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
19d273d6
AP		 399 /* start statistics polling */
400 schedule_delayed_work(&dev->stat_work, msecs_to_jiffies(2000));
038c6f24 401 dev->sleeping = false;
82041c0a 402
cd559e0b 403 return 0;
82041c0a 404err:
6e6aac65 405 dev_dbg(&client->dev, "failed=%d\n", ret);
82041c0a
TM		 406 return ret;
407}
408
409static int rtl2832_sleep(struct dvb_frontend *fe)
410{
038c6f24 411 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 412 struct i2c_client *client = dev->client;
a08c3781 413 int ret;
82041c0a 414
6e6aac65 415 dev_dbg(&client->dev, "\n");
a08c3781 416
038c6f24 417 dev->sleeping = true;
19d273d6
AP		 418 /* stop statistics polling */
419 cancel_delayed_work_sync(&dev->stat_work);
420 dev->fe_status = 0;
a08c3781
AP		 421
422 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
423 if (ret)
424 goto err;
425
82041c0a 426 return 0;
a08c3781
AP		 427err:
428 dev_dbg(&client->dev, "failed=%d\n", ret);
429 return ret;
82041c0a
TM		 430}
431
b0944ea2 432static int rtl2832_get_tune_settings(struct dvb_frontend *fe,
82041c0a
TM		 433 struct dvb_frontend_tune_settings *s)
434{
038c6f24 435 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 436 struct i2c_client *client = dev->client;
298efdd3 437
6e6aac65 438 dev_dbg(&client->dev, "\n");
82041c0a
TM		 439 s->min_delay_ms = 1000;
440 s->step_size = fe->ops.info.frequency_stepsize * 2;
441 s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
442 return 0;
443}
444
445static int rtl2832_set_frontend(struct dvb_frontend *fe)
446{
038c6f24 447 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 448 struct i2c_client *client = dev->client;
82041c0a
TM		 449 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
450 int ret, i, j;
451 u64 bw_mode, num, num2;
452 u32 resamp_ratio, cfreq_off_ratio;
82041c0a
TM		 453 static u8 bw_params[3][32] = {
454 /* 6 MHz bandwidth */
455 {
456 0xf5, 0xff, 0x15, 0x38, 0x5d, 0x6d, 0x52, 0x07, 0xfa, 0x2f,
457 0x53, 0xf5, 0x3f, 0xca, 0x0b, 0x91, 0xea, 0x30, 0x63, 0xb2,
458 0x13, 0xda, 0x0b, 0xc4, 0x18, 0x7e, 0x16, 0x66, 0x08, 0x67,
459 0x19, 0xe0,
460 },
461
462 /* 7 MHz bandwidth */
463 {
464 0xe7, 0xcc, 0xb5, 0xba, 0xe8, 0x2f, 0x67, 0x61, 0x00, 0xaf,
465 0x86, 0xf2, 0xbf, 0x59, 0x04, 0x11, 0xb6, 0x33, 0xa4, 0x30,
466 0x15, 0x10, 0x0a, 0x42, 0x18, 0xf8, 0x17, 0xd9, 0x07, 0x22,
467 0x19, 0x10,
468 },
469
470 /* 8 MHz bandwidth */
471 {
472 0x09, 0xf6, 0xd2, 0xa7, 0x9a, 0xc9, 0x27, 0x77, 0x06, 0xbf,
473 0xec, 0xf4, 0x4f, 0x0b, 0xfc, 0x01, 0x63, 0x35, 0x54, 0xa7,
474 0x16, 0x66, 0x08, 0xb4, 0x19, 0x6e, 0x19, 0x65, 0x05, 0xc8,
475 0x19, 0xe0,
476 },
477 };
478
6e6aac65
AP		 479 dev_dbg(&client->dev, "frequency=%u bandwidth_hz=%u inversion=%u\n",
480 c->frequency, c->bandwidth_hz, c->inversion);
82041c0a
TM		 481
482 /* program tuner */
483 if (fe->ops.tuner_ops.set_params)
484 fe->ops.tuner_ops.set_params(fe);
485
fe37b38b 486 /* PIP mode related */
eec21beb 487 ret = rtl2832_bulk_write(client, 0x192, "\x00\x0f\xff", 3);
fe37b38b
AP		 488 if (ret)
489 goto err;
490
fa4bfd2b
MCC		 491 /* If the frontend has get_if_frequency(), use it */
492 if (fe->ops.tuner_ops.get_if_frequency) {
493 u32 if_freq;
fa4bfd2b
MCC		 494
495 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
496 if (ret)
497 goto err;
498
884655ad 499 ret = rtl2832_set_if(fe, if_freq);
fa4bfd2b
MCC		 500 if (ret)
501 goto err;
502 }
503
82041c0a
TM		 504 switch (c->bandwidth_hz) {
505 case 6000000:
506 i = 0;
507 bw_mode = 48000000;
508 break;
509 case 7000000:
510 i = 1;
511 bw_mode = 56000000;
512 break;
513 case 8000000:
514 i = 2;
515 bw_mode = 64000000;
516 break;
517 default:
6e6aac65
AP		 518 dev_err(&client->dev, "invalid bandwidth_hz %u\n",
519 c->bandwidth_hz);
520 ret = -EINVAL;
521 goto err;
82041c0a
TM		 522 }
523
fc4b3fa7 524 for (j = 0; j < sizeof(bw_params[0]); j++) {
eec21beb 525 ret = rtl2832_bulk_write(client, 0x11c + j, &bw_params[i][j], 1);
82041c0a
TM		 526 if (ret)
527 goto err;
528 }
529
530 /* calculate and set resample ratio
531 * RSAMP_RATIO = floor(CrystalFreqHz * 7 * pow(2, 22)
532 * / ConstWithBandwidthMode)
533 */
e1174d78 534 num = dev->pdata->clk * 7;
82041c0a
TM		 535 num *= 0x400000;
536 num = div_u64(num, bw_mode);
537 resamp_ratio = num & 0x3ffffff;
038c6f24 538 ret = rtl2832_wr_demod_reg(dev, DVBT_RSAMP_RATIO, resamp_ratio);
82041c0a
TM		 539 if (ret)
540 goto err;
541
542 /* calculate and set cfreq off ratio
543 * CFREQ_OFF_RATIO = - floor(ConstWithBandwidthMode * pow(2, 20)
544 * / (CrystalFreqHz * 7))
545 */
546 num = bw_mode << 20;
e1174d78 547 num2 = dev->pdata->clk * 7;
82041c0a
TM		 548 num = div_u64(num, num2);
549 num = -num;
550 cfreq_off_ratio = num & 0xfffff;
038c6f24 551 ret = rtl2832_wr_demod_reg(dev, DVBT_CFREQ_OFF_RATIO, cfreq_off_ratio);
82041c0a
TM		 552 if (ret)
553 goto err;
554
82041c0a 555 /* soft reset */
038c6f24 556 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
82041c0a
TM		 557 if (ret)
558 goto err;
559
038c6f24 560 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
82041c0a
TM		 561 if (ret)
562 goto err;
563
cd559e0b 564 return 0;
82041c0a 565err:
6e6aac65 566 dev_dbg(&client->dev, "failed=%d\n", ret);
82041c0a
TM		 567 return ret;
568}
569
0ce67a2a
AP		 570static int rtl2832_get_frontend(struct dvb_frontend *fe)
571{
038c6f24 572 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 573 struct i2c_client *client = dev->client;
0ce67a2a
AP		 574 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
575 int ret;
576 u8 buf[3];
577
038c6f24 578 if (dev->sleeping)
0ce67a2a
AP		 579 return 0;
580
eec21beb 581 ret = rtl2832_bulk_read(client, 0x33c, buf, 2);
0ce67a2a
AP		 582 if (ret)
583 goto err;
584
eec21beb 585 ret = rtl2832_bulk_read(client, 0x351, &buf[2], 1);
0ce67a2a
AP		 586 if (ret)
587 goto err;
588
6e6aac65 589 dev_dbg(&client->dev, "TPS=%*ph\n", 3, buf);
0ce67a2a
AP		 590
591 switch ((buf[0] >> 2) & 3) {
592 case 0:
593 c->modulation = QPSK;
594 break;
595 case 1:
596 c->modulation = QAM_16;
597 break;
598 case 2:
599 c->modulation = QAM_64;
600 break;
601 }
602
603 switch ((buf[2] >> 2) & 1) {
604 case 0:
605 c->transmission_mode = TRANSMISSION_MODE_2K;
606 break;
607 case 1:
608 c->transmission_mode = TRANSMISSION_MODE_8K;
609 }
610
611 switch ((buf[2] >> 0) & 3) {
612 case 0:
613 c->guard_interval = GUARD_INTERVAL_1_32;
614 break;
615 case 1:
616 c->guard_interval = GUARD_INTERVAL_1_16;
617 break;
618 case 2:
619 c->guard_interval = GUARD_INTERVAL_1_8;
620 break;
621 case 3:
622 c->guard_interval = GUARD_INTERVAL_1_4;
623 break;
624 }
625
626 switch ((buf[0] >> 4) & 7) {
627 case 0:
628 c->hierarchy = HIERARCHY_NONE;
629 break;
630 case 1:
631 c->hierarchy = HIERARCHY_1;
632 break;
633 case 2:
634 c->hierarchy = HIERARCHY_2;
635 break;
636 case 3:
637 c->hierarchy = HIERARCHY_4;
638 break;
639 }
640
641 switch ((buf[1] >> 3) & 7) {
642 case 0:
643 c->code_rate_HP = FEC_1_2;
644 break;
645 case 1:
646 c->code_rate_HP = FEC_2_3;
647 break;
648 case 2:
649 c->code_rate_HP = FEC_3_4;
650 break;
651 case 3:
652 c->code_rate_HP = FEC_5_6;
653 break;
654 case 4:
655 c->code_rate_HP = FEC_7_8;
656 break;
657 }
658
659 switch ((buf[1] >> 0) & 7) {
660 case 0:
661 c->code_rate_LP = FEC_1_2;
662 break;
663 case 1:
664 c->code_rate_LP = FEC_2_3;
665 break;
666 case 2:
667 c->code_rate_LP = FEC_3_4;
668 break;
669 case 3:
670 c->code_rate_LP = FEC_5_6;
671 break;
672 case 4:
673 c->code_rate_LP = FEC_7_8;
674 break;
675 }
676
677 return 0;
678err:
6e6aac65 679 dev_dbg(&client->dev, "failed=%d\n", ret);
0ce67a2a
AP		 680 return ret;
681}
682
82041c0a
TM		 683static int rtl2832_read_status(struct dvb_frontend *fe, fe_status_t *status)
684{
038c6f24 685 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 686 struct i2c_client *client = dev->client;
82041c0a
TM		 687 int ret;
688 u32 tmp;
82041c0a 689
6e6aac65
AP		 690 dev_dbg(&client->dev, "\n");
691
692 *status = 0;
038c6f24 693 if (dev->sleeping)
82041c0a
TM		 694 return 0;
695
038c6f24 696 ret = rtl2832_rd_demod_reg(dev, DVBT_FSM_STAGE, &tmp);
82041c0a
TM		 697 if (ret)
698 goto err;
699
700 if (tmp == 11) {
701 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
702 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
1c7da405 703 } else if (tmp == 10) {
82041c0a
TM		 704 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
705 FE_HAS_VITERBI;
1c7da405 706 }
82041c0a 707
19d273d6 708 dev->fe_status = *status;
cd559e0b 709 return 0;
82041c0a 710err:
6e6aac65 711 dev_dbg(&client->dev, "failed=%d\n", ret);
82041c0a
TM		 712 return ret;
713}
714
73983497
AP		 715static int rtl2832_read_snr(struct dvb_frontend *fe, u16 *snr)
716{
f7caf93f 717 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
73983497 718
f7caf93f
AP		 719 /* report SNR in resolution of 0.1 dB */
720 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
721 *snr = div_s64(c->cnr.stat[0].svalue, 100);
73983497
AP		 722 else
723 *snr = 0;
724
725 return 0;
73983497
AP		 726}
727
db32d74a
AP		 728static int rtl2832_read_ber(struct dvb_frontend *fe, u32 *ber)
729{
038c6f24 730 struct rtl2832_dev *dev = fe->demodulator_priv;
db32d74a 731
084330b7
AP		 732 *ber = (dev->post_bit_error - dev->post_bit_error_prev);
733 dev->post_bit_error_prev = dev->post_bit_error;
db32d74a
AP		 734
735 return 0;
db32d74a
AP		 736}
737
19d273d6
AP		 738static void rtl2832_stat_work(struct work_struct *work)
739{
740 struct rtl2832_dev *dev = container_of(work, struct rtl2832_dev, stat_work.work);
741 struct i2c_client *client = dev->client;
742 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
743 int ret, tmp;
744 u8 u8tmp, buf[2];
745 u16 u16tmp;
746
747 dev_dbg(&client->dev, "\n");
748
25ef9f55
AP		 749 /* signal strength */
750 if (dev->fe_status & FE_HAS_SIGNAL) {
751 /* read digital AGC */
752 ret = rtl2832_bulk_read(client, 0x305, &u8tmp, 1);
753 if (ret)
754 goto err;
755
756 dev_dbg(&client->dev, "digital agc=%02x", u8tmp);
757
758 u8tmp = ~u8tmp;
759 u16tmp = u8tmp << 8 | u8tmp << 0;
760
761 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
762 c->strength.stat[0].uvalue = u16tmp;
763 } else {
764 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
765 }
766
19d273d6
AP		 767 /* CNR */
768 if (dev->fe_status & FE_HAS_VITERBI) {
769 unsigned hierarchy, constellation;
770 #define CONSTELLATION_NUM 3
771 #define HIERARCHY_NUM 4
772 static const u32 constant[CONSTELLATION_NUM][HIERARCHY_NUM] = {
773 {85387325, 85387325, 85387325, 85387325},
774 {86676178, 86676178, 87167949, 87795660},
775 {87659938, 87659938, 87885178, 88241743},
776 };
777
778 ret = rtl2832_bulk_read(client, 0x33c, &u8tmp, 1);
779 if (ret)
780 goto err;
781
782 constellation = (u8tmp >> 2) & 0x03; /* [3:2] */
783 if (constellation > CONSTELLATION_NUM - 1)
784 goto err_schedule_delayed_work;
785
786 hierarchy = (u8tmp >> 4) & 0x07; /* [6:4] */
787 if (hierarchy > HIERARCHY_NUM - 1)
788 goto err_schedule_delayed_work;
789
790 ret = rtl2832_bulk_read(client, 0x40c, buf, 2);
791 if (ret)
792 goto err;
793
794 u16tmp = buf[0] << 8 | buf[1] << 0;
795 if (u16tmp)
796 tmp = (constant[constellation][hierarchy] -
797 intlog10(u16tmp)) / ((1 << 24) / 10000);
798 else
799 tmp = 0;
800
801 dev_dbg(&client->dev, "cnr raw=%u\n", u16tmp);
802
803 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
804 c->cnr.stat[0].svalue = tmp;
805 } else {
806 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
807 }
808
6b4fd018
AP		 809 /* BER */
810 if (dev->fe_status & FE_HAS_LOCK) {
811 ret = rtl2832_bulk_read(client, 0x34e, buf, 2);
812 if (ret)
813 goto err;
814
815 u16tmp = buf[0] << 8 | buf[1] << 0;
816 dev->post_bit_error += u16tmp;
817 dev->post_bit_count += 1000000;
818
819 dev_dbg(&client->dev, "ber errors=%u total=1000000\n", u16tmp);
820
821 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
822 c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
823 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
824 c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
825 } else {
826 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
827 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
828 }
829
19d273d6
AP		 830err_schedule_delayed_work:
831 schedule_delayed_work(&dev->stat_work, msecs_to_jiffies(2000));
832 return;
833err:
834 dev_dbg(&client->dev, "failed=%d\n", ret);
835}
836
92d20d9f 837/*
d1016581
AP		 838 * I2C gate/mux/repeater logic
839 * We must use unlocked __i2c_transfer() here (through regmap) because of I2C
840 * adapter lock is already taken by tuner driver.
841 * There is delay mechanism to avoid unneeded I2C gate open / close. Gate close
842 * is delayed here a little bit in order to see if there is sequence of I2C
92d20d9f 843 * messages sent to same I2C bus.
92d20d9f
AP		 844 */
845static void rtl2832_i2c_gate_work(struct work_struct *work)
846{
d1016581 847 struct rtl2832_dev *dev = container_of(work, struct rtl2832_dev, i2c_gate_work.work);
6e6aac65 848 struct i2c_client *client = dev->client;
92d20d9f 849 int ret;
6e6aac65 850
d1016581
AP		 851 /* close gate */
852 ret = rtl2832_update_bits(dev->client, 0x101, 0x08, 0x00);
853 if (ret)
92d20d9f
AP		 854 goto err;
855
92d20d9f
AP		 856 return;
857err:
6e6aac65 858 dev_dbg(&client->dev, "failed=%d\n", ret);
92d20d9f
AP		 859}
860
0ea872d4 861static int rtl2832_select(struct i2c_adapter *adap, void *mux_priv, u32 chan_id)
8823f028 862{
038c6f24 863 struct rtl2832_dev *dev = mux_priv;
6e6aac65 864 struct i2c_client *client = dev->client;
0ea872d4 865 int ret;
92d20d9f
AP		 866
867 /* terminate possible gate closing */
d1016581 868 cancel_delayed_work(&dev->i2c_gate_work);
8823f028 869
d1016581 870 /*
d1016581
AP		 871 * I2C adapter lock is already taken and due to that we will use
872 * regmap_update_bits() which does not lock again I2C adapter.
873 */
0d117901 874 ret = regmap_update_bits(dev->regmap, 0x101, 0x08, 0x08);
d1016581 875 if (ret)
0ea872d4
AP		 876 goto err;
877
0ea872d4
AP		 878 return 0;
879err:
6e6aac65 880 dev_dbg(&client->dev, "failed=%d\n", ret);
d1016581 881 return ret;
8823f028
AP		 882}
883
92d20d9f 884static int rtl2832_deselect(struct i2c_adapter *adap, void *mux_priv,
d1016581 885 u32 chan_id)
92d20d9f 886{
038c6f24 887 struct rtl2832_dev *dev = mux_priv;
6e6aac65 888
038c6f24 889 schedule_delayed_work(&dev->i2c_gate_work, usecs_to_jiffies(100));
92d20d9f
AP		 890 return 0;
891}
892
82041c0a
TM		 893static struct dvb_frontend_ops rtl2832_ops = {
894 .delsys = { SYS_DVBT },
895 .info = {
896 .name = "Realtek RTL2832 (DVB-T)",
897 .frequency_min = 174000000,
898 .frequency_max = 862000000,
899 .frequency_stepsize = 166667,
900 .caps = FE_CAN_FEC_1_2 |
901 FE_CAN_FEC_2_3 |
902 FE_CAN_FEC_3_4 |
903 FE_CAN_FEC_5_6 |
904 FE_CAN_FEC_7_8 |
905 FE_CAN_FEC_AUTO |
906 FE_CAN_QPSK |
907 FE_CAN_QAM_16 |
908 FE_CAN_QAM_64 |
909 FE_CAN_QAM_AUTO |
910 FE_CAN_TRANSMISSION_MODE_AUTO |
911 FE_CAN_GUARD_INTERVAL_AUTO |
912 FE_CAN_HIERARCHY_AUTO |
913 FE_CAN_RECOVER |
914 FE_CAN_MUTE_TS
915 },
916
82041c0a
TM		 917 .init = rtl2832_init,
918 .sleep = rtl2832_sleep,
919
920 .get_tune_settings = rtl2832_get_tune_settings,
921
922 .set_frontend = rtl2832_set_frontend,
0ce67a2a 923 .get_frontend = rtl2832_get_frontend,
82041c0a
TM		 924
925 .read_status = rtl2832_read_status,
73983497 926 .read_snr = rtl2832_read_snr,
db32d74a 927 .read_ber = rtl2832_read_ber,
82041c0a
TM		 928};
929
dcadb82a
AP		 930static bool rtl2832_volatile_reg(struct device *dev, unsigned int reg)
931{
932 switch (reg) {
933 case 0x305:
934 case 0x33c:
935 case 0x34e:
936 case 0x351:
937 case 0x40c ... 0x40d:
938 return true;
939 default:
940 break;
941 }
942
943 return false;
944}
945
d1016581
AP		 946/*
947 * We implement own I2C access routines for regmap in order to get manual access
948 * to I2C adapter lock, which is needed for I2C mux adapter.
949 */
950static int rtl2832_regmap_read(void *context, const void *reg_buf,
951 size_t reg_size, void *val_buf, size_t val_size)
952{
953 struct i2c_client *client = context;
954 int ret;
955 struct i2c_msg msg[2] = {
956 {
957 .addr = client->addr,
958 .flags = 0,
959 .len = reg_size,
960 .buf = (u8 *)reg_buf,
961 }, {
962 .addr = client->addr,
963 .flags = I2C_M_RD,
964 .len = val_size,
965 .buf = val_buf,
966 }
967 };
968
969 ret = __i2c_transfer(client->adapter, msg, 2);
970 if (ret != 2) {
971 dev_warn(&client->dev, "i2c reg read failed %d\n", ret);
972 if (ret >= 0)
973 ret = -EREMOTEIO;
974 return ret;
975 }
976 return 0;
977}
978
979static int rtl2832_regmap_write(void *context, const void *data, size_t count)
980{
981 struct i2c_client *client = context;
982 int ret;
983 struct i2c_msg msg[1] = {
984 {
985 .addr = client->addr,
986 .flags = 0,
987 .len = count,
988 .buf = (u8 *)data,
989 }
990 };
991
992 ret = __i2c_transfer(client->adapter, msg, 1);
993 if (ret != 1) {
994 dev_warn(&client->dev, "i2c reg write failed %d\n", ret);
995 if (ret >= 0)
996 ret = -EREMOTEIO;
997 return ret;
998 }
999 return 0;
1000}
1001
1002static int rtl2832_regmap_gather_write(void *context, const void *reg,
1003 size_t reg_len, const void *val,
1004 size_t val_len)
1005{
1006 struct i2c_client *client = context;
1007 int ret;
1008 u8 buf[256];
1009 struct i2c_msg msg[1] = {
1010 {
1011 .addr = client->addr,
1012 .flags = 0,
1013 .len = 1 + val_len,
1014 .buf = buf,
1015 }
1016 };
1017
1018 buf[0] = *(u8 const *)reg;
1019 memcpy(&buf[1], val, val_len);
1020
1021 ret = __i2c_transfer(client->adapter, msg, 1);
1022 if (ret != 1) {
1023 dev_warn(&client->dev, "i2c reg write failed %d\n", ret);
1024 if (ret >= 0)
1025 ret = -EREMOTEIO;
1026 return ret;
1027 }
1028 return 0;
1029}
1030
b410dae4
AP		 1031/*
1032 * FIXME: Hack. Implement own regmap locking in order to silence lockdep
1033 * recursive lock warning. That happens when regmap I2C client calls I2C mux
1034 * adapter, which leads demod I2C repeater enable via demod regmap. Operation
1035 * takes two regmap locks recursively - but those are different regmap instances
1036 * in a two different I2C drivers, so it is not deadlock. Proper fix is to make
1037 * regmap aware of lockdep.
1038 */
1039static void rtl2832_regmap_lock(void *__dev)
1040{
1041 struct rtl2832_dev *dev = __dev;
1042 struct i2c_client *client = dev->client;
1043
1044 dev_dbg(&client->dev, "\n");
1045 mutex_lock(&dev->regmap_mutex);
1046}
1047
1048static void rtl2832_regmap_unlock(void *__dev)
1049{
1050 struct rtl2832_dev *dev = __dev;
1051 struct i2c_client *client = dev->client;
1052
1053 dev_dbg(&client->dev, "\n");
1054 mutex_unlock(&dev->regmap_mutex);
1055}
1056
6f5f6ee2
AP		 1057static struct dvb_frontend *rtl2832_get_dvb_frontend(struct i2c_client *client)
1058{
038c6f24 1059 struct rtl2832_dev *dev = i2c_get_clientdata(client);
6f5f6ee2
AP		 1060
1061 dev_dbg(&client->dev, "\n");
1062 return &dev->fe;
1063}
1064
cd559e0b 1065static struct i2c_adapter *rtl2832_get_i2c_adapter(struct i2c_client *client)
6f5f6ee2 1066{
038c6f24 1067 struct rtl2832_dev *dev = i2c_get_clientdata(client);
6f5f6ee2
AP		 1068
1069 dev_dbg(&client->dev, "\n");
1070 return dev->i2c_adapter_tuner;
1071}
1072
6f5f6ee2
AP		 1073static int rtl2832_enable_slave_ts(struct i2c_client *client)
1074{
038c6f24 1075 struct rtl2832_dev *dev = i2c_get_clientdata(client);
6f5f6ee2
AP		 1076 int ret;
1077
6e6aac65 1078 dev_dbg(&client->dev, "\n");
6f5f6ee2 1079
eec21beb 1080 ret = rtl2832_bulk_write(client, 0x10c, "\x5f\xff", 2);
6f5f6ee2
AP		 1081 if (ret)
1082 goto err;
1083
1084 ret = rtl2832_wr_demod_reg(dev, DVBT_PIP_ON, 0x1);
1085 if (ret)
1086 goto err;
1087
eec21beb 1088 ret = rtl2832_bulk_write(client, 0x0bc, "\x18", 1);
6f5f6ee2
AP		 1089 if (ret)
1090 goto err;
1091
eec21beb 1092 ret = rtl2832_bulk_write(client, 0x022, "\x01", 1);
6f5f6ee2
AP		 1093 if (ret)
1094 goto err;
1095
eec21beb 1096 ret = rtl2832_bulk_write(client, 0x026, "\x1f", 1);
6f5f6ee2
AP		 1097 if (ret)
1098 goto err;
1099
eec21beb 1100 ret = rtl2832_bulk_write(client, 0x027, "\xff", 1);
6f5f6ee2
AP		 1101 if (ret)
1102 goto err;
1103
eec21beb 1104 ret = rtl2832_bulk_write(client, 0x192, "\x7f\xf7\xff", 3);
6f5f6ee2
AP		 1105 if (ret)
1106 goto err;
1107
1108 /* soft reset */
1109 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
1110 if (ret)
1111 goto err;
1112
1113 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
1114 if (ret)
1115 goto err;
1116
1117 return 0;
1118err:
1119 dev_dbg(&client->dev, "failed=%d\n", ret);
1120 return ret;
1121}
1122
4b01e01a
AP		 1123static int rtl2832_pid_filter_ctrl(struct dvb_frontend *fe, int onoff)
1124{
1125 struct rtl2832_dev *dev = fe->demodulator_priv;
1126 struct i2c_client *client = dev->client;
1127 int ret;
1128 u8 u8tmp;
1129
1130 dev_dbg(&client->dev, "onoff=%d\n", onoff);
1131
1132 /* enable / disable PID filter */
1133 if (onoff)
1134 u8tmp = 0x80;
1135 else
1136 u8tmp = 0x00;
1137
1138 ret = rtl2832_update_bits(client, 0x061, 0xc0, u8tmp);
1139 if (ret)
1140 goto err;
1141
1142 return 0;
1143err:
1144 dev_dbg(&client->dev, "failed=%d\n", ret);
1145 return ret;
1146}
1147
1148static int rtl2832_pid_filter(struct dvb_frontend *fe, u8 index, u16 pid,
1149 int onoff)
1150{
1151 struct rtl2832_dev *dev = fe->demodulator_priv;
1152 struct i2c_client *client = dev->client;
1153 int ret;
1154 u8 buf[4];
1155
1156 dev_dbg(&client->dev, "index=%d pid=%04x onoff=%d\n",
1157 index, pid, onoff);
1158
1159 /* skip invalid PIDs (0x2000) */
1160 if (pid > 0x1fff || index > 32)
1161 return 0;
1162
1163 if (onoff)
1164 set_bit(index, &dev->filters);
1165 else
1166 clear_bit(index, &dev->filters);
1167
1168 /* enable / disable PIDs */
1169 buf[0] = (dev->filters >> 0) & 0xff;
1170 buf[1] = (dev->filters >> 8) & 0xff;
1171 buf[2] = (dev->filters >> 16) & 0xff;
1172 buf[3] = (dev->filters >> 24) & 0xff;
1173 ret = rtl2832_bulk_write(client, 0x062, buf, 4);
1174 if (ret)
1175 goto err;
1176
1177 /* add PID */
1178 buf[0] = (pid >> 8) & 0xff;
1179 buf[1] = (pid >> 0) & 0xff;
1180 ret = rtl2832_bulk_write(client, 0x066 + 2 * index, buf, 2);
1181 if (ret)
1182 goto err;
1183
1184 return 0;
1185err:
1186 dev_dbg(&client->dev, "failed=%d\n", ret);
1187 return ret;
1188}
1189
c2c8386f
AP		 1190static int rtl2832_probe(struct i2c_client *client,
1191 const struct i2c_device_id *id)
1192{
1193 struct rtl2832_platform_data *pdata = client->dev.platform_data;
c2c8386f 1194 struct i2c_adapter *i2c = client->adapter;
038c6f24 1195 struct rtl2832_dev *dev;
c2c8386f
AP		 1196 int ret;
1197 u8 tmp;
d1016581
AP		 1198 static const struct regmap_bus regmap_bus = {
1199 .read = rtl2832_regmap_read,
1200 .write = rtl2832_regmap_write,
1201 .gather_write = rtl2832_regmap_gather_write,
1202 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
1203 };
1204 static const struct regmap_range_cfg regmap_range_cfg[] = {
1205 {
1206 .selector_reg = 0x00,
1207 .selector_mask = 0xff,
1208 .selector_shift = 0,
1209 .window_start = 0,
1210 .window_len = 0x100,
1211 .range_min = 0 * 0x100,
1212 .range_max = 5 * 0x100,
1213 },
1214 };
c2c8386f
AP		 1215
1216 dev_dbg(&client->dev, "\n");
1217
c2c8386f 1218 /* allocate memory for the internal state */
038c6f24
AP		 1219 dev = kzalloc(sizeof(struct rtl2832_dev), GFP_KERNEL);
1220 if (dev == NULL) {
c2c8386f
AP		 1221 ret = -ENOMEM;
1222 goto err;
1223 }
1224
038c6f24 1225 /* setup the state */
d1016581 1226 i2c_set_clientdata(client, dev);
038c6f24 1227 dev->client = client;
e1174d78 1228 dev->pdata = client->dev.platform_data;
038c6f24 1229 dev->sleeping = true;
038c6f24 1230 INIT_DELAYED_WORK(&dev->i2c_gate_work, rtl2832_i2c_gate_work);
19d273d6 1231 INIT_DELAYED_WORK(&dev->stat_work, rtl2832_stat_work);
d1016581 1232 /* create regmap */
b410dae4
AP		 1233 mutex_init(&dev->regmap_mutex);
1234 dev->regmap_config.reg_bits = 8,
1235 dev->regmap_config.val_bits = 8,
1236 dev->regmap_config.lock = rtl2832_regmap_lock,
1237 dev->regmap_config.unlock = rtl2832_regmap_unlock,
1238 dev->regmap_config.lock_arg = dev,
1239 dev->regmap_config.volatile_reg = rtl2832_volatile_reg,
1240 dev->regmap_config.max_register = 5 * 0x100,
1241 dev->regmap_config.ranges = regmap_range_cfg,
1242 dev->regmap_config.num_ranges = ARRAY_SIZE(regmap_range_cfg),
1243 dev->regmap_config.cache_type = REGCACHE_RBTREE,
d1016581 1244 dev->regmap = regmap_init(&client->dev, &regmap_bus, client,
b410dae4 1245 &dev->regmap_config);
d1016581
AP		 1246 if (IS_ERR(dev->regmap)) {
1247 ret = PTR_ERR(dev->regmap);
1248 goto err_kfree;
1249 }
c2c8386f
AP		 1250
1251 /* check if the demod is there */
eec21beb 1252 ret = rtl2832_bulk_read(client, 0x000, &tmp, 1);
c2c8386f 1253 if (ret)
0d117901 1254 goto err_regmap_exit;
c2c8386f
AP		 1255
1256 /* create muxed i2c adapter for demod tuner bus */
038c6f24 1257 dev->i2c_adapter_tuner = i2c_add_mux_adapter(i2c, &i2c->dev, dev,
0d117901 1258 0, 0, 0, rtl2832_select, rtl2832_deselect);
038c6f24 1259 if (dev->i2c_adapter_tuner == NULL) {
c2c8386f 1260 ret = -ENODEV;
0d117901 1261 goto err_regmap_exit;
c2c8386f
AP		 1262 }
1263
1264 /* create dvb_frontend */
038c6f24
AP		 1265 memcpy(&dev->fe.ops, &rtl2832_ops, sizeof(struct dvb_frontend_ops));
1266 dev->fe.demodulator_priv = dev;
6f5f6ee2
AP		 1267
1268 /* setup callbacks */
1269 pdata->get_dvb_frontend = rtl2832_get_dvb_frontend;
cd559e0b 1270 pdata->get_i2c_adapter = rtl2832_get_i2c_adapter;
6f5f6ee2 1271 pdata->enable_slave_ts = rtl2832_enable_slave_ts;
4b01e01a
AP		 1272 pdata->pid_filter = rtl2832_pid_filter;
1273 pdata->pid_filter_ctrl = rtl2832_pid_filter_ctrl;
0aa32ef9
AP		 1274 pdata->bulk_read = rtl2832_bulk_read;
1275 pdata->bulk_write = rtl2832_bulk_write;
1276 pdata->update_bits = rtl2832_update_bits;
c2c8386f
AP		 1277
1278 dev_info(&client->dev, "Realtek RTL2832 successfully attached\n");
1279 return 0;
d1016581
AP		 1280err_regmap_exit:
1281 regmap_exit(dev->regmap);
c2c8386f 1282err_kfree:
038c6f24 1283 kfree(dev);
c2c8386f
AP		 1284err:
1285 dev_dbg(&client->dev, "failed=%d\n", ret);
1286 return ret;
1287}
1288
1289static int rtl2832_remove(struct i2c_client *client)
1290{
038c6f24 1291 struct rtl2832_dev *dev = i2c_get_clientdata(client);
c2c8386f
AP		 1292
1293 dev_dbg(&client->dev, "\n");
1294
038c6f24 1295 cancel_delayed_work_sync(&dev->i2c_gate_work);
c2c8386f 1296
038c6f24 1297 i2c_del_mux_adapter(dev->i2c_adapter_tuner);
c2c8386f 1298
d1016581
AP		 1299 regmap_exit(dev->regmap);
1300
038c6f24 1301 kfree(dev);
c2c8386f
AP		 1302
1303 return 0;
1304}
1305
1306static const struct i2c_device_id rtl2832_id_table[] = {
1307 {"rtl2832", 0},
1308 {}
1309};
1310MODULE_DEVICE_TABLE(i2c, rtl2832_id_table);
1311
1312static struct i2c_driver rtl2832_driver = {
1313 .driver = {
1314 .owner = THIS_MODULE,
1315 .name = "rtl2832",
1316 },
1317 .probe = rtl2832_probe,
1318 .remove = rtl2832_remove,
1319 .id_table = rtl2832_id_table,
1320};
1321
1322module_i2c_driver(rtl2832_driver);
1323
82041c0a 1324MODULE_AUTHOR("Thomas Mair <mair.thomas86@gmail.com>");
75c24005 1325MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
82041c0a
TM		 1326MODULE_DESCRIPTION("Realtek RTL2832 DVB-T demodulator driver");
1327MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)