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[media] rtl2832: wrap DVBv5 BER to DVBv3
[linux-2.6-block.git] / drivers / media / dvb-frontends / rtl2832.c
CommitLineData
82041c0a
TM		 1/*
2 * Realtek RTL2832 DVB-T demodulator driver
3 *
4 * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include "rtl2832_priv.h"
73983497 22#include "dvb_math.h"
298f18a3 23#include <linux/bitops.h>
82041c0a 24
298f18a3 25#define REG_MASK(b) (BIT(b + 1) - 1)
82041c0a
TM		 26
27static const struct rtl2832_reg_entry registers[] = {
28 [DVBT_SOFT_RST] = {0x1, 0x1, 2, 2},
29 [DVBT_IIC_REPEAT] = {0x1, 0x1, 3, 3},
30 [DVBT_TR_WAIT_MIN_8K] = {0x1, 0x88, 11, 2},
31 [DVBT_RSD_BER_FAIL_VAL] = {0x1, 0x8f, 15, 0},
32 [DVBT_EN_BK_TRK] = {0x1, 0xa6, 7, 7},
33 [DVBT_AD_EN_REG] = {0x0, 0x8, 7, 7},
34 [DVBT_AD_EN_REG1] = {0x0, 0x8, 6, 6},
35 [DVBT_EN_BBIN] = {0x1, 0xb1, 0, 0},
36 [DVBT_MGD_THD0] = {0x1, 0x95, 7, 0},
37 [DVBT_MGD_THD1] = {0x1, 0x96, 7, 0},
38 [DVBT_MGD_THD2] = {0x1, 0x97, 7, 0},
39 [DVBT_MGD_THD3] = {0x1, 0x98, 7, 0},
40 [DVBT_MGD_THD4] = {0x1, 0x99, 7, 0},
41 [DVBT_MGD_THD5] = {0x1, 0x9a, 7, 0},
42 [DVBT_MGD_THD6] = {0x1, 0x9b, 7, 0},
43 [DVBT_MGD_THD7] = {0x1, 0x9c, 7, 0},
44 [DVBT_EN_CACQ_NOTCH] = {0x1, 0x61, 4, 4},
45 [DVBT_AD_AV_REF] = {0x0, 0x9, 6, 0},
46 [DVBT_REG_PI] = {0x0, 0xa, 2, 0},
47 [DVBT_PIP_ON] = {0x0, 0x21, 3, 3},
48 [DVBT_SCALE1_B92] = {0x2, 0x92, 7, 0},
49 [DVBT_SCALE1_B93] = {0x2, 0x93, 7, 0},
50 [DVBT_SCALE1_BA7] = {0x2, 0xa7, 7, 0},
51 [DVBT_SCALE1_BA9] = {0x2, 0xa9, 7, 0},
52 [DVBT_SCALE1_BAA] = {0x2, 0xaa, 7, 0},
53 [DVBT_SCALE1_BAB] = {0x2, 0xab, 7, 0},
54 [DVBT_SCALE1_BAC] = {0x2, 0xac, 7, 0},
55 [DVBT_SCALE1_BB0] = {0x2, 0xb0, 7, 0},
56 [DVBT_SCALE1_BB1] = {0x2, 0xb1, 7, 0},
57 [DVBT_KB_P1] = {0x1, 0x64, 3, 1},
58 [DVBT_KB_P2] = {0x1, 0x64, 6, 4},
59 [DVBT_KB_P3] = {0x1, 0x65, 2, 0},
60 [DVBT_OPT_ADC_IQ] = {0x0, 0x6, 5, 4},
61 [DVBT_AD_AVI] = {0x0, 0x9, 1, 0},
62 [DVBT_AD_AVQ] = {0x0, 0x9, 3, 2},
63 [DVBT_K1_CR_STEP12] = {0x2, 0xad, 9, 4},
64 [DVBT_TRK_KS_P2] = {0x1, 0x6f, 2, 0},
65 [DVBT_TRK_KS_I2] = {0x1, 0x70, 5, 3},
66 [DVBT_TR_THD_SET2] = {0x1, 0x72, 3, 0},
67 [DVBT_TRK_KC_P2] = {0x1, 0x73, 5, 3},
68 [DVBT_TRK_KC_I2] = {0x1, 0x75, 2, 0},
69 [DVBT_CR_THD_SET2] = {0x1, 0x76, 7, 6},
70 [DVBT_PSET_IFFREQ] = {0x1, 0x19, 21, 0},
71 [DVBT_SPEC_INV] = {0x1, 0x15, 0, 0},
72 [DVBT_RSAMP_RATIO] = {0x1, 0x9f, 27, 2},
73 [DVBT_CFREQ_OFF_RATIO] = {0x1, 0x9d, 23, 4},
74 [DVBT_FSM_STAGE] = {0x3, 0x51, 6, 3},
75 [DVBT_RX_CONSTEL] = {0x3, 0x3c, 3, 2},
76 [DVBT_RX_HIER] = {0x3, 0x3c, 6, 4},
77 [DVBT_RX_C_RATE_LP] = {0x3, 0x3d, 2, 0},
78 [DVBT_RX_C_RATE_HP] = {0x3, 0x3d, 5, 3},
79 [DVBT_GI_IDX] = {0x3, 0x51, 1, 0},
80 [DVBT_FFT_MODE_IDX] = {0x3, 0x51, 2, 2},
81 [DVBT_RSD_BER_EST] = {0x3, 0x4e, 15, 0},
82 [DVBT_CE_EST_EVM] = {0x4, 0xc, 15, 0},
83 [DVBT_RF_AGC_VAL] = {0x3, 0x5b, 13, 0},
84 [DVBT_IF_AGC_VAL] = {0x3, 0x59, 13, 0},
85 [DVBT_DAGC_VAL] = {0x3, 0x5, 7, 0},
86 [DVBT_SFREQ_OFF] = {0x3, 0x18, 13, 0},
87 [DVBT_CFREQ_OFF] = {0x3, 0x5f, 17, 0},
88 [DVBT_POLAR_RF_AGC] = {0x0, 0xe, 1, 1},
89 [DVBT_POLAR_IF_AGC] = {0x0, 0xe, 0, 0},
90 [DVBT_AAGC_HOLD] = {0x1, 0x4, 5, 5},
91 [DVBT_EN_RF_AGC] = {0x1, 0x4, 6, 6},
92 [DVBT_EN_IF_AGC] = {0x1, 0x4, 7, 7},
93 [DVBT_IF_AGC_MIN] = {0x1, 0x8, 7, 0},
94 [DVBT_IF_AGC_MAX] = {0x1, 0x9, 7, 0},
95 [DVBT_RF_AGC_MIN] = {0x1, 0xa, 7, 0},
96 [DVBT_RF_AGC_MAX] = {0x1, 0xb, 7, 0},
97 [DVBT_IF_AGC_MAN] = {0x1, 0xc, 6, 6},
98 [DVBT_IF_AGC_MAN_VAL] = {0x1, 0xc, 13, 0},
99 [DVBT_RF_AGC_MAN] = {0x1, 0xe, 6, 6},
100 [DVBT_RF_AGC_MAN_VAL] = {0x1, 0xe, 13, 0},
101 [DVBT_DAGC_TRG_VAL] = {0x1, 0x12, 7, 0},
102 [DVBT_AGC_TARG_VAL_0] = {0x1, 0x2, 0, 0},
103 [DVBT_AGC_TARG_VAL_8_1] = {0x1, 0x3, 7, 0},
104 [DVBT_AAGC_LOOP_GAIN] = {0x1, 0xc7, 5, 1},
105 [DVBT_LOOP_GAIN2_3_0] = {0x1, 0x4, 4, 1},
106 [DVBT_LOOP_GAIN2_4] = {0x1, 0x5, 7, 7},
107 [DVBT_LOOP_GAIN3] = {0x1, 0xc8, 4, 0},
108 [DVBT_VTOP1] = {0x1, 0x6, 5, 0},
109 [DVBT_VTOP2] = {0x1, 0xc9, 5, 0},
110 [DVBT_VTOP3] = {0x1, 0xca, 5, 0},
111 [DVBT_KRF1] = {0x1, 0xcb, 7, 0},
112 [DVBT_KRF2] = {0x1, 0x7, 7, 0},
113 [DVBT_KRF3] = {0x1, 0xcd, 7, 0},
114 [DVBT_KRF4] = {0x1, 0xce, 7, 0},
115 [DVBT_EN_GI_PGA] = {0x1, 0xe5, 0, 0},
116 [DVBT_THD_LOCK_UP] = {0x1, 0xd9, 8, 0},
117 [DVBT_THD_LOCK_DW] = {0x1, 0xdb, 8, 0},
118 [DVBT_THD_UP1] = {0x1, 0xdd, 7, 0},
119 [DVBT_THD_DW1] = {0x1, 0xde, 7, 0},
120 [DVBT_INTER_CNT_LEN] = {0x1, 0xd8, 3, 0},
121 [DVBT_GI_PGA_STATE] = {0x1, 0xe6, 3, 3},
122 [DVBT_EN_AGC_PGA] = {0x1, 0xd7, 0, 0},
123 [DVBT_CKOUTPAR] = {0x1, 0x7b, 5, 5},
124 [DVBT_CKOUT_PWR] = {0x1, 0x7b, 6, 6},
125 [DVBT_SYNC_DUR] = {0x1, 0x7b, 7, 7},
126 [DVBT_ERR_DUR] = {0x1, 0x7c, 0, 0},
127 [DVBT_SYNC_LVL] = {0x1, 0x7c, 1, 1},
128 [DVBT_ERR_LVL] = {0x1, 0x7c, 2, 2},
129 [DVBT_VAL_LVL] = {0x1, 0x7c, 3, 3},
130 [DVBT_SERIAL] = {0x1, 0x7c, 4, 4},
131 [DVBT_SER_LSB] = {0x1, 0x7c, 5, 5},
132 [DVBT_CDIV_PH0] = {0x1, 0x7d, 3, 0},
133 [DVBT_CDIV_PH1] = {0x1, 0x7d, 7, 4},
134 [DVBT_MPEG_IO_OPT_2_2] = {0x0, 0x6, 7, 7},
135 [DVBT_MPEG_IO_OPT_1_0] = {0x0, 0x7, 7, 6},
136 [DVBT_CKOUTPAR_PIP] = {0x0, 0xb7, 4, 4},
137 [DVBT_CKOUT_PWR_PIP] = {0x0, 0xb7, 3, 3},
138 [DVBT_SYNC_LVL_PIP] = {0x0, 0xb7, 2, 2},
139 [DVBT_ERR_LVL_PIP] = {0x0, 0xb7, 1, 1},
140 [DVBT_VAL_LVL_PIP] = {0x0, 0xb7, 0, 0},
141 [DVBT_CKOUTPAR_PID] = {0x0, 0xb9, 4, 4},
142 [DVBT_CKOUT_PWR_PID] = {0x0, 0xb9, 3, 3},
143 [DVBT_SYNC_LVL_PID] = {0x0, 0xb9, 2, 2},
144 [DVBT_ERR_LVL_PID] = {0x0, 0xb9, 1, 1},
145 [DVBT_VAL_LVL_PID] = {0x0, 0xb9, 0, 0},
146 [DVBT_SM_PASS] = {0x1, 0x93, 11, 0},
147 [DVBT_AD7_SETTING] = {0x0, 0x11, 15, 0},
148 [DVBT_RSSI_R] = {0x3, 0x1, 6, 0},
149 [DVBT_ACI_DET_IND] = {0x3, 0x12, 0, 0},
150 [DVBT_REG_MON] = {0x0, 0xd, 1, 0},
151 [DVBT_REG_MONSEL] = {0x0, 0xd, 2, 2},
152 [DVBT_REG_GPE] = {0x0, 0xd, 7, 7},
153 [DVBT_REG_GPO] = {0x0, 0x10, 0, 0},
154 [DVBT_REG_4MSEL] = {0x0, 0x13, 0, 0},
155};
156
d1016581
AP		 157/* Our regmap is bypassing I2C adapter lock, thus we do it! */
158int rtl2832_bulk_write(struct i2c_client *client, unsigned int reg,
159 const void *val, size_t val_count)
82041c0a 160{
d1016581 161 struct rtl2832_dev *dev = i2c_get_clientdata(client);
82041c0a 162 int ret;
82041c0a 163
d1016581
AP		 164 i2c_lock_adapter(client->adapter);
165 ret = regmap_bulk_write(dev->regmap, reg, val, val_count);
166 i2c_unlock_adapter(client->adapter);
82041c0a
TM		 167 return ret;
168}
169
d1016581
AP		 170int rtl2832_update_bits(struct i2c_client *client, unsigned int reg,
171 unsigned int mask, unsigned int val)
82041c0a 172{
d1016581 173 struct rtl2832_dev *dev = i2c_get_clientdata(client);
82041c0a 174 int ret;
82041c0a 175
d1016581
AP		 176 i2c_lock_adapter(client->adapter);
177 ret = regmap_update_bits(dev->regmap, reg, mask, val);
178 i2c_unlock_adapter(client->adapter);
298efdd3 179 return ret;
82041c0a
TM		 180}
181
d1016581
AP		 182int rtl2832_bulk_read(struct i2c_client *client, unsigned int reg, void *val,
183 size_t val_count)
82041c0a 184{
d1016581 185 struct rtl2832_dev *dev = i2c_get_clientdata(client);
82041c0a
TM		 186 int ret;
187
d1016581
AP		 188 i2c_lock_adapter(client->adapter);
189 ret = regmap_bulk_read(dev->regmap, reg, val, val_count);
190 i2c_unlock_adapter(client->adapter);
191 return ret;
192}
82041c0a 193
d1016581
AP		 194/* write multiple registers */
195static int rtl2832_wr_regs(struct rtl2832_dev *dev, u8 reg, u8 page, u8 *val, int len)
196{
197 return rtl2832_bulk_write(dev->client, page << 8 | reg, val, len);
82041c0a
TM		 198}
199
200/* read multiple registers */
d1016581 201static int rtl2832_rd_regs(struct rtl2832_dev *dev, u8 reg, u8 page, u8 *val, int len)
82041c0a 202{
d1016581 203 return rtl2832_bulk_read(dev->client, page << 8 | reg, val, len);
82041c0a
TM		 204}
205
82041c0a 206/* write single register */
038c6f24 207static int rtl2832_wr_reg(struct rtl2832_dev *dev, u8 reg, u8 page, u8 val)
82041c0a 208{
038c6f24 209 return rtl2832_wr_regs(dev, reg, page, &val, 1);
82041c0a 210}
82041c0a
TM		 211
212/* read single register */
038c6f24 213static int rtl2832_rd_reg(struct rtl2832_dev *dev, u8 reg, u8 page, u8 *val)
82041c0a 214{
038c6f24 215 return rtl2832_rd_regs(dev, reg, page, val, 1);
82041c0a
TM		 216}
217
038c6f24 218static int rtl2832_rd_demod_reg(struct rtl2832_dev *dev, int reg, u32 *val)
82041c0a 219{
6e6aac65 220 struct i2c_client *client = dev->client;
82041c0a
TM		 221 int ret;
222
223 u8 reg_start_addr;
224 u8 msb, lsb;
225 u8 page;
226 u8 reading[4];
227 u32 reading_tmp;
228 int i;
229
230 u8 len;
231 u32 mask;
232
233 reg_start_addr = registers[reg].start_address;
234 msb = registers[reg].msb;
235 lsb = registers[reg].lsb;
236 page = registers[reg].page;
237
238 len = (msb >> 3) + 1;
298f18a3 239 mask = REG_MASK(msb - lsb);
82041c0a 240
038c6f24 241 ret = rtl2832_rd_regs(dev, reg_start_addr, page, &reading[0], len);
82041c0a
TM		 242 if (ret)
243 goto err;
244
245 reading_tmp = 0;
246 for (i = 0; i < len; i++)
247 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
248
249 *val = (reading_tmp >> lsb) & mask;
250
251 return ret;
252
253err:
6e6aac65 254 dev_dbg(&client->dev, "failed=%d\n", ret);
82041c0a
TM		 255 return ret;
256
257}
258
038c6f24 259static int rtl2832_wr_demod_reg(struct rtl2832_dev *dev, int reg, u32 val)
82041c0a 260{
6e6aac65 261 struct i2c_client *client = dev->client;
82041c0a
TM		 262 int ret, i;
263 u8 len;
264 u8 reg_start_addr;
265 u8 msb, lsb;
266 u8 page;
267 u32 mask;
268
269
270 u8 reading[4];
271 u8 writing[4];
272 u32 reading_tmp;
273 u32 writing_tmp;
274
275
276 reg_start_addr = registers[reg].start_address;
277 msb = registers[reg].msb;
278 lsb = registers[reg].lsb;
279 page = registers[reg].page;
280
281 len = (msb >> 3) + 1;
298f18a3 282 mask = REG_MASK(msb - lsb);
82041c0a
TM		 283
284
038c6f24 285 ret = rtl2832_rd_regs(dev, reg_start_addr, page, &reading[0], len);
82041c0a
TM		 286 if (ret)
287 goto err;
288
289 reading_tmp = 0;
290 for (i = 0; i < len; i++)
291 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
292
293 writing_tmp = reading_tmp & ~(mask << lsb);
294 writing_tmp |= ((val & mask) << lsb);
295
296
297 for (i = 0; i < len; i++)
298 writing[i] = (writing_tmp >> ((len - 1 - i) * 8)) & 0xff;
299
038c6f24 300 ret = rtl2832_wr_regs(dev, reg_start_addr, page, &writing[0], len);
82041c0a
TM		 301 if (ret)
302 goto err;
303
304 return ret;
305
306err:
6e6aac65 307 dev_dbg(&client->dev, "failed=%d\n", ret);
82041c0a
TM		 308 return ret;
309
310}
311
82041c0a
TM		 312static int rtl2832_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
313{
038c6f24 314 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65
AP		 315 struct i2c_client *client = dev->client;
316 int ret;
82041c0a 317
6e6aac65 318 dev_dbg(&client->dev, "enable=%d\n", enable);
82041c0a
TM		 319
320 /* gate already open or close */
038c6f24 321 if (dev->i2c_gate_state == enable)
82041c0a
TM		 322 return 0;
323
038c6f24 324 ret = rtl2832_wr_demod_reg(dev, DVBT_IIC_REPEAT, (enable ? 0x1 : 0x0));
82041c0a
TM		 325 if (ret)
326 goto err;
327
038c6f24 328 dev->i2c_gate_state = enable;
82041c0a
TM		 329
330 return ret;
331err:
6e6aac65 332 dev_dbg(&client->dev, "failed=%d\n", ret);
82041c0a
TM		 333 return ret;
334}
335
884655ad 336static int rtl2832_set_if(struct dvb_frontend *fe, u32 if_freq)
82041c0a 337{
038c6f24 338 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 339 struct i2c_client *client = dev->client;
884655ad 340 int ret;
82041c0a 341 u64 pset_iffreq;
884655ad
MCC		 342 u8 en_bbin = (if_freq == 0 ? 0x1 : 0x0);
343
344 /*
345 * PSET_IFFREQ = - floor((IfFreqHz % CrystalFreqHz) * pow(2, 22)
346 * / CrystalFreqHz)
347 */
348
e1174d78 349 pset_iffreq = if_freq % dev->pdata->clk;
884655ad 350 pset_iffreq *= 0x400000;
e1174d78 351 pset_iffreq = div_u64(pset_iffreq, dev->pdata->clk);
c8832e8f 352 pset_iffreq = -pset_iffreq;
884655ad 353 pset_iffreq = pset_iffreq & 0x3fffff;
6e6aac65
AP		 354 dev_dbg(&client->dev, "if_frequency=%d pset_iffreq=%08x\n",
355 if_freq, (unsigned)pset_iffreq);
c8832e8f 356
038c6f24 357 ret = rtl2832_wr_demod_reg(dev, DVBT_EN_BBIN, en_bbin);
884655ad
MCC		 358 if (ret)
359 return ret;
360
038c6f24 361 ret = rtl2832_wr_demod_reg(dev, DVBT_PSET_IFFREQ, pset_iffreq);
884655ad 362
3ca2418d 363 return ret;
884655ad
MCC		 364}
365
366static int rtl2832_init(struct dvb_frontend *fe)
367{
038c6f24 368 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 369 struct i2c_client *client = dev->client;
19d273d6 370 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
832cc7cd 371 const struct rtl2832_reg_value *init;
884655ad 372 int i, ret, len;
82041c0a
TM		 373 /* initialization values for the demodulator registers */
374 struct rtl2832_reg_value rtl2832_initial_regs[] = {
375 {DVBT_AD_EN_REG, 0x1},
376 {DVBT_AD_EN_REG1, 0x1},
377 {DVBT_RSD_BER_FAIL_VAL, 0x2800},
378 {DVBT_MGD_THD0, 0x10},
379 {DVBT_MGD_THD1, 0x20},
380 {DVBT_MGD_THD2, 0x20},
381 {DVBT_MGD_THD3, 0x40},
382 {DVBT_MGD_THD4, 0x22},
383 {DVBT_MGD_THD5, 0x32},
384 {DVBT_MGD_THD6, 0x37},
385 {DVBT_MGD_THD7, 0x39},
386 {DVBT_EN_BK_TRK, 0x0},
387 {DVBT_EN_CACQ_NOTCH, 0x0},
388 {DVBT_AD_AV_REF, 0x2a},
389 {DVBT_REG_PI, 0x6},
390 {DVBT_PIP_ON, 0x0},
391 {DVBT_CDIV_PH0, 0x8},
392 {DVBT_CDIV_PH1, 0x8},
393 {DVBT_SCALE1_B92, 0x4},
394 {DVBT_SCALE1_B93, 0xb0},
395 {DVBT_SCALE1_BA7, 0x78},
396 {DVBT_SCALE1_BA9, 0x28},
397 {DVBT_SCALE1_BAA, 0x59},
398 {DVBT_SCALE1_BAB, 0x83},
399 {DVBT_SCALE1_BAC, 0xd4},
400 {DVBT_SCALE1_BB0, 0x65},
401 {DVBT_SCALE1_BB1, 0x43},
402 {DVBT_KB_P1, 0x1},
403 {DVBT_KB_P2, 0x4},
404 {DVBT_KB_P3, 0x7},
405 {DVBT_K1_CR_STEP12, 0xa},
406 {DVBT_REG_GPE, 0x1},
407 {DVBT_SERIAL, 0x0},
408 {DVBT_CDIV_PH0, 0x9},
409 {DVBT_CDIV_PH1, 0x9},
410 {DVBT_MPEG_IO_OPT_2_2, 0x0},
411 {DVBT_MPEG_IO_OPT_1_0, 0x0},
412 {DVBT_TRK_KS_P2, 0x4},
413 {DVBT_TRK_KS_I2, 0x7},
414 {DVBT_TR_THD_SET2, 0x6},
415 {DVBT_TRK_KC_I2, 0x5},
416 {DVBT_CR_THD_SET2, 0x1},
82041c0a
TM		 417 };
418
6e6aac65 419 dev_dbg(&client->dev, "\n");
82041c0a 420
82041c0a 421 for (i = 0; i < ARRAY_SIZE(rtl2832_initial_regs); i++) {
038c6f24 422 ret = rtl2832_wr_demod_reg(dev, rtl2832_initial_regs[i].reg,
82041c0a
TM		 423 rtl2832_initial_regs[i].value);
424 if (ret)
425 goto err;
426 }
427
832cc7cd 428 /* load tuner specific settings */
e1174d78
AP		 429 dev_dbg(&client->dev, "load settings for tuner=%02x\n",
430 dev->pdata->tuner);
431 switch (dev->pdata->tuner) {
832cc7cd
AP		 432 case RTL2832_TUNER_FC0012:
433 case RTL2832_TUNER_FC0013:
434 len = ARRAY_SIZE(rtl2832_tuner_init_fc0012);
435 init = rtl2832_tuner_init_fc0012;
436 break;
5db4187a
AP		 437 case RTL2832_TUNER_TUA9001:
438 len = ARRAY_SIZE(rtl2832_tuner_init_tua9001);
439 init = rtl2832_tuner_init_tua9001;
440 break;
7e688de0
AP		 441 case RTL2832_TUNER_E4000:
442 len = ARRAY_SIZE(rtl2832_tuner_init_e4000);
443 init = rtl2832_tuner_init_e4000;
444 break;
fa4bfd2b 445 case RTL2832_TUNER_R820T:
a26758ed 446 case RTL2832_TUNER_R828D:
fa4bfd2b
MCC		 447 len = ARRAY_SIZE(rtl2832_tuner_init_r820t);
448 init = rtl2832_tuner_init_r820t;
449 break;
832cc7cd
AP		 450 default:
451 ret = -EINVAL;
452 goto err;
453 }
454
455 for (i = 0; i < len; i++) {
038c6f24 456 ret = rtl2832_wr_demod_reg(dev, init[i].reg, init[i].value);
832cc7cd
AP		 457 if (ret)
458 goto err;
459 }
460
fa4bfd2b
MCC		 461 /*
462 * r820t NIM code does a software reset here at the demod -
3ca2418d
AP		 463 * may not be needed, as there's already a software reset at
464 * set_params()
fa4bfd2b
MCC		 465 */
466#if 1
467 /* soft reset */
038c6f24 468 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
fa4bfd2b
MCC		 469 if (ret)
470 goto err;
471
038c6f24 472 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
fa4bfd2b
MCC		 473 if (ret)
474 goto err;
475#endif
19d273d6
AP		 476 /* init stats here in order signal app which stats are supported */
477 c->cnr.len = 1;
478 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6b4fd018
AP		 479 c->post_bit_error.len = 1;
480 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
481 c->post_bit_count.len = 1;
482 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
19d273d6
AP		 483 /* start statistics polling */
484 schedule_delayed_work(&dev->stat_work, msecs_to_jiffies(2000));
038c6f24 485 dev->sleeping = false;
82041c0a
TM		 486
487 return ret;
82041c0a 488err:
6e6aac65 489 dev_dbg(&client->dev, "failed=%d\n", ret);
82041c0a
TM		 490 return ret;
491}
492
493static int rtl2832_sleep(struct dvb_frontend *fe)
494{
038c6f24 495 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 496 struct i2c_client *client = dev->client;
82041c0a 497
6e6aac65 498 dev_dbg(&client->dev, "\n");
038c6f24 499 dev->sleeping = true;
19d273d6
AP		 500 /* stop statistics polling */
501 cancel_delayed_work_sync(&dev->stat_work);
502 dev->fe_status = 0;
82041c0a
TM		 503 return 0;
504}
505
b0944ea2 506static int rtl2832_get_tune_settings(struct dvb_frontend *fe,
82041c0a
TM		 507 struct dvb_frontend_tune_settings *s)
508{
038c6f24 509 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 510 struct i2c_client *client = dev->client;
298efdd3 511
6e6aac65 512 dev_dbg(&client->dev, "\n");
82041c0a
TM		 513 s->min_delay_ms = 1000;
514 s->step_size = fe->ops.info.frequency_stepsize * 2;
515 s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
516 return 0;
517}
518
519static int rtl2832_set_frontend(struct dvb_frontend *fe)
520{
038c6f24 521 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 522 struct i2c_client *client = dev->client;
82041c0a
TM		 523 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
524 int ret, i, j;
525 u64 bw_mode, num, num2;
526 u32 resamp_ratio, cfreq_off_ratio;
82041c0a
TM		 527 static u8 bw_params[3][32] = {
528 /* 6 MHz bandwidth */
529 {
530 0xf5, 0xff, 0x15, 0x38, 0x5d, 0x6d, 0x52, 0x07, 0xfa, 0x2f,
531 0x53, 0xf5, 0x3f, 0xca, 0x0b, 0x91, 0xea, 0x30, 0x63, 0xb2,
532 0x13, 0xda, 0x0b, 0xc4, 0x18, 0x7e, 0x16, 0x66, 0x08, 0x67,
533 0x19, 0xe0,
534 },
535
536 /* 7 MHz bandwidth */
537 {
538 0xe7, 0xcc, 0xb5, 0xba, 0xe8, 0x2f, 0x67, 0x61, 0x00, 0xaf,
539 0x86, 0xf2, 0xbf, 0x59, 0x04, 0x11, 0xb6, 0x33, 0xa4, 0x30,
540 0x15, 0x10, 0x0a, 0x42, 0x18, 0xf8, 0x17, 0xd9, 0x07, 0x22,
541 0x19, 0x10,
542 },
543
544 /* 8 MHz bandwidth */
545 {
546 0x09, 0xf6, 0xd2, 0xa7, 0x9a, 0xc9, 0x27, 0x77, 0x06, 0xbf,
547 0xec, 0xf4, 0x4f, 0x0b, 0xfc, 0x01, 0x63, 0x35, 0x54, 0xa7,
548 0x16, 0x66, 0x08, 0xb4, 0x19, 0x6e, 0x19, 0x65, 0x05, 0xc8,
549 0x19, 0xe0,
550 },
551 };
552
553
6e6aac65
AP		 554 dev_dbg(&client->dev, "frequency=%u bandwidth_hz=%u inversion=%u\n",
555 c->frequency, c->bandwidth_hz, c->inversion);
82041c0a
TM		 556
557 /* program tuner */
558 if (fe->ops.tuner_ops.set_params)
559 fe->ops.tuner_ops.set_params(fe);
560
fe37b38b 561 /* PIP mode related */
038c6f24 562 ret = rtl2832_wr_regs(dev, 0x92, 1, "\x00\x0f\xff", 3);
fe37b38b
AP		 563 if (ret)
564 goto err;
565
fa4bfd2b
MCC		 566 /* If the frontend has get_if_frequency(), use it */
567 if (fe->ops.tuner_ops.get_if_frequency) {
568 u32 if_freq;
fa4bfd2b
MCC		 569
570 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
571 if (ret)
572 goto err;
573
884655ad 574 ret = rtl2832_set_if(fe, if_freq);
fa4bfd2b
MCC		 575 if (ret)
576 goto err;
577 }
578
82041c0a
TM		 579 switch (c->bandwidth_hz) {
580 case 6000000:
581 i = 0;
582 bw_mode = 48000000;
583 break;
584 case 7000000:
585 i = 1;
586 bw_mode = 56000000;
587 break;
588 case 8000000:
589 i = 2;
590 bw_mode = 64000000;
591 break;
592 default:
6e6aac65
AP		 593 dev_err(&client->dev, "invalid bandwidth_hz %u\n",
594 c->bandwidth_hz);
595 ret = -EINVAL;
596 goto err;
82041c0a
TM		 597 }
598
fc4b3fa7 599 for (j = 0; j < sizeof(bw_params[0]); j++) {
038c6f24 600 ret = rtl2832_wr_regs(dev, 0x1c+j, 1, &bw_params[i][j], 1);
82041c0a
TM		 601 if (ret)
602 goto err;
603 }
604
605 /* calculate and set resample ratio
606 * RSAMP_RATIO = floor(CrystalFreqHz * 7 * pow(2, 22)
607 * / ConstWithBandwidthMode)
608 */
e1174d78 609 num = dev->pdata->clk * 7;
82041c0a
TM		 610 num *= 0x400000;
611 num = div_u64(num, bw_mode);
612 resamp_ratio = num & 0x3ffffff;
038c6f24 613 ret = rtl2832_wr_demod_reg(dev, DVBT_RSAMP_RATIO, resamp_ratio);
82041c0a
TM		 614 if (ret)
615 goto err;
616
617 /* calculate and set cfreq off ratio
618 * CFREQ_OFF_RATIO = - floor(ConstWithBandwidthMode * pow(2, 20)
619 * / (CrystalFreqHz * 7))
620 */
621 num = bw_mode << 20;
e1174d78 622 num2 = dev->pdata->clk * 7;
82041c0a
TM		 623 num = div_u64(num, num2);
624 num = -num;
625 cfreq_off_ratio = num & 0xfffff;
038c6f24 626 ret = rtl2832_wr_demod_reg(dev, DVBT_CFREQ_OFF_RATIO, cfreq_off_ratio);
82041c0a
TM		 627 if (ret)
628 goto err;
629
82041c0a 630 /* soft reset */
038c6f24 631 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
82041c0a
TM		 632 if (ret)
633 goto err;
634
038c6f24 635 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
82041c0a
TM		 636 if (ret)
637 goto err;
638
639 return ret;
640err:
6e6aac65 641 dev_dbg(&client->dev, "failed=%d\n", ret);
82041c0a
TM		 642 return ret;
643}
644
0ce67a2a
AP		 645static int rtl2832_get_frontend(struct dvb_frontend *fe)
646{
038c6f24 647 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 648 struct i2c_client *client = dev->client;
0ce67a2a
AP		 649 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
650 int ret;
651 u8 buf[3];
652
038c6f24 653 if (dev->sleeping)
0ce67a2a
AP		 654 return 0;
655
038c6f24 656 ret = rtl2832_rd_regs(dev, 0x3c, 3, buf, 2);
0ce67a2a
AP		 657 if (ret)
658 goto err;
659
038c6f24 660 ret = rtl2832_rd_reg(dev, 0x51, 3, &buf[2]);
0ce67a2a
AP		 661 if (ret)
662 goto err;
663
6e6aac65 664 dev_dbg(&client->dev, "TPS=%*ph\n", 3, buf);
0ce67a2a
AP		 665
666 switch ((buf[0] >> 2) & 3) {
667 case 0:
668 c->modulation = QPSK;
669 break;
670 case 1:
671 c->modulation = QAM_16;
672 break;
673 case 2:
674 c->modulation = QAM_64;
675 break;
676 }
677
678 switch ((buf[2] >> 2) & 1) {
679 case 0:
680 c->transmission_mode = TRANSMISSION_MODE_2K;
681 break;
682 case 1:
683 c->transmission_mode = TRANSMISSION_MODE_8K;
684 }
685
686 switch ((buf[2] >> 0) & 3) {
687 case 0:
688 c->guard_interval = GUARD_INTERVAL_1_32;
689 break;
690 case 1:
691 c->guard_interval = GUARD_INTERVAL_1_16;
692 break;
693 case 2:
694 c->guard_interval = GUARD_INTERVAL_1_8;
695 break;
696 case 3:
697 c->guard_interval = GUARD_INTERVAL_1_4;
698 break;
699 }
700
701 switch ((buf[0] >> 4) & 7) {
702 case 0:
703 c->hierarchy = HIERARCHY_NONE;
704 break;
705 case 1:
706 c->hierarchy = HIERARCHY_1;
707 break;
708 case 2:
709 c->hierarchy = HIERARCHY_2;
710 break;
711 case 3:
712 c->hierarchy = HIERARCHY_4;
713 break;
714 }
715
716 switch ((buf[1] >> 3) & 7) {
717 case 0:
718 c->code_rate_HP = FEC_1_2;
719 break;
720 case 1:
721 c->code_rate_HP = FEC_2_3;
722 break;
723 case 2:
724 c->code_rate_HP = FEC_3_4;
725 break;
726 case 3:
727 c->code_rate_HP = FEC_5_6;
728 break;
729 case 4:
730 c->code_rate_HP = FEC_7_8;
731 break;
732 }
733
734 switch ((buf[1] >> 0) & 7) {
735 case 0:
736 c->code_rate_LP = FEC_1_2;
737 break;
738 case 1:
739 c->code_rate_LP = FEC_2_3;
740 break;
741 case 2:
742 c->code_rate_LP = FEC_3_4;
743 break;
744 case 3:
745 c->code_rate_LP = FEC_5_6;
746 break;
747 case 4:
748 c->code_rate_LP = FEC_7_8;
749 break;
750 }
751
752 return 0;
753err:
6e6aac65 754 dev_dbg(&client->dev, "failed=%d\n", ret);
0ce67a2a
AP		 755 return ret;
756}
757
82041c0a
TM		 758static int rtl2832_read_status(struct dvb_frontend *fe, fe_status_t *status)
759{
038c6f24 760 struct rtl2832_dev *dev = fe->demodulator_priv;
6e6aac65 761 struct i2c_client *client = dev->client;
82041c0a
TM		 762 int ret;
763 u32 tmp;
82041c0a 764
6e6aac65
AP		 765 dev_dbg(&client->dev, "\n");
766
767 *status = 0;
038c6f24 768 if (dev->sleeping)
82041c0a
TM		 769 return 0;
770
038c6f24 771 ret = rtl2832_rd_demod_reg(dev, DVBT_FSM_STAGE, &tmp);
82041c0a
TM		 772 if (ret)
773 goto err;
774
775 if (tmp == 11) {
776 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
777 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
778 }
779 /* TODO find out if this is also true for rtl2832? */
780 /*else if (tmp == 10) {
781 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
782 FE_HAS_VITERBI;
783 }*/
784
19d273d6 785 dev->fe_status = *status;
82041c0a
TM		 786 return ret;
787err:
6e6aac65 788 dev_dbg(&client->dev, "failed=%d\n", ret);
82041c0a
TM		 789 return ret;
790}
791
73983497
AP		 792static int rtl2832_read_snr(struct dvb_frontend *fe, u16 *snr)
793{
f7caf93f 794 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
73983497 795
f7caf93f
AP		 796 /* report SNR in resolution of 0.1 dB */
797 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
798 *snr = div_s64(c->cnr.stat[0].svalue, 100);
73983497
AP		 799 else
800 *snr = 0;
801
802 return 0;
73983497
AP		 803}
804
db32d74a
AP		 805static int rtl2832_read_ber(struct dvb_frontend *fe, u32 *ber)
806{
038c6f24 807 struct rtl2832_dev *dev = fe->demodulator_priv;
db32d74a 808
084330b7
AP		 809 *ber = (dev->post_bit_error - dev->post_bit_error_prev);
810 dev->post_bit_error_prev = dev->post_bit_error;
db32d74a
AP		 811
812 return 0;
db32d74a
AP		 813}
814
19d273d6
AP		 815static void rtl2832_stat_work(struct work_struct *work)
816{
817 struct rtl2832_dev *dev = container_of(work, struct rtl2832_dev, stat_work.work);
818 struct i2c_client *client = dev->client;
819 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
820 int ret, tmp;
821 u8 u8tmp, buf[2];
822 u16 u16tmp;
823
824 dev_dbg(&client->dev, "\n");
825
826 /* CNR */
827 if (dev->fe_status & FE_HAS_VITERBI) {
828 unsigned hierarchy, constellation;
829 #define CONSTELLATION_NUM 3
830 #define HIERARCHY_NUM 4
831 static const u32 constant[CONSTELLATION_NUM][HIERARCHY_NUM] = {
832 {85387325, 85387325, 85387325, 85387325},
833 {86676178, 86676178, 87167949, 87795660},
834 {87659938, 87659938, 87885178, 88241743},
835 };
836
837 ret = rtl2832_bulk_read(client, 0x33c, &u8tmp, 1);
838 if (ret)
839 goto err;
840
841 constellation = (u8tmp >> 2) & 0x03; /* [3:2] */
842 if (constellation > CONSTELLATION_NUM - 1)
843 goto err_schedule_delayed_work;
844
845 hierarchy = (u8tmp >> 4) & 0x07; /* [6:4] */
846 if (hierarchy > HIERARCHY_NUM - 1)
847 goto err_schedule_delayed_work;
848
849 ret = rtl2832_bulk_read(client, 0x40c, buf, 2);
850 if (ret)
851 goto err;
852
853 u16tmp = buf[0] << 8 | buf[1] << 0;
854 if (u16tmp)
855 tmp = (constant[constellation][hierarchy] -
856 intlog10(u16tmp)) / ((1 << 24) / 10000);
857 else
858 tmp = 0;
859
860 dev_dbg(&client->dev, "cnr raw=%u\n", u16tmp);
861
862 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
863 c->cnr.stat[0].svalue = tmp;
864 } else {
865 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
866 }
867
6b4fd018
AP		 868 /* BER */
869 if (dev->fe_status & FE_HAS_LOCK) {
870 ret = rtl2832_bulk_read(client, 0x34e, buf, 2);
871 if (ret)
872 goto err;
873
874 u16tmp = buf[0] << 8 | buf[1] << 0;
875 dev->post_bit_error += u16tmp;
876 dev->post_bit_count += 1000000;
877
878 dev_dbg(&client->dev, "ber errors=%u total=1000000\n", u16tmp);
879
880 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
881 c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
882 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
883 c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
884 } else {
885 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
886 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
887 }
888
19d273d6
AP		 889err_schedule_delayed_work:
890 schedule_delayed_work(&dev->stat_work, msecs_to_jiffies(2000));
891 return;
892err:
893 dev_dbg(&client->dev, "failed=%d\n", ret);
894}
895
92d20d9f 896/*
d1016581
AP		 897 * I2C gate/mux/repeater logic
898 * We must use unlocked __i2c_transfer() here (through regmap) because of I2C
899 * adapter lock is already taken by tuner driver.
900 * There is delay mechanism to avoid unneeded I2C gate open / close. Gate close
901 * is delayed here a little bit in order to see if there is sequence of I2C
92d20d9f 902 * messages sent to same I2C bus.
92d20d9f
AP		 903 */
904static void rtl2832_i2c_gate_work(struct work_struct *work)
905{
d1016581 906 struct rtl2832_dev *dev = container_of(work, struct rtl2832_dev, i2c_gate_work.work);
6e6aac65 907 struct i2c_client *client = dev->client;
92d20d9f 908 int ret;
6e6aac65 909
d1016581
AP		 910 /* close gate */
911 ret = rtl2832_update_bits(dev->client, 0x101, 0x08, 0x00);
912 if (ret)
92d20d9f
AP		 913 goto err;
914
038c6f24 915 dev->i2c_gate_state = false;
92d20d9f
AP		 916
917 return;
918err:
6e6aac65 919 dev_dbg(&client->dev, "failed=%d\n", ret);
92d20d9f
AP		 920 return;
921}
922
0ea872d4 923static int rtl2832_select(struct i2c_adapter *adap, void *mux_priv, u32 chan_id)
8823f028 924{
038c6f24 925 struct rtl2832_dev *dev = mux_priv;
6e6aac65 926 struct i2c_client *client = dev->client;
0ea872d4 927 int ret;
92d20d9f
AP		 928
929 /* terminate possible gate closing */
d1016581 930 cancel_delayed_work(&dev->i2c_gate_work);
8823f028 931
038c6f24 932 if (dev->i2c_gate_state == chan_id)
0ea872d4
AP		 933 return 0;
934
d1016581
AP		 935 /*
936 * chan_id 1 is muxed adapter demod provides and chan_id 0 is demod
937 * itself. We need open gate when request is for chan_id 1. On that case
938 * I2C adapter lock is already taken and due to that we will use
939 * regmap_update_bits() which does not lock again I2C adapter.
940 */
0ea872d4 941 if (chan_id == 1)
d1016581 942 ret = regmap_update_bits(dev->regmap, 0x101, 0x08, 0x08);
0ea872d4 943 else
d1016581
AP		 944 ret = rtl2832_update_bits(dev->client, 0x101, 0x08, 0x00);
945 if (ret)
0ea872d4
AP		 946 goto err;
947
038c6f24 948 dev->i2c_gate_state = chan_id;
0ea872d4
AP		 949
950 return 0;
951err:
6e6aac65 952 dev_dbg(&client->dev, "failed=%d\n", ret);
d1016581 953 return ret;
8823f028
AP		 954}
955
92d20d9f 956static int rtl2832_deselect(struct i2c_adapter *adap, void *mux_priv,
d1016581 957 u32 chan_id)
92d20d9f 958{
038c6f24 959 struct rtl2832_dev *dev = mux_priv;
6e6aac65 960
038c6f24 961 schedule_delayed_work(&dev->i2c_gate_work, usecs_to_jiffies(100));
92d20d9f
AP		 962 return 0;
963}
964
82041c0a
TM		 965static struct dvb_frontend_ops rtl2832_ops = {
966 .delsys = { SYS_DVBT },
967 .info = {
968 .name = "Realtek RTL2832 (DVB-T)",
969 .frequency_min = 174000000,
970 .frequency_max = 862000000,
971 .frequency_stepsize = 166667,
972 .caps = FE_CAN_FEC_1_2 |
973 FE_CAN_FEC_2_3 |
974 FE_CAN_FEC_3_4 |
975 FE_CAN_FEC_5_6 |
976 FE_CAN_FEC_7_8 |
977 FE_CAN_FEC_AUTO |
978 FE_CAN_QPSK |
979 FE_CAN_QAM_16 |
980 FE_CAN_QAM_64 |
981 FE_CAN_QAM_AUTO |
982 FE_CAN_TRANSMISSION_MODE_AUTO |
983 FE_CAN_GUARD_INTERVAL_AUTO |
984 FE_CAN_HIERARCHY_AUTO |
985 FE_CAN_RECOVER |
986 FE_CAN_MUTE_TS
987 },
988
82041c0a
TM		 989 .init = rtl2832_init,
990 .sleep = rtl2832_sleep,
991
992 .get_tune_settings = rtl2832_get_tune_settings,
993
994 .set_frontend = rtl2832_set_frontend,
0ce67a2a 995 .get_frontend = rtl2832_get_frontend,
82041c0a
TM		 996
997 .read_status = rtl2832_read_status,
73983497 998 .read_snr = rtl2832_read_snr,
db32d74a 999 .read_ber = rtl2832_read_ber,
73983497 1000
82041c0a
TM		 1001 .i2c_gate_ctrl = rtl2832_i2c_gate_ctrl,
1002};
1003
d1016581
AP		 1004/*
1005 * We implement own I2C access routines for regmap in order to get manual access
1006 * to I2C adapter lock, which is needed for I2C mux adapter.
1007 */
1008static int rtl2832_regmap_read(void *context, const void *reg_buf,
1009 size_t reg_size, void *val_buf, size_t val_size)
1010{
1011 struct i2c_client *client = context;
1012 int ret;
1013 struct i2c_msg msg[2] = {
1014 {
1015 .addr = client->addr,
1016 .flags = 0,
1017 .len = reg_size,
1018 .buf = (u8 *)reg_buf,
1019 }, {
1020 .addr = client->addr,
1021 .flags = I2C_M_RD,
1022 .len = val_size,
1023 .buf = val_buf,
1024 }
1025 };
1026
1027 ret = __i2c_transfer(client->adapter, msg, 2);
1028 if (ret != 2) {
1029 dev_warn(&client->dev, "i2c reg read failed %d\n", ret);
1030 if (ret >= 0)
1031 ret = -EREMOTEIO;
1032 return ret;
1033 }
1034 return 0;
1035}
1036
1037static int rtl2832_regmap_write(void *context, const void *data, size_t count)
1038{
1039 struct i2c_client *client = context;
1040 int ret;
1041 struct i2c_msg msg[1] = {
1042 {
1043 .addr = client->addr,
1044 .flags = 0,
1045 .len = count,
1046 .buf = (u8 *)data,
1047 }
1048 };
1049
1050 ret = __i2c_transfer(client->adapter, msg, 1);
1051 if (ret != 1) {
1052 dev_warn(&client->dev, "i2c reg write failed %d\n", ret);
1053 if (ret >= 0)
1054 ret = -EREMOTEIO;
1055 return ret;
1056 }
1057 return 0;
1058}
1059
1060static int rtl2832_regmap_gather_write(void *context, const void *reg,
1061 size_t reg_len, const void *val,
1062 size_t val_len)
1063{
1064 struct i2c_client *client = context;
1065 int ret;
1066 u8 buf[256];
1067 struct i2c_msg msg[1] = {
1068 {
1069 .addr = client->addr,
1070 .flags = 0,
1071 .len = 1 + val_len,
1072 .buf = buf,
1073 }
1074 };
1075
1076 buf[0] = *(u8 const *)reg;
1077 memcpy(&buf[1], val, val_len);
1078
1079 ret = __i2c_transfer(client->adapter, msg, 1);
1080 if (ret != 1) {
1081 dev_warn(&client->dev, "i2c reg write failed %d\n", ret);
1082 if (ret >= 0)
1083 ret = -EREMOTEIO;
1084 return ret;
1085 }
1086 return 0;
1087}
1088
6f5f6ee2
AP		 1089static struct dvb_frontend *rtl2832_get_dvb_frontend(struct i2c_client *client)
1090{
038c6f24 1091 struct rtl2832_dev *dev = i2c_get_clientdata(client);
6f5f6ee2
AP		 1092
1093 dev_dbg(&client->dev, "\n");
1094 return &dev->fe;
1095}
1096
1097static struct i2c_adapter *rtl2832_get_i2c_adapter_(struct i2c_client *client)
1098{
038c6f24 1099 struct rtl2832_dev *dev = i2c_get_clientdata(client);
6f5f6ee2
AP		 1100
1101 dev_dbg(&client->dev, "\n");
1102 return dev->i2c_adapter_tuner;
1103}
1104
1105static struct i2c_adapter *rtl2832_get_private_i2c_adapter_(struct i2c_client *client)
1106{
038c6f24 1107 struct rtl2832_dev *dev = i2c_get_clientdata(client);
6f5f6ee2
AP		 1108
1109 dev_dbg(&client->dev, "\n");
1110 return dev->i2c_adapter;
1111}
1112
1113static int rtl2832_enable_slave_ts(struct i2c_client *client)
1114{
038c6f24 1115 struct rtl2832_dev *dev = i2c_get_clientdata(client);
6f5f6ee2
AP		 1116 int ret;
1117
6e6aac65 1118 dev_dbg(&client->dev, "\n");
6f5f6ee2
AP		 1119
1120 ret = rtl2832_wr_regs(dev, 0x0c, 1, "\x5f\xff", 2);
1121 if (ret)
1122 goto err;
1123
1124 ret = rtl2832_wr_demod_reg(dev, DVBT_PIP_ON, 0x1);
1125 if (ret)
1126 goto err;
1127
1128 ret = rtl2832_wr_reg(dev, 0xbc, 0, 0x18);
1129 if (ret)
1130 goto err;
1131
1132 ret = rtl2832_wr_reg(dev, 0x22, 0, 0x01);
1133 if (ret)
1134 goto err;
1135
1136 ret = rtl2832_wr_reg(dev, 0x26, 0, 0x1f);
1137 if (ret)
1138 goto err;
1139
1140 ret = rtl2832_wr_reg(dev, 0x27, 0, 0xff);
1141 if (ret)
1142 goto err;
1143
1144 ret = rtl2832_wr_regs(dev, 0x92, 1, "\x7f\xf7\xff", 3);
1145 if (ret)
1146 goto err;
1147
1148 /* soft reset */
1149 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
1150 if (ret)
1151 goto err;
1152
1153 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
1154 if (ret)
1155 goto err;
1156
1157 return 0;
1158err:
1159 dev_dbg(&client->dev, "failed=%d\n", ret);
1160 return ret;
1161}
1162
c2c8386f
AP		 1163static int rtl2832_probe(struct i2c_client *client,
1164 const struct i2c_device_id *id)
1165{
1166 struct rtl2832_platform_data *pdata = client->dev.platform_data;
c2c8386f 1167 struct i2c_adapter *i2c = client->adapter;
038c6f24 1168 struct rtl2832_dev *dev;
c2c8386f
AP		 1169 int ret;
1170 u8 tmp;
d1016581
AP		 1171 static const struct regmap_bus regmap_bus = {
1172 .read = rtl2832_regmap_read,
1173 .write = rtl2832_regmap_write,
1174 .gather_write = rtl2832_regmap_gather_write,
1175 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
1176 };
1177 static const struct regmap_range_cfg regmap_range_cfg[] = {
1178 {
1179 .selector_reg = 0x00,
1180 .selector_mask = 0xff,
1181 .selector_shift = 0,
1182 .window_start = 0,
1183 .window_len = 0x100,
1184 .range_min = 0 * 0x100,
1185 .range_max = 5 * 0x100,
1186 },
1187 };
1188 static const struct regmap_config regmap_config = {
1189 .reg_bits = 8,
1190 .val_bits = 8,
1191 .max_register = 5 * 0x100,
1192 .ranges = regmap_range_cfg,
1193 .num_ranges = ARRAY_SIZE(regmap_range_cfg),
1194 };
c2c8386f
AP		 1195
1196 dev_dbg(&client->dev, "\n");
1197
c2c8386f 1198 /* allocate memory for the internal state */
038c6f24
AP		 1199 dev = kzalloc(sizeof(struct rtl2832_dev), GFP_KERNEL);
1200 if (dev == NULL) {
c2c8386f
AP		 1201 ret = -ENOMEM;
1202 goto err;
1203 }
1204
038c6f24 1205 /* setup the state */
d1016581 1206 i2c_set_clientdata(client, dev);
038c6f24 1207 dev->client = client;
e1174d78
AP		 1208 dev->pdata = client->dev.platform_data;
1209 if (pdata->config) {
1210 dev->pdata->clk = pdata->config->xtal;
1211 dev->pdata->tuner = pdata->config->tuner;
1212 }
038c6f24 1213 dev->sleeping = true;
038c6f24 1214 INIT_DELAYED_WORK(&dev->i2c_gate_work, rtl2832_i2c_gate_work);
19d273d6 1215 INIT_DELAYED_WORK(&dev->stat_work, rtl2832_stat_work);
d1016581
AP		 1216 /* create regmap */
1217 dev->regmap = regmap_init(&client->dev, &regmap_bus, client,
1218 &regmap_config);
1219 if (IS_ERR(dev->regmap)) {
1220 ret = PTR_ERR(dev->regmap);
1221 goto err_kfree;
1222 }
c2c8386f 1223 /* create muxed i2c adapter for demod itself */
038c6f24 1224 dev->i2c_adapter = i2c_add_mux_adapter(i2c, &i2c->dev, dev, 0, 0, 0,
c2c8386f 1225 rtl2832_select, NULL);
038c6f24 1226 if (dev->i2c_adapter == NULL) {
c2c8386f 1227 ret = -ENODEV;
d1016581 1228 goto err_regmap_exit;
c2c8386f
AP		 1229 }
1230
1231 /* check if the demod is there */
038c6f24 1232 ret = rtl2832_rd_reg(dev, 0x00, 0x0, &tmp);
c2c8386f
AP		 1233 if (ret)
1234 goto err_i2c_del_mux_adapter;
1235
1236 /* create muxed i2c adapter for demod tuner bus */
038c6f24 1237 dev->i2c_adapter_tuner = i2c_add_mux_adapter(i2c, &i2c->dev, dev,
c2c8386f 1238 0, 1, 0, rtl2832_select, rtl2832_deselect);
038c6f24 1239 if (dev->i2c_adapter_tuner == NULL) {
c2c8386f
AP		 1240 ret = -ENODEV;
1241 goto err_i2c_del_mux_adapter;
1242 }
1243
1244 /* create dvb_frontend */
038c6f24
AP		 1245 memcpy(&dev->fe.ops, &rtl2832_ops, sizeof(struct dvb_frontend_ops));
1246 dev->fe.demodulator_priv = dev;
6f5f6ee2
AP		 1247
1248 /* setup callbacks */
1249 pdata->get_dvb_frontend = rtl2832_get_dvb_frontend;
1250 pdata->get_i2c_adapter = rtl2832_get_i2c_adapter_;
1251 pdata->get_private_i2c_adapter = rtl2832_get_private_i2c_adapter_;
1252 pdata->enable_slave_ts = rtl2832_enable_slave_ts;
c2c8386f
AP		 1253
1254 dev_info(&client->dev, "Realtek RTL2832 successfully attached\n");
1255 return 0;
1256err_i2c_del_mux_adapter:
038c6f24 1257 i2c_del_mux_adapter(dev->i2c_adapter);
d1016581
AP		 1258err_regmap_exit:
1259 regmap_exit(dev->regmap);
c2c8386f 1260err_kfree:
038c6f24 1261 kfree(dev);
c2c8386f
AP		 1262err:
1263 dev_dbg(&client->dev, "failed=%d\n", ret);
1264 return ret;
1265}
1266
1267static int rtl2832_remove(struct i2c_client *client)
1268{
038c6f24 1269 struct rtl2832_dev *dev = i2c_get_clientdata(client);
c2c8386f
AP		 1270
1271 dev_dbg(&client->dev, "\n");
1272
038c6f24 1273 cancel_delayed_work_sync(&dev->i2c_gate_work);
c2c8386f 1274
038c6f24 1275 i2c_del_mux_adapter(dev->i2c_adapter_tuner);
c2c8386f 1276
038c6f24 1277 i2c_del_mux_adapter(dev->i2c_adapter);
c2c8386f 1278
d1016581
AP		 1279 regmap_exit(dev->regmap);
1280
038c6f24 1281 kfree(dev);
c2c8386f
AP		 1282
1283 return 0;
1284}
1285
1286static const struct i2c_device_id rtl2832_id_table[] = {
1287 {"rtl2832", 0},
1288 {}
1289};
1290MODULE_DEVICE_TABLE(i2c, rtl2832_id_table);
1291
1292static struct i2c_driver rtl2832_driver = {
1293 .driver = {
1294 .owner = THIS_MODULE,
1295 .name = "rtl2832",
1296 },
1297 .probe = rtl2832_probe,
1298 .remove = rtl2832_remove,
1299 .id_table = rtl2832_id_table,
1300};
1301
1302module_i2c_driver(rtl2832_driver);
1303
82041c0a
TM		 1304MODULE_AUTHOR("Thomas Mair <mair.thomas86@gmail.com>");
1305MODULE_DESCRIPTION("Realtek RTL2832 DVB-T demodulator driver");
1306MODULE_LICENSE("GPL");
1307MODULE_VERSION("0.5");
Linux 6.x block layer and io_uring tree(s)