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media: dvb-frontends/mxl5xx: cleanup and fix licensing boilerplates
[linux-2.6-block.git] / drivers / media / dvb-frontends / mxl5xx.c
CommitLineData
3c4e0415
DS		 1/*
2 * Driver for the MaxLinear MxL5xx family of tuners/demods
3 *
4 * Copyright (C) 2014-2015 Ralph Metzler <rjkm@metzlerbros.de>
5 * Marcus Metzler <mocm@metzlerbros.de>
6 * developed for Digital Devices GmbH
7 *
8 * based on code:
9 * Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved
10 * which was released under GPL V2
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * version 2, as published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
3c4e0415
DS		 20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/firmware.h>
28#include <linux/i2c.h>
29#include <linux/version.h>
30#include <linux/mutex.h>
31#include <linux/vmalloc.h>
32#include <asm/div64.h>
33#include <asm/unaligned.h>
34
fada1935 35#include <media/dvb_frontend.h>
3c4e0415
DS		 36#include "mxl5xx.h"
37#include "mxl5xx_regs.h"
38#include "mxl5xx_defs.h"
39
40#define BYTE0(v) ((v >> 0) & 0xff)
41#define BYTE1(v) ((v >> 8) & 0xff)
42#define BYTE2(v) ((v >> 16) & 0xff)
43#define BYTE3(v) ((v >> 24) & 0xff)
44
f71c4306 45static LIST_HEAD(mxllist);
3c4e0415
DS		 46
47struct mxl_base {
48 struct list_head mxllist;
49 struct list_head mxls;
50
51 u8 adr;
52 struct i2c_adapter *i2c;
53
54 u32 count;
55 u32 type;
56 u32 sku_type;
57 u32 chipversion;
58 u32 clock;
59 u32 fwversion;
60
61 u8 *ts_map;
62 u8 can_clkout;
63 u8 chan_bond;
64 u8 demod_num;
65 u8 tuner_num;
66
67 unsigned long next_tune;
68
69 struct mutex i2c_lock;
70 struct mutex status_lock;
71 struct mutex tune_lock;
72
73 u8 buf[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN];
74
75 u32 cmd_size;
76 u8 cmd_data[MAX_CMD_DATA];
77};
78
79struct mxl {
80 struct list_head mxl;
81
82 struct mxl_base *base;
83 struct dvb_frontend fe;
84 struct device *i2cdev;
85 u32 demod;
86 u32 tuner;
87 u32 tuner_in_use;
88 u8 xbar[3];
89
90 unsigned long tune_time;
91};
92
93static void convert_endian(u8 flag, u32 size, u8 *d)
94{
95 u32 i;
96
97 if (!flag)
98 return;
99 for (i = 0; i < (size & ~3); i += 4) {
100 d[i + 0] ^= d[i + 3];
101 d[i + 3] ^= d[i + 0];
102 d[i + 0] ^= d[i + 3];
103
104 d[i + 1] ^= d[i + 2];
105 d[i + 2] ^= d[i + 1];
106 d[i + 1] ^= d[i + 2];
107 }
108
109 switch (size & 3) {
110 case 0:
111 case 1:
112 /* do nothing */
113 break;
114 case 2:
115 d[i + 0] ^= d[i + 1];
116 d[i + 1] ^= d[i + 0];
117 d[i + 0] ^= d[i + 1];
118 break;
119
120 case 3:
121 d[i + 0] ^= d[i + 2];
122 d[i + 2] ^= d[i + 0];
123 d[i + 0] ^= d[i + 2];
124 break;
125 }
126
127}
128
129static int i2c_write(struct i2c_adapter *adap, u8 adr,
130 u8 *data, u32 len)
131{
132 struct i2c_msg msg = {.addr = adr, .flags = 0,
133 .buf = data, .len = len};
134
135 return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1;
136}
137
138static int i2c_read(struct i2c_adapter *adap, u8 adr,
139 u8 *data, u32 len)
140{
141 struct i2c_msg msg = {.addr = adr, .flags = I2C_M_RD,
142 .buf = data, .len = len};
143
144 return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1;
145}
146
147static int i2cread(struct mxl *state, u8 *data, int len)
148{
149 return i2c_read(state->base->i2c, state->base->adr, data, len);
150}
151
152static int i2cwrite(struct mxl *state, u8 *data, int len)
153{
154 return i2c_write(state->base->i2c, state->base->adr, data, len);
155}
156
157static int read_register_unlocked(struct mxl *state, u32 reg, u32 *val)
158{
159 int stat;
160 u8 data[MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE] = {
161 MXL_HYDRA_PLID_REG_READ, 0x04,
162 GET_BYTE(reg, 0), GET_BYTE(reg, 1),
163 GET_BYTE(reg, 2), GET_BYTE(reg, 3),
164 };
165
166 stat = i2cwrite(state, data,
167 MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE);
168 if (stat)
169 dev_err(state->i2cdev, "i2c read error 1\n");
170 if (!stat)
171 stat = i2cread(state, (u8 *) val,
172 MXL_HYDRA_REG_SIZE_IN_BYTES);
173 le32_to_cpus(val);
174 if (stat)
175 dev_err(state->i2cdev, "i2c read error 2\n");
176 return stat;
177}
178
179#define DMA_I2C_INTERRUPT_ADDR 0x8000011C
180#define DMA_INTR_PROT_WR_CMP 0x08
181
182static int send_command(struct mxl *state, u32 size, u8 *buf)
183{
184 int stat;
185 u32 val, count = 10;
186
187 mutex_lock(&state->base->i2c_lock);
188 if (state->base->fwversion > 0x02010109) {
189 read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR, &val);
190 if (DMA_INTR_PROT_WR_CMP & val)
191 dev_info(state->i2cdev, "%s busy\n", __func__);
192 while ((DMA_INTR_PROT_WR_CMP & val) && --count) {
193 mutex_unlock(&state->base->i2c_lock);
194 usleep_range(1000, 2000);
195 mutex_lock(&state->base->i2c_lock);
196 read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR,
197 &val);
198 }
199 if (!count) {
200 dev_info(state->i2cdev, "%s busy\n", __func__);
201 mutex_unlock(&state->base->i2c_lock);
202 return -EBUSY;
203 }
204 }
205 stat = i2cwrite(state, buf, size);
206 mutex_unlock(&state->base->i2c_lock);
207 return stat;
208}
209
210static int write_register(struct mxl *state, u32 reg, u32 val)
211{
212 int stat;
213 u8 data[MXL_HYDRA_REG_WRITE_LEN] = {
214 MXL_HYDRA_PLID_REG_WRITE, 0x08,
215 BYTE0(reg), BYTE1(reg), BYTE2(reg), BYTE3(reg),
216 BYTE0(val), BYTE1(val), BYTE2(val), BYTE3(val),
217 };
218 mutex_lock(&state->base->i2c_lock);
219 stat = i2cwrite(state, data, sizeof(data));
220 mutex_unlock(&state->base->i2c_lock);
221 if (stat)
222 dev_err(state->i2cdev, "i2c write error\n");
223 return stat;
224}
225
226static int write_firmware_block(struct mxl *state,
227 u32 reg, u32 size, u8 *reg_data_ptr)
228{
229 int stat;
230 u8 *buf = state->base->buf;
231
232 mutex_lock(&state->base->i2c_lock);
233 buf[0] = MXL_HYDRA_PLID_REG_WRITE;
234 buf[1] = size + 4;
235 buf[2] = GET_BYTE(reg, 0);
236 buf[3] = GET_BYTE(reg, 1);
237 buf[4] = GET_BYTE(reg, 2);
238 buf[5] = GET_BYTE(reg, 3);
239 memcpy(&buf[6], reg_data_ptr, size);
240 stat = i2cwrite(state, buf,
241 MXL_HYDRA_I2C_HDR_SIZE +
242 MXL_HYDRA_REG_SIZE_IN_BYTES + size);
243 mutex_unlock(&state->base->i2c_lock);
244 if (stat)
245 dev_err(state->i2cdev, "fw block write failed\n");
246 return stat;
247}
248
249static int read_register(struct mxl *state, u32 reg, u32 *val)
250{
251 int stat;
252 u8 data[MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE] = {
253 MXL_HYDRA_PLID_REG_READ, 0x04,
254 GET_BYTE(reg, 0), GET_BYTE(reg, 1),
255 GET_BYTE(reg, 2), GET_BYTE(reg, 3),
256 };
257
258 mutex_lock(&state->base->i2c_lock);
259 stat = i2cwrite(state, data,
260 MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE);
261 if (stat)
262 dev_err(state->i2cdev, "i2c read error 1\n");
263 if (!stat)
264 stat = i2cread(state, (u8 *) val,
265 MXL_HYDRA_REG_SIZE_IN_BYTES);
266 mutex_unlock(&state->base->i2c_lock);
267 le32_to_cpus(val);
268 if (stat)
269 dev_err(state->i2cdev, "i2c read error 2\n");
270 return stat;
271}
272
273static int read_register_block(struct mxl *state, u32 reg, u32 size, u8 *data)
274{
275 int stat;
276 u8 *buf = state->base->buf;
277
278 mutex_lock(&state->base->i2c_lock);
279
280 buf[0] = MXL_HYDRA_PLID_REG_READ;
281 buf[1] = size + 4;
282 buf[2] = GET_BYTE(reg, 0);
283 buf[3] = GET_BYTE(reg, 1);
284 buf[4] = GET_BYTE(reg, 2);
285 buf[5] = GET_BYTE(reg, 3);
286 stat = i2cwrite(state, buf,
287 MXL_HYDRA_I2C_HDR_SIZE + MXL_HYDRA_REG_SIZE_IN_BYTES);
288 if (!stat) {
289 stat = i2cread(state, data, size);
290 convert_endian(MXL_ENABLE_BIG_ENDIAN, size, data);
291 }
292 mutex_unlock(&state->base->i2c_lock);
293 return stat;
294}
295
296static int read_by_mnemonic(struct mxl *state,
297 u32 reg, u8 lsbloc, u8 numofbits, u32 *val)
298{
299 u32 data = 0, mask = 0;
300 int stat;
301
302 stat = read_register(state, reg, &data);
303 if (stat)
304 return stat;
305 mask = MXL_GET_REG_MASK_32(lsbloc, numofbits);
306 data &= mask;
307 data >>= lsbloc;
308 *val = data;
309 return 0;
310}
311
312
313static int update_by_mnemonic(struct mxl *state,
314 u32 reg, u8 lsbloc, u8 numofbits, u32 val)
315{
316 u32 data, mask;
317 int stat;
318
319 stat = read_register(state, reg, &data);
320 if (stat)
321 return stat;
322 mask = MXL_GET_REG_MASK_32(lsbloc, numofbits);
323 data = (data & ~mask) | ((val << lsbloc) & mask);
324 stat = write_register(state, reg, data);
325 return stat;
326}
327
328static int firmware_is_alive(struct mxl *state)
329{
330 u32 hb0, hb1;
331
332 if (read_register(state, HYDRA_HEAR_BEAT, &hb0))
333 return 0;
334 msleep(20);
335 if (read_register(state, HYDRA_HEAR_BEAT, &hb1))
336 return 0;
337 if (hb1 == hb0)
338 return 0;
339 return 1;
340}
341
342static int init(struct dvb_frontend *fe)
343{
344 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
345
346 /* init fe stats */
347 p->strength.len = 1;
348 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
349 p->cnr.len = 1;
350 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
351 p->pre_bit_error.len = 1;
352 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
353 p->pre_bit_count.len = 1;
354 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
355 p->post_bit_error.len = 1;
356 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
357 p->post_bit_count.len = 1;
358 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
359
360 return 0;
361}
362
363static void release(struct dvb_frontend *fe)
364{
365 struct mxl *state = fe->demodulator_priv;
366
367 list_del(&state->mxl);
368 /* Release one frontend, two more shall take its place! */
369 state->base->count--;
370 if (state->base->count == 0) {
371 list_del(&state->base->mxllist);
372 kfree(state->base);
373 }
374 kfree(state);
375}
376
8d718e53 377static enum dvbfe_algo get_algo(struct dvb_frontend *fe)
3c4e0415
DS		 378{
379 return DVBFE_ALGO_HW;
380}
381
62474660
DS		 382static u32 gold2root(u32 gold)
383{
384 u32 x, g, tmp = gold;
385
386 if (tmp >= 0x3ffff)
387 tmp = 0;
388 for (g = 0, x = 1; g < tmp; g++)
389 x = (((x ^ (x >> 7)) & 1) << 17) | (x >> 1);
390 return x;
391}
392
393static int cfg_scrambler(struct mxl *state, u32 gold)
394{
395 u32 root;
396 u8 buf[26] = {
397 MXL_HYDRA_PLID_CMD_WRITE, 24,
398 0, MXL_HYDRA_DEMOD_SCRAMBLE_CODE_CMD, 0, 0,
399 state->demod, 0, 0, 0,
400 0, 0, 0, 0, 0, 0, 0, 0,
401 0, 0, 0, 0, 1, 0, 0, 0,
402 };
403
404 root = gold2root(gold);
405
406 buf[25] = (root >> 24) & 0xff;
407 buf[24] = (root >> 16) & 0xff;
408 buf[23] = (root >> 8) & 0xff;
409 buf[22] = root & 0xff;
410
411 return send_command(state, sizeof(buf), buf);
412}
413
3c4e0415
DS		 414static int cfg_demod_abort_tune(struct mxl *state)
415{
416 struct MXL_HYDRA_DEMOD_ABORT_TUNE_T abort_tune_cmd;
417 u8 cmd_size = sizeof(abort_tune_cmd);
418 u8 cmd_buff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN];
419
420 abort_tune_cmd.demod_id = state->demod;
421 BUILD_HYDRA_CMD(MXL_HYDRA_ABORT_TUNE_CMD, MXL_CMD_WRITE,
422 cmd_size, &abort_tune_cmd, cmd_buff);
423 return send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
424 &cmd_buff[0]);
425}
426
427static int send_master_cmd(struct dvb_frontend *fe,
428 struct dvb_diseqc_master_cmd *cmd)
429{
430 /*struct mxl *state = fe->demodulator_priv;*/
431
432 return 0; /*CfgDemodAbortTune(state);*/
433}
434
435static int set_parameters(struct dvb_frontend *fe)
436{
437 struct mxl *state = fe->demodulator_priv;
438 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
439 struct MXL_HYDRA_DEMOD_PARAM_T demod_chan_cfg;
440 u8 cmd_size = sizeof(demod_chan_cfg);
441 u8 cmd_buff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN];
442 u32 srange = 10;
443 int stat;
444
445 if (p->frequency < 950000 || p->frequency > 2150000)
446 return -EINVAL;
447 if (p->symbol_rate < 1000000 || p->symbol_rate > 45000000)
448 return -EINVAL;
449
450 /* CfgDemodAbortTune(state); */
451
452 switch (p->delivery_system) {
453 case SYS_DSS:
454 demod_chan_cfg.standard = MXL_HYDRA_DSS;
455 demod_chan_cfg.roll_off = MXL_HYDRA_ROLLOFF_AUTO;
456 break;
457 case SYS_DVBS:
458 srange = p->symbol_rate / 1000000;
459 if (srange > 10)
460 srange = 10;
461 demod_chan_cfg.standard = MXL_HYDRA_DVBS;
462 demod_chan_cfg.roll_off = MXL_HYDRA_ROLLOFF_0_35;
463 demod_chan_cfg.modulation_scheme = MXL_HYDRA_MOD_QPSK;
464 demod_chan_cfg.pilots = MXL_HYDRA_PILOTS_OFF;
465 break;
466 case SYS_DVBS2:
467 demod_chan_cfg.standard = MXL_HYDRA_DVBS2;
468 demod_chan_cfg.roll_off = MXL_HYDRA_ROLLOFF_AUTO;
469 demod_chan_cfg.modulation_scheme = MXL_HYDRA_MOD_AUTO;
470 demod_chan_cfg.pilots = MXL_HYDRA_PILOTS_AUTO;
62474660 471 cfg_scrambler(state, p->scrambling_sequence_index);
3c4e0415
DS		 472 break;
473 default:
474 return -EINVAL;
475 }
476 demod_chan_cfg.tuner_index = state->tuner;
477 demod_chan_cfg.demod_index = state->demod;
478 demod_chan_cfg.frequency_in_hz = p->frequency * 1000;
479 demod_chan_cfg.symbol_rate_in_hz = p->symbol_rate;
480 demod_chan_cfg.max_carrier_offset_in_mhz = srange;
481 demod_chan_cfg.spectrum_inversion = MXL_HYDRA_SPECTRUM_AUTO;
482 demod_chan_cfg.fec_code_rate = MXL_HYDRA_FEC_AUTO;
483
484 mutex_lock(&state->base->tune_lock);
485 if (time_after(jiffies + msecs_to_jiffies(200),
486 state->base->next_tune))
487 while (time_before(jiffies, state->base->next_tune))
488 usleep_range(10000, 11000);
489 state->base->next_tune = jiffies + msecs_to_jiffies(100);
490 state->tuner_in_use = state->tuner;
491 BUILD_HYDRA_CMD(MXL_HYDRA_DEMOD_SET_PARAM_CMD, MXL_CMD_WRITE,
492 cmd_size, &demod_chan_cfg, cmd_buff);
493 stat = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
494 &cmd_buff[0]);
495 mutex_unlock(&state->base->tune_lock);
496 return stat;
497}
498
499static int enable_tuner(struct mxl *state, u32 tuner, u32 enable);
500
501static int sleep(struct dvb_frontend *fe)
502{
503 struct mxl *state = fe->demodulator_priv;
504 struct mxl *p;
505
506 cfg_demod_abort_tune(state);
507 if (state->tuner_in_use != 0xffffffff) {
508 mutex_lock(&state->base->tune_lock);
509 state->tuner_in_use = 0xffffffff;
510 list_for_each_entry(p, &state->base->mxls, mxl) {
511 if (p->tuner_in_use == state->tuner)
512 break;
513 }
514 if (&p->mxl == &state->base->mxls)
515 enable_tuner(state, state->tuner, 0);
516 mutex_unlock(&state->base->tune_lock);
517 }
518 return 0;
519}
520
521static int read_snr(struct dvb_frontend *fe)
522{
523 struct mxl *state = fe->demodulator_priv;
524 int stat;
525 u32 reg_data = 0;
526 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
527
528 mutex_lock(&state->base->status_lock);
529 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
530 stat = read_register(state, (HYDRA_DMD_SNR_ADDR_OFFSET +
531 HYDRA_DMD_STATUS_OFFSET(state->demod)),
532 &reg_data);
533 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
534 mutex_unlock(&state->base->status_lock);
535
536 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
537 p->cnr.stat[0].svalue = (s16)reg_data * 10;
538
539 return stat;
540}
541
542static int read_ber(struct dvb_frontend *fe)
543{
544 struct mxl *state = fe->demodulator_priv;
545 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
546 u32 reg[8];
547
548 mutex_lock(&state->base->status_lock);
549 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
550 read_register_block(state,
551 (HYDRA_DMD_DVBS_1ST_CORR_RS_ERRORS_ADDR_OFFSET +
552 HYDRA_DMD_STATUS_OFFSET(state->demod)),
553 (4 * sizeof(u32)),
554 (u8 *) &reg[0]);
555 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
556
557 switch (p->delivery_system) {
558 case SYS_DSS:
559 case SYS_DVBS:
560 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
561 p->pre_bit_error.stat[0].uvalue = reg[2];
562 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
563 p->pre_bit_count.stat[0].uvalue = reg[3];
564 break;
565 default:
566 break;
567 }
568
569 read_register_block(state,
570 (HYDRA_DMD_DVBS2_CRC_ERRORS_ADDR_OFFSET +
571 HYDRA_DMD_STATUS_OFFSET(state->demod)),
572 (7 * sizeof(u32)),
573 (u8 *) &reg[0]);
574
575 switch (p->delivery_system) {
576 case SYS_DSS:
577 case SYS_DVBS:
578 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
579 p->post_bit_error.stat[0].uvalue = reg[5];
580 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
581 p->post_bit_count.stat[0].uvalue = reg[6];
582 break;
583 case SYS_DVBS2:
584 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
585 p->post_bit_error.stat[0].uvalue = reg[1];
586 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
587 p->post_bit_count.stat[0].uvalue = reg[2];
588 break;
589 default:
590 break;
591 }
592
593 mutex_unlock(&state->base->status_lock);
594
595 return 0;
596}
597
598static int read_signal_strength(struct dvb_frontend *fe)
599{
600 struct mxl *state = fe->demodulator_priv;
601 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
602 int stat;
603 u32 reg_data = 0;
604
605 mutex_lock(&state->base->status_lock);
606 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
607 stat = read_register(state, (HYDRA_DMD_STATUS_INPUT_POWER_ADDR +
608 HYDRA_DMD_STATUS_OFFSET(state->demod)),
609 &reg_data);
610 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
611 mutex_unlock(&state->base->status_lock);
612
613 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
614 p->strength.stat[0].svalue = (s16) reg_data * 10; /* fix scale */
615
616 return stat;
617}
618
619static int read_status(struct dvb_frontend *fe, enum fe_status *status)
620{
621 struct mxl *state = fe->demodulator_priv;
622 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
623 u32 reg_data = 0;
624
625 mutex_lock(&state->base->status_lock);
626 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
627 read_register(state, (HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET +
628 HYDRA_DMD_STATUS_OFFSET(state->demod)),
629 &reg_data);
630 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
631 mutex_unlock(&state->base->status_lock);
632
633 *status = (reg_data == 1) ? 0x1f : 0;
634
635 /* signal statistics */
636
637 /* signal strength is always available */
638 read_signal_strength(fe);
639
640 if (*status & FE_HAS_CARRIER)
641 read_snr(fe);
642 else
643 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
644
645 if (*status & FE_HAS_SYNC)
646 read_ber(fe);
647 else {
648 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
649 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
650 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
651 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
652 }
653
654 return 0;
655}
656
657static int tune(struct dvb_frontend *fe, bool re_tune,
658 unsigned int mode_flags,
659 unsigned int *delay, enum fe_status *status)
660{
661 struct mxl *state = fe->demodulator_priv;
662 int r = 0;
663
664 *delay = HZ / 2;
665 if (re_tune) {
666 r = set_parameters(fe);
667 if (r)
668 return r;
669 state->tune_time = jiffies;
3c4e0415 670 }
3c4e0415 671
2919d12d 672 return read_status(fe, status);
3c4e0415
DS		 673}
674
675static enum fe_code_rate conv_fec(enum MXL_HYDRA_FEC_E fec)
676{
677 enum fe_code_rate fec2fec[11] = {
678 FEC_NONE, FEC_1_2, FEC_3_5, FEC_2_3,
679 FEC_3_4, FEC_4_5, FEC_5_6, FEC_6_7,
680 FEC_7_8, FEC_8_9, FEC_9_10
681 };
682
683 if (fec > MXL_HYDRA_FEC_9_10)
684 return FEC_NONE;
685 return fec2fec[fec];
686}
687
688static int get_frontend(struct dvb_frontend *fe,
689 struct dtv_frontend_properties *p)
690{
691 struct mxl *state = fe->demodulator_priv;
692 u32 reg_data[MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE];
693 u32 freq;
694
695 mutex_lock(&state->base->status_lock);
696 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
697 read_register_block(state,
698 (HYDRA_DMD_STANDARD_ADDR_OFFSET +
699 HYDRA_DMD_STATUS_OFFSET(state->demod)),
700 (MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE * 4), /* 25 * 4 bytes */
701 (u8 *) &reg_data[0]);
702 /* read demod channel parameters */
703 read_register_block(state,
704 (HYDRA_DMD_STATUS_CENTER_FREQ_IN_KHZ_ADDR +
705 HYDRA_DMD_STATUS_OFFSET(state->demod)),
706 (4), /* 4 bytes */
707 (u8 *) &freq);
708 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
709 mutex_unlock(&state->base->status_lock);
710
711 dev_dbg(state->i2cdev, "freq=%u delsys=%u srate=%u\n",
712 freq * 1000, reg_data[DMD_STANDARD_ADDR],
713 reg_data[DMD_SYMBOL_RATE_ADDR]);
714 p->symbol_rate = reg_data[DMD_SYMBOL_RATE_ADDR];
715 p->frequency = freq;
716 /*
717 * p->delivery_system =
718 * (MXL_HYDRA_BCAST_STD_E) regData[DMD_STANDARD_ADDR];
719 * p->inversion =
720 * (MXL_HYDRA_SPECTRUM_E) regData[DMD_SPECTRUM_INVERSION_ADDR];
721 * freqSearchRangeKHz =
722 * (regData[DMD_FREQ_SEARCH_RANGE_IN_KHZ_ADDR]);
723 */
724
725 p->fec_inner = conv_fec(reg_data[DMD_FEC_CODE_RATE_ADDR]);
726 switch (p->delivery_system) {
727 case SYS_DSS:
728 break;
729 case SYS_DVBS2:
730 switch ((enum MXL_HYDRA_PILOTS_E)
731 reg_data[DMD_DVBS2_PILOT_ON_OFF_ADDR]) {
732 case MXL_HYDRA_PILOTS_OFF:
733 p->pilot = PILOT_OFF;
734 break;
735 case MXL_HYDRA_PILOTS_ON:
736 p->pilot = PILOT_ON;
737 break;
738 default:
739 break;
740 }
741 case SYS_DVBS:
742 switch ((enum MXL_HYDRA_MODULATION_E)
743 reg_data[DMD_MODULATION_SCHEME_ADDR]) {
744 case MXL_HYDRA_MOD_QPSK:
745 p->modulation = QPSK;
746 break;
747 case MXL_HYDRA_MOD_8PSK:
748 p->modulation = PSK_8;
749 break;
750 default:
751 break;
752 }
753 switch ((enum MXL_HYDRA_ROLLOFF_E)
754 reg_data[DMD_SPECTRUM_ROLL_OFF_ADDR]) {
755 case MXL_HYDRA_ROLLOFF_0_20:
756 p->rolloff = ROLLOFF_20;
757 break;
758 case MXL_HYDRA_ROLLOFF_0_35:
759 p->rolloff = ROLLOFF_35;
760 break;
761 case MXL_HYDRA_ROLLOFF_0_25:
762 p->rolloff = ROLLOFF_25;
763 break;
764 default:
765 break;
766 }
767 break;
768 default:
769 return -EINVAL;
770 }
771 return 0;
772}
773
774static int set_input(struct dvb_frontend *fe, int input)
775{
776 struct mxl *state = fe->demodulator_priv;
777
778 state->tuner = input;
779 return 0;
780}
781
782static struct dvb_frontend_ops mxl_ops = {
783 .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
784 .info = {
785 .name = "MaxLinear MxL5xx DVB-S/S2 tuner-demodulator",
f1b1eabf
MCC		 786 .frequency_min_hz = 300 * MHz,
787 .frequency_max_hz = 2350 * MHz,
3c4e0415
DS		 788 .symbol_rate_min = 1000000,
789 .symbol_rate_max = 45000000,
790 .caps = FE_CAN_INVERSION_AUTO |
791 FE_CAN_FEC_AUTO |
792 FE_CAN_QPSK |
793 FE_CAN_2G_MODULATION
794 },
795 .init = init,
796 .release = release,
797 .get_frontend_algo = get_algo,
798 .tune = tune,
799 .read_status = read_status,
800 .sleep = sleep,
801 .get_frontend = get_frontend,
802 .diseqc_send_master_cmd = send_master_cmd,
803};
804
805static struct mxl_base *match_base(struct i2c_adapter *i2c, u8 adr)
806{
807 struct mxl_base *p;
808
809 list_for_each_entry(p, &mxllist, mxllist)
810 if (p->i2c == i2c && p->adr == adr)
811 return p;
812 return NULL;
813}
814
815static void cfg_dev_xtal(struct mxl *state, u32 freq, u32 cap, u32 enable)
816{
817 if (state->base->can_clkout || !enable)
818 update_by_mnemonic(state, 0x90200054, 23, 1, enable);
819
820 if (freq == 24000000)
821 write_register(state, HYDRA_CRYSTAL_SETTING, 0);
822 else
823 write_register(state, HYDRA_CRYSTAL_SETTING, 1);
824
825 write_register(state, HYDRA_CRYSTAL_CAP, cap);
826}
827
828static u32 get_big_endian(u8 num_of_bits, const u8 buf[])
829{
830 u32 ret_value = 0;
831
832 switch (num_of_bits) {
833 case 24:
834 ret_value = (((u32) buf[0]) << 16) |
835 (((u32) buf[1]) << 8) | buf[2];
836 break;
837 case 32:
838 ret_value = (((u32) buf[0]) << 24) |
839 (((u32) buf[1]) << 16) |
840 (((u32) buf[2]) << 8) | buf[3];
841 break;
842 default:
843 break;
844 }
845
846 return ret_value;
847}
848
849static int write_fw_segment(struct mxl *state,
850 u32 mem_addr, u32 total_size, u8 *data_ptr)
851{
852 int status;
853 u32 data_count = 0;
854 u32 size = 0;
855 u32 orig_size = 0;
856 u8 *w_buf_ptr = NULL;
857 u32 block_size = ((MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH -
858 (MXL_HYDRA_I2C_HDR_SIZE +
859 MXL_HYDRA_REG_SIZE_IN_BYTES)) / 4) * 4;
860 u8 w_msg_buffer[MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH -
861 (MXL_HYDRA_I2C_HDR_SIZE + MXL_HYDRA_REG_SIZE_IN_BYTES)];
862
863 do {
864 size = orig_size = (((u32)(data_count + block_size)) > total_size) ?
865 (total_size - data_count) : block_size;
866
867 if (orig_size & 3)
868 size = (orig_size + 4) & ~3;
869 w_buf_ptr = &w_msg_buffer[0];
870 memset((void *) w_buf_ptr, 0, size);
871 memcpy((void *) w_buf_ptr, (void *) data_ptr, orig_size);
872 convert_endian(1, size, w_buf_ptr);
873 status = write_firmware_block(state, mem_addr, size, w_buf_ptr);
874 if (status)
875 return status;
876 data_count += size;
877 mem_addr += size;
878 data_ptr += size;
879 } while (data_count < total_size);
880
881 return status;
882}
883
884static int do_firmware_download(struct mxl *state, u8 *mbin_buffer_ptr,
885 u32 mbin_buffer_size)
886
887{
888 int status;
889 u32 index = 0;
890 u32 seg_length = 0;
891 u32 seg_address = 0;
892 struct MBIN_FILE_T *mbin_ptr = (struct MBIN_FILE_T *)mbin_buffer_ptr;
893 struct MBIN_SEGMENT_T *segment_ptr;
894 enum MXL_BOOL_E xcpu_fw_flag = MXL_FALSE;
895
896 if (mbin_ptr->header.id != MBIN_FILE_HEADER_ID) {
897 dev_err(state->i2cdev, "%s: Invalid file header ID (%c)\n",
898 __func__, mbin_ptr->header.id);
899 return -EINVAL;
900 }
901 status = write_register(state, FW_DL_SIGN_ADDR, 0);
902 if (status)
903 return status;
904 segment_ptr = (struct MBIN_SEGMENT_T *) (&mbin_ptr->data[0]);
905 for (index = 0; index < mbin_ptr->header.num_segments; index++) {
906 if (segment_ptr->header.id != MBIN_SEGMENT_HEADER_ID) {
907 dev_err(state->i2cdev, "%s: Invalid segment header ID (%c)\n",
908 __func__, segment_ptr->header.id);
909 return -EINVAL;
910 }
911 seg_length = get_big_endian(24,
912 &(segment_ptr->header.len24[0]));
913 seg_address = get_big_endian(32,
914 &(segment_ptr->header.address[0]));
915
916 if (state->base->type == MXL_HYDRA_DEVICE_568) {
917 if ((((seg_address & 0x90760000) == 0x90760000) ||
918 ((seg_address & 0x90740000) == 0x90740000)) &&
919 (xcpu_fw_flag == MXL_FALSE)) {
920 update_by_mnemonic(state, 0x8003003C, 0, 1, 1);
921 msleep(200);
922 write_register(state, 0x90720000, 0);
923 usleep_range(10000, 11000);
924 xcpu_fw_flag = MXL_TRUE;
925 }
926 status = write_fw_segment(state, seg_address,
927 seg_length,
928 (u8 *) segment_ptr->data);
929 } else {
930 if (((seg_address & 0x90760000) != 0x90760000) &&
931 ((seg_address & 0x90740000) != 0x90740000))
932 status = write_fw_segment(state, seg_address,
933 seg_length, (u8 *) segment_ptr->data);
934 }
935 if (status)
936 return status;
937 segment_ptr = (struct MBIN_SEGMENT_T *)
938 &(segment_ptr->data[((seg_length + 3) / 4) * 4]);
939 }
940 return status;
941}
942
943static int check_fw(struct mxl *state, u8 *mbin, u32 mbin_len)
944{
945 struct MBIN_FILE_HEADER_T *fh = (struct MBIN_FILE_HEADER_T *) mbin;
946 u32 flen = (fh->image_size24[0] << 16) |
947 (fh->image_size24[1] << 8) | fh->image_size24[2];
948 u8 *fw, cs = 0;
949 u32 i;
950
951 if (fh->id != 'M' || fh->fmt_version != '1' || flen > 0x3FFF0) {
952 dev_info(state->i2cdev, "Invalid FW Header\n");
953 return -1;
954 }
955 fw = mbin + sizeof(struct MBIN_FILE_HEADER_T);
956 for (i = 0; i < flen; i += 1)
957 cs += fw[i];
958 if (cs != fh->image_checksum) {
959 dev_info(state->i2cdev, "Invalid FW Checksum\n");
960 return -1;
961 }
962 return 0;
963}
964
965static int firmware_download(struct mxl *state, u8 *mbin, u32 mbin_len)
966{
967 int status;
968 u32 reg_data = 0;
969 struct MXL_HYDRA_SKU_COMMAND_T dev_sku_cfg;
970 u8 cmd_size = sizeof(struct MXL_HYDRA_SKU_COMMAND_T);
971 u8 cmd_buff[sizeof(struct MXL_HYDRA_SKU_COMMAND_T) + 6];
972
973 if (check_fw(state, mbin, mbin_len))
974 return -1;
975
976 /* put CPU into reset */
977 status = update_by_mnemonic(state, 0x8003003C, 0, 1, 0);
978 if (status)
979 return status;
980 usleep_range(1000, 2000);
981
982 /* Reset TX FIFO's, BBAND, XBAR */
983 status = write_register(state, HYDRA_RESET_TRANSPORT_FIFO_REG,
984 HYDRA_RESET_TRANSPORT_FIFO_DATA);
985 if (status)
986 return status;
987 status = write_register(state, HYDRA_RESET_BBAND_REG,
988 HYDRA_RESET_BBAND_DATA);
989 if (status)
990 return status;
991 status = write_register(state, HYDRA_RESET_XBAR_REG,
992 HYDRA_RESET_XBAR_DATA);
993 if (status)
994 return status;
995
996 /* Disable clock to Baseband, Wideband, SerDes,
997 * Alias ext & Transport modules
998 */
999 status = write_register(state, HYDRA_MODULES_CLK_2_REG,
1000 HYDRA_DISABLE_CLK_2);
1001 if (status)
1002 return status;
1003 /* Clear Software & Host interrupt status - (Clear on read) */
1004 status = read_register(state, HYDRA_PRCM_ROOT_CLK_REG, &reg_data);
1005 if (status)
1006 return status;
1007 status = do_firmware_download(state, mbin, mbin_len);
1008 if (status)
1009 return status;
1010
1011 if (state->base->type == MXL_HYDRA_DEVICE_568) {
1012 usleep_range(10000, 11000);
1013
1014 /* bring XCPU out of reset */
1015 status = write_register(state, 0x90720000, 1);
1016 if (status)
1017 return status;
1018 msleep(500);
1019
1020 /* Enable XCPU UART message processing in MCPU */
1021 status = write_register(state, 0x9076B510, 1);
1022 if (status)
1023 return status;
1024 } else {
1025 /* Bring CPU out of reset */
1026 status = update_by_mnemonic(state, 0x8003003C, 0, 1, 1);
1027 if (status)
1028 return status;
1029 /* Wait until FW boots */
1030 msleep(150);
1031 }
1032
1033 /* Initialize XPT XBAR */
1034 status = write_register(state, XPT_DMD0_BASEADDR, 0x76543210);
1035 if (status)
1036 return status;
1037
1038 if (!firmware_is_alive(state))
1039 return -1;
1040
1041 dev_info(state->i2cdev, "Hydra FW alive. Hail!\n");
1042
1043 /* sometimes register values are wrong shortly
1044 * after first heart beats
1045 */
1046 msleep(50);
1047
1048 dev_sku_cfg.sku_type = state->base->sku_type;
1049 BUILD_HYDRA_CMD(MXL_HYDRA_DEV_CFG_SKU_CMD, MXL_CMD_WRITE,
1050 cmd_size, &dev_sku_cfg, cmd_buff);
1051 status = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
1052 &cmd_buff[0]);
1053
1054 return status;
1055}
1056
1057static int cfg_ts_pad_mux(struct mxl *state, enum MXL_BOOL_E enable_serial_ts)
1058{
1059 int status = 0;
1060 u32 pad_mux_value = 0;
1061
1062 if (enable_serial_ts == MXL_TRUE) {
1063 pad_mux_value = 0;
1064 if ((state->base->type == MXL_HYDRA_DEVICE_541) ||
1065 (state->base->type == MXL_HYDRA_DEVICE_541S))
1066 pad_mux_value = 2;
1067 } else {
1068 if ((state->base->type == MXL_HYDRA_DEVICE_581) ||
1069 (state->base->type == MXL_HYDRA_DEVICE_581S))
1070 pad_mux_value = 2;
1071 else
1072 pad_mux_value = 3;
1073 }
1074
1075 switch (state->base->type) {
1076 case MXL_HYDRA_DEVICE_561:
1077 case MXL_HYDRA_DEVICE_581:
1078 case MXL_HYDRA_DEVICE_541:
1079 case MXL_HYDRA_DEVICE_541S:
1080 case MXL_HYDRA_DEVICE_561S:
1081 case MXL_HYDRA_DEVICE_581S:
1082 status |= update_by_mnemonic(state, 0x90000170, 24, 3,
1083 pad_mux_value);
1084 status |= update_by_mnemonic(state, 0x90000170, 28, 3,
1085 pad_mux_value);
1086 status |= update_by_mnemonic(state, 0x90000174, 0, 3,
1087 pad_mux_value);
1088 status |= update_by_mnemonic(state, 0x90000174, 4, 3,
1089 pad_mux_value);
1090 status |= update_by_mnemonic(state, 0x90000174, 8, 3,
1091 pad_mux_value);
1092 status |= update_by_mnemonic(state, 0x90000174, 12, 3,
1093 pad_mux_value);
1094 status |= update_by_mnemonic(state, 0x90000174, 16, 3,
1095 pad_mux_value);
1096 status |= update_by_mnemonic(state, 0x90000174, 20, 3,
1097 pad_mux_value);
1098 status |= update_by_mnemonic(state, 0x90000174, 24, 3,
1099 pad_mux_value);
1100 status |= update_by_mnemonic(state, 0x90000174, 28, 3,
1101 pad_mux_value);
1102 status |= update_by_mnemonic(state, 0x90000178, 0, 3,
1103 pad_mux_value);
1104 status |= update_by_mnemonic(state, 0x90000178, 4, 3,
1105 pad_mux_value);
1106 status |= update_by_mnemonic(state, 0x90000178, 8, 3,
1107 pad_mux_value);
1108 break;
1109
1110 case MXL_HYDRA_DEVICE_544:
1111 case MXL_HYDRA_DEVICE_542:
1112 status |= update_by_mnemonic(state, 0x9000016C, 4, 3, 1);
1113 status |= update_by_mnemonic(state, 0x9000016C, 8, 3, 0);
1114 status |= update_by_mnemonic(state, 0x9000016C, 12, 3, 0);
1115 status |= update_by_mnemonic(state, 0x9000016C, 16, 3, 0);
1116 status |= update_by_mnemonic(state, 0x90000170, 0, 3, 0);
1117 status |= update_by_mnemonic(state, 0x90000178, 12, 3, 1);
1118 status |= update_by_mnemonic(state, 0x90000178, 16, 3, 1);
1119 status |= update_by_mnemonic(state, 0x90000178, 20, 3, 1);
1120 status |= update_by_mnemonic(state, 0x90000178, 24, 3, 1);
1121 status |= update_by_mnemonic(state, 0x9000017C, 0, 3, 1);
1122 status |= update_by_mnemonic(state, 0x9000017C, 4, 3, 1);
1123 if (enable_serial_ts == MXL_ENABLE) {
1124 status |= update_by_mnemonic(state,
1125 0x90000170, 4, 3, 0);
1126 status |= update_by_mnemonic(state,
1127 0x90000170, 8, 3, 0);
1128 status |= update_by_mnemonic(state,
1129 0x90000170, 12, 3, 0);
1130 status |= update_by_mnemonic(state,
1131 0x90000170, 16, 3, 0);
1132 status |= update_by_mnemonic(state,
1133 0x90000170, 20, 3, 1);
1134 status |= update_by_mnemonic(state,
1135 0x90000170, 24, 3, 1);
1136 status |= update_by_mnemonic(state,
1137 0x90000170, 28, 3, 2);
1138 status |= update_by_mnemonic(state,
1139 0x90000174, 0, 3, 2);
1140 status |= update_by_mnemonic(state,
1141 0x90000174, 4, 3, 2);
1142 status |= update_by_mnemonic(state,
1143 0x90000174, 8, 3, 2);
1144 status |= update_by_mnemonic(state,
1145 0x90000174, 12, 3, 2);
1146 status |= update_by_mnemonic(state,
1147 0x90000174, 16, 3, 2);
1148 status |= update_by_mnemonic(state,
1149 0x90000174, 20, 3, 2);
1150 status |= update_by_mnemonic(state,
1151 0x90000174, 24, 3, 2);
1152 status |= update_by_mnemonic(state,
1153 0x90000174, 28, 3, 2);
1154 status |= update_by_mnemonic(state,
1155 0x90000178, 0, 3, 2);
1156 status |= update_by_mnemonic(state,
1157 0x90000178, 4, 3, 2);
1158 status |= update_by_mnemonic(state,
1159 0x90000178, 8, 3, 2);
1160 } else {
1161 status |= update_by_mnemonic(state,
1162 0x90000170, 4, 3, 3);
1163 status |= update_by_mnemonic(state,
1164 0x90000170, 8, 3, 3);
1165 status |= update_by_mnemonic(state,
1166 0x90000170, 12, 3, 3);
1167 status |= update_by_mnemonic(state,
1168 0x90000170, 16, 3, 3);
1169 status |= update_by_mnemonic(state,
1170 0x90000170, 20, 3, 3);
1171 status |= update_by_mnemonic(state,
1172 0x90000170, 24, 3, 3);
1173 status |= update_by_mnemonic(state,
1174 0x90000170, 28, 3, 3);
1175 status |= update_by_mnemonic(state,
1176 0x90000174, 0, 3, 3);
1177 status |= update_by_mnemonic(state,
1178 0x90000174, 4, 3, 3);
1179 status |= update_by_mnemonic(state,
1180 0x90000174, 8, 3, 3);
1181 status |= update_by_mnemonic(state,
1182 0x90000174, 12, 3, 3);
1183 status |= update_by_mnemonic(state,
1184 0x90000174, 16, 3, 3);
1185 status |= update_by_mnemonic(state,
1186 0x90000174, 20, 3, 1);
1187 status |= update_by_mnemonic(state,
1188 0x90000174, 24, 3, 1);
1189 status |= update_by_mnemonic(state,
1190 0x90000174, 28, 3, 1);
1191 status |= update_by_mnemonic(state,
1192 0x90000178, 0, 3, 1);
1193 status |= update_by_mnemonic(state,
1194 0x90000178, 4, 3, 1);
1195 status |= update_by_mnemonic(state,
1196 0x90000178, 8, 3, 1);
1197 }
1198 break;
1199
1200 case MXL_HYDRA_DEVICE_568:
1201 if (enable_serial_ts == MXL_FALSE) {
1202 status |= update_by_mnemonic(state,
1203 0x9000016C, 8, 3, 5);
1204 status |= update_by_mnemonic(state,
1205 0x9000016C, 12, 3, 5);
1206 status |= update_by_mnemonic(state,
1207 0x9000016C, 16, 3, 5);
1208 status |= update_by_mnemonic(state,
1209 0x9000016C, 20, 3, 5);
1210 status |= update_by_mnemonic(state,
1211 0x9000016C, 24, 3, 5);
1212 status |= update_by_mnemonic(state,
1213 0x9000016C, 28, 3, 5);
1214 status |= update_by_mnemonic(state,
1215 0x90000170, 0, 3, 5);
1216 status |= update_by_mnemonic(state,
1217 0x90000170, 4, 3, 5);
1218 status |= update_by_mnemonic(state,
1219 0x90000170, 8, 3, 5);
1220 status |= update_by_mnemonic(state,
1221 0x90000170, 12, 3, 5);
1222 status |= update_by_mnemonic(state,
1223 0x90000170, 16, 3, 5);
1224 status |= update_by_mnemonic(state,
1225 0x90000170, 20, 3, 5);
1226
1227 status |= update_by_mnemonic(state,
1228 0x90000170, 24, 3, pad_mux_value);
1229 status |= update_by_mnemonic(state,
1230 0x90000174, 0, 3, pad_mux_value);
1231 status |= update_by_mnemonic(state,
1232 0x90000174, 4, 3, pad_mux_value);
1233 status |= update_by_mnemonic(state,
1234 0x90000174, 8, 3, pad_mux_value);
1235 status |= update_by_mnemonic(state,
1236 0x90000174, 12, 3, pad_mux_value);
1237 status |= update_by_mnemonic(state,
1238 0x90000174, 16, 3, pad_mux_value);
1239 status |= update_by_mnemonic(state,
1240 0x90000174, 20, 3, pad_mux_value);
1241 status |= update_by_mnemonic(state,
1242 0x90000174, 24, 3, pad_mux_value);
1243 status |= update_by_mnemonic(state,
1244 0x90000174, 28, 3, pad_mux_value);
1245 status |= update_by_mnemonic(state,
1246 0x90000178, 0, 3, pad_mux_value);
1247 status |= update_by_mnemonic(state,
1248 0x90000178, 4, 3, pad_mux_value);
1249
1250 status |= update_by_mnemonic(state,
1251 0x90000178, 8, 3, 5);
1252 status |= update_by_mnemonic(state,
1253 0x90000178, 12, 3, 5);
1254 status |= update_by_mnemonic(state,
1255 0x90000178, 16, 3, 5);
1256 status |= update_by_mnemonic(state,
1257 0x90000178, 20, 3, 5);
1258 status |= update_by_mnemonic(state,
1259 0x90000178, 24, 3, 5);
1260 status |= update_by_mnemonic(state,
1261 0x90000178, 28, 3, 5);
1262 status |= update_by_mnemonic(state,
1263 0x9000017C, 0, 3, 5);
1264 status |= update_by_mnemonic(state,
1265 0x9000017C, 4, 3, 5);
1266 } else {
1267 status |= update_by_mnemonic(state,
1268 0x90000170, 4, 3, pad_mux_value);
1269 status |= update_by_mnemonic(state,
1270 0x90000170, 8, 3, pad_mux_value);
1271 status |= update_by_mnemonic(state,
1272 0x90000170, 12, 3, pad_mux_value);
1273 status |= update_by_mnemonic(state,
1274 0x90000170, 16, 3, pad_mux_value);
1275 status |= update_by_mnemonic(state,
1276 0x90000170, 20, 3, pad_mux_value);
1277 status |= update_by_mnemonic(state,
1278 0x90000170, 24, 3, pad_mux_value);
1279 status |= update_by_mnemonic(state,
1280 0x90000170, 28, 3, pad_mux_value);
1281 status |= update_by_mnemonic(state,
1282 0x90000174, 0, 3, pad_mux_value);
1283 status |= update_by_mnemonic(state,
1284 0x90000174, 4, 3, pad_mux_value);
1285 status |= update_by_mnemonic(state,
1286 0x90000174, 8, 3, pad_mux_value);
1287 status |= update_by_mnemonic(state,
1288 0x90000174, 12, 3, pad_mux_value);
1289 }
1290 break;
1291
1292
1293 case MXL_HYDRA_DEVICE_584:
1294 default:
1295 status |= update_by_mnemonic(state,
1296 0x90000170, 4, 3, pad_mux_value);
1297 status |= update_by_mnemonic(state,
1298 0x90000170, 8, 3, pad_mux_value);
1299 status |= update_by_mnemonic(state,
1300 0x90000170, 12, 3, pad_mux_value);
1301 status |= update_by_mnemonic(state,
1302 0x90000170, 16, 3, pad_mux_value);
1303 status |= update_by_mnemonic(state,
1304 0x90000170, 20, 3, pad_mux_value);
1305 status |= update_by_mnemonic(state,
1306 0x90000170, 24, 3, pad_mux_value);
1307 status |= update_by_mnemonic(state,
1308 0x90000170, 28, 3, pad_mux_value);
1309 status |= update_by_mnemonic(state,
1310 0x90000174, 0, 3, pad_mux_value);
1311 status |= update_by_mnemonic(state,
1312 0x90000174, 4, 3, pad_mux_value);
1313 status |= update_by_mnemonic(state,
1314 0x90000174, 8, 3, pad_mux_value);
1315 status |= update_by_mnemonic(state,
1316 0x90000174, 12, 3, pad_mux_value);
1317 break;
1318 }
1319 return status;
1320}
1321
1322static int set_drive_strength(struct mxl *state,
1323 enum MXL_HYDRA_TS_DRIVE_STRENGTH_E ts_drive_strength)
1324{
1325 int stat = 0;
1326 u32 val;
1327
1328 read_register(state, 0x90000194, &val);
1329 dev_info(state->i2cdev, "DIGIO = %08x\n", val);
1330 dev_info(state->i2cdev, "set drive_strength = %u\n", ts_drive_strength);
1331
1332
1333 stat |= update_by_mnemonic(state, 0x90000194, 0, 3, ts_drive_strength);
1334 stat |= update_by_mnemonic(state, 0x90000194, 20, 3, ts_drive_strength);
1335 stat |= update_by_mnemonic(state, 0x90000194, 24, 3, ts_drive_strength);
1336 stat |= update_by_mnemonic(state, 0x90000198, 12, 3, ts_drive_strength);
1337 stat |= update_by_mnemonic(state, 0x90000198, 16, 3, ts_drive_strength);
1338 stat |= update_by_mnemonic(state, 0x90000198, 20, 3, ts_drive_strength);
1339 stat |= update_by_mnemonic(state, 0x90000198, 24, 3, ts_drive_strength);
1340 stat |= update_by_mnemonic(state, 0x9000019C, 0, 3, ts_drive_strength);
1341 stat |= update_by_mnemonic(state, 0x9000019C, 4, 3, ts_drive_strength);
1342 stat |= update_by_mnemonic(state, 0x9000019C, 8, 3, ts_drive_strength);
1343 stat |= update_by_mnemonic(state, 0x9000019C, 24, 3, ts_drive_strength);
1344 stat |= update_by_mnemonic(state, 0x9000019C, 28, 3, ts_drive_strength);
1345 stat |= update_by_mnemonic(state, 0x900001A0, 0, 3, ts_drive_strength);
1346 stat |= update_by_mnemonic(state, 0x900001A0, 4, 3, ts_drive_strength);
1347 stat |= update_by_mnemonic(state, 0x900001A0, 20, 3, ts_drive_strength);
1348 stat |= update_by_mnemonic(state, 0x900001A0, 24, 3, ts_drive_strength);
1349 stat |= update_by_mnemonic(state, 0x900001A0, 28, 3, ts_drive_strength);
1350
1351 return stat;
1352}
1353
1354static int enable_tuner(struct mxl *state, u32 tuner, u32 enable)
1355{
1356 int stat = 0;
1357 struct MXL_HYDRA_TUNER_CMD ctrl_tuner_cmd;
1358 u8 cmd_size = sizeof(ctrl_tuner_cmd);
1359 u8 cmd_buff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN];
1360 u32 val, count = 10;
1361
1362 ctrl_tuner_cmd.tuner_id = tuner;
1363 ctrl_tuner_cmd.enable = enable;
1364 BUILD_HYDRA_CMD(MXL_HYDRA_TUNER_ACTIVATE_CMD, MXL_CMD_WRITE,
1365 cmd_size, &ctrl_tuner_cmd, cmd_buff);
1366 stat = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
1367 &cmd_buff[0]);
1368 if (stat)
1369 return stat;
1370 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
1371 while (--count && ((val >> tuner) & 1) != enable) {
1372 msleep(20);
1373 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
1374 }
1375 if (!count)
1376 return -1;
1377 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
1378 dev_dbg(state->i2cdev, "tuner %u ready = %u\n",
1379 tuner, (val >> tuner) & 1);
1380
1381 return 0;
1382}
1383
1384
1385static int config_ts(struct mxl *state, enum MXL_HYDRA_DEMOD_ID_E demod_id,
1386 struct MXL_HYDRA_MPEGOUT_PARAM_T *mpeg_out_param_ptr)
1387{
1388 int status = 0;
1389 u32 nco_count_min = 0;
1390 u32 clk_type = 0;
1391
1392 struct MXL_REG_FIELD_T xpt_sync_polarity[MXL_HYDRA_DEMOD_MAX] = {
1393 {0x90700010, 8, 1}, {0x90700010, 9, 1},
1394 {0x90700010, 10, 1}, {0x90700010, 11, 1},
1395 {0x90700010, 12, 1}, {0x90700010, 13, 1},
1396 {0x90700010, 14, 1}, {0x90700010, 15, 1} };
1397 struct MXL_REG_FIELD_T xpt_clock_polarity[MXL_HYDRA_DEMOD_MAX] = {
1398 {0x90700010, 16, 1}, {0x90700010, 17, 1},
1399 {0x90700010, 18, 1}, {0x90700010, 19, 1},
1400 {0x90700010, 20, 1}, {0x90700010, 21, 1},
1401 {0x90700010, 22, 1}, {0x90700010, 23, 1} };
1402 struct MXL_REG_FIELD_T xpt_valid_polarity[MXL_HYDRA_DEMOD_MAX] = {
1403 {0x90700014, 0, 1}, {0x90700014, 1, 1},
1404 {0x90700014, 2, 1}, {0x90700014, 3, 1},
1405 {0x90700014, 4, 1}, {0x90700014, 5, 1},
1406 {0x90700014, 6, 1}, {0x90700014, 7, 1} };
1407 struct MXL_REG_FIELD_T xpt_ts_clock_phase[MXL_HYDRA_DEMOD_MAX] = {
1408 {0x90700018, 0, 3}, {0x90700018, 4, 3},
1409 {0x90700018, 8, 3}, {0x90700018, 12, 3},
1410 {0x90700018, 16, 3}, {0x90700018, 20, 3},
1411 {0x90700018, 24, 3}, {0x90700018, 28, 3} };
1412 struct MXL_REG_FIELD_T xpt_lsb_first[MXL_HYDRA_DEMOD_MAX] = {
1413 {0x9070000C, 16, 1}, {0x9070000C, 17, 1},
1414 {0x9070000C, 18, 1}, {0x9070000C, 19, 1},
1415 {0x9070000C, 20, 1}, {0x9070000C, 21, 1},
1416 {0x9070000C, 22, 1}, {0x9070000C, 23, 1} };
1417 struct MXL_REG_FIELD_T xpt_sync_byte[MXL_HYDRA_DEMOD_MAX] = {
1418 {0x90700010, 0, 1}, {0x90700010, 1, 1},
1419 {0x90700010, 2, 1}, {0x90700010, 3, 1},
1420 {0x90700010, 4, 1}, {0x90700010, 5, 1},
1421 {0x90700010, 6, 1}, {0x90700010, 7, 1} };
1422 struct MXL_REG_FIELD_T xpt_enable_output[MXL_HYDRA_DEMOD_MAX] = {
1423 {0x9070000C, 0, 1}, {0x9070000C, 1, 1},
1424 {0x9070000C, 2, 1}, {0x9070000C, 3, 1},
1425 {0x9070000C, 4, 1}, {0x9070000C, 5, 1},
1426 {0x9070000C, 6, 1}, {0x9070000C, 7, 1} };
1427 struct MXL_REG_FIELD_T xpt_err_replace_sync[MXL_HYDRA_DEMOD_MAX] = {
1428 {0x9070000C, 24, 1}, {0x9070000C, 25, 1},
1429 {0x9070000C, 26, 1}, {0x9070000C, 27, 1},
1430 {0x9070000C, 28, 1}, {0x9070000C, 29, 1},
1431 {0x9070000C, 30, 1}, {0x9070000C, 31, 1} };
1432 struct MXL_REG_FIELD_T xpt_err_replace_valid[MXL_HYDRA_DEMOD_MAX] = {
1433 {0x90700014, 8, 1}, {0x90700014, 9, 1},
1434 {0x90700014, 10, 1}, {0x90700014, 11, 1},
1435 {0x90700014, 12, 1}, {0x90700014, 13, 1},
1436 {0x90700014, 14, 1}, {0x90700014, 15, 1} };
1437 struct MXL_REG_FIELD_T xpt_continuous_clock[MXL_HYDRA_DEMOD_MAX] = {
1438 {0x907001D4, 0, 1}, {0x907001D4, 1, 1},
1439 {0x907001D4, 2, 1}, {0x907001D4, 3, 1},
1440 {0x907001D4, 4, 1}, {0x907001D4, 5, 1},
1441 {0x907001D4, 6, 1}, {0x907001D4, 7, 1} };
1442 struct MXL_REG_FIELD_T xpt_nco_clock_rate[MXL_HYDRA_DEMOD_MAX] = {
1443 {0x90700044, 16, 80}, {0x90700044, 16, 81},
1444 {0x90700044, 16, 82}, {0x90700044, 16, 83},
1445 {0x90700044, 16, 84}, {0x90700044, 16, 85},
1446 {0x90700044, 16, 86}, {0x90700044, 16, 87} };
1447
1448 demod_id = state->base->ts_map[demod_id];
1449
1450 if (mpeg_out_param_ptr->enable == MXL_ENABLE) {
1451 if (mpeg_out_param_ptr->mpeg_mode ==
1452 MXL_HYDRA_MPEG_MODE_PARALLEL) {
1453 } else {
1454 cfg_ts_pad_mux(state, MXL_TRUE);
1455 update_by_mnemonic(state,
1456 0x90700010, 27, 1, MXL_FALSE);
1457 }
1458 }
1459
1460 nco_count_min =
1461 (u32)(MXL_HYDRA_NCO_CLK / mpeg_out_param_ptr->max_mpeg_clk_rate);
1462
1463 if (state->base->chipversion >= 2) {
1464 status |= update_by_mnemonic(state,
1465 xpt_nco_clock_rate[demod_id].reg_addr, /* Reg Addr */
1466 xpt_nco_clock_rate[demod_id].lsb_pos, /* LSB pos */
1467 xpt_nco_clock_rate[demod_id].num_of_bits, /* Num of bits */
1468 nco_count_min); /* Data */
1469 } else
1470 update_by_mnemonic(state, 0x90700044, 16, 8, nco_count_min);
1471
1472 if (mpeg_out_param_ptr->mpeg_clk_type == MXL_HYDRA_MPEG_CLK_CONTINUOUS)
1473 clk_type = 1;
1474
1475 if (mpeg_out_param_ptr->mpeg_mode < MXL_HYDRA_MPEG_MODE_PARALLEL) {
1476 status |= update_by_mnemonic(state,
1477 xpt_continuous_clock[demod_id].reg_addr,
1478 xpt_continuous_clock[demod_id].lsb_pos,
1479 xpt_continuous_clock[demod_id].num_of_bits,
1480 clk_type);
1481 } else
1482 update_by_mnemonic(state, 0x907001D4, 8, 1, clk_type);
1483
1484 status |= update_by_mnemonic(state,
1485 xpt_sync_polarity[demod_id].reg_addr,
1486 xpt_sync_polarity[demod_id].lsb_pos,
1487 xpt_sync_polarity[demod_id].num_of_bits,
1488 mpeg_out_param_ptr->mpeg_sync_pol);
1489
1490 status |= update_by_mnemonic(state,
1491 xpt_valid_polarity[demod_id].reg_addr,
1492 xpt_valid_polarity[demod_id].lsb_pos,
1493 xpt_valid_polarity[demod_id].num_of_bits,
1494 mpeg_out_param_ptr->mpeg_valid_pol);
1495
1496 status |= update_by_mnemonic(state,
1497 xpt_clock_polarity[demod_id].reg_addr,
1498 xpt_clock_polarity[demod_id].lsb_pos,
1499 xpt_clock_polarity[demod_id].num_of_bits,
1500 mpeg_out_param_ptr->mpeg_clk_pol);
1501
1502 status |= update_by_mnemonic(state,
1503 xpt_sync_byte[demod_id].reg_addr,
1504 xpt_sync_byte[demod_id].lsb_pos,
1505 xpt_sync_byte[demod_id].num_of_bits,
1506 mpeg_out_param_ptr->mpeg_sync_pulse_width);
1507
1508 status |= update_by_mnemonic(state,
1509 xpt_ts_clock_phase[demod_id].reg_addr,
1510 xpt_ts_clock_phase[demod_id].lsb_pos,
1511 xpt_ts_clock_phase[demod_id].num_of_bits,
1512 mpeg_out_param_ptr->mpeg_clk_phase);
1513
1514 status |= update_by_mnemonic(state,
1515 xpt_lsb_first[demod_id].reg_addr,
1516 xpt_lsb_first[demod_id].lsb_pos,
1517 xpt_lsb_first[demod_id].num_of_bits,
1518 mpeg_out_param_ptr->lsb_or_msb_first);
1519
1520 switch (mpeg_out_param_ptr->mpeg_error_indication) {
1521 case MXL_HYDRA_MPEG_ERR_REPLACE_SYNC:
1522 status |= update_by_mnemonic(state,
1523 xpt_err_replace_sync[demod_id].reg_addr,
1524 xpt_err_replace_sync[demod_id].lsb_pos,
1525 xpt_err_replace_sync[demod_id].num_of_bits,
1526 MXL_TRUE);
1527 status |= update_by_mnemonic(state,
1528 xpt_err_replace_valid[demod_id].reg_addr,
1529 xpt_err_replace_valid[demod_id].lsb_pos,
1530 xpt_err_replace_valid[demod_id].num_of_bits,
1531 MXL_FALSE);
1532 break;
1533
1534 case MXL_HYDRA_MPEG_ERR_REPLACE_VALID:
1535 status |= update_by_mnemonic(state,
1536 xpt_err_replace_sync[demod_id].reg_addr,
1537 xpt_err_replace_sync[demod_id].lsb_pos,
1538 xpt_err_replace_sync[demod_id].num_of_bits,
1539 MXL_FALSE);
1540
1541 status |= update_by_mnemonic(state,
1542 xpt_err_replace_valid[demod_id].reg_addr,
1543 xpt_err_replace_valid[demod_id].lsb_pos,
1544 xpt_err_replace_valid[demod_id].num_of_bits,
1545 MXL_TRUE);
1546 break;
1547
1548 case MXL_HYDRA_MPEG_ERR_INDICATION_DISABLED:
1549 default:
1550 status |= update_by_mnemonic(state,
1551 xpt_err_replace_sync[demod_id].reg_addr,
1552 xpt_err_replace_sync[demod_id].lsb_pos,
1553 xpt_err_replace_sync[demod_id].num_of_bits,
1554 MXL_FALSE);
1555
1556 status |= update_by_mnemonic(state,
1557 xpt_err_replace_valid[demod_id].reg_addr,
1558 xpt_err_replace_valid[demod_id].lsb_pos,
1559 xpt_err_replace_valid[demod_id].num_of_bits,
1560 MXL_FALSE);
1561
1562 break;
1563
1564 }
1565
1566 if (mpeg_out_param_ptr->mpeg_mode != MXL_HYDRA_MPEG_MODE_PARALLEL) {
1567 status |= update_by_mnemonic(state,
1568 xpt_enable_output[demod_id].reg_addr,
1569 xpt_enable_output[demod_id].lsb_pos,
1570 xpt_enable_output[demod_id].num_of_bits,
1571 mpeg_out_param_ptr->enable);
1572 }
1573 return status;
1574}
1575
1576static int config_mux(struct mxl *state)
1577{
1578 update_by_mnemonic(state, 0x9070000C, 0, 1, 0);
1579 update_by_mnemonic(state, 0x9070000C, 1, 1, 0);
1580 update_by_mnemonic(state, 0x9070000C, 2, 1, 0);
1581 update_by_mnemonic(state, 0x9070000C, 3, 1, 0);
1582 update_by_mnemonic(state, 0x9070000C, 4, 1, 0);
1583 update_by_mnemonic(state, 0x9070000C, 5, 1, 0);
1584 update_by_mnemonic(state, 0x9070000C, 6, 1, 0);
1585 update_by_mnemonic(state, 0x9070000C, 7, 1, 0);
1586 update_by_mnemonic(state, 0x90700008, 0, 2, 1);
1587 update_by_mnemonic(state, 0x90700008, 2, 2, 1);
1588 return 0;
1589}
1590
1591static int load_fw(struct mxl *state, struct mxl5xx_cfg *cfg)
1592{
1593 int stat = 0;
1594 u8 *buf;
1595
1596 if (cfg->fw)
1597 return firmware_download(state, cfg->fw, cfg->fw_len);
1598
1599 if (!cfg->fw_read)
1600 return -1;
1601
1602 buf = vmalloc(0x40000);
1603 if (!buf)
1604 return -ENOMEM;
1605
1606 cfg->fw_read(cfg->fw_priv, buf, 0x40000);
1607 stat = firmware_download(state, buf, 0x40000);
1608 vfree(buf);
1609
1610 return stat;
1611}
1612
1613static int validate_sku(struct mxl *state)
1614{
1615 u32 pad_mux_bond = 0, prcm_chip_id = 0, prcm_so_cid = 0;
1616 int status;
1617 u32 type = state->base->type;
1618
1619 status = read_by_mnemonic(state, 0x90000190, 0, 3, &pad_mux_bond);
1620 status |= read_by_mnemonic(state, 0x80030000, 0, 12, &prcm_chip_id);
1621 status |= read_by_mnemonic(state, 0x80030004, 24, 8, &prcm_so_cid);
1622 if (status)
1623 return -1;
1624
1625 dev_info(state->i2cdev, "padMuxBond=%08x, prcmChipId=%08x, prcmSoCId=%08x\n",
1626 pad_mux_bond, prcm_chip_id, prcm_so_cid);
1627
1628 if (prcm_chip_id != 0x560) {
1629 switch (pad_mux_bond) {
1630 case MXL_HYDRA_SKU_ID_581:
1631 if (type == MXL_HYDRA_DEVICE_581)
1632 return 0;
1633 if (type == MXL_HYDRA_DEVICE_581S) {
1634 state->base->type = MXL_HYDRA_DEVICE_581;
1635 return 0;
1636 }
1637 break;
1638 case MXL_HYDRA_SKU_ID_584:
1639 if (type == MXL_HYDRA_DEVICE_584)
1640 return 0;
1641 break;
1642 case MXL_HYDRA_SKU_ID_544:
1643 if (type == MXL_HYDRA_DEVICE_544)
1644 return 0;
1645 if (type == MXL_HYDRA_DEVICE_542)
1646 return 0;
1647 break;
1648 case MXL_HYDRA_SKU_ID_582:
1649 if (type == MXL_HYDRA_DEVICE_582)
1650 return 0;
1651 break;
1652 default:
1653 return -1;
1654 }
1655 } else {
1656
1657 }
1658 return -1;
1659}
1660
1661static int get_fwinfo(struct mxl *state)
1662{
1663 int status;
1664 u32 val = 0;
1665
1666 status = read_by_mnemonic(state, 0x90000190, 0, 3, &val);
1667 if (status)
1668 return status;
1669 dev_info(state->i2cdev, "chipID=%08x\n", val);
1670
1671 status = read_by_mnemonic(state, 0x80030004, 8, 8, &val);
1672 if (status)
1673 return status;
1674 dev_info(state->i2cdev, "chipVer=%08x\n", val);
1675
1676 status = read_register(state, HYDRA_FIRMWARE_VERSION, &val);
1677 if (status)
1678 return status;
1679 dev_info(state->i2cdev, "FWVer=%08x\n", val);
1680
1681 state->base->fwversion = val;
1682 return status;
1683}
1684
1685
1686static u8 ts_map1_to_1[MXL_HYDRA_DEMOD_MAX] = {
1687 MXL_HYDRA_DEMOD_ID_0,
1688 MXL_HYDRA_DEMOD_ID_1,
1689 MXL_HYDRA_DEMOD_ID_2,
1690 MXL_HYDRA_DEMOD_ID_3,
1691 MXL_HYDRA_DEMOD_ID_4,
1692 MXL_HYDRA_DEMOD_ID_5,
1693 MXL_HYDRA_DEMOD_ID_6,
1694 MXL_HYDRA_DEMOD_ID_7,
1695};
1696
1697static u8 ts_map54x[MXL_HYDRA_DEMOD_MAX] = {
1698 MXL_HYDRA_DEMOD_ID_2,
1699 MXL_HYDRA_DEMOD_ID_3,
1700 MXL_HYDRA_DEMOD_ID_4,
1701 MXL_HYDRA_DEMOD_ID_5,
1702 MXL_HYDRA_DEMOD_MAX,
1703 MXL_HYDRA_DEMOD_MAX,
1704 MXL_HYDRA_DEMOD_MAX,
1705 MXL_HYDRA_DEMOD_MAX,
1706};
1707
1708static int probe(struct mxl *state, struct mxl5xx_cfg *cfg)
1709{
1710 u32 chipver;
1711 int fw, status, j;
1712 struct MXL_HYDRA_MPEGOUT_PARAM_T mpeg_interface_cfg;
1713
1714 state->base->ts_map = ts_map1_to_1;
1715
1716 switch (state->base->type) {
1717 case MXL_HYDRA_DEVICE_581:
1718 case MXL_HYDRA_DEVICE_581S:
1719 state->base->can_clkout = 1;
1720 state->base->demod_num = 8;
1721 state->base->tuner_num = 1;
1722 state->base->sku_type = MXL_HYDRA_SKU_TYPE_581;
1723 break;
1724 case MXL_HYDRA_DEVICE_582:
1725 state->base->can_clkout = 1;
1726 state->base->demod_num = 8;
1727 state->base->tuner_num = 3;
1728 state->base->sku_type = MXL_HYDRA_SKU_TYPE_582;
1729 break;
1730 case MXL_HYDRA_DEVICE_585:
1731 state->base->can_clkout = 0;
1732 state->base->demod_num = 8;
1733 state->base->tuner_num = 4;
1734 state->base->sku_type = MXL_HYDRA_SKU_TYPE_585;
1735 break;
1736 case MXL_HYDRA_DEVICE_544:
1737 state->base->can_clkout = 0;
1738 state->base->demod_num = 4;
1739 state->base->tuner_num = 4;
1740 state->base->sku_type = MXL_HYDRA_SKU_TYPE_544;
1741 state->base->ts_map = ts_map54x;
1742 break;
1743 case MXL_HYDRA_DEVICE_541:
1744 case MXL_HYDRA_DEVICE_541S:
1745 state->base->can_clkout = 0;
1746 state->base->demod_num = 4;
1747 state->base->tuner_num = 1;
1748 state->base->sku_type = MXL_HYDRA_SKU_TYPE_541;
1749 state->base->ts_map = ts_map54x;
1750 break;
1751 case MXL_HYDRA_DEVICE_561:
1752 case MXL_HYDRA_DEVICE_561S:
1753 state->base->can_clkout = 0;
1754 state->base->demod_num = 6;
1755 state->base->tuner_num = 1;
1756 state->base->sku_type = MXL_HYDRA_SKU_TYPE_561;
1757 break;
1758 case MXL_HYDRA_DEVICE_568:
1759 state->base->can_clkout = 0;
1760 state->base->demod_num = 8;
1761 state->base->tuner_num = 1;
1762 state->base->chan_bond = 1;
1763 state->base->sku_type = MXL_HYDRA_SKU_TYPE_568;
1764 break;
1765 case MXL_HYDRA_DEVICE_542:
1766 state->base->can_clkout = 1;
1767 state->base->demod_num = 4;
1768 state->base->tuner_num = 3;
1769 state->base->sku_type = MXL_HYDRA_SKU_TYPE_542;
1770 state->base->ts_map = ts_map54x;
1771 break;
1772 case MXL_HYDRA_DEVICE_TEST:
1773 case MXL_HYDRA_DEVICE_584:
1774 default:
1775 state->base->can_clkout = 0;
1776 state->base->demod_num = 8;
1777 state->base->tuner_num = 4;
1778 state->base->sku_type = MXL_HYDRA_SKU_TYPE_584;
1779 break;
1780 }
1781
1782 status = validate_sku(state);
1783 if (status)
1784 return status;
1785
1786 update_by_mnemonic(state, 0x80030014, 9, 1, 1);
1787 update_by_mnemonic(state, 0x8003003C, 12, 1, 1);
1788 status = read_by_mnemonic(state, 0x80030000, 12, 4, &chipver);
1789 if (status)
1790 state->base->chipversion = 0;
1791 else
1792 state->base->chipversion = (chipver == 2) ? 2 : 1;
1793 dev_info(state->i2cdev, "Hydra chip version %u\n",
1794 state->base->chipversion);
1795
1796 cfg_dev_xtal(state, cfg->clk, cfg->cap, 0);
1797
1798 fw = firmware_is_alive(state);
1799 if (!fw) {
1800 status = load_fw(state, cfg);
1801 if (status)
1802 return status;
1803 }
1804 get_fwinfo(state);
1805
1806 config_mux(state);
1807 mpeg_interface_cfg.enable = MXL_ENABLE;
1808 mpeg_interface_cfg.lsb_or_msb_first = MXL_HYDRA_MPEG_SERIAL_MSB_1ST;
1809 /* supports only (0-104&139)MHz */
1810 if (cfg->ts_clk)
1811 mpeg_interface_cfg.max_mpeg_clk_rate = cfg->ts_clk;
1812 else
1813 mpeg_interface_cfg.max_mpeg_clk_rate = 69; /* 139; */
1814 mpeg_interface_cfg.mpeg_clk_phase = MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_0_DEG;
1815 mpeg_interface_cfg.mpeg_clk_pol = MXL_HYDRA_MPEG_CLK_IN_PHASE;
1816 /* MXL_HYDRA_MPEG_CLK_GAPPED; */
1817 mpeg_interface_cfg.mpeg_clk_type = MXL_HYDRA_MPEG_CLK_CONTINUOUS;
1818 mpeg_interface_cfg.mpeg_error_indication =
1819 MXL_HYDRA_MPEG_ERR_INDICATION_DISABLED;
1820 mpeg_interface_cfg.mpeg_mode = MXL_HYDRA_MPEG_MODE_SERIAL_3_WIRE;
1821 mpeg_interface_cfg.mpeg_sync_pol = MXL_HYDRA_MPEG_ACTIVE_HIGH;
1822 mpeg_interface_cfg.mpeg_sync_pulse_width = MXL_HYDRA_MPEG_SYNC_WIDTH_BIT;
1823 mpeg_interface_cfg.mpeg_valid_pol = MXL_HYDRA_MPEG_ACTIVE_HIGH;
1824
1825 for (j = 0; j < state->base->demod_num; j++) {
1826 status = config_ts(state, (enum MXL_HYDRA_DEMOD_ID_E) j,
1827 &mpeg_interface_cfg);
1828 if (status)
1829 return status;
1830 }
1831 set_drive_strength(state, 1);
1832 return 0;
1833}
1834
1835struct dvb_frontend *mxl5xx_attach(struct i2c_adapter *i2c,
1836 struct mxl5xx_cfg *cfg, u32 demod, u32 tuner,
1837 int (**fn_set_input)(struct dvb_frontend *, int))
1838{
1839 struct mxl *state;
1840 struct mxl_base *base;
1841
1842 state = kzalloc(sizeof(struct mxl), GFP_KERNEL);
1843 if (!state)
1844 return NULL;
1845
1846 state->demod = demod;
1847 state->tuner = tuner;
1848 state->tuner_in_use = 0xffffffff;
1849 state->i2cdev = &i2c->dev;
1850
1851 base = match_base(i2c, cfg->adr);
1852 if (base) {
1853 base->count++;
1854 if (base->count > base->demod_num)
1855 goto fail;
1856 state->base = base;
1857 } else {
1858 base = kzalloc(sizeof(struct mxl_base), GFP_KERNEL);
1859 if (!base)
1860 goto fail;
1861 base->i2c = i2c;
1862 base->adr = cfg->adr;
1863 base->type = cfg->type;
1864 base->count = 1;
1865 mutex_init(&base->i2c_lock);
1866 mutex_init(&base->status_lock);
1867 mutex_init(&base->tune_lock);
1868 INIT_LIST_HEAD(&base->mxls);
1869
1870 state->base = base;
1871 if (probe(state, cfg) < 0) {
1872 kfree(base);
1873 goto fail;
1874 }
1875 list_add(&base->mxllist, &mxllist);
1876 }
1877 state->fe.ops = mxl_ops;
1878 state->xbar[0] = 4;
1879 state->xbar[1] = demod;
1880 state->xbar[2] = 8;
1881 state->fe.demodulator_priv = state;
1882 *fn_set_input = set_input;
1883
1884 list_add(&state->mxl, &base->mxls);
1885 return &state->fe;
1886
1887fail:
1888 kfree(state);
1889 return NULL;
1890}
1891EXPORT_SYMBOL_GPL(mxl5xx_attach);
1892
1893MODULE_DESCRIPTION("MaxLinear MxL5xx DVB-S/S2 tuner-demodulator driver");
1894MODULE_AUTHOR("Ralph and Marcus Metzler, Metzler Brothers Systementwicklung GbR");
229b6ea6 1895MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)