Commit | Line | Data |
---|---|---|
74ba9207 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 | 2 | /* |
6a5cbd59 | 3 | Driver for Zarlink VP310/MT312/ZL10313 Satellite Channel Decoder |
1da177e4 LT |
4 | |
5 | Copyright (C) 2003 Andreas Oberritter <obi@linuxtv.org> | |
6a5cbd59 | 6 | Copyright (C) 2008 Matthias Schwarzott <zzam@gentoo.org> |
1da177e4 | 7 | |
1da177e4 LT |
8 | |
9 | References: | |
10 | http://products.zarlink.com/product_profiles/MT312.htm | |
11 | http://products.zarlink.com/product_profiles/SL1935.htm | |
12 | */ | |
13 | ||
14 | #include <linux/delay.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
4e57b681 TS |
19 | #include <linux/string.h> |
20 | #include <linux/slab.h> | |
1da177e4 | 21 | |
fada1935 | 22 | #include <media/dvb_frontend.h> |
1da177e4 LT |
23 | #include "mt312_priv.h" |
24 | #include "mt312.h" | |
25 | ||
8393796d MCC |
26 | /* Max transfer size done by I2C transfer functions */ |
27 | #define MAX_XFER_SIZE 64 | |
1da177e4 LT |
28 | |
29 | struct mt312_state { | |
89f64758 | 30 | struct i2c_adapter *i2c; |
1da177e4 | 31 | /* configuration settings */ |
89f64758 | 32 | const struct mt312_config *config; |
1da177e4 LT |
33 | struct dvb_frontend frontend; |
34 | ||
35 | u8 id; | |
111221fb MS |
36 | unsigned long xtal; |
37 | u8 freq_mult; | |
1da177e4 LT |
38 | }; |
39 | ||
40 | static int debug; | |
41 | #define dprintk(args...) \ | |
42 | do { \ | |
89f64758 MS |
43 | if (debug) \ |
44 | printk(KERN_DEBUG "mt312: " args); \ | |
1da177e4 LT |
45 | } while (0) |
46 | ||
1da177e4 | 47 | #define MT312_PLL_CLK 10000000UL /* 10 MHz */ |
6a5cbd59 | 48 | #define MT312_PLL_CLK_10_111 10111000UL /* 10.111 MHz */ |
1da177e4 | 49 | |
89f64758 | 50 | static int mt312_read(struct mt312_state *state, const enum mt312_reg_addr reg, |
1881ee89 | 51 | u8 *buf, const size_t count) |
1da177e4 LT |
52 | { |
53 | int ret; | |
54 | struct i2c_msg msg[2]; | |
55 | u8 regbuf[1] = { reg }; | |
56 | ||
57 | msg[0].addr = state->config->demod_address; | |
58 | msg[0].flags = 0; | |
59 | msg[0].buf = regbuf; | |
60 | msg[0].len = 1; | |
61 | msg[1].addr = state->config->demod_address; | |
62 | msg[1].flags = I2C_M_RD; | |
63 | msg[1].buf = buf; | |
64 | msg[1].len = count; | |
65 | ||
66 | ret = i2c_transfer(state->i2c, msg, 2); | |
67 | ||
68 | if (ret != 2) { | |
302e8acc | 69 | printk(KERN_DEBUG "%s: ret == %d\n", __func__, ret); |
1da177e4 LT |
70 | return -EREMOTEIO; |
71 | } | |
72 | ||
89f64758 | 73 | if (debug) { |
1da177e4 LT |
74 | int i; |
75 | dprintk("R(%d):", reg & 0x7f); | |
76 | for (i = 0; i < count; i++) | |
0389b34e | 77 | printk(KERN_CONT " %02x", buf[i]); |
1da177e4 LT |
78 | printk("\n"); |
79 | } | |
80 | ||
81 | return 0; | |
82 | } | |
83 | ||
89f64758 | 84 | static int mt312_write(struct mt312_state *state, const enum mt312_reg_addr reg, |
1881ee89 | 85 | const u8 *src, const size_t count) |
1da177e4 LT |
86 | { |
87 | int ret; | |
8393796d | 88 | u8 buf[MAX_XFER_SIZE]; |
1da177e4 LT |
89 | struct i2c_msg msg; |
90 | ||
8393796d MCC |
91 | if (1 + count > sizeof(buf)) { |
92 | printk(KERN_WARNING | |
35f30f36 | 93 | "mt312: write: len=%zu is too big!\n", count); |
8393796d MCC |
94 | return -EINVAL; |
95 | } | |
96 | ||
89f64758 | 97 | if (debug) { |
1da177e4 LT |
98 | int i; |
99 | dprintk("W(%d):", reg & 0x7f); | |
100 | for (i = 0; i < count; i++) | |
0389b34e | 101 | printk(KERN_CONT " %02x", src[i]); |
1da177e4 LT |
102 | printk("\n"); |
103 | } | |
104 | ||
105 | buf[0] = reg; | |
106 | memcpy(&buf[1], src, count); | |
107 | ||
108 | msg.addr = state->config->demod_address; | |
109 | msg.flags = 0; | |
110 | msg.buf = buf; | |
111 | msg.len = count + 1; | |
112 | ||
113 | ret = i2c_transfer(state->i2c, &msg, 1); | |
114 | ||
115 | if (ret != 1) { | |
271ddbf7 | 116 | dprintk("%s: ret == %d\n", __func__, ret); |
1da177e4 LT |
117 | return -EREMOTEIO; |
118 | } | |
119 | ||
120 | return 0; | |
121 | } | |
122 | ||
89f64758 | 123 | static inline int mt312_readreg(struct mt312_state *state, |
1da177e4 LT |
124 | const enum mt312_reg_addr reg, u8 *val) |
125 | { | |
126 | return mt312_read(state, reg, val, 1); | |
127 | } | |
128 | ||
89f64758 | 129 | static inline int mt312_writereg(struct mt312_state *state, |
1da177e4 LT |
130 | const enum mt312_reg_addr reg, const u8 val) |
131 | { | |
3cd890db AB |
132 | u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ |
133 | ||
134 | ||
135 | return mt312_write(state, reg, &tmp, 1); | |
1da177e4 LT |
136 | } |
137 | ||
138 | static inline u32 mt312_div(u32 a, u32 b) | |
139 | { | |
140 | return (a + (b / 2)) / b; | |
141 | } | |
142 | ||
89f64758 | 143 | static int mt312_reset(struct mt312_state *state, const u8 full) |
1da177e4 LT |
144 | { |
145 | return mt312_writereg(state, RESET, full ? 0x80 : 0x40); | |
146 | } | |
147 | ||
89f64758 | 148 | static int mt312_get_inversion(struct mt312_state *state, |
0df289a2 | 149 | enum fe_spectral_inversion *i) |
1da177e4 LT |
150 | { |
151 | int ret; | |
152 | u8 vit_mode; | |
153 | ||
994fc28b MS |
154 | ret = mt312_readreg(state, VIT_MODE, &vit_mode); |
155 | if (ret < 0) | |
1da177e4 LT |
156 | return ret; |
157 | ||
158 | if (vit_mode & 0x80) /* auto inversion was used */ | |
159 | *i = (vit_mode & 0x40) ? INVERSION_ON : INVERSION_OFF; | |
160 | ||
161 | return 0; | |
162 | } | |
163 | ||
89f64758 | 164 | static int mt312_get_symbol_rate(struct mt312_state *state, u32 *sr) |
1da177e4 LT |
165 | { |
166 | int ret; | |
167 | u8 sym_rate_h; | |
168 | u8 dec_ratio; | |
169 | u16 sym_rat_op; | |
170 | u16 monitor; | |
171 | u8 buf[2]; | |
172 | ||
994fc28b MS |
173 | ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h); |
174 | if (ret < 0) | |
1da177e4 LT |
175 | return ret; |
176 | ||
89f64758 MS |
177 | if (sym_rate_h & 0x80) { |
178 | /* symbol rate search was used */ | |
994fc28b MS |
179 | ret = mt312_writereg(state, MON_CTRL, 0x03); |
180 | if (ret < 0) | |
1da177e4 LT |
181 | return ret; |
182 | ||
994fc28b MS |
183 | ret = mt312_read(state, MONITOR_H, buf, sizeof(buf)); |
184 | if (ret < 0) | |
1da177e4 LT |
185 | return ret; |
186 | ||
187 | monitor = (buf[0] << 8) | buf[1]; | |
188 | ||
0b6a3342 | 189 | dprintk("sr(auto) = %u\n", |
1da177e4 LT |
190 | mt312_div(monitor * 15625, 4)); |
191 | } else { | |
994fc28b MS |
192 | ret = mt312_writereg(state, MON_CTRL, 0x05); |
193 | if (ret < 0) | |
1da177e4 LT |
194 | return ret; |
195 | ||
994fc28b MS |
196 | ret = mt312_read(state, MONITOR_H, buf, sizeof(buf)); |
197 | if (ret < 0) | |
1da177e4 LT |
198 | return ret; |
199 | ||
200 | dec_ratio = ((buf[0] >> 5) & 0x07) * 32; | |
201 | ||
994fc28b MS |
202 | ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf)); |
203 | if (ret < 0) | |
1da177e4 LT |
204 | return ret; |
205 | ||
206 | sym_rat_op = (buf[0] << 8) | buf[1]; | |
207 | ||
0b6a3342 | 208 | dprintk("sym_rat_op=%d dec_ratio=%d\n", |
1da177e4 | 209 | sym_rat_op, dec_ratio); |
0b6a3342 | 210 | dprintk("*sr(manual) = %lu\n", |
111221fb | 211 | (((state->xtal * 8192) / (sym_rat_op + 8192)) * |
1da177e4 LT |
212 | 2) - dec_ratio); |
213 | } | |
214 | ||
215 | return 0; | |
216 | } | |
217 | ||
0df289a2 | 218 | static int mt312_get_code_rate(struct mt312_state *state, enum fe_code_rate *cr) |
1da177e4 | 219 | { |
0df289a2 | 220 | const enum fe_code_rate fec_tab[8] = |
1da177e4 LT |
221 | { FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_6_7, FEC_7_8, |
222 | FEC_AUTO, FEC_AUTO }; | |
223 | ||
224 | int ret; | |
225 | u8 fec_status; | |
226 | ||
994fc28b MS |
227 | ret = mt312_readreg(state, FEC_STATUS, &fec_status); |
228 | if (ret < 0) | |
1da177e4 LT |
229 | return ret; |
230 | ||
231 | *cr = fec_tab[(fec_status >> 4) & 0x07]; | |
232 | ||
233 | return 0; | |
234 | } | |
235 | ||
89f64758 | 236 | static int mt312_initfe(struct dvb_frontend *fe) |
1da177e4 | 237 | { |
b8742700 | 238 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
239 | int ret; |
240 | u8 buf[2]; | |
241 | ||
242 | /* wake up */ | |
994fc28b | 243 | ret = mt312_writereg(state, CONFIG, |
111221fb | 244 | (state->freq_mult == 6 ? 0x88 : 0x8c)); |
994fc28b | 245 | if (ret < 0) |
1da177e4 LT |
246 | return ret; |
247 | ||
248 | /* wait at least 150 usec */ | |
249 | udelay(150); | |
250 | ||
251 | /* full reset */ | |
994fc28b MS |
252 | ret = mt312_reset(state, 1); |
253 | if (ret < 0) | |
1da177e4 LT |
254 | return ret; |
255 | ||
89f64758 MS |
256 | /* Per datasheet, write correct values. 09/28/03 ACCJr. |
257 | * If we don't do this, we won't get FE_HAS_VITERBI in the VP310. */ | |
1da177e4 | 258 | { |
89f64758 MS |
259 | u8 buf_def[8] = { 0x14, 0x12, 0x03, 0x02, |
260 | 0x01, 0x00, 0x00, 0x00 }; | |
1da177e4 | 261 | |
994fc28b MS |
262 | ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def)); |
263 | if (ret < 0) | |
1da177e4 LT |
264 | return ret; |
265 | } | |
266 | ||
6a5cbd59 MS |
267 | switch (state->id) { |
268 | case ID_ZL10313: | |
269 | /* enable ADC */ | |
270 | ret = mt312_writereg(state, GPP_CTRL, 0x80); | |
271 | if (ret < 0) | |
272 | return ret; | |
273 | ||
274 | /* configure ZL10313 for optimal ADC performance */ | |
275 | buf[0] = 0x80; | |
276 | buf[1] = 0xB0; | |
277 | ret = mt312_write(state, HW_CTRL, buf, 2); | |
278 | if (ret < 0) | |
279 | return ret; | |
280 | ||
281 | /* enable MPEG output and ADCs */ | |
282 | ret = mt312_writereg(state, HW_CTRL, 0x00); | |
283 | if (ret < 0) | |
284 | return ret; | |
285 | ||
286 | ret = mt312_writereg(state, MPEG_CTRL, 0x00); | |
287 | if (ret < 0) | |
288 | return ret; | |
289 | ||
290 | break; | |
291 | } | |
292 | ||
1da177e4 | 293 | /* SYS_CLK */ |
111221fb | 294 | buf[0] = mt312_div(state->xtal * state->freq_mult * 2, 1000000); |
1da177e4 LT |
295 | |
296 | /* DISEQC_RATIO */ | |
111221fb | 297 | buf[1] = mt312_div(state->xtal, 22000 * 4); |
1da177e4 | 298 | |
994fc28b MS |
299 | ret = mt312_write(state, SYS_CLK, buf, sizeof(buf)); |
300 | if (ret < 0) | |
1da177e4 LT |
301 | return ret; |
302 | ||
994fc28b MS |
303 | ret = mt312_writereg(state, SNR_THS_HIGH, 0x32); |
304 | if (ret < 0) | |
1da177e4 LT |
305 | return ret; |
306 | ||
6a5cbd59 MS |
307 | /* different MOCLK polarity */ |
308 | switch (state->id) { | |
309 | case ID_ZL10313: | |
310 | buf[0] = 0x33; | |
311 | break; | |
312 | default: | |
313 | buf[0] = 0x53; | |
314 | break; | |
315 | } | |
316 | ||
317 | ret = mt312_writereg(state, OP_CTRL, buf[0]); | |
994fc28b | 318 | if (ret < 0) |
1da177e4 LT |
319 | return ret; |
320 | ||
321 | /* TS_SW_LIM */ | |
322 | buf[0] = 0x8c; | |
323 | buf[1] = 0x98; | |
324 | ||
994fc28b MS |
325 | ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf)); |
326 | if (ret < 0) | |
1da177e4 LT |
327 | return ret; |
328 | ||
994fc28b MS |
329 | ret = mt312_writereg(state, CS_SW_LIM, 0x69); |
330 | if (ret < 0) | |
1da177e4 LT |
331 | return ret; |
332 | ||
1da177e4 LT |
333 | return 0; |
334 | } | |
335 | ||
89f64758 | 336 | static int mt312_send_master_cmd(struct dvb_frontend *fe, |
1da177e4 LT |
337 | struct dvb_diseqc_master_cmd *c) |
338 | { | |
b8742700 | 339 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
340 | int ret; |
341 | u8 diseqc_mode; | |
342 | ||
343 | if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg))) | |
344 | return -EINVAL; | |
345 | ||
994fc28b MS |
346 | ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); |
347 | if (ret < 0) | |
1da177e4 LT |
348 | return ret; |
349 | ||
994fc28b MS |
350 | ret = mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len); |
351 | if (ret < 0) | |
1da177e4 LT |
352 | return ret; |
353 | ||
994fc28b MS |
354 | ret = mt312_writereg(state, DISEQC_MODE, |
355 | (diseqc_mode & 0x40) | ((c->msg_len - 1) << 3) | |
356 | | 0x04); | |
357 | if (ret < 0) | |
1da177e4 LT |
358 | return ret; |
359 | ||
82cd2dff MS |
360 | /* is there a better way to wait for message to be transmitted */ |
361 | msleep(100); | |
362 | ||
1da177e4 | 363 | /* set DISEQC_MODE[2:0] to zero if a return message is expected */ |
994fc28b MS |
364 | if (c->msg[0] & 0x02) { |
365 | ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40)); | |
366 | if (ret < 0) | |
1da177e4 | 367 | return ret; |
994fc28b | 368 | } |
1da177e4 LT |
369 | |
370 | return 0; | |
371 | } | |
372 | ||
0df289a2 MCC |
373 | static int mt312_send_burst(struct dvb_frontend *fe, |
374 | const enum fe_sec_mini_cmd c) | |
1da177e4 | 375 | { |
b8742700 | 376 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
377 | const u8 mini_tab[2] = { 0x02, 0x03 }; |
378 | ||
379 | int ret; | |
380 | u8 diseqc_mode; | |
381 | ||
382 | if (c > SEC_MINI_B) | |
383 | return -EINVAL; | |
384 | ||
994fc28b MS |
385 | ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); |
386 | if (ret < 0) | |
1da177e4 LT |
387 | return ret; |
388 | ||
994fc28b MS |
389 | ret = mt312_writereg(state, DISEQC_MODE, |
390 | (diseqc_mode & 0x40) | mini_tab[c]); | |
391 | if (ret < 0) | |
1da177e4 LT |
392 | return ret; |
393 | ||
394 | return 0; | |
395 | } | |
396 | ||
0df289a2 MCC |
397 | static int mt312_set_tone(struct dvb_frontend *fe, |
398 | const enum fe_sec_tone_mode t) | |
1da177e4 | 399 | { |
b8742700 | 400 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
401 | const u8 tone_tab[2] = { 0x01, 0x00 }; |
402 | ||
403 | int ret; | |
404 | u8 diseqc_mode; | |
405 | ||
406 | if (t > SEC_TONE_OFF) | |
407 | return -EINVAL; | |
408 | ||
994fc28b MS |
409 | ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); |
410 | if (ret < 0) | |
1da177e4 LT |
411 | return ret; |
412 | ||
994fc28b MS |
413 | ret = mt312_writereg(state, DISEQC_MODE, |
414 | (diseqc_mode & 0x40) | tone_tab[t]); | |
415 | if (ret < 0) | |
1da177e4 LT |
416 | return ret; |
417 | ||
418 | return 0; | |
419 | } | |
420 | ||
0df289a2 MCC |
421 | static int mt312_set_voltage(struct dvb_frontend *fe, |
422 | const enum fe_sec_voltage v) | |
1da177e4 | 423 | { |
b8742700 | 424 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 | 425 | const u8 volt_tab[3] = { 0x00, 0x40, 0x00 }; |
11d3f323 | 426 | u8 val; |
1da177e4 LT |
427 | |
428 | if (v > SEC_VOLTAGE_OFF) | |
429 | return -EINVAL; | |
430 | ||
11d3f323 MS |
431 | val = volt_tab[v]; |
432 | if (state->config->voltage_inverted) | |
433 | val ^= 0x40; | |
434 | ||
435 | return mt312_writereg(state, DISEQC_MODE, val); | |
1da177e4 LT |
436 | } |
437 | ||
0df289a2 | 438 | static int mt312_read_status(struct dvb_frontend *fe, enum fe_status *s) |
1da177e4 | 439 | { |
b8742700 | 440 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
441 | int ret; |
442 | u8 status[3]; | |
443 | ||
444 | *s = 0; | |
445 | ||
994fc28b MS |
446 | ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status)); |
447 | if (ret < 0) | |
1da177e4 LT |
448 | return ret; |
449 | ||
4bd69e7b MCC |
450 | dprintk("QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x, FEC_STATUS: 0x%02x\n", |
451 | status[0], status[1], status[2]); | |
1da177e4 LT |
452 | |
453 | if (status[0] & 0xc0) | |
454 | *s |= FE_HAS_SIGNAL; /* signal noise ratio */ | |
455 | if (status[0] & 0x04) | |
456 | *s |= FE_HAS_CARRIER; /* qpsk carrier lock */ | |
457 | if (status[2] & 0x02) | |
458 | *s |= FE_HAS_VITERBI; /* viterbi lock */ | |
459 | if (status[2] & 0x04) | |
460 | *s |= FE_HAS_SYNC; /* byte align lock */ | |
461 | if (status[0] & 0x01) | |
462 | *s |= FE_HAS_LOCK; /* qpsk lock */ | |
463 | ||
464 | return 0; | |
465 | } | |
466 | ||
89f64758 | 467 | static int mt312_read_ber(struct dvb_frontend *fe, u32 *ber) |
1da177e4 | 468 | { |
b8742700 | 469 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
470 | int ret; |
471 | u8 buf[3]; | |
472 | ||
994fc28b MS |
473 | ret = mt312_read(state, RS_BERCNT_H, buf, 3); |
474 | if (ret < 0) | |
1da177e4 LT |
475 | return ret; |
476 | ||
477 | *ber = ((buf[0] << 16) | (buf[1] << 8) | buf[2]) * 64; | |
478 | ||
479 | return 0; | |
480 | } | |
481 | ||
89f64758 MS |
482 | static int mt312_read_signal_strength(struct dvb_frontend *fe, |
483 | u16 *signal_strength) | |
1da177e4 | 484 | { |
b8742700 | 485 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
486 | int ret; |
487 | u8 buf[3]; | |
488 | u16 agc; | |
489 | s16 err_db; | |
490 | ||
994fc28b MS |
491 | ret = mt312_read(state, AGC_H, buf, sizeof(buf)); |
492 | if (ret < 0) | |
1da177e4 LT |
493 | return ret; |
494 | ||
495 | agc = (buf[0] << 6) | (buf[1] >> 2); | |
496 | err_db = (s16) (((buf[1] & 0x03) << 14) | buf[2] << 6) >> 6; | |
497 | ||
498 | *signal_strength = agc; | |
499 | ||
0b6a3342 | 500 | dprintk("agc=%08x err_db=%hd\n", agc, err_db); |
1da177e4 LT |
501 | |
502 | return 0; | |
503 | } | |
504 | ||
89f64758 | 505 | static int mt312_read_snr(struct dvb_frontend *fe, u16 *snr) |
1da177e4 | 506 | { |
b8742700 | 507 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
508 | int ret; |
509 | u8 buf[2]; | |
510 | ||
1881ee89 | 511 | ret = mt312_read(state, M_SNR_H, buf, sizeof(buf)); |
994fc28b | 512 | if (ret < 0) |
1da177e4 LT |
513 | return ret; |
514 | ||
515 | *snr = 0xFFFF - ((((buf[0] & 0x7f) << 8) | buf[1]) << 1); | |
516 | ||
517 | return 0; | |
518 | } | |
519 | ||
89f64758 | 520 | static int mt312_read_ucblocks(struct dvb_frontend *fe, u32 *ubc) |
1da177e4 | 521 | { |
b8742700 | 522 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
523 | int ret; |
524 | u8 buf[2]; | |
525 | ||
1881ee89 | 526 | ret = mt312_read(state, RS_UBC_H, buf, sizeof(buf)); |
994fc28b | 527 | if (ret < 0) |
1da177e4 LT |
528 | return ret; |
529 | ||
530 | *ubc = (buf[0] << 8) | buf[1]; | |
531 | ||
532 | return 0; | |
533 | } | |
534 | ||
827b5f3e | 535 | static int mt312_set_frontend(struct dvb_frontend *fe) |
1da177e4 | 536 | { |
827b5f3e | 537 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
b8742700 | 538 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
539 | int ret; |
540 | u8 buf[5], config_val; | |
541 | u16 sr; | |
542 | ||
543 | const u8 fec_tab[10] = | |
544 | { 0x00, 0x01, 0x02, 0x04, 0x3f, 0x08, 0x10, 0x20, 0x3f, 0x3f }; | |
545 | const u8 inv_tab[3] = { 0x00, 0x40, 0x80 }; | |
546 | ||
271ddbf7 | 547 | dprintk("%s: Freq %d\n", __func__, p->frequency); |
1da177e4 | 548 | |
f1b1eabf MCC |
549 | if ((p->frequency < fe->ops.info.frequency_min_hz / kHz) |
550 | || (p->frequency > fe->ops.info.frequency_max_hz / kHz)) | |
1da177e4 LT |
551 | return -EINVAL; |
552 | ||
830e4b55 | 553 | if (((int)p->inversion < INVERSION_OFF) |
1da177e4 LT |
554 | || (p->inversion > INVERSION_ON)) |
555 | return -EINVAL; | |
556 | ||
827b5f3e MCC |
557 | if ((p->symbol_rate < fe->ops.info.symbol_rate_min) |
558 | || (p->symbol_rate > fe->ops.info.symbol_rate_max)) | |
1da177e4 LT |
559 | return -EINVAL; |
560 | ||
830e4b55 | 561 | if (((int)p->fec_inner < FEC_NONE) |
827b5f3e | 562 | || (p->fec_inner > FEC_AUTO)) |
1da177e4 LT |
563 | return -EINVAL; |
564 | ||
827b5f3e MCC |
565 | if ((p->fec_inner == FEC_4_5) |
566 | || (p->fec_inner == FEC_8_9)) | |
1da177e4 LT |
567 | return -EINVAL; |
568 | ||
569 | switch (state->id) { | |
570 | case ID_VP310: | |
89f64758 MS |
571 | /* For now we will do this only for the VP310. |
572 | * It should be better for the mt312 as well, | |
573 | * but tuning will be slower. ACCJr 09/29/03 | |
574 | */ | |
682e852e AD |
575 | ret = mt312_readreg(state, CONFIG, &config_val); |
576 | if (ret < 0) | |
1da177e4 | 577 | return ret; |
827b5f3e | 578 | if (p->symbol_rate >= 30000000) { |
89f64758 | 579 | /* Note that 30MS/s should use 90MHz */ |
111221fb | 580 | if (state->freq_mult == 6) { |
89f64758 | 581 | /* We are running 60MHz */ |
111221fb | 582 | state->freq_mult = 9; |
994fc28b MS |
583 | ret = mt312_initfe(fe); |
584 | if (ret < 0) | |
1da177e4 LT |
585 | return ret; |
586 | } | |
89f64758 | 587 | } else { |
111221fb | 588 | if (state->freq_mult == 9) { |
89f64758 | 589 | /* We are running 90MHz */ |
111221fb | 590 | state->freq_mult = 6; |
994fc28b MS |
591 | ret = mt312_initfe(fe); |
592 | if (ret < 0) | |
1da177e4 LT |
593 | return ret; |
594 | } | |
595 | } | |
596 | break; | |
597 | ||
598 | case ID_MT312: | |
6a5cbd59 | 599 | case ID_ZL10313: |
1da177e4 LT |
600 | break; |
601 | ||
602 | default: | |
603 | return -EINVAL; | |
604 | } | |
605 | ||
dea74869 | 606 | if (fe->ops.tuner_ops.set_params) { |
14d24d14 | 607 | fe->ops.tuner_ops.set_params(fe); |
89f64758 MS |
608 | if (fe->ops.i2c_gate_ctrl) |
609 | fe->ops.i2c_gate_ctrl(fe, 0); | |
a81870e0 | 610 | } |
1da177e4 LT |
611 | |
612 | /* sr = (u16)(sr * 256.0 / 1000000.0) */ | |
827b5f3e | 613 | sr = mt312_div(p->symbol_rate * 4, 15625); |
1da177e4 LT |
614 | |
615 | /* SYM_RATE */ | |
616 | buf[0] = (sr >> 8) & 0x3f; | |
617 | buf[1] = (sr >> 0) & 0xff; | |
618 | ||
619 | /* VIT_MODE */ | |
827b5f3e | 620 | buf[2] = inv_tab[p->inversion] | fec_tab[p->fec_inner]; |
1da177e4 LT |
621 | |
622 | /* QPSK_CTRL */ | |
623 | buf[3] = 0x40; /* swap I and Q before QPSK demodulation */ | |
624 | ||
827b5f3e | 625 | if (p->symbol_rate < 10000000) |
1da177e4 LT |
626 | buf[3] |= 0x04; /* use afc mode */ |
627 | ||
628 | /* GO */ | |
629 | buf[4] = 0x01; | |
630 | ||
994fc28b MS |
631 | ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf)); |
632 | if (ret < 0) | |
1da177e4 LT |
633 | return ret; |
634 | ||
9502cdf0 KL |
635 | ret = mt312_reset(state, 0); |
636 | if (ret < 0) | |
637 | return ret; | |
1da177e4 LT |
638 | |
639 | return 0; | |
640 | } | |
641 | ||
7e3e68bc MCC |
642 | static int mt312_get_frontend(struct dvb_frontend *fe, |
643 | struct dtv_frontend_properties *p) | |
1da177e4 | 644 | { |
b8742700 | 645 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
646 | int ret; |
647 | ||
994fc28b MS |
648 | ret = mt312_get_inversion(state, &p->inversion); |
649 | if (ret < 0) | |
1da177e4 LT |
650 | return ret; |
651 | ||
827b5f3e | 652 | ret = mt312_get_symbol_rate(state, &p->symbol_rate); |
994fc28b | 653 | if (ret < 0) |
1da177e4 LT |
654 | return ret; |
655 | ||
827b5f3e | 656 | ret = mt312_get_code_rate(state, &p->fec_inner); |
994fc28b | 657 | if (ret < 0) |
1da177e4 LT |
658 | return ret; |
659 | ||
660 | return 0; | |
661 | } | |
662 | ||
89f64758 | 663 | static int mt312_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) |
a81870e0 | 664 | { |
89f64758 | 665 | struct mt312_state *state = fe->demodulator_priv; |
a81870e0 | 666 | |
6a5cbd59 MS |
667 | u8 val = 0x00; |
668 | int ret; | |
669 | ||
670 | switch (state->id) { | |
671 | case ID_ZL10313: | |
672 | ret = mt312_readreg(state, GPP_CTRL, &val); | |
673 | if (ret < 0) | |
674 | goto error; | |
675 | ||
25985edc | 676 | /* preserve this bit to not accidentally shutdown ADC */ |
6a5cbd59 MS |
677 | val &= 0x80; |
678 | break; | |
a81870e0 | 679 | } |
6a5cbd59 MS |
680 | |
681 | if (enable) | |
682 | val |= 0x40; | |
683 | else | |
684 | val &= ~0x40; | |
685 | ||
686 | ret = mt312_writereg(state, GPP_CTRL, val); | |
687 | ||
688 | error: | |
689 | return ret; | |
a81870e0 AQ |
690 | } |
691 | ||
89f64758 | 692 | static int mt312_sleep(struct dvb_frontend *fe) |
1da177e4 | 693 | { |
b8742700 | 694 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
695 | int ret; |
696 | u8 config; | |
697 | ||
698 | /* reset all registers to defaults */ | |
994fc28b MS |
699 | ret = mt312_reset(state, 1); |
700 | if (ret < 0) | |
1da177e4 LT |
701 | return ret; |
702 | ||
6a5cbd59 MS |
703 | if (state->id == ID_ZL10313) { |
704 | /* reset ADC */ | |
705 | ret = mt312_writereg(state, GPP_CTRL, 0x00); | |
706 | if (ret < 0) | |
707 | return ret; | |
708 | ||
709 | /* full shutdown of ADCs, mpeg bus tristated */ | |
710 | ret = mt312_writereg(state, HW_CTRL, 0x0d); | |
711 | if (ret < 0) | |
712 | return ret; | |
713 | } | |
714 | ||
994fc28b MS |
715 | ret = mt312_readreg(state, CONFIG, &config); |
716 | if (ret < 0) | |
1da177e4 LT |
717 | return ret; |
718 | ||
719 | /* enter standby */ | |
994fc28b MS |
720 | ret = mt312_writereg(state, CONFIG, config & 0x7f); |
721 | if (ret < 0) | |
1da177e4 LT |
722 | return ret; |
723 | ||
724 | return 0; | |
725 | } | |
726 | ||
89f64758 MS |
727 | static int mt312_get_tune_settings(struct dvb_frontend *fe, |
728 | struct dvb_frontend_tune_settings *fesettings) | |
1da177e4 LT |
729 | { |
730 | fesettings->min_delay_ms = 50; | |
731 | fesettings->step_size = 0; | |
732 | fesettings->max_drift = 0; | |
733 | return 0; | |
734 | } | |
735 | ||
89f64758 | 736 | static void mt312_release(struct dvb_frontend *fe) |
1da177e4 | 737 | { |
89f64758 | 738 | struct mt312_state *state = fe->demodulator_priv; |
1da177e4 LT |
739 | kfree(state); |
740 | } | |
741 | ||
111221fb | 742 | #define MT312_SYS_CLK 90000000UL /* 90 MHz */ |
bd336e63 | 743 | static const struct dvb_frontend_ops mt312_ops = { |
827b5f3e | 744 | .delsys = { SYS_DVBS }, |
1da177e4 LT |
745 | .info = { |
746 | .name = "Zarlink ???? DVB-S", | |
f1b1eabf MCC |
747 | .frequency_min_hz = 950 * MHz, |
748 | .frequency_max_hz = 2150 * MHz, | |
0389b34e | 749 | /* FIXME: adjust freq to real used xtal */ |
f1b1eabf | 750 | .frequency_stepsize_hz = MT312_PLL_CLK / 128, |
111221fb | 751 | .symbol_rate_min = MT312_SYS_CLK / 128, /* FIXME as above */ |
1da177e4 LT |
752 | .symbol_rate_max = MT312_SYS_CLK / 2, |
753 | .caps = | |
754 | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | | |
755 | FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | | |
756 | FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_MUTE_TS | | |
9101e622 | 757 | FE_CAN_RECOVER |
1da177e4 LT |
758 | }, |
759 | ||
760 | .release = mt312_release, | |
761 | ||
762 | .init = mt312_initfe, | |
763 | .sleep = mt312_sleep, | |
a81870e0 | 764 | .i2c_gate_ctrl = mt312_i2c_gate_ctrl, |
1da177e4 | 765 | |
827b5f3e MCC |
766 | .set_frontend = mt312_set_frontend, |
767 | .get_frontend = mt312_get_frontend, | |
1da177e4 LT |
768 | .get_tune_settings = mt312_get_tune_settings, |
769 | ||
770 | .read_status = mt312_read_status, | |
771 | .read_ber = mt312_read_ber, | |
772 | .read_signal_strength = mt312_read_signal_strength, | |
773 | .read_snr = mt312_read_snr, | |
774 | .read_ucblocks = mt312_read_ucblocks, | |
775 | ||
776 | .diseqc_send_master_cmd = mt312_send_master_cmd, | |
777 | .diseqc_send_burst = mt312_send_burst, | |
778 | .set_tone = mt312_set_tone, | |
779 | .set_voltage = mt312_set_voltage, | |
780 | }; | |
781 | ||
e4671b6b | 782 | struct dvb_frontend *mt312_attach(const struct mt312_config *config, |
89f64758 | 783 | struct i2c_adapter *i2c) |
805e660c | 784 | { |
89f64758 | 785 | struct mt312_state *state = NULL; |
805e660c AB |
786 | |
787 | /* allocate memory for the internal state */ | |
084e24ac | 788 | state = kzalloc(sizeof(struct mt312_state), GFP_KERNEL); |
805e660c AB |
789 | if (state == NULL) |
790 | goto error; | |
791 | ||
792 | /* setup the state */ | |
793 | state->config = config; | |
794 | state->i2c = i2c; | |
805e660c AB |
795 | |
796 | /* check if the demod is there */ | |
797 | if (mt312_readreg(state, ID, &state->id) < 0) | |
798 | goto error; | |
799 | ||
dea74869 | 800 | /* create dvb_frontend */ |
e4671b6b | 801 | memcpy(&state->frontend.ops, &mt312_ops, |
89f64758 | 802 | sizeof(struct dvb_frontend_ops)); |
dea74869 PB |
803 | state->frontend.demodulator_priv = state; |
804 | ||
805e660c AB |
805 | switch (state->id) { |
806 | case ID_VP310: | |
cc1e6315 MCC |
807 | strscpy(state->frontend.ops.info.name, "Zarlink VP310 DVB-S", |
808 | sizeof(state->frontend.ops.info.name)); | |
111221fb MS |
809 | state->xtal = MT312_PLL_CLK; |
810 | state->freq_mult = 9; | |
805e660c AB |
811 | break; |
812 | case ID_MT312: | |
cc1e6315 MCC |
813 | strscpy(state->frontend.ops.info.name, "Zarlink MT312 DVB-S", |
814 | sizeof(state->frontend.ops.info.name)); | |
111221fb MS |
815 | state->xtal = MT312_PLL_CLK; |
816 | state->freq_mult = 6; | |
805e660c | 817 | break; |
6a5cbd59 | 818 | case ID_ZL10313: |
cc1e6315 MCC |
819 | strscpy(state->frontend.ops.info.name, "Zarlink ZL10313 DVB-S", |
820 | sizeof(state->frontend.ops.info.name)); | |
6a5cbd59 MS |
821 | state->xtal = MT312_PLL_CLK_10_111; |
822 | state->freq_mult = 9; | |
823 | break; | |
805e660c | 824 | default: |
4bd69e7b | 825 | printk(KERN_WARNING "Only Zarlink VP310/MT312/ZL10313 are supported chips.\n"); |
805e660c AB |
826 | goto error; |
827 | } | |
828 | ||
805e660c AB |
829 | return &state->frontend; |
830 | ||
831 | error: | |
832 | kfree(state); | |
833 | return NULL; | |
834 | } | |
e4671b6b | 835 | EXPORT_SYMBOL(mt312_attach); |
805e660c | 836 | |
1da177e4 LT |
837 | module_param(debug, int, 0644); |
838 | MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); | |
839 | ||
6a5cbd59 | 840 | MODULE_DESCRIPTION("Zarlink VP310/MT312/ZL10313 DVB-S Demodulator driver"); |
1da177e4 | 841 | MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>"); |
e4671b6b | 842 | MODULE_AUTHOR("Matthias Schwarzott <zzam@gentoo.org>"); |
1da177e4 LT |
843 | MODULE_LICENSE("GPL"); |
844 |