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[media] mb86a20s: Fix estimate_rate setting
[linux-2.6-block.git] / drivers / media / dvb-frontends / mb86a20s.c
CommitLineData
b9ede79a
MCC		 1/*
2 * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver
3 *
a77cfcac 4 * Copyright (C) 2010-2013 Mauro Carvalho Chehab <mchehab@redhat.com>
b9ede79a
MCC		 5 * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com>
6 *
b9ede79a
MCC		 7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 */
16
17#include <linux/kernel.h>
18#include <asm/div64.h>
19
20#include "dvb_frontend.h"
21#include "mb86a20s.h"
22
4f62a20d
MCC		 23#define NUM_LAYERS 3
24
b9ede79a
MCC		 25static int debug = 1;
26module_param(debug, int, 0644);
27MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
28
04fa725e
MCC		 29enum mb86a20s_bandwidth {
30 MB86A20S_13SEG = 0,
31 MB86A20S_13SEG_PARTIAL = 1,
32 MB86A20S_1SEG = 2,
33 MB86A20S_3SEG = 3,
34};
35
36u8 mb86a20s_subchannel[] = {
37 0xb0, 0xc0, 0xd0, 0xe0,
38 0xf0, 0x00, 0x10, 0x20,
39};
40
b9ede79a
MCC		 41struct mb86a20s_state {
42 struct i2c_adapter *i2c;
43 const struct mb86a20s_config *config;
09b6d21e 44 u32 last_frequency;
b9ede79a
MCC		 45
46 struct dvb_frontend frontend;
c736a5f2 47
768e6dad 48 u32 if_freq;
04fa725e
MCC		 49 enum mb86a20s_bandwidth bw;
50 bool inversion;
51 u32 subchannel;
768e6dad 52
4f62a20d 53 u32 estimated_rate[NUM_LAYERS];
0921ecfd 54 unsigned long get_strength_time;
d01a8ee3 55
c736a5f2 56 bool need_init;
b9ede79a
MCC		 57};
58
59struct regdata {
60 u8 reg;
61 u8 data;
62};
63
d01a8ee3
MCC		 64#define BER_SAMPLING_RATE 1 /* Seconds */
65
b9ede79a
MCC		 66/*
67 * Initialization sequence: Use whatevere default values that PV SBTVD
68 * does on its initialisation, obtained via USB snoop
69 */
768e6dad 70static struct regdata mb86a20s_init1[] = {
b9ede79a
MCC		 71 { 0x70, 0x0f },
72 { 0x70, 0xff },
73 { 0x08, 0x01 },
17e67d4c 74 { 0x50, 0xd1 }, { 0x51, 0x20 },
768e6dad
MCC		 75};
76
77static struct regdata mb86a20s_init2[] = {
ebe96749 78 { 0x28, 0x22 }, { 0x29, 0x00 }, { 0x2a, 0x1f }, { 0x2b, 0xf0 },
b9ede79a 79 { 0x3b, 0x21 },
17e67d4c 80 { 0x3c, 0x38 },
b9ede79a 81 { 0x01, 0x0d },
17e67d4c 82 { 0x04, 0x08 }, { 0x05, 0x03 },
a7025edf 83 { 0x04, 0x0e }, { 0x05, 0x00 },
17e67d4c
MCC		 84 { 0x04, 0x0f }, { 0x05, 0x37 },
85 { 0x04, 0x0b }, { 0x05, 0x78 },
a7025edf 86 { 0x04, 0x00 }, { 0x05, 0x00 },
17e67d4c
MCC		 87 { 0x04, 0x01 }, { 0x05, 0x1e },
88 { 0x04, 0x02 }, { 0x05, 0x07 },
89 { 0x04, 0x03 }, { 0x05, 0xd0 },
a7025edf
MCC		 90 { 0x04, 0x09 }, { 0x05, 0x00 },
91 { 0x04, 0x0a }, { 0x05, 0xff },
17e67d4c 92 { 0x04, 0x27 }, { 0x05, 0x00 },
a7025edf 93 { 0x04, 0x28 }, { 0x05, 0x00 },
17e67d4c
MCC		 94 { 0x04, 0x1e }, { 0x05, 0x00 },
95 { 0x04, 0x29 }, { 0x05, 0x64 },
96 { 0x04, 0x32 }, { 0x05, 0x02 },
a7025edf
MCC		 97 { 0x04, 0x14 }, { 0x05, 0x02 },
98 { 0x04, 0x04 }, { 0x05, 0x00 },
99 { 0x04, 0x05 }, { 0x05, 0x22 },
100 { 0x04, 0x06 }, { 0x05, 0x0e },
101 { 0x04, 0x07 }, { 0x05, 0xd8 },
102 { 0x04, 0x12 }, { 0x05, 0x00 },
103 { 0x04, 0x13 }, { 0x05, 0xff },
ebe96749
MCC		 104 { 0x04, 0x15 }, { 0x05, 0x4e },
105 { 0x04, 0x16 }, { 0x05, 0x20 },
09b6d21e
MCC		 106
107 /*
108 * On this demod, when the bit count reaches the count below,
109 * it collects the bit error count. The bit counters are initialized
110 * to 65535 here. This warrants that all of them will be quickly
111 * calculated when device gets locked. As TMCC is parsed, the values
d01a8ee3 112 * will be adjusted later in the driver's code.
09b6d21e
MCC		 113 */
114 { 0x52, 0x01 }, /* Turn on BER before Viterbi */
115 { 0x50, 0xa7 }, { 0x51, 0x00 },
a7025edf
MCC		 116 { 0x50, 0xa8 }, { 0x51, 0xff },
117 { 0x50, 0xa9 }, { 0x51, 0xff },
09b6d21e 118 { 0x50, 0xaa }, { 0x51, 0x00 },
a7025edf
MCC		 119 { 0x50, 0xab }, { 0x51, 0xff },
120 { 0x50, 0xac }, { 0x51, 0xff },
09b6d21e 121 { 0x50, 0xad }, { 0x51, 0x00 },
a7025edf
MCC		 122 { 0x50, 0xae }, { 0x51, 0xff },
123 { 0x50, 0xaf }, { 0x51, 0xff },
09b6d21e 124
d9b6f08a
MCC		 125 /*
126 * On this demod, post BER counts blocks. When the count reaches the
127 * value below, it collects the block error count. The block counters
128 * are initialized to 127 here. This warrants that all of them will be
129 * quickly calculated when device gets locked. As TMCC is parsed, the
130 * values will be adjusted later in the driver's code.
131 */
132 { 0x5e, 0x07 }, /* Turn on BER after Viterbi */
133 { 0x50, 0xdc }, { 0x51, 0x00 },
134 { 0x50, 0xdd }, { 0x51, 0x7f },
135 { 0x50, 0xde }, { 0x51, 0x00 },
136 { 0x50, 0xdf }, { 0x51, 0x7f },
137 { 0x50, 0xe0 }, { 0x51, 0x00 },
138 { 0x50, 0xe1 }, { 0x51, 0x7f },
593ae89a
MCC		 139
140 /*
141 * On this demod, when the block count reaches the count below,
142 * it collects the block error count. The block counters are initialized
143 * to 127 here. This warrants that all of them will be quickly
144 * calculated when device gets locked. As TMCC is parsed, the values
145 * will be adjusted later in the driver's code.
146 */
147 { 0x50, 0xb0 }, { 0x51, 0x07 }, /* Enable PER */
148 { 0x50, 0xb2 }, { 0x51, 0x00 },
149 { 0x50, 0xb3 }, { 0x51, 0x7f },
150 { 0x50, 0xb4 }, { 0x51, 0x00 },
151 { 0x50, 0xb5 }, { 0x51, 0x7f },
152 { 0x50, 0xb6 }, { 0x51, 0x00 },
153 { 0x50, 0xb7 }, { 0x51, 0x7f },
25188bd0
MCC		 154
155 { 0x50, 0x50 }, { 0x51, 0x02 }, /* MER manual mode */
09b6d21e
MCC		 156 { 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */
157 { 0x45, 0x04 }, /* CN symbol 4 */
25188bd0
MCC		 158 { 0x48, 0x04 }, /* CN manual mode */
159
a7025edf
MCC		 160 { 0x50, 0xd5 }, { 0x51, 0x01 }, /* Serial */
161 { 0x50, 0xd6 }, { 0x51, 0x1f },
162 { 0x50, 0xd2 }, { 0x51, 0x03 },
17e67d4c
MCC		 163 { 0x50, 0xd7 }, { 0x51, 0xbf },
164 { 0x28, 0x74 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0xff },
165 { 0x28, 0x46 }, { 0x29, 0x00 }, { 0x2a, 0x1a }, { 0x2b, 0x0c },
ce77d120
MCC		 166
167 { 0x04, 0x40 }, { 0x05, 0x00 },
17e67d4c
MCC		 168 { 0x28, 0x00 }, { 0x2b, 0x08 },
169 { 0x28, 0x05 }, { 0x2b, 0x00 },
b9ede79a 170 { 0x1c, 0x01 },
17e67d4c
MCC		 171 { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x1f },
172 { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x18 },
173 { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x12 },
174 { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x30 },
175 { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x37 },
176 { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 },
177 { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x09 },
178 { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x06 },
179 { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x7b },
180 { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x76 },
181 { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x7d },
182 { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x08 },
183 { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0b },
184 { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 },
185 { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xf2 },
186 { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xf3 },
187 { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x05 },
188 { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 },
189 { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f },
190 { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xef },
191 { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xd8 },
192 { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xf1 },
193 { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x3d },
194 { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x94 },
195 { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0xba },
a7025edf
MCC		 196 { 0x50, 0x1e }, { 0x51, 0x5d },
197 { 0x50, 0x22 }, { 0x51, 0x00 },
198 { 0x50, 0x23 }, { 0x51, 0xc8 },
199 { 0x50, 0x24 }, { 0x51, 0x00 },
200 { 0x50, 0x25 }, { 0x51, 0xf0 },
201 { 0x50, 0x26 }, { 0x51, 0x00 },
202 { 0x50, 0x27 }, { 0x51, 0xc3 },
203 { 0x50, 0x39 }, { 0x51, 0x02 },
17e67d4c
MCC		 204 { 0xec, 0x0f },
205 { 0xeb, 0x1f },
ebe96749 206 { 0x28, 0x6a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 },
b9ede79a
MCC		 207 { 0xd0, 0x00 },
208};
209
210static struct regdata mb86a20s_reset_reception[] = {
211 { 0x70, 0xf0 },
212 { 0x70, 0xff },
213 { 0x08, 0x01 },
214 { 0x08, 0x00 },
215};
216
d9b6f08a
MCC		 217static struct regdata mb86a20s_per_ber_reset[] = {
218 { 0x53, 0x00 }, /* pre BER Counter reset */
09b6d21e 219 { 0x53, 0x07 },
09b6d21e 220
d9b6f08a
MCC		 221 { 0x5f, 0x00 }, /* post BER Counter reset */
222 { 0x5f, 0x07 },
223
09b6d21e
MCC		 224 { 0x50, 0xb1 }, /* PER Counter reset */
225 { 0x51, 0x07 },
226 { 0x51, 0x00 },
227};
228
dd4493ef
MCC		 229/*
230 * I2C read/write functions and macros
231 */
232
b9ede79a 233static int mb86a20s_i2c_writereg(struct mb86a20s_state *state,
09b6d21e 234 u8 i2c_addr, u8 reg, u8 data)
b9ede79a
MCC		 235{
236 u8 buf[] = { reg, data };
237 struct i2c_msg msg = {
238 .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
239 };
240 int rc;
241
242 rc = i2c_transfer(state->i2c, &msg, 1);
243 if (rc != 1) {
f66d81b5
MCC		 244 dev_err(&state->i2c->dev,
245 "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n",
246 __func__, rc, reg, data);
b9ede79a
MCC		 247 return rc;
248 }
249
250 return 0;
251}
252
253static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state,
254 u8 i2c_addr, struct regdata *rd, int size)
255{
256 int i, rc;
257
258 for (i = 0; i < size; i++) {
259 rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg,
260 rd[i].data);
261 if (rc < 0)
262 return rc;
263 }
264 return 0;
265}
266
267static int mb86a20s_i2c_readreg(struct mb86a20s_state *state,
268 u8 i2c_addr, u8 reg)
269{
270 u8 val;
271 int rc;
272 struct i2c_msg msg[] = {
273 { .addr = i2c_addr, .flags = 0, .buf = &reg, .len = 1 },
274 { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 }
275 };
276
277 rc = i2c_transfer(state->i2c, msg, 2);
278
279 if (rc != 2) {
f66d81b5
MCC		 280 dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n",
281 __func__, reg, rc);
282 return (rc < 0) ? rc : -EIO;
b9ede79a
MCC		 283 }
284
285 return val;
286}
287
288#define mb86a20s_readreg(state, reg) \
289 mb86a20s_i2c_readreg(state, state->config->demod_address, reg)
290#define mb86a20s_writereg(state, reg, val) \
291 mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val)
292#define mb86a20s_writeregdata(state, regdata) \
293 mb86a20s_i2c_writeregdata(state, state->config->demod_address, \
294 regdata, ARRAY_SIZE(regdata))
295
09b6d21e
MCC		 296/*
297 * Ancillary internal routines (likely compiled inlined)
298 *
299 * The functions below assume that gateway lock has already obtained
300 */
301
dd4493ef 302static int mb86a20s_read_status(struct dvb_frontend *fe, fe_status_t *status)
b9ede79a
MCC		 303{
304 struct mb86a20s_state *state = fe->demodulator_priv;
dd4493ef 305 int val;
b9ede79a 306
dd4493ef 307 *status = 0;
b9ede79a 308
dd4493ef
MCC		 309 val = mb86a20s_readreg(state, 0x0a) & 0xf;
310 if (val < 0)
311 return val;
68541cda 312
dd4493ef
MCC		 313 if (val >= 2)
314 *status |= FE_HAS_SIGNAL;
b9ede79a 315
dd4493ef
MCC		 316 if (val >= 4)
317 *status |= FE_HAS_CARRIER;
7572f9c5 318
dd4493ef
MCC		 319 if (val >= 5)
320 *status |= FE_HAS_VITERBI;
7572f9c5 321
dd4493ef
MCC		 322 if (val >= 7)
323 *status |= FE_HAS_SYNC;
68541cda 324
dd4493ef
MCC		 325 if (val >= 8) /* Maybe 9? */
326 *status |= FE_HAS_LOCK;
327
f66d81b5
MCC		 328 dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n",
329 __func__, *status, val);
dd4493ef 330
15b1c5a0 331 return val;
b9ede79a
MCC		 332}
333
09b6d21e 334static int mb86a20s_read_signal_strength(struct dvb_frontend *fe)
b9ede79a
MCC		 335{
336 struct mb86a20s_state *state = fe->demodulator_priv;
0921ecfd 337 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
09b6d21e 338 int rc;
b9ede79a 339 unsigned rf_max, rf_min, rf;
68541cda 340
0921ecfd
MCC		 341 if (state->get_strength_time &&
342 (!time_after(jiffies, state->get_strength_time)))
343 return c->strength.stat[0].uvalue;
344
345 /* Reset its value if an error happen */
346 c->strength.stat[0].uvalue = 0;
347
b9ede79a
MCC		 348 /* Does a binary search to get RF strength */
349 rf_max = 0xfff;
350 rf_min = 0;
351 do {
352 rf = (rf_max + rf_min) / 2;
09b6d21e
MCC		 353 rc = mb86a20s_writereg(state, 0x04, 0x1f);
354 if (rc < 0)
355 return rc;
356 rc = mb86a20s_writereg(state, 0x05, rf >> 8);
357 if (rc < 0)
358 return rc;
359 rc = mb86a20s_writereg(state, 0x04, 0x20);
360 if (rc < 0)
361 return rc;
dad78c56 362 rc = mb86a20s_writereg(state, 0x05, rf);
09b6d21e
MCC		 363 if (rc < 0)
364 return rc;
b9ede79a 365
09b6d21e
MCC		 366 rc = mb86a20s_readreg(state, 0x02);
367 if (rc < 0)
368 return rc;
369 if (rc & 0x08)
b9ede79a
MCC		 370 rf_min = (rf_max + rf_min) / 2;
371 else
372 rf_max = (rf_max + rf_min) / 2;
373 if (rf_max - rf_min < 4) {
09b6d21e
MCC		 374 rf = (rf_max + rf_min) / 2;
375
376 /* Rescale it from 2^12 (4096) to 2^16 */
0921ecfd
MCC		 377 rf = rf << (16 - 12);
378 if (rf)
379 rf |= (1 << 12) - 1;
380
f66d81b5
MCC		 381 dev_dbg(&state->i2c->dev,
382 "%s: signal strength = %d (%d < RF=%d < %d)\n",
383 __func__, rf, rf_min, rf >> 4, rf_max);
0921ecfd
MCC		 384 c->strength.stat[0].uvalue = rf;
385 state->get_strength_time = jiffies +
386 msecs_to_jiffies(1000);
387 return 0;
b9ede79a
MCC		 388 }
389 } while (1);
b9ede79a
MCC		 390}
391
959a119f
MCC		 392static int mb86a20s_get_modulation(struct mb86a20s_state *state,
393 unsigned layer)
394{
395 int rc;
396 static unsigned char reg[] = {
397 [0] = 0x86, /* Layer A */
398 [1] = 0x8a, /* Layer B */
399 [2] = 0x8e, /* Layer C */
400 };
401
82033bc5 402 if (layer >= ARRAY_SIZE(reg))
959a119f
MCC		 403 return -EINVAL;
404 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
405 if (rc < 0)
406 return rc;
407 rc = mb86a20s_readreg(state, 0x6e);
408 if (rc < 0)
409 return rc;
04585921 410 switch ((rc >> 4) & 0x07) {
959a119f
MCC		 411 case 0:
412 return DQPSK;
413 case 1:
414 return QPSK;
415 case 2:
416 return QAM_16;
417 case 3:
418 return QAM_64;
419 default:
420 return QAM_AUTO;
421 }
422}
423
424static int mb86a20s_get_fec(struct mb86a20s_state *state,
425 unsigned layer)
426{
427 int rc;
428
429 static unsigned char reg[] = {
430 [0] = 0x87, /* Layer A */
431 [1] = 0x8b, /* Layer B */
432 [2] = 0x8f, /* Layer C */
433 };
434
82033bc5 435 if (layer >= ARRAY_SIZE(reg))
959a119f
MCC		 436 return -EINVAL;
437 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
438 if (rc < 0)
439 return rc;
440 rc = mb86a20s_readreg(state, 0x6e);
441 if (rc < 0)
442 return rc;
04585921 443 switch ((rc >> 4) & 0x07) {
959a119f
MCC		 444 case 0:
445 return FEC_1_2;
446 case 1:
447 return FEC_2_3;
448 case 2:
449 return FEC_3_4;
450 case 3:
451 return FEC_5_6;
452 case 4:
453 return FEC_7_8;
454 default:
455 return FEC_AUTO;
456 }
457}
458
459static int mb86a20s_get_interleaving(struct mb86a20s_state *state,
460 unsigned layer)
461{
462 int rc;
463
464 static unsigned char reg[] = {
465 [0] = 0x88, /* Layer A */
466 [1] = 0x8c, /* Layer B */
467 [2] = 0x90, /* Layer C */
468 };
469
82033bc5 470 if (layer >= ARRAY_SIZE(reg))
959a119f
MCC		 471 return -EINVAL;
472 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
473 if (rc < 0)
474 return rc;
475 rc = mb86a20s_readreg(state, 0x6e);
476 if (rc < 0)
477 return rc;
04585921
MCC		 478
479 switch ((rc >> 4) & 0x07) {
480 case 1:
481 return GUARD_INTERVAL_1_4;
482 case 2:
483 return GUARD_INTERVAL_1_8;
484 case 3:
485 return GUARD_INTERVAL_1_16;
486 case 4:
487 return GUARD_INTERVAL_1_32;
488
489 default:
490 case 0:
491 return GUARD_INTERVAL_AUTO;
492 }
959a119f
MCC		 493}
494
495static int mb86a20s_get_segment_count(struct mb86a20s_state *state,
496 unsigned layer)
497{
498 int rc, count;
959a119f
MCC		 499 static unsigned char reg[] = {
500 [0] = 0x89, /* Layer A */
501 [1] = 0x8d, /* Layer B */
502 [2] = 0x91, /* Layer C */
503 };
504
f66d81b5
MCC		 505 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
506
82033bc5 507 if (layer >= ARRAY_SIZE(reg))
959a119f 508 return -EINVAL;
f66d81b5 509
959a119f
MCC		 510 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
511 if (rc < 0)
512 return rc;
513 rc = mb86a20s_readreg(state, 0x6e);
514 if (rc < 0)
515 return rc;
516 count = (rc >> 4) & 0x0f;
517
f66d81b5
MCC		 518 dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count);
519
959a119f
MCC		 520 return count;
521}
522
a77cfcac
MCC		 523static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe)
524{
f66d81b5 525 struct mb86a20s_state *state = fe->demodulator_priv;
a77cfcac
MCC		 526 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
527
f66d81b5
MCC		 528 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
529
a77cfcac
MCC		 530 /* Fixed parameters */
531 c->delivery_system = SYS_ISDBT;
532 c->bandwidth_hz = 6000000;
533
534 /* Initialize values that will be later autodetected */
535 c->isdbt_layer_enabled = 0;
536 c->transmission_mode = TRANSMISSION_MODE_AUTO;
537 c->guard_interval = GUARD_INTERVAL_AUTO;
538 c->isdbt_sb_mode = 0;
539 c->isdbt_sb_segment_count = 0;
540}
541
d01a8ee3
MCC		 542/*
543 * Estimates the bit rate using the per-segment bit rate given by
544 * ABNT/NBR 15601 spec (table 4).
545 */
546static u32 isdbt_rate[3][5][4] = {
547 { /* DQPSK/QPSK */
548 { 280850, 312060, 330420, 340430 }, /* 1/2 */
549 { 374470, 416080, 440560, 453910 }, /* 2/3 */
550 { 421280, 468090, 495630, 510650 }, /* 3/4 */
551 { 468090, 520100, 550700, 567390 }, /* 5/6 */
552 { 491500, 546110, 578230, 595760 }, /* 7/8 */
553 }, { /* QAM16 */
554 { 561710, 624130, 660840, 680870 }, /* 1/2 */
555 { 748950, 832170, 881120, 907820 }, /* 2/3 */
556 { 842570, 936190, 991260, 1021300 }, /* 3/4 */
557 { 936190, 1040210, 1101400, 1134780 }, /* 5/6 */
558 { 983000, 1092220, 1156470, 1191520 }, /* 7/8 */
559 }, { /* QAM64 */
560 { 842570, 936190, 991260, 1021300 }, /* 1/2 */
561 { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */
562 { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */
563 { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */
564 { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */
565 }
566};
567
568static void mb86a20s_layer_bitrate(struct dvb_frontend *fe, u32 layer,
569 u32 modulation, u32 fec, u32 interleaving,
570 u32 segment)
571{
572 struct mb86a20s_state *state = fe->demodulator_priv;
573 u32 rate;
574 int m, f, i;
575
576 /*
577 * If modulation/fec/interleaving is not detected, the default is
578 * to consider the lowest bit rate, to avoid taking too long time
579 * to get BER.
580 */
581 switch (modulation) {
582 case DQPSK:
583 case QPSK:
584 default:
585 m = 0;
586 break;
587 case QAM_16:
588 m = 1;
589 break;
590 case QAM_64:
591 m = 2;
592 break;
593 }
594
595 switch (fec) {
596 default:
597 case FEC_1_2:
598 case FEC_AUTO:
599 f = 0;
600 break;
601 case FEC_2_3:
602 f = 1;
603 break;
604 case FEC_3_4:
605 f = 2;
606 break;
607 case FEC_5_6:
608 f = 3;
609 break;
610 case FEC_7_8:
611 f = 4;
612 break;
613 }
614
615 switch (interleaving) {
616 default:
617 case GUARD_INTERVAL_1_4:
618 i = 0;
619 break;
620 case GUARD_INTERVAL_1_8:
621 i = 1;
622 break;
623 case GUARD_INTERVAL_1_16:
624 i = 2;
625 break;
626 case GUARD_INTERVAL_1_32:
627 i = 3;
628 break;
629 }
630
631 /* Samples BER at BER_SAMPLING_RATE seconds */
632 rate = isdbt_rate[m][f][i] * segment * BER_SAMPLING_RATE;
633
634 /* Avoids sampling too quickly or to overflow the register */
635 if (rate < 256)
636 rate = 256;
637 else if (rate > (1 << 24) - 1)
638 rate = (1 << 24) - 1;
639
640 dev_dbg(&state->i2c->dev,
641 "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n",
642 __func__, 'A' + layer, segment * isdbt_rate[m][f][i]/1000,
643 rate, rate);
644
b1f89331 645 state->estimated_rate[layer] = rate;
d01a8ee3
MCC		 646}
647
648
7c61d80a 649static int mb86a20s_get_frontend(struct dvb_frontend *fe)
b9ede79a 650{
959a119f 651 struct mb86a20s_state *state = fe->demodulator_priv;
a77cfcac 652 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
5cb88ca8 653 int layer, rc;
b9ede79a 654
f66d81b5
MCC		 655 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
656
a77cfcac
MCC		 657 /* Reset frontend cache to default values */
658 mb86a20s_reset_frontend_cache(fe);
959a119f 659
959a119f
MCC		 660 /* Check for partial reception */
661 rc = mb86a20s_writereg(state, 0x6d, 0x85);
a77cfcac
MCC		 662 if (rc < 0)
663 return rc;
664 rc = mb86a20s_readreg(state, 0x6e);
665 if (rc < 0)
666 return rc;
667 c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0;
959a119f
MCC		 668
669 /* Get per-layer data */
a77cfcac 670
5cb88ca8 671 for (layer = 0; layer < NUM_LAYERS; layer++) {
f66d81b5 672 dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n",
5cb88ca8 673 __func__, 'A' + layer);
f66d81b5 674
5cb88ca8 675 rc = mb86a20s_get_segment_count(state, layer);
a77cfcac 676 if (rc < 0)
f66d81b5 677 goto noperlayer_error;
d01a8ee3 678 if (rc >= 0 && rc < 14) {
5cb88ca8 679 c->layer[layer].segment_count = rc;
d01a8ee3 680 } else {
5cb88ca8
MCC		 681 c->layer[layer].segment_count = 0;
682 state->estimated_rate[layer] = 0;
959a119f 683 continue;
a77cfcac 684 }
5cb88ca8
MCC		 685 c->isdbt_layer_enabled |= 1 << layer;
686 rc = mb86a20s_get_modulation(state, layer);
a77cfcac 687 if (rc < 0)
f66d81b5
MCC		 688 goto noperlayer_error;
689 dev_dbg(&state->i2c->dev, "%s: modulation %d.\n",
690 __func__, rc);
5cb88ca8
MCC		 691 c->layer[layer].modulation = rc;
692 rc = mb86a20s_get_fec(state, layer);
a77cfcac 693 if (rc < 0)
f66d81b5
MCC		 694 goto noperlayer_error;
695 dev_dbg(&state->i2c->dev, "%s: FEC %d.\n",
696 __func__, rc);
5cb88ca8
MCC		 697 c->layer[layer].fec = rc;
698 rc = mb86a20s_get_interleaving(state, layer);
a77cfcac 699 if (rc < 0)
f66d81b5
MCC		 700 goto noperlayer_error;
701 dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n",
702 __func__, rc);
5cb88ca8
MCC		 703 c->layer[layer].interleaving = rc;
704 mb86a20s_layer_bitrate(fe, layer, c->layer[layer].modulation,
705 c->layer[layer].fec,
706 c->layer[layer].interleaving,
707 c->layer[layer].segment_count);
959a119f
MCC		 708 }
709
959a119f 710 rc = mb86a20s_writereg(state, 0x6d, 0x84);
a77cfcac
MCC		 711 if (rc < 0)
712 return rc;
713 if ((rc & 0x60) == 0x20) {
714 c->isdbt_sb_mode = 1;
959a119f 715 /* At least, one segment should exist */
a77cfcac
MCC		 716 if (!c->isdbt_sb_segment_count)
717 c->isdbt_sb_segment_count = 1;
718 }
959a119f
MCC		 719
720 /* Get transmission mode and guard interval */
959a119f 721 rc = mb86a20s_readreg(state, 0x07);
a77cfcac
MCC		 722 if (rc < 0)
723 return rc;
724 if ((rc & 0x60) == 0x20) {
725 switch (rc & 0x0c >> 2) {
726 case 0:
727 c->transmission_mode = TRANSMISSION_MODE_2K;
728 break;
729 case 1:
730 c->transmission_mode = TRANSMISSION_MODE_4K;
731 break;
732 case 2:
733 c->transmission_mode = TRANSMISSION_MODE_8K;
734 break;
959a119f 735 }
a77cfcac
MCC		 736 }
737 if (!(rc & 0x10)) {
738 switch (rc & 0x3) {
739 case 0:
740 c->guard_interval = GUARD_INTERVAL_1_4;
741 break;
742 case 1:
743 c->guard_interval = GUARD_INTERVAL_1_8;
744 break;
745 case 2:
746 c->guard_interval = GUARD_INTERVAL_1_16;
747 break;
959a119f
MCC		 748 }
749 }
09b6d21e 750 return 0;
959a119f 751
f66d81b5 752noperlayer_error:
b9ede79a 753
09b6d21e
MCC		 754 /* per-layer info is incomplete; discard all per-layer */
755 c->isdbt_layer_enabled = 0;
756
757 return rc;
758}
759
760static int mb86a20s_reset_counters(struct dvb_frontend *fe)
761{
762 struct mb86a20s_state *state = fe->demodulator_priv;
763 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
764 int rc, val;
765
766 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
767
768 /* Reset the counters, if the channel changed */
769 if (state->last_frequency != c->frequency) {
09b6d21e
MCC		 770 memset(&c->cnr, 0, sizeof(c->cnr));
771 memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error));
772 memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count));
d9b6f08a
MCC		 773 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
774 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
09b6d21e
MCC		 775 memset(&c->block_error, 0, sizeof(c->block_error));
776 memset(&c->block_count, 0, sizeof(c->block_count));
777
778 state->last_frequency = c->frequency;
779 }
780
781 /* Clear status for most stats */
782
d9b6f08a
MCC		 783 /* BER/PER counter reset */
784 rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset);
09b6d21e
MCC		 785 if (rc < 0)
786 goto err;
787
788 /* CNR counter reset */
789 rc = mb86a20s_readreg(state, 0x45);
790 if (rc < 0)
791 goto err;
792 val = rc;
793 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
794 if (rc < 0)
795 goto err;
796 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
797 if (rc < 0)
798 goto err;
799
800 /* MER counter reset */
801 rc = mb86a20s_writereg(state, 0x50, 0x50);
802 if (rc < 0)
803 goto err;
804 rc = mb86a20s_readreg(state, 0x51);
805 if (rc < 0)
806 goto err;
807 val = rc;
808 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
809 if (rc < 0)
810 goto err;
811 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
812 if (rc < 0)
813 goto err;
814
149d518a 815 goto ok;
09b6d21e 816err:
149d518a
MCC		 817 dev_err(&state->i2c->dev,
818 "%s: Can't reset FE statistics (error %d).\n",
819 __func__, rc);
820ok:
a77cfcac 821 return rc;
09b6d21e
MCC		 822}
823
ad0abbf1
MCC		 824static int mb86a20s_get_pre_ber(struct dvb_frontend *fe,
825 unsigned layer,
826 u32 *error, u32 *count)
149d518a
MCC		 827{
828 struct mb86a20s_state *state = fe->demodulator_priv;
ad0abbf1 829 int rc, val;
149d518a
MCC		 830
831 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
832
4f62a20d 833 if (layer >= NUM_LAYERS)
149d518a
MCC		 834 return -EINVAL;
835
836 /* Check if the BER measures are already available */
837 rc = mb86a20s_readreg(state, 0x54);
838 if (rc < 0)
839 return rc;
840
841 /* Check if data is available for that layer */
842 if (!(rc & (1 << layer))) {
843 dev_dbg(&state->i2c->dev,
ad0abbf1 844 "%s: preBER for layer %c is not available yet.\n",
149d518a
MCC		 845 __func__, 'A' + layer);
846 return -EBUSY;
847 }
848
849 /* Read Bit Error Count */
850 rc = mb86a20s_readreg(state, 0x55 + layer * 3);
851 if (rc < 0)
852 return rc;
853 *error = rc << 16;
854 rc = mb86a20s_readreg(state, 0x56 + layer * 3);
855 if (rc < 0)
856 return rc;
857 *error |= rc << 8;
858 rc = mb86a20s_readreg(state, 0x57 + layer * 3);
859 if (rc < 0)
860 return rc;
861 *error |= rc;
862
863 dev_dbg(&state->i2c->dev,
864 "%s: bit error before Viterbi for layer %c: %d.\n",
865 __func__, 'A' + layer, *error);
866
867 /* Read Bit Count */
868 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
869 if (rc < 0)
870 return rc;
871 rc = mb86a20s_readreg(state, 0x51);
872 if (rc < 0)
873 return rc;
874 *count = rc << 16;
875 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
876 if (rc < 0)
877 return rc;
878 rc = mb86a20s_readreg(state, 0x51);
879 if (rc < 0)
880 return rc;
881 *count |= rc << 8;
882 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
883 if (rc < 0)
884 return rc;
885 rc = mb86a20s_readreg(state, 0x51);
886 if (rc < 0)
887 return rc;
888 *count |= rc;
889
890 dev_dbg(&state->i2c->dev,
891 "%s: bit count before Viterbi for layer %c: %d.\n",
892 __func__, 'A' + layer, *count);
893
894
d01a8ee3
MCC		 895 /*
896 * As we get TMCC data from the frontend, we can better estimate the
897 * BER bit counters, in order to do the BER measure during a longer
898 * time. Use those data, if available, to update the bit count
899 * measure.
900 */
901
902 if (state->estimated_rate[layer]
903 && state->estimated_rate[layer] != *count) {
904 dev_dbg(&state->i2c->dev,
ad0abbf1 905 "%s: updating layer %c preBER counter to %d.\n",
d01a8ee3 906 __func__, 'A' + layer, state->estimated_rate[layer]);
ad0abbf1
MCC		 907
908 /* Turn off BER before Viterbi */
909 rc = mb86a20s_writereg(state, 0x52, 0x00);
910
911 /* Update counter for this layer */
d01a8ee3
MCC		 912 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
913 if (rc < 0)
914 return rc;
915 rc = mb86a20s_writereg(state, 0x51,
916 state->estimated_rate[layer] >> 16);
917 if (rc < 0)
918 return rc;
919 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
920 if (rc < 0)
921 return rc;
922 rc = mb86a20s_writereg(state, 0x51,
923 state->estimated_rate[layer] >> 8);
924 if (rc < 0)
925 return rc;
926 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
927 if (rc < 0)
928 return rc;
929 rc = mb86a20s_writereg(state, 0x51,
930 state->estimated_rate[layer]);
931 if (rc < 0)
932 return rc;
ad0abbf1
MCC		 933
934 /* Turn on BER before Viterbi */
935 rc = mb86a20s_writereg(state, 0x52, 0x01);
936
937 /* Reset all preBER counters */
938 rc = mb86a20s_writereg(state, 0x53, 0x00);
939 if (rc < 0)
940 return rc;
941 rc = mb86a20s_writereg(state, 0x53, 0x07);
942 } else {
943 /* Reset counter to collect new data */
944 rc = mb86a20s_readreg(state, 0x53);
945 if (rc < 0)
946 return rc;
947 val = rc;
948 rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer));
949 if (rc < 0)
950 return rc;
951 rc = mb86a20s_writereg(state, 0x53, val | (1 << layer));
d01a8ee3
MCC		 952 }
953
d9b6f08a
MCC		 954 return rc;
955}
956
957static int mb86a20s_get_post_ber(struct dvb_frontend *fe,
958 unsigned layer,
959 u32 *error, u32 *count)
960{
961 struct mb86a20s_state *state = fe->demodulator_priv;
962 u32 counter, collect_rate;
963 int rc, val;
964
965 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
966
4f62a20d 967 if (layer >= NUM_LAYERS)
d9b6f08a
MCC		 968 return -EINVAL;
969
970 /* Check if the BER measures are already available */
971 rc = mb86a20s_readreg(state, 0x60);
972 if (rc < 0)
973 return rc;
974
975 /* Check if data is available for that layer */
976 if (!(rc & (1 << layer))) {
977 dev_dbg(&state->i2c->dev,
978 "%s: post BER for layer %c is not available yet.\n",
979 __func__, 'A' + layer);
980 return -EBUSY;
981 }
d01a8ee3 982
d9b6f08a
MCC		 983 /* Read Bit Error Count */
984 rc = mb86a20s_readreg(state, 0x64 + layer * 3);
985 if (rc < 0)
986 return rc;
987 *error = rc << 16;
988 rc = mb86a20s_readreg(state, 0x65 + layer * 3);
989 if (rc < 0)
990 return rc;
991 *error |= rc << 8;
992 rc = mb86a20s_readreg(state, 0x66 + layer * 3);
993 if (rc < 0)
994 return rc;
995 *error |= rc;
996
997 dev_dbg(&state->i2c->dev,
998 "%s: post bit error for layer %c: %d.\n",
999 __func__, 'A' + layer, *error);
1000
1001 /* Read Bit Count */
1002 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
1003 if (rc < 0)
1004 return rc;
1005 rc = mb86a20s_readreg(state, 0x51);
1006 if (rc < 0)
1007 return rc;
1008 counter = rc << 8;
1009 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
1010 if (rc < 0)
1011 return rc;
1012 rc = mb86a20s_readreg(state, 0x51);
1013 if (rc < 0)
1014 return rc;
1015 counter |= rc;
1016 *count = counter * 204 * 8;
1017
1018 dev_dbg(&state->i2c->dev,
1019 "%s: post bit count for layer %c: %d.\n",
1020 __func__, 'A' + layer, *count);
1021
1022 /*
1023 * As we get TMCC data from the frontend, we can better estimate the
1024 * BER bit counters, in order to do the BER measure during a longer
1025 * time. Use those data, if available, to update the bit count
1026 * measure.
1027 */
1028
1029 if (!state->estimated_rate[layer])
1030 goto reset_measurement;
1031
1032 collect_rate = state->estimated_rate[layer] / 204 / 8;
1033 if (collect_rate < 32)
1034 collect_rate = 32;
1035 if (collect_rate > 65535)
1036 collect_rate = 65535;
1037 if (collect_rate != counter) {
1038 dev_dbg(&state->i2c->dev,
1039 "%s: updating postBER counter on layer %c to %d.\n",
1040 __func__, 'A' + layer, collect_rate);
1041
1042 /* Turn off BER after Viterbi */
1043 rc = mb86a20s_writereg(state, 0x5e, 0x00);
1044
1045 /* Update counter for this layer */
1046 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
1047 if (rc < 0)
1048 return rc;
1049 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1050 if (rc < 0)
1051 return rc;
1052 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
1053 if (rc < 0)
1054 return rc;
1055 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1056 if (rc < 0)
1057 return rc;
1058
1059 /* Turn on BER after Viterbi */
1060 rc = mb86a20s_writereg(state, 0x5e, 0x07);
1061
1062 /* Reset all preBER counters */
1063 rc = mb86a20s_writereg(state, 0x5f, 0x00);
1064 if (rc < 0)
1065 return rc;
1066 rc = mb86a20s_writereg(state, 0x5f, 0x07);
1067
1068 return rc;
1069 }
1070
1071reset_measurement:
149d518a 1072 /* Reset counter to collect new data */
ad0abbf1
MCC		 1073 rc = mb86a20s_readreg(state, 0x5f);
1074 if (rc < 0)
1075 return rc;
1076 val = rc;
1077 rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer));
149d518a
MCC		 1078 if (rc < 0)
1079 return rc;
d9b6f08a 1080 rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer));
149d518a 1081
ad0abbf1 1082 return rc;
149d518a
MCC		 1083}
1084
593ae89a
MCC		 1085static int mb86a20s_get_blk_error(struct dvb_frontend *fe,
1086 unsigned layer,
1087 u32 *error, u32 *count)
1088{
1089 struct mb86a20s_state *state = fe->demodulator_priv;
313cf4ef 1090 int rc, val;
593ae89a
MCC		 1091 u32 collect_rate;
1092 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1093
4f62a20d 1094 if (layer >= NUM_LAYERS)
593ae89a
MCC		 1095 return -EINVAL;
1096
1097 /* Check if the PER measures are already available */
1098 rc = mb86a20s_writereg(state, 0x50, 0xb8);
1099 if (rc < 0)
1100 return rc;
1101 rc = mb86a20s_readreg(state, 0x51);
1102 if (rc < 0)
1103 return rc;
1104
1105 /* Check if data is available for that layer */
1106
1107 if (!(rc & (1 << layer))) {
1108 dev_dbg(&state->i2c->dev,
1109 "%s: block counts for layer %c aren't available yet.\n",
1110 __func__, 'A' + layer);
1111 return -EBUSY;
1112 }
1113
1114 /* Read Packet error Count */
1115 rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2);
1116 if (rc < 0)
1117 return rc;
1118 rc = mb86a20s_readreg(state, 0x51);
1119 if (rc < 0)
1120 return rc;
1121 *error = rc << 8;
1122 rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2);
1123 if (rc < 0)
1124 return rc;
1125 rc = mb86a20s_readreg(state, 0x51);
1126 if (rc < 0)
1127 return rc;
1128 *error |= rc;
d56e326f 1129 dev_dbg(&state->i2c->dev, "%s: block error for layer %c: %d.\n",
593ae89a
MCC		 1130 __func__, 'A' + layer, *error);
1131
1132 /* Read Bit Count */
1133 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1134 if (rc < 0)
1135 return rc;
1136 rc = mb86a20s_readreg(state, 0x51);
1137 if (rc < 0)
1138 return rc;
1139 *count = rc << 8;
1140 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1141 if (rc < 0)
1142 return rc;
1143 rc = mb86a20s_readreg(state, 0x51);
1144 if (rc < 0)
1145 return rc;
1146 *count |= rc;
1147
1148 dev_dbg(&state->i2c->dev,
1149 "%s: block count for layer %c: %d.\n",
1150 __func__, 'A' + layer, *count);
1151
1152 /*
1153 * As we get TMCC data from the frontend, we can better estimate the
1154 * BER bit counters, in order to do the BER measure during a longer
1155 * time. Use those data, if available, to update the bit count
1156 * measure.
1157 */
1158
1159 if (!state->estimated_rate[layer])
1160 goto reset_measurement;
1161
1162 collect_rate = state->estimated_rate[layer] / 204 / 8;
593ae89a
MCC		 1163 if (collect_rate < 32)
1164 collect_rate = 32;
1165 if (collect_rate > 65535)
1166 collect_rate = 65535;
1167
1168 if (collect_rate != *count) {
1169 dev_dbg(&state->i2c->dev,
1170 "%s: updating PER counter on layer %c to %d.\n",
1171 __func__, 'A' + layer, collect_rate);
313cf4ef
MCC		 1172
1173 /* Stop PER measurement */
1174 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1175 if (rc < 0)
1176 return rc;
1177 rc = mb86a20s_writereg(state, 0x51, 0x00);
1178 if (rc < 0)
1179 return rc;
1180
1181 /* Update this layer's counter */
593ae89a
MCC		 1182 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1183 if (rc < 0)
1184 return rc;
1185 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1186 if (rc < 0)
1187 return rc;
1188 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1189 if (rc < 0)
1190 return rc;
1191 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1192 if (rc < 0)
1193 return rc;
313cf4ef
MCC		 1194
1195 /* start PER measurement */
1196 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1197 if (rc < 0)
1198 return rc;
1199 rc = mb86a20s_writereg(state, 0x51, 0x07);
1200 if (rc < 0)
1201 return rc;
1202
1203 /* Reset all counters to collect new data */
1204 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1205 if (rc < 0)
1206 return rc;
1207 rc = mb86a20s_writereg(state, 0x51, 0x07);
1208 if (rc < 0)
1209 return rc;
1210 rc = mb86a20s_writereg(state, 0x51, 0x00);
1211
1212 return rc;
593ae89a
MCC		 1213 }
1214
1215reset_measurement:
1216 /* Reset counter to collect new data */
1217 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1218 if (rc < 0)
1219 return rc;
313cf4ef 1220 rc = mb86a20s_readreg(state, 0x51);
593ae89a
MCC		 1221 if (rc < 0)
1222 return rc;
313cf4ef
MCC		 1223 val = rc;
1224 rc = mb86a20s_writereg(state, 0x51, val | (1 << layer));
593ae89a
MCC		 1225 if (rc < 0)
1226 return rc;
313cf4ef 1227 rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer));
593ae89a 1228
313cf4ef 1229 return rc;
593ae89a
MCC		 1230}
1231
25188bd0
MCC		 1232struct linear_segments {
1233 unsigned x, y;
1234};
1235
1236/*
1237 * All tables below return a dB/1000 measurement
1238 */
1239
1240static struct linear_segments cnr_to_db_table[] = {
1241 { 19648, 0},
1242 { 18187, 1000},
1243 { 16534, 2000},
1244 { 14823, 3000},
1245 { 13161, 4000},
1246 { 11622, 5000},
1247 { 10279, 6000},
1248 { 9089, 7000},
1249 { 8042, 8000},
1250 { 7137, 9000},
1251 { 6342, 10000},
1252 { 5641, 11000},
1253 { 5030, 12000},
1254 { 4474, 13000},
1255 { 3988, 14000},
1256 { 3556, 15000},
1257 { 3180, 16000},
1258 { 2841, 17000},
1259 { 2541, 18000},
1260 { 2276, 19000},
1261 { 2038, 20000},
1262 { 1800, 21000},
1263 { 1625, 22000},
1264 { 1462, 23000},
1265 { 1324, 24000},
1266 { 1175, 25000},
1267 { 1063, 26000},
1268 { 980, 27000},
1269 { 907, 28000},
1270 { 840, 29000},
1271 { 788, 30000},
1272};
1273
1274static struct linear_segments cnr_64qam_table[] = {
1275 { 3922688, 0},
1276 { 3920384, 1000},
1277 { 3902720, 2000},
1278 { 3894784, 3000},
1279 { 3882496, 4000},
1280 { 3872768, 5000},
1281 { 3858944, 6000},
1282 { 3851520, 7000},
1283 { 3838976, 8000},
1284 { 3829248, 9000},
1285 { 3818240, 10000},
1286 { 3806976, 11000},
1287 { 3791872, 12000},
1288 { 3767040, 13000},
1289 { 3720960, 14000},
1290 { 3637504, 15000},
1291 { 3498496, 16000},
1292 { 3296000, 17000},
1293 { 3031040, 18000},
1294 { 2715392, 19000},
1295 { 2362624, 20000},
1296 { 1963264, 21000},
1297 { 1649664, 22000},
1298 { 1366784, 23000},
1299 { 1120768, 24000},
1300 { 890880, 25000},
1301 { 723456, 26000},
1302 { 612096, 27000},
1303 { 518912, 28000},
1304 { 448256, 29000},
1305 { 388864, 30000},
1306};
1307
1308static struct linear_segments cnr_16qam_table[] = {
1309 { 5314816, 0},
1310 { 5219072, 1000},
1311 { 5118720, 2000},
1312 { 4998912, 3000},
1313 { 4875520, 4000},
1314 { 4736000, 5000},
1315 { 4604160, 6000},
1316 { 4458752, 7000},
1317 { 4300288, 8000},
1318 { 4092928, 9000},
1319 { 3836160, 10000},
1320 { 3521024, 11000},
1321 { 3155968, 12000},
1322 { 2756864, 13000},
1323 { 2347008, 14000},
1324 { 1955072, 15000},
1325 { 1593600, 16000},
1326 { 1297920, 17000},
1327 { 1043968, 18000},
1328 { 839680, 19000},
1329 { 672256, 20000},
1330 { 523008, 21000},
1331 { 424704, 22000},
1332 { 345088, 23000},
1333 { 280064, 24000},
1334 { 221440, 25000},
1335 { 179712, 26000},
1336 { 151040, 27000},
1337 { 128512, 28000},
1338 { 110080, 29000},
1339 { 95744, 30000},
1340};
1341
1342struct linear_segments cnr_qpsk_table[] = {
1343 { 2834176, 0},
1344 { 2683648, 1000},
1345 { 2536960, 2000},
1346 { 2391808, 3000},
1347 { 2133248, 4000},
1348 { 1906176, 5000},
1349 { 1666560, 6000},
1350 { 1422080, 7000},
1351 { 1189632, 8000},
1352 { 976384, 9000},
1353 { 790272, 10000},
1354 { 633344, 11000},
1355 { 505600, 12000},
1356 { 402944, 13000},
1357 { 320768, 14000},
1358 { 255488, 15000},
1359 { 204032, 16000},
1360 { 163072, 17000},
1361 { 130304, 18000},
1362 { 105216, 19000},
1363 { 83456, 20000},
1364 { 65024, 21000},
1365 { 52480, 22000},
1366 { 42752, 23000},
1367 { 34560, 24000},
1368 { 27136, 25000},
1369 { 22016, 26000},
1370 { 18432, 27000},
1371 { 15616, 28000},
1372 { 13312, 29000},
1373 { 11520, 30000},
1374};
1375
1376static u32 interpolate_value(u32 value, struct linear_segments *segments,
1377 unsigned len)
1378{
1379 u64 tmp64;
1380 u32 dx, dy;
1381 int i, ret;
1382
1383 if (value >= segments[0].x)
1384 return segments[0].y;
1385 if (value < segments[len-1].x)
1386 return segments[len-1].y;
1387
1388 for (i = 1; i < len - 1; i++) {
1389 /* If value is identical, no need to interpolate */
1390 if (value == segments[i].x)
1391 return segments[i].y;
1392 if (value > segments[i].x)
1393 break;
1394 }
1395
1396 /* Linear interpolation between the two (x,y) points */
1397 dy = segments[i].y - segments[i - 1].y;
1398 dx = segments[i - 1].x - segments[i].x;
1399 tmp64 = value - segments[i].x;
1400 tmp64 *= dy;
1401 do_div(tmp64, dx);
1402 ret = segments[i].y - tmp64;
1403
1404 return ret;
1405}
1406
1407static int mb86a20s_get_main_CNR(struct dvb_frontend *fe)
1408{
1409 struct mb86a20s_state *state = fe->demodulator_priv;
1410 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1411 u32 cnr_linear, cnr;
1412 int rc, val;
1413
1414 /* Check if CNR is available */
1415 rc = mb86a20s_readreg(state, 0x45);
1416 if (rc < 0)
1417 return rc;
1418
1419 if (!(rc & 0x40)) {
d56e326f 1420 dev_dbg(&state->i2c->dev, "%s: CNR is not available yet.\n",
25188bd0
MCC		 1421 __func__);
1422 return -EBUSY;
1423 }
1424 val = rc;
1425
1426 rc = mb86a20s_readreg(state, 0x46);
1427 if (rc < 0)
1428 return rc;
1429 cnr_linear = rc << 8;
1430
1431 rc = mb86a20s_readreg(state, 0x46);
1432 if (rc < 0)
1433 return rc;
1434 cnr_linear |= rc;
1435
1436 cnr = interpolate_value(cnr_linear,
1437 cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table));
1438
1439 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1440 c->cnr.stat[0].svalue = cnr;
1441
1442 dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n",
1443 __func__, cnr / 1000, cnr % 1000, cnr_linear);
1444
1445 /* CNR counter reset */
1446 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
1447 if (rc < 0)
1448 return rc;
1449 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
1450
1451 return rc;
1452}
1453
593ae89a 1454static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe)
25188bd0
MCC		 1455{
1456 struct mb86a20s_state *state = fe->demodulator_priv;
1457 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1458 u32 mer, cnr;
5cb88ca8 1459 int rc, val, layer;
25188bd0
MCC		 1460 struct linear_segments *segs;
1461 unsigned segs_len;
1462
1463 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1464
1465 /* Check if the measures are already available */
1466 rc = mb86a20s_writereg(state, 0x50, 0x5b);
1467 if (rc < 0)
1468 return rc;
1469 rc = mb86a20s_readreg(state, 0x51);
1470 if (rc < 0)
1471 return rc;
1472
1473 /* Check if data is available */
1474 if (!(rc & 0x01)) {
d56e326f 1475 dev_dbg(&state->i2c->dev,
25188bd0
MCC		 1476 "%s: MER measures aren't available yet.\n", __func__);
1477 return -EBUSY;
1478 }
1479
1480 /* Read all layers */
5cb88ca8
MCC		 1481 for (layer = 0; layer < NUM_LAYERS; layer++) {
1482 if (!(c->isdbt_layer_enabled & (1 << layer))) {
1483 c->cnr.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
25188bd0
MCC		 1484 continue;
1485 }
1486
5cb88ca8 1487 rc = mb86a20s_writereg(state, 0x50, 0x52 + layer * 3);
25188bd0
MCC		 1488 if (rc < 0)
1489 return rc;
1490 rc = mb86a20s_readreg(state, 0x51);
1491 if (rc < 0)
1492 return rc;
1493 mer = rc << 16;
5cb88ca8 1494 rc = mb86a20s_writereg(state, 0x50, 0x53 + layer * 3);
25188bd0
MCC		 1495 if (rc < 0)
1496 return rc;
1497 rc = mb86a20s_readreg(state, 0x51);
1498 if (rc < 0)
1499 return rc;
1500 mer |= rc << 8;
5cb88ca8 1501 rc = mb86a20s_writereg(state, 0x50, 0x54 + layer * 3);
25188bd0
MCC		 1502 if (rc < 0)
1503 return rc;
1504 rc = mb86a20s_readreg(state, 0x51);
1505 if (rc < 0)
1506 return rc;
1507 mer |= rc;
1508
5cb88ca8 1509 switch (c->layer[layer].modulation) {
25188bd0
MCC		 1510 case DQPSK:
1511 case QPSK:
1512 segs = cnr_qpsk_table;
1513 segs_len = ARRAY_SIZE(cnr_qpsk_table);
1514 break;
1515 case QAM_16:
1516 segs = cnr_16qam_table;
1517 segs_len = ARRAY_SIZE(cnr_16qam_table);
1518 break;
1519 default:
1520 case QAM_64:
1521 segs = cnr_64qam_table;
1522 segs_len = ARRAY_SIZE(cnr_64qam_table);
1523 break;
1524 }
1525 cnr = interpolate_value(mer, segs, segs_len);
1526
5cb88ca8
MCC		 1527 c->cnr.stat[1 + layer].scale = FE_SCALE_DECIBEL;
1528 c->cnr.stat[1 + layer].svalue = cnr;
25188bd0
MCC		 1529
1530 dev_dbg(&state->i2c->dev,
1531 "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n",
5cb88ca8 1532 __func__, 'A' + layer, cnr / 1000, cnr % 1000, mer);
25188bd0
MCC		 1533
1534 }
1535
1536 /* Start a new MER measurement */
1537 /* MER counter reset */
1538 rc = mb86a20s_writereg(state, 0x50, 0x50);
1539 if (rc < 0)
1540 return rc;
1541 rc = mb86a20s_readreg(state, 0x51);
1542 if (rc < 0)
1543 return rc;
1544 val = rc;
1545
1546 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
1547 if (rc < 0)
1548 return rc;
1549 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
1550 if (rc < 0)
1551 return rc;
1552
1553 return 0;
1554}
1555
09b6d21e
MCC		 1556static void mb86a20s_stats_not_ready(struct dvb_frontend *fe)
1557{
1558 struct mb86a20s_state *state = fe->demodulator_priv;
1559 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
5cb88ca8 1560 int layer;
09b6d21e
MCC		 1561
1562 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
a77cfcac 1563
09b6d21e
MCC		 1564 /* Fill the length of each status counter */
1565
1566 /* Only global stats */
1567 c->strength.len = 1;
1568
1569 /* Per-layer stats - 3 layers + global */
4f62a20d
MCC		 1570 c->cnr.len = NUM_LAYERS + 1;
1571 c->pre_bit_error.len = NUM_LAYERS + 1;
1572 c->pre_bit_count.len = NUM_LAYERS + 1;
1573 c->post_bit_error.len = NUM_LAYERS + 1;
1574 c->post_bit_count.len = NUM_LAYERS + 1;
1575 c->block_error.len = NUM_LAYERS + 1;
1576 c->block_count.len = NUM_LAYERS + 1;
09b6d21e
MCC		 1577
1578 /* Signal is always available */
1579 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
1580 c->strength.stat[0].uvalue = 0;
1581
1582 /* Put all of them at FE_SCALE_NOT_AVAILABLE */
5cb88ca8
MCC		 1583 for (layer = 0; layer < NUM_LAYERS + 1; layer++) {
1584 c->cnr.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1585 c->pre_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1586 c->pre_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1587 c->post_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1588 c->post_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1589 c->block_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1590 c->block_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
09b6d21e 1591 }
b9ede79a
MCC		 1592}
1593
15b1c5a0 1594static int mb86a20s_get_stats(struct dvb_frontend *fe, int status_nr)
149d518a
MCC		 1595{
1596 struct mb86a20s_state *state = fe->demodulator_priv;
1597 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
5cb88ca8 1598 int rc = 0, layer;
149d518a
MCC		 1599 u32 bit_error = 0, bit_count = 0;
1600 u32 t_pre_bit_error = 0, t_pre_bit_count = 0;
d9b6f08a 1601 u32 t_post_bit_error = 0, t_post_bit_count = 0;
593ae89a
MCC		 1602 u32 block_error = 0, block_count = 0;
1603 u32 t_block_error = 0, t_block_count = 0;
d9b6f08a
MCC		 1604 int active_layers = 0, pre_ber_layers = 0, post_ber_layers = 0;
1605 int per_layers = 0;
149d518a 1606
25188bd0
MCC		 1607 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1608
1609 mb86a20s_get_main_CNR(fe);
1610
149d518a 1611 /* Get per-layer stats */
593ae89a 1612 mb86a20s_get_blk_error_layer_CNR(fe);
25188bd0 1613
15b1c5a0
MCC		 1614 /*
1615 * At state 7, only CNR is available
1616 * For BER measures, state=9 is required
1617 * FIXME: we may get MER measures with state=8
1618 */
1619 if (status_nr < 9)
1620 return 0;
1621
5cb88ca8
MCC		 1622 for (layer = 0; layer < NUM_LAYERS; layer++) {
1623 if (c->isdbt_layer_enabled & (1 << layer)) {
149d518a
MCC		 1624 /* Layer is active and has rc segments */
1625 active_layers++;
1626
149d518a 1627 /* Handle BER before vterbi */
5cb88ca8 1628 rc = mb86a20s_get_pre_ber(fe, layer,
ad0abbf1 1629 &bit_error, &bit_count);
149d518a 1630 if (rc >= 0) {
5cb88ca8
MCC		 1631 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1632 c->pre_bit_error.stat[1 + layer].uvalue += bit_error;
1633 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1634 c->pre_bit_count.stat[1 + layer].uvalue += bit_count;
149d518a
MCC		 1635 } else if (rc != -EBUSY) {
1636 /*
1637 * If an I/O error happened,
1638 * measures are now unavailable
1639 */
5cb88ca8
MCC		 1640 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1641 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
149d518a
MCC		 1642 dev_err(&state->i2c->dev,
1643 "%s: Can't get BER for layer %c (error %d).\n",
5cb88ca8 1644 __func__, 'A' + layer, rc);
149d518a 1645 }
5cb88ca8 1646 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
d9b6f08a
MCC		 1647 pre_ber_layers++;
1648
1649 /* Handle BER post vterbi */
5cb88ca8 1650 rc = mb86a20s_get_post_ber(fe, layer,
d9b6f08a
MCC		 1651 &bit_error, &bit_count);
1652 if (rc >= 0) {
5cb88ca8
MCC		 1653 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1654 c->post_bit_error.stat[1 + layer].uvalue += bit_error;
1655 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1656 c->post_bit_count.stat[1 + layer].uvalue += bit_count;
d9b6f08a
MCC		 1657 } else if (rc != -EBUSY) {
1658 /*
1659 * If an I/O error happened,
1660 * measures are now unavailable
1661 */
5cb88ca8
MCC		 1662 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1663 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
d9b6f08a
MCC		 1664 dev_err(&state->i2c->dev,
1665 "%s: Can't get BER for layer %c (error %d).\n",
5cb88ca8 1666 __func__, 'A' + layer, rc);
d9b6f08a 1667 }
5cb88ca8 1668 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
d9b6f08a 1669 post_ber_layers++;
149d518a 1670
593ae89a 1671 /* Handle Block errors for PER/UCB reports */
5cb88ca8 1672 rc = mb86a20s_get_blk_error(fe, layer,
593ae89a
MCC		 1673 &block_error,
1674 &block_count);
1675 if (rc >= 0) {
5cb88ca8
MCC		 1676 c->block_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1677 c->block_error.stat[1 + layer].uvalue += block_error;
1678 c->block_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1679 c->block_count.stat[1 + layer].uvalue += block_count;
593ae89a
MCC		 1680 } else if (rc != -EBUSY) {
1681 /*
1682 * If an I/O error happened,
1683 * measures are now unavailable
1684 */
5cb88ca8
MCC		 1685 c->block_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1686 c->block_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
593ae89a
MCC		 1687 dev_err(&state->i2c->dev,
1688 "%s: Can't get PER for layer %c (error %d).\n",
5cb88ca8 1689 __func__, 'A' + layer, rc);
593ae89a
MCC		 1690
1691 }
5cb88ca8 1692 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
593ae89a
MCC		 1693 per_layers++;
1694
d9b6f08a 1695 /* Update total preBER */
5cb88ca8
MCC		 1696 t_pre_bit_error += c->pre_bit_error.stat[1 + layer].uvalue;
1697 t_pre_bit_count += c->pre_bit_count.stat[1 + layer].uvalue;
593ae89a 1698
d9b6f08a 1699 /* Update total postBER */
5cb88ca8
MCC		 1700 t_post_bit_error += c->post_bit_error.stat[1 + layer].uvalue;
1701 t_post_bit_count += c->post_bit_count.stat[1 + layer].uvalue;
d9b6f08a 1702
593ae89a 1703 /* Update total PER */
5cb88ca8
MCC		 1704 t_block_error += c->block_error.stat[1 + layer].uvalue;
1705 t_block_count += c->block_count.stat[1 + layer].uvalue;
149d518a
MCC		 1706 }
1707 }
1708
1709 /*
1710 * Start showing global count if at least one error count is
1711 * available.
1712 */
d9b6f08a 1713 if (pre_ber_layers) {
149d518a
MCC		 1714 /*
1715 * At least one per-layer BER measure was read. We can now
1716 * calculate the total BER
1717 *
1718 * Total Bit Error/Count is calculated as the sum of the
1719 * bit errors on all active layers.
1720 */
1721 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1722 c->pre_bit_error.stat[0].uvalue = t_pre_bit_error;
1723 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1724 c->pre_bit_count.stat[0].uvalue = t_pre_bit_count;
f67102c4
MCC		 1725 } else {
1726 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1727 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
149d518a
MCC		 1728 }
1729
d9b6f08a
MCC		 1730 /*
1731 * Start showing global count if at least one error count is
1732 * available.
1733 */
1734 if (post_ber_layers) {
1735 /*
1736 * At least one per-layer BER measure was read. We can now
1737 * calculate the total BER
1738 *
1739 * Total Bit Error/Count is calculated as the sum of the
1740 * bit errors on all active layers.
1741 */
1742 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1743 c->post_bit_error.stat[0].uvalue = t_post_bit_error;
1744 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1745 c->post_bit_count.stat[0].uvalue = t_post_bit_count;
f67102c4
MCC		 1746 } else {
1747 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1748 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
d9b6f08a
MCC		 1749 }
1750
593ae89a
MCC		 1751 if (per_layers) {
1752 /*
1753 * At least one per-layer UCB measure was read. We can now
1754 * calculate the total UCB
1755 *
1756 * Total block Error/Count is calculated as the sum of the
1757 * block errors on all active layers.
1758 */
1759 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
1760 c->block_error.stat[0].uvalue = t_block_error;
1761 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1762 c->block_count.stat[0].uvalue = t_block_count;
f67102c4
MCC		 1763 } else {
1764 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1765 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
593ae89a
MCC		 1766 }
1767
149d518a
MCC		 1768 return rc;
1769}
09b6d21e
MCC		 1770
1771/*
1772 * The functions below are called via DVB callbacks, so they need to
1773 * properly use the I2C gate control
1774 */
1775
dd4493ef
MCC		 1776static int mb86a20s_initfe(struct dvb_frontend *fe)
1777{
1778 struct mb86a20s_state *state = fe->demodulator_priv;
768e6dad 1779 u64 pll;
0e4bbedd 1780 u32 fclk;
dd4493ef 1781 int rc;
04fa725e 1782 u8 regD5 = 1, reg71, reg09 = 0x3a;
dd4493ef 1783
f66d81b5 1784 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
dd4493ef
MCC		 1785
1786 if (fe->ops.i2c_gate_ctrl)
1787 fe->ops.i2c_gate_ctrl(fe, 0);
1788
1789 /* Initialize the frontend */
768e6dad 1790 rc = mb86a20s_writeregdata(state, mb86a20s_init1);
dd4493ef
MCC		 1791 if (rc < 0)
1792 goto err;
1793
04fa725e
MCC		 1794 if (!state->inversion)
1795 reg09 |= 0x04;
1796 rc = mb86a20s_writereg(state, 0x09, reg09);
1797 if (rc < 0)
1798 goto err;
1799 if (!state->bw)
1800 reg71 = 1;
1801 else
1802 reg71 = 0;
1803 rc = mb86a20s_writereg(state, 0x39, reg71);
1804 if (rc < 0)
1805 goto err;
1806 rc = mb86a20s_writereg(state, 0x71, state->bw);
1807 if (rc < 0)
1808 goto err;
1809 if (state->subchannel) {
1810 rc = mb86a20s_writereg(state, 0x44, state->subchannel);
1811 if (rc < 0)
1812 goto err;
1813 }
1814
0e4bbedd
MCC		 1815 fclk = state->config->fclk;
1816 if (!fclk)
1817 fclk = 32571428;
1818
768e6dad
MCC		 1819 /* Adjust IF frequency to match tuner */
1820 if (fe->ops.tuner_ops.get_if_frequency)
1821 fe->ops.tuner_ops.get_if_frequency(fe, &state->if_freq);
1822
1823 if (!state->if_freq)
1824 state->if_freq = 3300000;
1825
0e4bbedd
MCC		 1826 pll = (((u64)1) << 34) * state->if_freq;
1827 do_div(pll, 63 * fclk);
1828 pll = (1 << 25) - pll;
1829 rc = mb86a20s_writereg(state, 0x28, 0x2a);
1830 if (rc < 0)
1831 goto err;
1832 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1833 if (rc < 0)
1834 goto err;
1835 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1836 if (rc < 0)
1837 goto err;
1838 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1839 if (rc < 0)
1840 goto err;
1841 dev_dbg(&state->i2c->dev, "%s: fclk=%d, IF=%d, clock reg=0x%06llx\n",
1842 __func__, fclk, state->if_freq, (long long)pll);
1843
768e6dad
MCC		 1844 /* pll = freq[Hz] * 2^24/10^6 / 16.285714286 */
1845 pll = state->if_freq * 1677721600L;
1846 do_div(pll, 1628571429L);
1847 rc = mb86a20s_writereg(state, 0x28, 0x20);
1848 if (rc < 0)
1849 goto err;
1850 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1851 if (rc < 0)
1852 goto err;
1853 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1854 if (rc < 0)
1855 goto err;
1856 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1857 if (rc < 0)
1858 goto err;
0e4bbedd 1859 dev_dbg(&state->i2c->dev, "%s: IF=%d, IF reg=0x%06llx\n",
768e6dad
MCC		 1860 __func__, state->if_freq, (long long)pll);
1861
dd4493ef
MCC		 1862 if (!state->config->is_serial) {
1863 regD5 &= ~1;
1864
1865 rc = mb86a20s_writereg(state, 0x50, 0xd5);
1866 if (rc < 0)
1867 goto err;
1868 rc = mb86a20s_writereg(state, 0x51, regD5);
1869 if (rc < 0)
1870 goto err;
1871 }
1872
768e6dad
MCC		 1873 rc = mb86a20s_writeregdata(state, mb86a20s_init2);
1874 if (rc < 0)
1875 goto err;
1876
1877
dd4493ef
MCC		 1878err:
1879 if (fe->ops.i2c_gate_ctrl)
1880 fe->ops.i2c_gate_ctrl(fe, 1);
1881
1882 if (rc < 0) {
1883 state->need_init = true;
f66d81b5
MCC		 1884 dev_info(&state->i2c->dev,
1885 "mb86a20s: Init failed. Will try again later\n");
dd4493ef
MCC		 1886 } else {
1887 state->need_init = false;
f66d81b5 1888 dev_dbg(&state->i2c->dev, "Initialization succeeded.\n");
dd4493ef
MCC		 1889 }
1890 return rc;
1891}
1892
1893static int mb86a20s_set_frontend(struct dvb_frontend *fe)
1894{
1895 struct mb86a20s_state *state = fe->demodulator_priv;
dd4493ef 1896 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
04fa725e 1897 int rc, if_freq;
f66d81b5 1898 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
dd4493ef 1899
04fa725e
MCC		 1900 if (!c->isdbt_layer_enabled)
1901 c->isdbt_layer_enabled = 7;
1902
1903 if (c->isdbt_layer_enabled == 1)
1904 state->bw = MB86A20S_1SEG;
1905 else if (c->isdbt_partial_reception)
1906 state->bw = MB86A20S_13SEG_PARTIAL;
1907 else
1908 state->bw = MB86A20S_13SEG;
1909
1910 if (c->inversion == INVERSION_ON)
1911 state->inversion = true;
1912 else
1913 state->inversion = false;
1914
1915 if (!c->isdbt_sb_mode) {
1916 state->subchannel = 0;
1917 } else {
41c6e9dd 1918 if (c->isdbt_sb_subchannel >= ARRAY_SIZE(mb86a20s_subchannel))
04fa725e
MCC		 1919 c->isdbt_sb_subchannel = 0;
1920
1921 state->subchannel = mb86a20s_subchannel[c->isdbt_sb_subchannel];
1922 }
1923
dd4493ef
MCC		 1924 /*
1925 * Gate should already be opened, but it doesn't hurt to
1926 * double-check
1927 */
1928 if (fe->ops.i2c_gate_ctrl)
1929 fe->ops.i2c_gate_ctrl(fe, 1);
dd4493ef
MCC		 1930 fe->ops.tuner_ops.set_params(fe);
1931
a78b41d5 1932 if (fe->ops.tuner_ops.get_if_frequency)
768e6dad
MCC		 1933 fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
1934
dd4493ef
MCC		 1935 /*
1936 * Make it more reliable: if, for some reason, the initial
1937 * device initialization doesn't happen, initialize it when
1938 * a SBTVD parameters are adjusted.
1939 *
1940 * Unfortunately, due to a hard to track bug at tda829x/tda18271,
1941 * the agc callback logic is not called during DVB attach time,
1942 * causing mb86a20s to not be initialized with Kworld SBTVD.
1943 * So, this hack is needed, in order to make Kworld SBTVD to work.
768e6dad
MCC		 1944 *
1945 * It is also needed to change the IF after the initial init.
a78b41d5
MCC		 1946 *
1947 * HACK: Always init the frontend when set_frontend is called:
1948 * it was noticed that, on some devices, it fails to lock on a
1949 * different channel. So, it is better to reset everything, even
1950 * wasting some time, than to loose channel lock.
dd4493ef 1951 */
a78b41d5 1952 mb86a20s_initfe(fe);
dd4493ef
MCC		 1953
1954 if (fe->ops.i2c_gate_ctrl)
1955 fe->ops.i2c_gate_ctrl(fe, 0);
d01a8ee3 1956
dd4493ef 1957 rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception);
09b6d21e 1958 mb86a20s_reset_counters(fe);
3a2e4751 1959 mb86a20s_stats_not_ready(fe);
d01a8ee3 1960
dd4493ef
MCC		 1961 if (fe->ops.i2c_gate_ctrl)
1962 fe->ops.i2c_gate_ctrl(fe, 1);
1963
1964 return rc;
1965}
1966
09b6d21e
MCC		 1967static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe,
1968 fe_status_t *status)
d36e418a 1969{
09b6d21e 1970 struct mb86a20s_state *state = fe->demodulator_priv;
15b1c5a0 1971 int rc, status_nr;
d36e418a 1972
09b6d21e 1973 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
d36e418a
MCC		 1974
1975 if (fe->ops.i2c_gate_ctrl)
1976 fe->ops.i2c_gate_ctrl(fe, 0);
1977
09b6d21e 1978 /* Get lock */
15b1c5a0
MCC		 1979 status_nr = mb86a20s_read_status(fe, status);
1980 if (status_nr < 7) {
09b6d21e
MCC		 1981 mb86a20s_stats_not_ready(fe);
1982 mb86a20s_reset_frontend_cache(fe);
1983 }
15b1c5a0 1984 if (status_nr < 0) {
149d518a
MCC		 1985 dev_err(&state->i2c->dev,
1986 "%s: Can't read frontend lock status\n", __func__);
09b6d21e 1987 goto error;
149d518a 1988 }
09b6d21e
MCC		 1989
1990 /* Get signal strength */
1991 rc = mb86a20s_read_signal_strength(fe);
1992 if (rc < 0) {
149d518a
MCC		 1993 dev_err(&state->i2c->dev,
1994 "%s: Can't reset VBER registers.\n", __func__);
09b6d21e
MCC		 1995 mb86a20s_stats_not_ready(fe);
1996 mb86a20s_reset_frontend_cache(fe);
149d518a
MCC		 1997
1998 rc = 0; /* Status is OK */
09b6d21e
MCC		 1999 goto error;
2000 }
09b6d21e 2001
15b1c5a0 2002 if (status_nr >= 7) {
09b6d21e
MCC		 2003 /* Get TMCC info*/
2004 rc = mb86a20s_get_frontend(fe);
149d518a
MCC		 2005 if (rc < 0) {
2006 dev_err(&state->i2c->dev,
2007 "%s: Can't get FE TMCC data.\n", __func__);
2008 rc = 0; /* Status is OK */
2009 goto error;
2010 }
2011
2012 /* Get statistics */
15b1c5a0 2013 rc = mb86a20s_get_stats(fe, status_nr);
149d518a
MCC		 2014 if (rc < 0 && rc != -EBUSY) {
2015 dev_err(&state->i2c->dev,
2016 "%s: Can't get FE statistics.\n", __func__);
2017 rc = 0;
09b6d21e 2018 goto error;
149d518a
MCC		 2019 }
2020 rc = 0; /* Don't return EBUSY to userspace */
09b6d21e 2021 }
149d518a 2022 goto ok;
09b6d21e 2023
149d518a 2024error:
09b6d21e 2025 mb86a20s_stats_not_ready(fe);
d36e418a 2026
149d518a 2027ok:
d36e418a
MCC		 2028 if (fe->ops.i2c_gate_ctrl)
2029 fe->ops.i2c_gate_ctrl(fe, 1);
149d518a 2030
09b6d21e
MCC		 2031 return rc;
2032}
2033
2034static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe,
2035 u16 *strength)
2036{
2037 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
2038
2039
2040 *strength = c->strength.stat[0].uvalue;
d36e418a 2041
09b6d21e 2042 return 0;
d36e418a
MCC		 2043}
2044
09b6d21e
MCC		 2045static int mb86a20s_get_frontend_dummy(struct dvb_frontend *fe)
2046{
2047 /*
2048 * get_frontend is now handled together with other stats
2049 * retrival, when read_status() is called, as some statistics
2050 * will depend on the layers detection.
2051 */
2052 return 0;
2053};
2054
b9ede79a 2055static int mb86a20s_tune(struct dvb_frontend *fe,
7e072221 2056 bool re_tune,
b9ede79a
MCC		 2057 unsigned int mode_flags,
2058 unsigned int *delay,
2059 fe_status_t *status)
2060{
f66d81b5 2061 struct mb86a20s_state *state = fe->demodulator_priv;
b9ede79a
MCC		 2062 int rc = 0;
2063
f66d81b5 2064 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
b9ede79a 2065
7e072221 2066 if (re_tune)
2d76e22b 2067 rc = mb86a20s_set_frontend(fe);
b9ede79a
MCC		 2068
2069 if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
09b6d21e 2070 mb86a20s_read_status_and_stats(fe, status);
b9ede79a
MCC		 2071
2072 return rc;
2073}
2074
2075static void mb86a20s_release(struct dvb_frontend *fe)
2076{
2077 struct mb86a20s_state *state = fe->demodulator_priv;
2078
f66d81b5 2079 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
b9ede79a
MCC		 2080
2081 kfree(state);
2082}
2083
2084static struct dvb_frontend_ops mb86a20s_ops;
2085
2086struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config,
2087 struct i2c_adapter *i2c)
2088{
f66d81b5 2089 struct mb86a20s_state *state;
b9ede79a
MCC		 2090 u8 rev;
2091
f167e302
MCC		 2092 dev_dbg(&i2c->dev, "%s called.\n", __func__);
2093
b9ede79a 2094 /* allocate memory for the internal state */
f66d81b5 2095 state = kzalloc(sizeof(struct mb86a20s_state), GFP_KERNEL);
b9ede79a 2096 if (state == NULL) {
f167e302 2097 dev_err(&i2c->dev,
f66d81b5 2098 "%s: unable to allocate memory for state\n", __func__);
b9ede79a
MCC		 2099 goto error;
2100 }
2101
2102 /* setup the state */
2103 state->config = config;
2104 state->i2c = i2c;
2105
2106 /* create dvb_frontend */
2107 memcpy(&state->frontend.ops, &mb86a20s_ops,
2108 sizeof(struct dvb_frontend_ops));
2109 state->frontend.demodulator_priv = state;
2110
2111 /* Check if it is a mb86a20s frontend */
2112 rev = mb86a20s_readreg(state, 0);
2113
2114 if (rev == 0x13) {
f167e302 2115 dev_info(&i2c->dev,
f66d81b5 2116 "Detected a Fujitsu mb86a20s frontend\n");
b9ede79a 2117 } else {
f167e302 2118 dev_dbg(&i2c->dev,
f66d81b5 2119 "Frontend revision %d is unknown - aborting.\n",
b9ede79a
MCC		 2120 rev);
2121 goto error;
2122 }
2123
2124 return &state->frontend;
2125
2126error:
2127 kfree(state);
2128 return NULL;
2129}
2130EXPORT_SYMBOL(mb86a20s_attach);
2131
2132static struct dvb_frontend_ops mb86a20s_ops = {
2d76e22b 2133 .delsys = { SYS_ISDBT },
b9ede79a
MCC		 2134 /* Use dib8000 values per default */
2135 .info = {
2136 .name = "Fujitsu mb86A20s",
04fa725e 2137 .caps = FE_CAN_RECOVER |
b9ede79a
MCC		 2138 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
2139 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
2140 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2141 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO |
2142 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
2143 /* Actually, those values depend on the used tuner */
2144 .frequency_min = 45000000,
2145 .frequency_max = 864000000,
2146 .frequency_stepsize = 62500,
2147 },
2148
2149 .release = mb86a20s_release,
2150
2151 .init = mb86a20s_initfe,
2d76e22b 2152 .set_frontend = mb86a20s_set_frontend,
09b6d21e
MCC		 2153 .get_frontend = mb86a20s_get_frontend_dummy,
2154 .read_status = mb86a20s_read_status_and_stats,
2155 .read_signal_strength = mb86a20s_read_signal_strength_from_cache,
b9ede79a
MCC		 2156 .tune = mb86a20s_tune,
2157};
2158
2159MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware");
2160MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
2161MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)