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Merge tag 'upstream-3.11-rc1' of git://git.infradead.org/linux-ubifs
[linux-2.6-block.git] / drivers / media / dvb-frontends / mb86a20s.c
CommitLineData
b9ede79a
MCC		 1/*
2 * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver
3 *
a77cfcac 4 * Copyright (C) 2010-2013 Mauro Carvalho Chehab <mchehab@redhat.com>
b9ede79a
MCC		 5 * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com>
6 *
b9ede79a
MCC		 7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 */
16
17#include <linux/kernel.h>
18#include <asm/div64.h>
19
20#include "dvb_frontend.h"
21#include "mb86a20s.h"
22
4f62a20d
MCC		 23#define NUM_LAYERS 3
24
b9ede79a
MCC		 25static int debug = 1;
26module_param(debug, int, 0644);
27MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
28
04fa725e
MCC		 29enum mb86a20s_bandwidth {
30 MB86A20S_13SEG = 0,
31 MB86A20S_13SEG_PARTIAL = 1,
32 MB86A20S_1SEG = 2,
33 MB86A20S_3SEG = 3,
34};
35
36u8 mb86a20s_subchannel[] = {
37 0xb0, 0xc0, 0xd0, 0xe0,
38 0xf0, 0x00, 0x10, 0x20,
39};
40
b9ede79a
MCC		 41struct mb86a20s_state {
42 struct i2c_adapter *i2c;
43 const struct mb86a20s_config *config;
09b6d21e 44 u32 last_frequency;
b9ede79a
MCC		 45
46 struct dvb_frontend frontend;
c736a5f2 47
768e6dad 48 u32 if_freq;
04fa725e
MCC		 49 enum mb86a20s_bandwidth bw;
50 bool inversion;
51 u32 subchannel;
768e6dad 52
4f62a20d 53 u32 estimated_rate[NUM_LAYERS];
0921ecfd 54 unsigned long get_strength_time;
d01a8ee3 55
c736a5f2 56 bool need_init;
b9ede79a
MCC		 57};
58
59struct regdata {
60 u8 reg;
61 u8 data;
62};
63
d01a8ee3
MCC		 64#define BER_SAMPLING_RATE 1 /* Seconds */
65
b9ede79a
MCC		 66/*
67 * Initialization sequence: Use whatevere default values that PV SBTVD
68 * does on its initialisation, obtained via USB snoop
69 */
768e6dad 70static struct regdata mb86a20s_init1[] = {
b9ede79a
MCC		 71 { 0x70, 0x0f },
72 { 0x70, 0xff },
73 { 0x08, 0x01 },
17e67d4c 74 { 0x50, 0xd1 }, { 0x51, 0x20 },
768e6dad
MCC		 75};
76
77static struct regdata mb86a20s_init2[] = {
ebe96749 78 { 0x28, 0x22 }, { 0x29, 0x00 }, { 0x2a, 0x1f }, { 0x2b, 0xf0 },
b9ede79a 79 { 0x3b, 0x21 },
17e67d4c 80 { 0x3c, 0x38 },
b9ede79a 81 { 0x01, 0x0d },
17e67d4c 82 { 0x04, 0x08 }, { 0x05, 0x03 },
a7025edf 83 { 0x04, 0x0e }, { 0x05, 0x00 },
17e67d4c
MCC		 84 { 0x04, 0x0f }, { 0x05, 0x37 },
85 { 0x04, 0x0b }, { 0x05, 0x78 },
a7025edf 86 { 0x04, 0x00 }, { 0x05, 0x00 },
17e67d4c
MCC		 87 { 0x04, 0x01 }, { 0x05, 0x1e },
88 { 0x04, 0x02 }, { 0x05, 0x07 },
89 { 0x04, 0x03 }, { 0x05, 0xd0 },
a7025edf
MCC		 90 { 0x04, 0x09 }, { 0x05, 0x00 },
91 { 0x04, 0x0a }, { 0x05, 0xff },
17e67d4c 92 { 0x04, 0x27 }, { 0x05, 0x00 },
a7025edf 93 { 0x04, 0x28 }, { 0x05, 0x00 },
17e67d4c
MCC		 94 { 0x04, 0x1e }, { 0x05, 0x00 },
95 { 0x04, 0x29 }, { 0x05, 0x64 },
96 { 0x04, 0x32 }, { 0x05, 0x02 },
a7025edf
MCC		 97 { 0x04, 0x14 }, { 0x05, 0x02 },
98 { 0x04, 0x04 }, { 0x05, 0x00 },
99 { 0x04, 0x05 }, { 0x05, 0x22 },
100 { 0x04, 0x06 }, { 0x05, 0x0e },
101 { 0x04, 0x07 }, { 0x05, 0xd8 },
102 { 0x04, 0x12 }, { 0x05, 0x00 },
103 { 0x04, 0x13 }, { 0x05, 0xff },
ebe96749
MCC		 104 { 0x04, 0x15 }, { 0x05, 0x4e },
105 { 0x04, 0x16 }, { 0x05, 0x20 },
09b6d21e
MCC		 106
107 /*
108 * On this demod, when the bit count reaches the count below,
109 * it collects the bit error count. The bit counters are initialized
110 * to 65535 here. This warrants that all of them will be quickly
111 * calculated when device gets locked. As TMCC is parsed, the values
d01a8ee3 112 * will be adjusted later in the driver's code.
09b6d21e
MCC		 113 */
114 { 0x52, 0x01 }, /* Turn on BER before Viterbi */
115 { 0x50, 0xa7 }, { 0x51, 0x00 },
a7025edf
MCC		 116 { 0x50, 0xa8 }, { 0x51, 0xff },
117 { 0x50, 0xa9 }, { 0x51, 0xff },
09b6d21e 118 { 0x50, 0xaa }, { 0x51, 0x00 },
a7025edf
MCC		 119 { 0x50, 0xab }, { 0x51, 0xff },
120 { 0x50, 0xac }, { 0x51, 0xff },
09b6d21e 121 { 0x50, 0xad }, { 0x51, 0x00 },
a7025edf
MCC		 122 { 0x50, 0xae }, { 0x51, 0xff },
123 { 0x50, 0xaf }, { 0x51, 0xff },
09b6d21e 124
d9b6f08a
MCC		 125 /*
126 * On this demod, post BER counts blocks. When the count reaches the
127 * value below, it collects the block error count. The block counters
128 * are initialized to 127 here. This warrants that all of them will be
129 * quickly calculated when device gets locked. As TMCC is parsed, the
130 * values will be adjusted later in the driver's code.
131 */
132 { 0x5e, 0x07 }, /* Turn on BER after Viterbi */
133 { 0x50, 0xdc }, { 0x51, 0x00 },
134 { 0x50, 0xdd }, { 0x51, 0x7f },
135 { 0x50, 0xde }, { 0x51, 0x00 },
136 { 0x50, 0xdf }, { 0x51, 0x7f },
137 { 0x50, 0xe0 }, { 0x51, 0x00 },
138 { 0x50, 0xe1 }, { 0x51, 0x7f },
593ae89a
MCC		 139
140 /*
141 * On this demod, when the block count reaches the count below,
142 * it collects the block error count. The block counters are initialized
143 * to 127 here. This warrants that all of them will be quickly
144 * calculated when device gets locked. As TMCC is parsed, the values
145 * will be adjusted later in the driver's code.
146 */
147 { 0x50, 0xb0 }, { 0x51, 0x07 }, /* Enable PER */
148 { 0x50, 0xb2 }, { 0x51, 0x00 },
149 { 0x50, 0xb3 }, { 0x51, 0x7f },
150 { 0x50, 0xb4 }, { 0x51, 0x00 },
151 { 0x50, 0xb5 }, { 0x51, 0x7f },
152 { 0x50, 0xb6 }, { 0x51, 0x00 },
153 { 0x50, 0xb7 }, { 0x51, 0x7f },
25188bd0
MCC		 154
155 { 0x50, 0x50 }, { 0x51, 0x02 }, /* MER manual mode */
09b6d21e
MCC		 156 { 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */
157 { 0x45, 0x04 }, /* CN symbol 4 */
25188bd0
MCC		 158 { 0x48, 0x04 }, /* CN manual mode */
159
a7025edf
MCC		 160 { 0x50, 0xd5 }, { 0x51, 0x01 }, /* Serial */
161 { 0x50, 0xd6 }, { 0x51, 0x1f },
162 { 0x50, 0xd2 }, { 0x51, 0x03 },
17e67d4c
MCC		 163 { 0x50, 0xd7 }, { 0x51, 0xbf },
164 { 0x28, 0x74 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0xff },
165 { 0x28, 0x46 }, { 0x29, 0x00 }, { 0x2a, 0x1a }, { 0x2b, 0x0c },
ce77d120
MCC		 166
167 { 0x04, 0x40 }, { 0x05, 0x00 },
17e67d4c
MCC		 168 { 0x28, 0x00 }, { 0x2b, 0x08 },
169 { 0x28, 0x05 }, { 0x2b, 0x00 },
b9ede79a 170 { 0x1c, 0x01 },
17e67d4c
MCC		 171 { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x1f },
172 { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x18 },
173 { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x12 },
174 { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x30 },
175 { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x37 },
176 { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 },
177 { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x09 },
178 { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x06 },
179 { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x7b },
180 { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x76 },
181 { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x7d },
182 { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x08 },
183 { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0b },
184 { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 },
185 { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xf2 },
186 { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xf3 },
187 { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x05 },
188 { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 },
189 { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f },
190 { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xef },
191 { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xd8 },
192 { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xf1 },
193 { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x3d },
194 { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x94 },
195 { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0xba },
a7025edf
MCC		 196 { 0x50, 0x1e }, { 0x51, 0x5d },
197 { 0x50, 0x22 }, { 0x51, 0x00 },
198 { 0x50, 0x23 }, { 0x51, 0xc8 },
199 { 0x50, 0x24 }, { 0x51, 0x00 },
200 { 0x50, 0x25 }, { 0x51, 0xf0 },
201 { 0x50, 0x26 }, { 0x51, 0x00 },
202 { 0x50, 0x27 }, { 0x51, 0xc3 },
203 { 0x50, 0x39 }, { 0x51, 0x02 },
17e67d4c
MCC		 204 { 0xec, 0x0f },
205 { 0xeb, 0x1f },
ebe96749 206 { 0x28, 0x6a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 },
b9ede79a
MCC		 207 { 0xd0, 0x00 },
208};
209
210static struct regdata mb86a20s_reset_reception[] = {
211 { 0x70, 0xf0 },
212 { 0x70, 0xff },
213 { 0x08, 0x01 },
214 { 0x08, 0x00 },
215};
216
d9b6f08a
MCC		 217static struct regdata mb86a20s_per_ber_reset[] = {
218 { 0x53, 0x00 }, /* pre BER Counter reset */
09b6d21e 219 { 0x53, 0x07 },
09b6d21e 220
d9b6f08a
MCC		 221 { 0x5f, 0x00 }, /* post BER Counter reset */
222 { 0x5f, 0x07 },
223
09b6d21e
MCC		 224 { 0x50, 0xb1 }, /* PER Counter reset */
225 { 0x51, 0x07 },
226 { 0x51, 0x00 },
227};
228
dd4493ef
MCC		 229/*
230 * I2C read/write functions and macros
231 */
232
b9ede79a 233static int mb86a20s_i2c_writereg(struct mb86a20s_state *state,
09b6d21e 234 u8 i2c_addr, u8 reg, u8 data)
b9ede79a
MCC		 235{
236 u8 buf[] = { reg, data };
237 struct i2c_msg msg = {
238 .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
239 };
240 int rc;
241
242 rc = i2c_transfer(state->i2c, &msg, 1);
243 if (rc != 1) {
f66d81b5
MCC		 244 dev_err(&state->i2c->dev,
245 "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n",
246 __func__, rc, reg, data);
b9ede79a
MCC		 247 return rc;
248 }
249
250 return 0;
251}
252
253static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state,
254 u8 i2c_addr, struct regdata *rd, int size)
255{
256 int i, rc;
257
258 for (i = 0; i < size; i++) {
259 rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg,
260 rd[i].data);
261 if (rc < 0)
262 return rc;
263 }
264 return 0;
265}
266
267static int mb86a20s_i2c_readreg(struct mb86a20s_state *state,
268 u8 i2c_addr, u8 reg)
269{
270 u8 val;
271 int rc;
272 struct i2c_msg msg[] = {
273 { .addr = i2c_addr, .flags = 0, .buf = &reg, .len = 1 },
274 { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 }
275 };
276
277 rc = i2c_transfer(state->i2c, msg, 2);
278
279 if (rc != 2) {
f66d81b5
MCC		 280 dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n",
281 __func__, reg, rc);
282 return (rc < 0) ? rc : -EIO;
b9ede79a
MCC		 283 }
284
285 return val;
286}
287
288#define mb86a20s_readreg(state, reg) \
289 mb86a20s_i2c_readreg(state, state->config->demod_address, reg)
290#define mb86a20s_writereg(state, reg, val) \
291 mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val)
292#define mb86a20s_writeregdata(state, regdata) \
293 mb86a20s_i2c_writeregdata(state, state->config->demod_address, \
294 regdata, ARRAY_SIZE(regdata))
295
09b6d21e
MCC		 296/*
297 * Ancillary internal routines (likely compiled inlined)
298 *
299 * The functions below assume that gateway lock has already obtained
300 */
301
dd4493ef 302static int mb86a20s_read_status(struct dvb_frontend *fe, fe_status_t *status)
b9ede79a
MCC		 303{
304 struct mb86a20s_state *state = fe->demodulator_priv;
dd4493ef 305 int val;
b9ede79a 306
dd4493ef 307 *status = 0;
b9ede79a 308
dd4493ef
MCC		 309 val = mb86a20s_readreg(state, 0x0a) & 0xf;
310 if (val < 0)
311 return val;
68541cda 312
dd4493ef
MCC		 313 if (val >= 2)
314 *status |= FE_HAS_SIGNAL;
b9ede79a 315
dd4493ef
MCC		 316 if (val >= 4)
317 *status |= FE_HAS_CARRIER;
7572f9c5 318
dd4493ef
MCC		 319 if (val >= 5)
320 *status |= FE_HAS_VITERBI;
7572f9c5 321
dd4493ef
MCC		 322 if (val >= 7)
323 *status |= FE_HAS_SYNC;
68541cda 324
dd4493ef
MCC		 325 if (val >= 8) /* Maybe 9? */
326 *status |= FE_HAS_LOCK;
327
f66d81b5
MCC		 328 dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n",
329 __func__, *status, val);
dd4493ef 330
15b1c5a0 331 return val;
b9ede79a
MCC		 332}
333
09b6d21e 334static int mb86a20s_read_signal_strength(struct dvb_frontend *fe)
b9ede79a
MCC		 335{
336 struct mb86a20s_state *state = fe->demodulator_priv;
0921ecfd 337 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
09b6d21e 338 int rc;
b9ede79a 339 unsigned rf_max, rf_min, rf;
68541cda 340
0921ecfd
MCC		 341 if (state->get_strength_time &&
342 (!time_after(jiffies, state->get_strength_time)))
343 return c->strength.stat[0].uvalue;
344
345 /* Reset its value if an error happen */
346 c->strength.stat[0].uvalue = 0;
347
b9ede79a
MCC		 348 /* Does a binary search to get RF strength */
349 rf_max = 0xfff;
350 rf_min = 0;
351 do {
352 rf = (rf_max + rf_min) / 2;
09b6d21e
MCC		 353 rc = mb86a20s_writereg(state, 0x04, 0x1f);
354 if (rc < 0)
355 return rc;
356 rc = mb86a20s_writereg(state, 0x05, rf >> 8);
357 if (rc < 0)
358 return rc;
359 rc = mb86a20s_writereg(state, 0x04, 0x20);
360 if (rc < 0)
361 return rc;
dad78c56 362 rc = mb86a20s_writereg(state, 0x05, rf);
09b6d21e
MCC		 363 if (rc < 0)
364 return rc;
b9ede79a 365
09b6d21e
MCC		 366 rc = mb86a20s_readreg(state, 0x02);
367 if (rc < 0)
368 return rc;
369 if (rc & 0x08)
b9ede79a
MCC		 370 rf_min = (rf_max + rf_min) / 2;
371 else
372 rf_max = (rf_max + rf_min) / 2;
373 if (rf_max - rf_min < 4) {
09b6d21e
MCC		 374 rf = (rf_max + rf_min) / 2;
375
376 /* Rescale it from 2^12 (4096) to 2^16 */
0921ecfd
MCC		 377 rf = rf << (16 - 12);
378 if (rf)
379 rf |= (1 << 12) - 1;
380
f66d81b5
MCC		 381 dev_dbg(&state->i2c->dev,
382 "%s: signal strength = %d (%d < RF=%d < %d)\n",
383 __func__, rf, rf_min, rf >> 4, rf_max);
0921ecfd
MCC		 384 c->strength.stat[0].uvalue = rf;
385 state->get_strength_time = jiffies +
386 msecs_to_jiffies(1000);
387 return 0;
b9ede79a
MCC		 388 }
389 } while (1);
b9ede79a
MCC		 390}
391
959a119f
MCC		 392static int mb86a20s_get_modulation(struct mb86a20s_state *state,
393 unsigned layer)
394{
395 int rc;
396 static unsigned char reg[] = {
397 [0] = 0x86, /* Layer A */
398 [1] = 0x8a, /* Layer B */
399 [2] = 0x8e, /* Layer C */
400 };
401
82033bc5 402 if (layer >= ARRAY_SIZE(reg))
959a119f
MCC		 403 return -EINVAL;
404 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
405 if (rc < 0)
406 return rc;
407 rc = mb86a20s_readreg(state, 0x6e);
408 if (rc < 0)
409 return rc;
04585921 410 switch ((rc >> 4) & 0x07) {
959a119f
MCC		 411 case 0:
412 return DQPSK;
413 case 1:
414 return QPSK;
415 case 2:
416 return QAM_16;
417 case 3:
418 return QAM_64;
419 default:
420 return QAM_AUTO;
421 }
422}
423
424static int mb86a20s_get_fec(struct mb86a20s_state *state,
425 unsigned layer)
426{
427 int rc;
428
429 static unsigned char reg[] = {
430 [0] = 0x87, /* Layer A */
431 [1] = 0x8b, /* Layer B */
432 [2] = 0x8f, /* Layer C */
433 };
434
82033bc5 435 if (layer >= ARRAY_SIZE(reg))
959a119f
MCC		 436 return -EINVAL;
437 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
438 if (rc < 0)
439 return rc;
440 rc = mb86a20s_readreg(state, 0x6e);
441 if (rc < 0)
442 return rc;
04585921 443 switch ((rc >> 4) & 0x07) {
959a119f
MCC		 444 case 0:
445 return FEC_1_2;
446 case 1:
447 return FEC_2_3;
448 case 2:
449 return FEC_3_4;
450 case 3:
451 return FEC_5_6;
452 case 4:
453 return FEC_7_8;
454 default:
455 return FEC_AUTO;
456 }
457}
458
459static int mb86a20s_get_interleaving(struct mb86a20s_state *state,
460 unsigned layer)
461{
462 int rc;
463
464 static unsigned char reg[] = {
465 [0] = 0x88, /* Layer A */
466 [1] = 0x8c, /* Layer B */
467 [2] = 0x90, /* Layer C */
468 };
469
82033bc5 470 if (layer >= ARRAY_SIZE(reg))
959a119f
MCC		 471 return -EINVAL;
472 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
473 if (rc < 0)
474 return rc;
475 rc = mb86a20s_readreg(state, 0x6e);
476 if (rc < 0)
477 return rc;
04585921
MCC		 478
479 switch ((rc >> 4) & 0x07) {
480 case 1:
481 return GUARD_INTERVAL_1_4;
482 case 2:
483 return GUARD_INTERVAL_1_8;
484 case 3:
485 return GUARD_INTERVAL_1_16;
486 case 4:
487 return GUARD_INTERVAL_1_32;
488
489 default:
490 case 0:
491 return GUARD_INTERVAL_AUTO;
492 }
959a119f
MCC		 493}
494
495static int mb86a20s_get_segment_count(struct mb86a20s_state *state,
496 unsigned layer)
497{
498 int rc, count;
959a119f
MCC		 499 static unsigned char reg[] = {
500 [0] = 0x89, /* Layer A */
501 [1] = 0x8d, /* Layer B */
502 [2] = 0x91, /* Layer C */
503 };
504
f66d81b5
MCC		 505 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
506
82033bc5 507 if (layer >= ARRAY_SIZE(reg))
959a119f 508 return -EINVAL;
f66d81b5 509
959a119f
MCC		 510 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
511 if (rc < 0)
512 return rc;
513 rc = mb86a20s_readreg(state, 0x6e);
514 if (rc < 0)
515 return rc;
516 count = (rc >> 4) & 0x0f;
517
f66d81b5
MCC		 518 dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count);
519
959a119f
MCC		 520 return count;
521}
522
a77cfcac
MCC		 523static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe)
524{
f66d81b5 525 struct mb86a20s_state *state = fe->demodulator_priv;
a77cfcac
MCC		 526 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
527
f66d81b5
MCC		 528 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
529
a77cfcac
MCC		 530 /* Fixed parameters */
531 c->delivery_system = SYS_ISDBT;
532 c->bandwidth_hz = 6000000;
533
534 /* Initialize values that will be later autodetected */
535 c->isdbt_layer_enabled = 0;
536 c->transmission_mode = TRANSMISSION_MODE_AUTO;
537 c->guard_interval = GUARD_INTERVAL_AUTO;
538 c->isdbt_sb_mode = 0;
539 c->isdbt_sb_segment_count = 0;
540}
541
d01a8ee3
MCC		 542/*
543 * Estimates the bit rate using the per-segment bit rate given by
544 * ABNT/NBR 15601 spec (table 4).
545 */
546static u32 isdbt_rate[3][5][4] = {
547 { /* DQPSK/QPSK */
548 { 280850, 312060, 330420, 340430 }, /* 1/2 */
549 { 374470, 416080, 440560, 453910 }, /* 2/3 */
550 { 421280, 468090, 495630, 510650 }, /* 3/4 */
551 { 468090, 520100, 550700, 567390 }, /* 5/6 */
552 { 491500, 546110, 578230, 595760 }, /* 7/8 */
553 }, { /* QAM16 */
554 { 561710, 624130, 660840, 680870 }, /* 1/2 */
555 { 748950, 832170, 881120, 907820 }, /* 2/3 */
556 { 842570, 936190, 991260, 1021300 }, /* 3/4 */
557 { 936190, 1040210, 1101400, 1134780 }, /* 5/6 */
558 { 983000, 1092220, 1156470, 1191520 }, /* 7/8 */
559 }, { /* QAM64 */
560 { 842570, 936190, 991260, 1021300 }, /* 1/2 */
561 { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */
562 { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */
563 { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */
564 { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */
565 }
566};
567
568static void mb86a20s_layer_bitrate(struct dvb_frontend *fe, u32 layer,
0562aef2
MCC		 569 u32 modulation, u32 forward_error_correction,
570 u32 interleaving,
d01a8ee3
MCC		 571 u32 segment)
572{
573 struct mb86a20s_state *state = fe->demodulator_priv;
574 u32 rate;
0562aef2 575 int mod, fec, guard;
d01a8ee3
MCC		 576
577 /*
578 * If modulation/fec/interleaving is not detected, the default is
579 * to consider the lowest bit rate, to avoid taking too long time
580 * to get BER.
581 */
582 switch (modulation) {
583 case DQPSK:
584 case QPSK:
585 default:
0562aef2 586 mod = 0;
d01a8ee3
MCC		 587 break;
588 case QAM_16:
0562aef2 589 mod = 1;
d01a8ee3
MCC		 590 break;
591 case QAM_64:
0562aef2 592 mod = 2;
d01a8ee3
MCC		 593 break;
594 }
595
0562aef2 596 switch (forward_error_correction) {
d01a8ee3
MCC		 597 default:
598 case FEC_1_2:
599 case FEC_AUTO:
0562aef2 600 fec = 0;
d01a8ee3
MCC		 601 break;
602 case FEC_2_3:
0562aef2 603 fec = 1;
d01a8ee3
MCC		 604 break;
605 case FEC_3_4:
0562aef2 606 fec = 2;
d01a8ee3
MCC		 607 break;
608 case FEC_5_6:
0562aef2 609 fec = 3;
d01a8ee3
MCC		 610 break;
611 case FEC_7_8:
0562aef2 612 fec = 4;
d01a8ee3
MCC		 613 break;
614 }
615
616 switch (interleaving) {
617 default:
618 case GUARD_INTERVAL_1_4:
0562aef2 619 guard = 0;
d01a8ee3
MCC		 620 break;
621 case GUARD_INTERVAL_1_8:
0562aef2 622 guard = 1;
d01a8ee3
MCC		 623 break;
624 case GUARD_INTERVAL_1_16:
0562aef2 625 guard = 2;
d01a8ee3
MCC		 626 break;
627 case GUARD_INTERVAL_1_32:
0562aef2 628 guard = 3;
d01a8ee3
MCC		 629 break;
630 }
631
632 /* Samples BER at BER_SAMPLING_RATE seconds */
0562aef2 633 rate = isdbt_rate[mod][fec][guard] * segment * BER_SAMPLING_RATE;
d01a8ee3
MCC		 634
635 /* Avoids sampling too quickly or to overflow the register */
636 if (rate < 256)
637 rate = 256;
638 else if (rate > (1 << 24) - 1)
639 rate = (1 << 24) - 1;
640
641 dev_dbg(&state->i2c->dev,
642 "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n",
0562aef2
MCC		 643 __func__, 'A' + layer,
644 segment * isdbt_rate[mod][fec][guard]/1000,
d01a8ee3
MCC		 645 rate, rate);
646
b1f89331 647 state->estimated_rate[layer] = rate;
d01a8ee3
MCC		 648}
649
7c61d80a 650static int mb86a20s_get_frontend(struct dvb_frontend *fe)
b9ede79a 651{
959a119f 652 struct mb86a20s_state *state = fe->demodulator_priv;
a77cfcac 653 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
5cb88ca8 654 int layer, rc;
b9ede79a 655
f66d81b5
MCC		 656 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
657
a77cfcac
MCC		 658 /* Reset frontend cache to default values */
659 mb86a20s_reset_frontend_cache(fe);
959a119f 660
959a119f
MCC		 661 /* Check for partial reception */
662 rc = mb86a20s_writereg(state, 0x6d, 0x85);
a77cfcac
MCC		 663 if (rc < 0)
664 return rc;
665 rc = mb86a20s_readreg(state, 0x6e);
666 if (rc < 0)
667 return rc;
668 c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0;
959a119f
MCC		 669
670 /* Get per-layer data */
a77cfcac 671
5cb88ca8 672 for (layer = 0; layer < NUM_LAYERS; layer++) {
f66d81b5 673 dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n",
5cb88ca8 674 __func__, 'A' + layer);
f66d81b5 675
5cb88ca8 676 rc = mb86a20s_get_segment_count(state, layer);
a77cfcac 677 if (rc < 0)
f66d81b5 678 goto noperlayer_error;
d01a8ee3 679 if (rc >= 0 && rc < 14) {
5cb88ca8 680 c->layer[layer].segment_count = rc;
d01a8ee3 681 } else {
5cb88ca8
MCC		 682 c->layer[layer].segment_count = 0;
683 state->estimated_rate[layer] = 0;
959a119f 684 continue;
a77cfcac 685 }
5cb88ca8
MCC		 686 c->isdbt_layer_enabled |= 1 << layer;
687 rc = mb86a20s_get_modulation(state, layer);
a77cfcac 688 if (rc < 0)
f66d81b5
MCC		 689 goto noperlayer_error;
690 dev_dbg(&state->i2c->dev, "%s: modulation %d.\n",
691 __func__, rc);
5cb88ca8
MCC		 692 c->layer[layer].modulation = rc;
693 rc = mb86a20s_get_fec(state, layer);
a77cfcac 694 if (rc < 0)
f66d81b5
MCC		 695 goto noperlayer_error;
696 dev_dbg(&state->i2c->dev, "%s: FEC %d.\n",
697 __func__, rc);
5cb88ca8
MCC		 698 c->layer[layer].fec = rc;
699 rc = mb86a20s_get_interleaving(state, layer);
a77cfcac 700 if (rc < 0)
f66d81b5
MCC		 701 goto noperlayer_error;
702 dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n",
703 __func__, rc);
5cb88ca8
MCC		 704 c->layer[layer].interleaving = rc;
705 mb86a20s_layer_bitrate(fe, layer, c->layer[layer].modulation,
706 c->layer[layer].fec,
707 c->layer[layer].interleaving,
708 c->layer[layer].segment_count);
959a119f
MCC		 709 }
710
959a119f 711 rc = mb86a20s_writereg(state, 0x6d, 0x84);
a77cfcac
MCC		 712 if (rc < 0)
713 return rc;
714 if ((rc & 0x60) == 0x20) {
715 c->isdbt_sb_mode = 1;
959a119f 716 /* At least, one segment should exist */
a77cfcac
MCC		 717 if (!c->isdbt_sb_segment_count)
718 c->isdbt_sb_segment_count = 1;
719 }
959a119f
MCC		 720
721 /* Get transmission mode and guard interval */
959a119f 722 rc = mb86a20s_readreg(state, 0x07);
a77cfcac
MCC		 723 if (rc < 0)
724 return rc;
725 if ((rc & 0x60) == 0x20) {
726 switch (rc & 0x0c >> 2) {
727 case 0:
728 c->transmission_mode = TRANSMISSION_MODE_2K;
729 break;
730 case 1:
731 c->transmission_mode = TRANSMISSION_MODE_4K;
732 break;
733 case 2:
734 c->transmission_mode = TRANSMISSION_MODE_8K;
735 break;
959a119f 736 }
a77cfcac
MCC		 737 }
738 if (!(rc & 0x10)) {
739 switch (rc & 0x3) {
740 case 0:
741 c->guard_interval = GUARD_INTERVAL_1_4;
742 break;
743 case 1:
744 c->guard_interval = GUARD_INTERVAL_1_8;
745 break;
746 case 2:
747 c->guard_interval = GUARD_INTERVAL_1_16;
748 break;
959a119f
MCC		 749 }
750 }
09b6d21e 751 return 0;
959a119f 752
f66d81b5 753noperlayer_error:
b9ede79a 754
09b6d21e
MCC		 755 /* per-layer info is incomplete; discard all per-layer */
756 c->isdbt_layer_enabled = 0;
757
758 return rc;
759}
760
761static int mb86a20s_reset_counters(struct dvb_frontend *fe)
762{
763 struct mb86a20s_state *state = fe->demodulator_priv;
764 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
765 int rc, val;
766
767 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
768
769 /* Reset the counters, if the channel changed */
770 if (state->last_frequency != c->frequency) {
09b6d21e
MCC		 771 memset(&c->cnr, 0, sizeof(c->cnr));
772 memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error));
773 memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count));
d9b6f08a
MCC		 774 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
775 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
09b6d21e
MCC		 776 memset(&c->block_error, 0, sizeof(c->block_error));
777 memset(&c->block_count, 0, sizeof(c->block_count));
778
779 state->last_frequency = c->frequency;
780 }
781
782 /* Clear status for most stats */
783
d9b6f08a
MCC		 784 /* BER/PER counter reset */
785 rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset);
09b6d21e
MCC		 786 if (rc < 0)
787 goto err;
788
789 /* CNR counter reset */
790 rc = mb86a20s_readreg(state, 0x45);
791 if (rc < 0)
792 goto err;
793 val = rc;
794 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
795 if (rc < 0)
796 goto err;
797 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
798 if (rc < 0)
799 goto err;
800
801 /* MER counter reset */
802 rc = mb86a20s_writereg(state, 0x50, 0x50);
803 if (rc < 0)
804 goto err;
805 rc = mb86a20s_readreg(state, 0x51);
806 if (rc < 0)
807 goto err;
808 val = rc;
809 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
810 if (rc < 0)
811 goto err;
812 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
813 if (rc < 0)
814 goto err;
815
149d518a 816 goto ok;
09b6d21e 817err:
149d518a
MCC		 818 dev_err(&state->i2c->dev,
819 "%s: Can't reset FE statistics (error %d).\n",
820 __func__, rc);
821ok:
a77cfcac 822 return rc;
09b6d21e
MCC		 823}
824
ad0abbf1
MCC		 825static int mb86a20s_get_pre_ber(struct dvb_frontend *fe,
826 unsigned layer,
827 u32 *error, u32 *count)
149d518a
MCC		 828{
829 struct mb86a20s_state *state = fe->demodulator_priv;
ad0abbf1 830 int rc, val;
149d518a
MCC		 831
832 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
833
4f62a20d 834 if (layer >= NUM_LAYERS)
149d518a
MCC		 835 return -EINVAL;
836
837 /* Check if the BER measures are already available */
838 rc = mb86a20s_readreg(state, 0x54);
839 if (rc < 0)
840 return rc;
841
842 /* Check if data is available for that layer */
843 if (!(rc & (1 << layer))) {
844 dev_dbg(&state->i2c->dev,
ad0abbf1 845 "%s: preBER for layer %c is not available yet.\n",
149d518a
MCC		 846 __func__, 'A' + layer);
847 return -EBUSY;
848 }
849
850 /* Read Bit Error Count */
851 rc = mb86a20s_readreg(state, 0x55 + layer * 3);
852 if (rc < 0)
853 return rc;
854 *error = rc << 16;
855 rc = mb86a20s_readreg(state, 0x56 + layer * 3);
856 if (rc < 0)
857 return rc;
858 *error |= rc << 8;
859 rc = mb86a20s_readreg(state, 0x57 + layer * 3);
860 if (rc < 0)
861 return rc;
862 *error |= rc;
863
864 dev_dbg(&state->i2c->dev,
865 "%s: bit error before Viterbi for layer %c: %d.\n",
866 __func__, 'A' + layer, *error);
867
868 /* Read Bit Count */
869 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
870 if (rc < 0)
871 return rc;
872 rc = mb86a20s_readreg(state, 0x51);
873 if (rc < 0)
874 return rc;
875 *count = rc << 16;
876 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
877 if (rc < 0)
878 return rc;
879 rc = mb86a20s_readreg(state, 0x51);
880 if (rc < 0)
881 return rc;
882 *count |= rc << 8;
883 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
884 if (rc < 0)
885 return rc;
886 rc = mb86a20s_readreg(state, 0x51);
887 if (rc < 0)
888 return rc;
889 *count |= rc;
890
891 dev_dbg(&state->i2c->dev,
892 "%s: bit count before Viterbi for layer %c: %d.\n",
893 __func__, 'A' + layer, *count);
894
895
d01a8ee3
MCC		 896 /*
897 * As we get TMCC data from the frontend, we can better estimate the
898 * BER bit counters, in order to do the BER measure during a longer
899 * time. Use those data, if available, to update the bit count
900 * measure.
901 */
902
903 if (state->estimated_rate[layer]
904 && state->estimated_rate[layer] != *count) {
905 dev_dbg(&state->i2c->dev,
ad0abbf1 906 "%s: updating layer %c preBER counter to %d.\n",
d01a8ee3 907 __func__, 'A' + layer, state->estimated_rate[layer]);
ad0abbf1
MCC		 908
909 /* Turn off BER before Viterbi */
910 rc = mb86a20s_writereg(state, 0x52, 0x00);
911
912 /* Update counter for this layer */
d01a8ee3
MCC		 913 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
914 if (rc < 0)
915 return rc;
916 rc = mb86a20s_writereg(state, 0x51,
917 state->estimated_rate[layer] >> 16);
918 if (rc < 0)
919 return rc;
920 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
921 if (rc < 0)
922 return rc;
923 rc = mb86a20s_writereg(state, 0x51,
924 state->estimated_rate[layer] >> 8);
925 if (rc < 0)
926 return rc;
927 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
928 if (rc < 0)
929 return rc;
930 rc = mb86a20s_writereg(state, 0x51,
931 state->estimated_rate[layer]);
932 if (rc < 0)
933 return rc;
ad0abbf1
MCC		 934
935 /* Turn on BER before Viterbi */
936 rc = mb86a20s_writereg(state, 0x52, 0x01);
937
938 /* Reset all preBER counters */
939 rc = mb86a20s_writereg(state, 0x53, 0x00);
940 if (rc < 0)
941 return rc;
942 rc = mb86a20s_writereg(state, 0x53, 0x07);
943 } else {
944 /* Reset counter to collect new data */
945 rc = mb86a20s_readreg(state, 0x53);
946 if (rc < 0)
947 return rc;
948 val = rc;
949 rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer));
950 if (rc < 0)
951 return rc;
952 rc = mb86a20s_writereg(state, 0x53, val | (1 << layer));
d01a8ee3
MCC		 953 }
954
d9b6f08a
MCC		 955 return rc;
956}
957
958static int mb86a20s_get_post_ber(struct dvb_frontend *fe,
959 unsigned layer,
960 u32 *error, u32 *count)
961{
962 struct mb86a20s_state *state = fe->demodulator_priv;
963 u32 counter, collect_rate;
964 int rc, val;
965
966 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
967
4f62a20d 968 if (layer >= NUM_LAYERS)
d9b6f08a
MCC		 969 return -EINVAL;
970
971 /* Check if the BER measures are already available */
972 rc = mb86a20s_readreg(state, 0x60);
973 if (rc < 0)
974 return rc;
975
976 /* Check if data is available for that layer */
977 if (!(rc & (1 << layer))) {
978 dev_dbg(&state->i2c->dev,
979 "%s: post BER for layer %c is not available yet.\n",
980 __func__, 'A' + layer);
981 return -EBUSY;
982 }
d01a8ee3 983
d9b6f08a
MCC		 984 /* Read Bit Error Count */
985 rc = mb86a20s_readreg(state, 0x64 + layer * 3);
986 if (rc < 0)
987 return rc;
988 *error = rc << 16;
989 rc = mb86a20s_readreg(state, 0x65 + layer * 3);
990 if (rc < 0)
991 return rc;
992 *error |= rc << 8;
993 rc = mb86a20s_readreg(state, 0x66 + layer * 3);
994 if (rc < 0)
995 return rc;
996 *error |= rc;
997
998 dev_dbg(&state->i2c->dev,
999 "%s: post bit error for layer %c: %d.\n",
1000 __func__, 'A' + layer, *error);
1001
1002 /* Read Bit Count */
1003 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
1004 if (rc < 0)
1005 return rc;
1006 rc = mb86a20s_readreg(state, 0x51);
1007 if (rc < 0)
1008 return rc;
1009 counter = rc << 8;
1010 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
1011 if (rc < 0)
1012 return rc;
1013 rc = mb86a20s_readreg(state, 0x51);
1014 if (rc < 0)
1015 return rc;
1016 counter |= rc;
1017 *count = counter * 204 * 8;
1018
1019 dev_dbg(&state->i2c->dev,
1020 "%s: post bit count for layer %c: %d.\n",
1021 __func__, 'A' + layer, *count);
1022
1023 /*
1024 * As we get TMCC data from the frontend, we can better estimate the
1025 * BER bit counters, in order to do the BER measure during a longer
1026 * time. Use those data, if available, to update the bit count
1027 * measure.
1028 */
1029
1030 if (!state->estimated_rate[layer])
1031 goto reset_measurement;
1032
1033 collect_rate = state->estimated_rate[layer] / 204 / 8;
1034 if (collect_rate < 32)
1035 collect_rate = 32;
1036 if (collect_rate > 65535)
1037 collect_rate = 65535;
1038 if (collect_rate != counter) {
1039 dev_dbg(&state->i2c->dev,
1040 "%s: updating postBER counter on layer %c to %d.\n",
1041 __func__, 'A' + layer, collect_rate);
1042
1043 /* Turn off BER after Viterbi */
1044 rc = mb86a20s_writereg(state, 0x5e, 0x00);
1045
1046 /* Update counter for this layer */
1047 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
1048 if (rc < 0)
1049 return rc;
1050 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1051 if (rc < 0)
1052 return rc;
1053 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
1054 if (rc < 0)
1055 return rc;
1056 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1057 if (rc < 0)
1058 return rc;
1059
1060 /* Turn on BER after Viterbi */
1061 rc = mb86a20s_writereg(state, 0x5e, 0x07);
1062
1063 /* Reset all preBER counters */
1064 rc = mb86a20s_writereg(state, 0x5f, 0x00);
1065 if (rc < 0)
1066 return rc;
1067 rc = mb86a20s_writereg(state, 0x5f, 0x07);
1068
1069 return rc;
1070 }
1071
1072reset_measurement:
149d518a 1073 /* Reset counter to collect new data */
ad0abbf1
MCC		 1074 rc = mb86a20s_readreg(state, 0x5f);
1075 if (rc < 0)
1076 return rc;
1077 val = rc;
1078 rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer));
149d518a
MCC		 1079 if (rc < 0)
1080 return rc;
d9b6f08a 1081 rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer));
149d518a 1082
ad0abbf1 1083 return rc;
149d518a
MCC		 1084}
1085
593ae89a
MCC		 1086static int mb86a20s_get_blk_error(struct dvb_frontend *fe,
1087 unsigned layer,
1088 u32 *error, u32 *count)
1089{
1090 struct mb86a20s_state *state = fe->demodulator_priv;
313cf4ef 1091 int rc, val;
593ae89a
MCC		 1092 u32 collect_rate;
1093 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1094
4f62a20d 1095 if (layer >= NUM_LAYERS)
593ae89a
MCC		 1096 return -EINVAL;
1097
1098 /* Check if the PER measures are already available */
1099 rc = mb86a20s_writereg(state, 0x50, 0xb8);
1100 if (rc < 0)
1101 return rc;
1102 rc = mb86a20s_readreg(state, 0x51);
1103 if (rc < 0)
1104 return rc;
1105
1106 /* Check if data is available for that layer */
1107
1108 if (!(rc & (1 << layer))) {
1109 dev_dbg(&state->i2c->dev,
1110 "%s: block counts for layer %c aren't available yet.\n",
1111 __func__, 'A' + layer);
1112 return -EBUSY;
1113 }
1114
1115 /* Read Packet error Count */
1116 rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2);
1117 if (rc < 0)
1118 return rc;
1119 rc = mb86a20s_readreg(state, 0x51);
1120 if (rc < 0)
1121 return rc;
1122 *error = rc << 8;
1123 rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2);
1124 if (rc < 0)
1125 return rc;
1126 rc = mb86a20s_readreg(state, 0x51);
1127 if (rc < 0)
1128 return rc;
1129 *error |= rc;
d56e326f 1130 dev_dbg(&state->i2c->dev, "%s: block error for layer %c: %d.\n",
593ae89a
MCC		 1131 __func__, 'A' + layer, *error);
1132
1133 /* Read Bit Count */
1134 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1135 if (rc < 0)
1136 return rc;
1137 rc = mb86a20s_readreg(state, 0x51);
1138 if (rc < 0)
1139 return rc;
1140 *count = rc << 8;
1141 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1142 if (rc < 0)
1143 return rc;
1144 rc = mb86a20s_readreg(state, 0x51);
1145 if (rc < 0)
1146 return rc;
1147 *count |= rc;
1148
1149 dev_dbg(&state->i2c->dev,
1150 "%s: block count for layer %c: %d.\n",
1151 __func__, 'A' + layer, *count);
1152
1153 /*
1154 * As we get TMCC data from the frontend, we can better estimate the
1155 * BER bit counters, in order to do the BER measure during a longer
1156 * time. Use those data, if available, to update the bit count
1157 * measure.
1158 */
1159
1160 if (!state->estimated_rate[layer])
1161 goto reset_measurement;
1162
1163 collect_rate = state->estimated_rate[layer] / 204 / 8;
593ae89a
MCC		 1164 if (collect_rate < 32)
1165 collect_rate = 32;
1166 if (collect_rate > 65535)
1167 collect_rate = 65535;
1168
1169 if (collect_rate != *count) {
1170 dev_dbg(&state->i2c->dev,
1171 "%s: updating PER counter on layer %c to %d.\n",
1172 __func__, 'A' + layer, collect_rate);
313cf4ef
MCC		 1173
1174 /* Stop PER measurement */
1175 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1176 if (rc < 0)
1177 return rc;
1178 rc = mb86a20s_writereg(state, 0x51, 0x00);
1179 if (rc < 0)
1180 return rc;
1181
1182 /* Update this layer's counter */
593ae89a
MCC		 1183 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1184 if (rc < 0)
1185 return rc;
1186 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1187 if (rc < 0)
1188 return rc;
1189 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1190 if (rc < 0)
1191 return rc;
1192 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1193 if (rc < 0)
1194 return rc;
313cf4ef
MCC		 1195
1196 /* start PER measurement */
1197 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1198 if (rc < 0)
1199 return rc;
1200 rc = mb86a20s_writereg(state, 0x51, 0x07);
1201 if (rc < 0)
1202 return rc;
1203
1204 /* Reset all counters to collect new data */
1205 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1206 if (rc < 0)
1207 return rc;
1208 rc = mb86a20s_writereg(state, 0x51, 0x07);
1209 if (rc < 0)
1210 return rc;
1211 rc = mb86a20s_writereg(state, 0x51, 0x00);
1212
1213 return rc;
593ae89a
MCC		 1214 }
1215
1216reset_measurement:
1217 /* Reset counter to collect new data */
1218 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1219 if (rc < 0)
1220 return rc;
313cf4ef 1221 rc = mb86a20s_readreg(state, 0x51);
593ae89a
MCC		 1222 if (rc < 0)
1223 return rc;
313cf4ef
MCC		 1224 val = rc;
1225 rc = mb86a20s_writereg(state, 0x51, val | (1 << layer));
593ae89a
MCC		 1226 if (rc < 0)
1227 return rc;
313cf4ef 1228 rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer));
593ae89a 1229
313cf4ef 1230 return rc;
593ae89a
MCC		 1231}
1232
25188bd0
MCC		 1233struct linear_segments {
1234 unsigned x, y;
1235};
1236
1237/*
1238 * All tables below return a dB/1000 measurement
1239 */
1240
1241static struct linear_segments cnr_to_db_table[] = {
1242 { 19648, 0},
1243 { 18187, 1000},
1244 { 16534, 2000},
1245 { 14823, 3000},
1246 { 13161, 4000},
1247 { 11622, 5000},
1248 { 10279, 6000},
1249 { 9089, 7000},
1250 { 8042, 8000},
1251 { 7137, 9000},
1252 { 6342, 10000},
1253 { 5641, 11000},
1254 { 5030, 12000},
1255 { 4474, 13000},
1256 { 3988, 14000},
1257 { 3556, 15000},
1258 { 3180, 16000},
1259 { 2841, 17000},
1260 { 2541, 18000},
1261 { 2276, 19000},
1262 { 2038, 20000},
1263 { 1800, 21000},
1264 { 1625, 22000},
1265 { 1462, 23000},
1266 { 1324, 24000},
1267 { 1175, 25000},
1268 { 1063, 26000},
1269 { 980, 27000},
1270 { 907, 28000},
1271 { 840, 29000},
1272 { 788, 30000},
1273};
1274
1275static struct linear_segments cnr_64qam_table[] = {
1276 { 3922688, 0},
1277 { 3920384, 1000},
1278 { 3902720, 2000},
1279 { 3894784, 3000},
1280 { 3882496, 4000},
1281 { 3872768, 5000},
1282 { 3858944, 6000},
1283 { 3851520, 7000},
1284 { 3838976, 8000},
1285 { 3829248, 9000},
1286 { 3818240, 10000},
1287 { 3806976, 11000},
1288 { 3791872, 12000},
1289 { 3767040, 13000},
1290 { 3720960, 14000},
1291 { 3637504, 15000},
1292 { 3498496, 16000},
1293 { 3296000, 17000},
1294 { 3031040, 18000},
1295 { 2715392, 19000},
1296 { 2362624, 20000},
1297 { 1963264, 21000},
1298 { 1649664, 22000},
1299 { 1366784, 23000},
1300 { 1120768, 24000},
1301 { 890880, 25000},
1302 { 723456, 26000},
1303 { 612096, 27000},
1304 { 518912, 28000},
1305 { 448256, 29000},
1306 { 388864, 30000},
1307};
1308
1309static struct linear_segments cnr_16qam_table[] = {
1310 { 5314816, 0},
1311 { 5219072, 1000},
1312 { 5118720, 2000},
1313 { 4998912, 3000},
1314 { 4875520, 4000},
1315 { 4736000, 5000},
1316 { 4604160, 6000},
1317 { 4458752, 7000},
1318 { 4300288, 8000},
1319 { 4092928, 9000},
1320 { 3836160, 10000},
1321 { 3521024, 11000},
1322 { 3155968, 12000},
1323 { 2756864, 13000},
1324 { 2347008, 14000},
1325 { 1955072, 15000},
1326 { 1593600, 16000},
1327 { 1297920, 17000},
1328 { 1043968, 18000},
1329 { 839680, 19000},
1330 { 672256, 20000},
1331 { 523008, 21000},
1332 { 424704, 22000},
1333 { 345088, 23000},
1334 { 280064, 24000},
1335 { 221440, 25000},
1336 { 179712, 26000},
1337 { 151040, 27000},
1338 { 128512, 28000},
1339 { 110080, 29000},
1340 { 95744, 30000},
1341};
1342
1343struct linear_segments cnr_qpsk_table[] = {
1344 { 2834176, 0},
1345 { 2683648, 1000},
1346 { 2536960, 2000},
1347 { 2391808, 3000},
1348 { 2133248, 4000},
1349 { 1906176, 5000},
1350 { 1666560, 6000},
1351 { 1422080, 7000},
1352 { 1189632, 8000},
1353 { 976384, 9000},
1354 { 790272, 10000},
1355 { 633344, 11000},
1356 { 505600, 12000},
1357 { 402944, 13000},
1358 { 320768, 14000},
1359 { 255488, 15000},
1360 { 204032, 16000},
1361 { 163072, 17000},
1362 { 130304, 18000},
1363 { 105216, 19000},
1364 { 83456, 20000},
1365 { 65024, 21000},
1366 { 52480, 22000},
1367 { 42752, 23000},
1368 { 34560, 24000},
1369 { 27136, 25000},
1370 { 22016, 26000},
1371 { 18432, 27000},
1372 { 15616, 28000},
1373 { 13312, 29000},
1374 { 11520, 30000},
1375};
1376
1377static u32 interpolate_value(u32 value, struct linear_segments *segments,
1378 unsigned len)
1379{
1380 u64 tmp64;
1381 u32 dx, dy;
1382 int i, ret;
1383
1384 if (value >= segments[0].x)
1385 return segments[0].y;
1386 if (value < segments[len-1].x)
1387 return segments[len-1].y;
1388
1389 for (i = 1; i < len - 1; i++) {
1390 /* If value is identical, no need to interpolate */
1391 if (value == segments[i].x)
1392 return segments[i].y;
1393 if (value > segments[i].x)
1394 break;
1395 }
1396
1397 /* Linear interpolation between the two (x,y) points */
1398 dy = segments[i].y - segments[i - 1].y;
1399 dx = segments[i - 1].x - segments[i].x;
1400 tmp64 = value - segments[i].x;
1401 tmp64 *= dy;
1402 do_div(tmp64, dx);
1403 ret = segments[i].y - tmp64;
1404
1405 return ret;
1406}
1407
1408static int mb86a20s_get_main_CNR(struct dvb_frontend *fe)
1409{
1410 struct mb86a20s_state *state = fe->demodulator_priv;
1411 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1412 u32 cnr_linear, cnr;
1413 int rc, val;
1414
1415 /* Check if CNR is available */
1416 rc = mb86a20s_readreg(state, 0x45);
1417 if (rc < 0)
1418 return rc;
1419
1420 if (!(rc & 0x40)) {
d56e326f 1421 dev_dbg(&state->i2c->dev, "%s: CNR is not available yet.\n",
25188bd0
MCC		 1422 __func__);
1423 return -EBUSY;
1424 }
1425 val = rc;
1426
1427 rc = mb86a20s_readreg(state, 0x46);
1428 if (rc < 0)
1429 return rc;
1430 cnr_linear = rc << 8;
1431
1432 rc = mb86a20s_readreg(state, 0x46);
1433 if (rc < 0)
1434 return rc;
1435 cnr_linear |= rc;
1436
1437 cnr = interpolate_value(cnr_linear,
1438 cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table));
1439
1440 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1441 c->cnr.stat[0].svalue = cnr;
1442
1443 dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n",
1444 __func__, cnr / 1000, cnr % 1000, cnr_linear);
1445
1446 /* CNR counter reset */
1447 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
1448 if (rc < 0)
1449 return rc;
1450 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
1451
1452 return rc;
1453}
1454
593ae89a 1455static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe)
25188bd0
MCC		 1456{
1457 struct mb86a20s_state *state = fe->demodulator_priv;
1458 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1459 u32 mer, cnr;
5cb88ca8 1460 int rc, val, layer;
25188bd0
MCC		 1461 struct linear_segments *segs;
1462 unsigned segs_len;
1463
1464 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1465
1466 /* Check if the measures are already available */
1467 rc = mb86a20s_writereg(state, 0x50, 0x5b);
1468 if (rc < 0)
1469 return rc;
1470 rc = mb86a20s_readreg(state, 0x51);
1471 if (rc < 0)
1472 return rc;
1473
1474 /* Check if data is available */
1475 if (!(rc & 0x01)) {
d56e326f 1476 dev_dbg(&state->i2c->dev,
25188bd0
MCC		 1477 "%s: MER measures aren't available yet.\n", __func__);
1478 return -EBUSY;
1479 }
1480
1481 /* Read all layers */
5cb88ca8
MCC		 1482 for (layer = 0; layer < NUM_LAYERS; layer++) {
1483 if (!(c->isdbt_layer_enabled & (1 << layer))) {
1484 c->cnr.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
25188bd0
MCC		 1485 continue;
1486 }
1487
5cb88ca8 1488 rc = mb86a20s_writereg(state, 0x50, 0x52 + layer * 3);
25188bd0
MCC		 1489 if (rc < 0)
1490 return rc;
1491 rc = mb86a20s_readreg(state, 0x51);
1492 if (rc < 0)
1493 return rc;
1494 mer = rc << 16;
5cb88ca8 1495 rc = mb86a20s_writereg(state, 0x50, 0x53 + layer * 3);
25188bd0
MCC		 1496 if (rc < 0)
1497 return rc;
1498 rc = mb86a20s_readreg(state, 0x51);
1499 if (rc < 0)
1500 return rc;
1501 mer |= rc << 8;
5cb88ca8 1502 rc = mb86a20s_writereg(state, 0x50, 0x54 + layer * 3);
25188bd0
MCC		 1503 if (rc < 0)
1504 return rc;
1505 rc = mb86a20s_readreg(state, 0x51);
1506 if (rc < 0)
1507 return rc;
1508 mer |= rc;
1509
5cb88ca8 1510 switch (c->layer[layer].modulation) {
25188bd0
MCC		 1511 case DQPSK:
1512 case QPSK:
1513 segs = cnr_qpsk_table;
1514 segs_len = ARRAY_SIZE(cnr_qpsk_table);
1515 break;
1516 case QAM_16:
1517 segs = cnr_16qam_table;
1518 segs_len = ARRAY_SIZE(cnr_16qam_table);
1519 break;
1520 default:
1521 case QAM_64:
1522 segs = cnr_64qam_table;
1523 segs_len = ARRAY_SIZE(cnr_64qam_table);
1524 break;
1525 }
1526 cnr = interpolate_value(mer, segs, segs_len);
1527
5cb88ca8
MCC		 1528 c->cnr.stat[1 + layer].scale = FE_SCALE_DECIBEL;
1529 c->cnr.stat[1 + layer].svalue = cnr;
25188bd0
MCC		 1530
1531 dev_dbg(&state->i2c->dev,
1532 "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n",
5cb88ca8 1533 __func__, 'A' + layer, cnr / 1000, cnr % 1000, mer);
25188bd0
MCC		 1534
1535 }
1536
1537 /* Start a new MER measurement */
1538 /* MER counter reset */
1539 rc = mb86a20s_writereg(state, 0x50, 0x50);
1540 if (rc < 0)
1541 return rc;
1542 rc = mb86a20s_readreg(state, 0x51);
1543 if (rc < 0)
1544 return rc;
1545 val = rc;
1546
1547 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
1548 if (rc < 0)
1549 return rc;
1550 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
1551 if (rc < 0)
1552 return rc;
1553
1554 return 0;
1555}
1556
09b6d21e
MCC		 1557static void mb86a20s_stats_not_ready(struct dvb_frontend *fe)
1558{
1559 struct mb86a20s_state *state = fe->demodulator_priv;
1560 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
5cb88ca8 1561 int layer;
09b6d21e
MCC		 1562
1563 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
a77cfcac 1564
09b6d21e
MCC		 1565 /* Fill the length of each status counter */
1566
1567 /* Only global stats */
1568 c->strength.len = 1;
1569
1570 /* Per-layer stats - 3 layers + global */
4f62a20d
MCC		 1571 c->cnr.len = NUM_LAYERS + 1;
1572 c->pre_bit_error.len = NUM_LAYERS + 1;
1573 c->pre_bit_count.len = NUM_LAYERS + 1;
1574 c->post_bit_error.len = NUM_LAYERS + 1;
1575 c->post_bit_count.len = NUM_LAYERS + 1;
1576 c->block_error.len = NUM_LAYERS + 1;
1577 c->block_count.len = NUM_LAYERS + 1;
09b6d21e
MCC		 1578
1579 /* Signal is always available */
1580 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
1581 c->strength.stat[0].uvalue = 0;
1582
1583 /* Put all of them at FE_SCALE_NOT_AVAILABLE */
5cb88ca8
MCC		 1584 for (layer = 0; layer < NUM_LAYERS + 1; layer++) {
1585 c->cnr.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1586 c->pre_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1587 c->pre_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1588 c->post_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1589 c->post_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1590 c->block_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1591 c->block_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
09b6d21e 1592 }
b9ede79a
MCC		 1593}
1594
15b1c5a0 1595static int mb86a20s_get_stats(struct dvb_frontend *fe, int status_nr)
149d518a
MCC		 1596{
1597 struct mb86a20s_state *state = fe->demodulator_priv;
1598 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
5cb88ca8 1599 int rc = 0, layer;
149d518a
MCC		 1600 u32 bit_error = 0, bit_count = 0;
1601 u32 t_pre_bit_error = 0, t_pre_bit_count = 0;
d9b6f08a 1602 u32 t_post_bit_error = 0, t_post_bit_count = 0;
593ae89a
MCC		 1603 u32 block_error = 0, block_count = 0;
1604 u32 t_block_error = 0, t_block_count = 0;
d9b6f08a
MCC		 1605 int active_layers = 0, pre_ber_layers = 0, post_ber_layers = 0;
1606 int per_layers = 0;
149d518a 1607
25188bd0
MCC		 1608 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1609
1610 mb86a20s_get_main_CNR(fe);
1611
149d518a 1612 /* Get per-layer stats */
593ae89a 1613 mb86a20s_get_blk_error_layer_CNR(fe);
25188bd0 1614
15b1c5a0
MCC		 1615 /*
1616 * At state 7, only CNR is available
1617 * For BER measures, state=9 is required
1618 * FIXME: we may get MER measures with state=8
1619 */
1620 if (status_nr < 9)
1621 return 0;
1622
5cb88ca8
MCC		 1623 for (layer = 0; layer < NUM_LAYERS; layer++) {
1624 if (c->isdbt_layer_enabled & (1 << layer)) {
149d518a
MCC		 1625 /* Layer is active and has rc segments */
1626 active_layers++;
1627
149d518a 1628 /* Handle BER before vterbi */
5cb88ca8 1629 rc = mb86a20s_get_pre_ber(fe, layer,
ad0abbf1 1630 &bit_error, &bit_count);
149d518a 1631 if (rc >= 0) {
5cb88ca8
MCC		 1632 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1633 c->pre_bit_error.stat[1 + layer].uvalue += bit_error;
1634 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1635 c->pre_bit_count.stat[1 + layer].uvalue += bit_count;
149d518a
MCC		 1636 } else if (rc != -EBUSY) {
1637 /*
1638 * If an I/O error happened,
1639 * measures are now unavailable
1640 */
5cb88ca8
MCC		 1641 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1642 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
149d518a
MCC		 1643 dev_err(&state->i2c->dev,
1644 "%s: Can't get BER for layer %c (error %d).\n",
5cb88ca8 1645 __func__, 'A' + layer, rc);
149d518a 1646 }
5cb88ca8 1647 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
d9b6f08a
MCC		 1648 pre_ber_layers++;
1649
1650 /* Handle BER post vterbi */
5cb88ca8 1651 rc = mb86a20s_get_post_ber(fe, layer,
d9b6f08a
MCC		 1652 &bit_error, &bit_count);
1653 if (rc >= 0) {
5cb88ca8
MCC		 1654 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1655 c->post_bit_error.stat[1 + layer].uvalue += bit_error;
1656 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1657 c->post_bit_count.stat[1 + layer].uvalue += bit_count;
d9b6f08a
MCC		 1658 } else if (rc != -EBUSY) {
1659 /*
1660 * If an I/O error happened,
1661 * measures are now unavailable
1662 */
5cb88ca8
MCC		 1663 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1664 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
d9b6f08a
MCC		 1665 dev_err(&state->i2c->dev,
1666 "%s: Can't get BER for layer %c (error %d).\n",
5cb88ca8 1667 __func__, 'A' + layer, rc);
d9b6f08a 1668 }
5cb88ca8 1669 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
d9b6f08a 1670 post_ber_layers++;
149d518a 1671
593ae89a 1672 /* Handle Block errors for PER/UCB reports */
5cb88ca8 1673 rc = mb86a20s_get_blk_error(fe, layer,
593ae89a
MCC		 1674 &block_error,
1675 &block_count);
1676 if (rc >= 0) {
5cb88ca8
MCC		 1677 c->block_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1678 c->block_error.stat[1 + layer].uvalue += block_error;
1679 c->block_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1680 c->block_count.stat[1 + layer].uvalue += block_count;
593ae89a
MCC		 1681 } else if (rc != -EBUSY) {
1682 /*
1683 * If an I/O error happened,
1684 * measures are now unavailable
1685 */
5cb88ca8
MCC		 1686 c->block_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1687 c->block_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
593ae89a
MCC		 1688 dev_err(&state->i2c->dev,
1689 "%s: Can't get PER for layer %c (error %d).\n",
5cb88ca8 1690 __func__, 'A' + layer, rc);
593ae89a
MCC		 1691
1692 }
5cb88ca8 1693 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
593ae89a
MCC		 1694 per_layers++;
1695
d9b6f08a 1696 /* Update total preBER */
5cb88ca8
MCC		 1697 t_pre_bit_error += c->pre_bit_error.stat[1 + layer].uvalue;
1698 t_pre_bit_count += c->pre_bit_count.stat[1 + layer].uvalue;
593ae89a 1699
d9b6f08a 1700 /* Update total postBER */
5cb88ca8
MCC		 1701 t_post_bit_error += c->post_bit_error.stat[1 + layer].uvalue;
1702 t_post_bit_count += c->post_bit_count.stat[1 + layer].uvalue;
d9b6f08a 1703
593ae89a 1704 /* Update total PER */
5cb88ca8
MCC		 1705 t_block_error += c->block_error.stat[1 + layer].uvalue;
1706 t_block_count += c->block_count.stat[1 + layer].uvalue;
149d518a
MCC		 1707 }
1708 }
1709
1710 /*
1711 * Start showing global count if at least one error count is
1712 * available.
1713 */
d9b6f08a 1714 if (pre_ber_layers) {
149d518a
MCC		 1715 /*
1716 * At least one per-layer BER measure was read. We can now
1717 * calculate the total BER
1718 *
1719 * Total Bit Error/Count is calculated as the sum of the
1720 * bit errors on all active layers.
1721 */
1722 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1723 c->pre_bit_error.stat[0].uvalue = t_pre_bit_error;
1724 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1725 c->pre_bit_count.stat[0].uvalue = t_pre_bit_count;
f67102c4
MCC		 1726 } else {
1727 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1728 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
149d518a
MCC		 1729 }
1730
d9b6f08a
MCC		 1731 /*
1732 * Start showing global count if at least one error count is
1733 * available.
1734 */
1735 if (post_ber_layers) {
1736 /*
1737 * At least one per-layer BER measure was read. We can now
1738 * calculate the total BER
1739 *
1740 * Total Bit Error/Count is calculated as the sum of the
1741 * bit errors on all active layers.
1742 */
1743 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1744 c->post_bit_error.stat[0].uvalue = t_post_bit_error;
1745 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1746 c->post_bit_count.stat[0].uvalue = t_post_bit_count;
f67102c4
MCC		 1747 } else {
1748 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1749 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
d9b6f08a
MCC		 1750 }
1751
593ae89a
MCC		 1752 if (per_layers) {
1753 /*
1754 * At least one per-layer UCB measure was read. We can now
1755 * calculate the total UCB
1756 *
1757 * Total block Error/Count is calculated as the sum of the
1758 * block errors on all active layers.
1759 */
1760 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
1761 c->block_error.stat[0].uvalue = t_block_error;
1762 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1763 c->block_count.stat[0].uvalue = t_block_count;
f67102c4
MCC		 1764 } else {
1765 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1766 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
593ae89a
MCC		 1767 }
1768
149d518a
MCC		 1769 return rc;
1770}
09b6d21e
MCC		 1771
1772/*
1773 * The functions below are called via DVB callbacks, so they need to
1774 * properly use the I2C gate control
1775 */
1776
dd4493ef
MCC		 1777static int mb86a20s_initfe(struct dvb_frontend *fe)
1778{
1779 struct mb86a20s_state *state = fe->demodulator_priv;
768e6dad 1780 u64 pll;
0e4bbedd 1781 u32 fclk;
dd4493ef 1782 int rc;
04fa725e 1783 u8 regD5 = 1, reg71, reg09 = 0x3a;
dd4493ef 1784
f66d81b5 1785 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
dd4493ef
MCC		 1786
1787 if (fe->ops.i2c_gate_ctrl)
1788 fe->ops.i2c_gate_ctrl(fe, 0);
1789
1790 /* Initialize the frontend */
768e6dad 1791 rc = mb86a20s_writeregdata(state, mb86a20s_init1);
dd4493ef
MCC		 1792 if (rc < 0)
1793 goto err;
1794
04fa725e
MCC		 1795 if (!state->inversion)
1796 reg09 |= 0x04;
1797 rc = mb86a20s_writereg(state, 0x09, reg09);
1798 if (rc < 0)
1799 goto err;
1800 if (!state->bw)
1801 reg71 = 1;
1802 else
1803 reg71 = 0;
1804 rc = mb86a20s_writereg(state, 0x39, reg71);
1805 if (rc < 0)
1806 goto err;
1807 rc = mb86a20s_writereg(state, 0x71, state->bw);
1808 if (rc < 0)
1809 goto err;
1810 if (state->subchannel) {
1811 rc = mb86a20s_writereg(state, 0x44, state->subchannel);
1812 if (rc < 0)
1813 goto err;
1814 }
1815
0e4bbedd
MCC		 1816 fclk = state->config->fclk;
1817 if (!fclk)
1818 fclk = 32571428;
1819
768e6dad
MCC		 1820 /* Adjust IF frequency to match tuner */
1821 if (fe->ops.tuner_ops.get_if_frequency)
1822 fe->ops.tuner_ops.get_if_frequency(fe, &state->if_freq);
1823
1824 if (!state->if_freq)
1825 state->if_freq = 3300000;
1826
0e4bbedd
MCC		 1827 pll = (((u64)1) << 34) * state->if_freq;
1828 do_div(pll, 63 * fclk);
1829 pll = (1 << 25) - pll;
1830 rc = mb86a20s_writereg(state, 0x28, 0x2a);
1831 if (rc < 0)
1832 goto err;
1833 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1834 if (rc < 0)
1835 goto err;
1836 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1837 if (rc < 0)
1838 goto err;
1839 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1840 if (rc < 0)
1841 goto err;
1842 dev_dbg(&state->i2c->dev, "%s: fclk=%d, IF=%d, clock reg=0x%06llx\n",
1843 __func__, fclk, state->if_freq, (long long)pll);
1844
768e6dad
MCC		 1845 /* pll = freq[Hz] * 2^24/10^6 / 16.285714286 */
1846 pll = state->if_freq * 1677721600L;
1847 do_div(pll, 1628571429L);
1848 rc = mb86a20s_writereg(state, 0x28, 0x20);
1849 if (rc < 0)
1850 goto err;
1851 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1852 if (rc < 0)
1853 goto err;
1854 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1855 if (rc < 0)
1856 goto err;
1857 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1858 if (rc < 0)
1859 goto err;
0e4bbedd 1860 dev_dbg(&state->i2c->dev, "%s: IF=%d, IF reg=0x%06llx\n",
768e6dad
MCC		 1861 __func__, state->if_freq, (long long)pll);
1862
dd4493ef
MCC		 1863 if (!state->config->is_serial) {
1864 regD5 &= ~1;
1865
1866 rc = mb86a20s_writereg(state, 0x50, 0xd5);
1867 if (rc < 0)
1868 goto err;
1869 rc = mb86a20s_writereg(state, 0x51, regD5);
1870 if (rc < 0)
1871 goto err;
1872 }
1873
768e6dad
MCC		 1874 rc = mb86a20s_writeregdata(state, mb86a20s_init2);
1875 if (rc < 0)
1876 goto err;
1877
1878
dd4493ef
MCC		 1879err:
1880 if (fe->ops.i2c_gate_ctrl)
1881 fe->ops.i2c_gate_ctrl(fe, 1);
1882
1883 if (rc < 0) {
1884 state->need_init = true;
f66d81b5
MCC		 1885 dev_info(&state->i2c->dev,
1886 "mb86a20s: Init failed. Will try again later\n");
dd4493ef
MCC		 1887 } else {
1888 state->need_init = false;
f66d81b5 1889 dev_dbg(&state->i2c->dev, "Initialization succeeded.\n");
dd4493ef
MCC		 1890 }
1891 return rc;
1892}
1893
1894static int mb86a20s_set_frontend(struct dvb_frontend *fe)
1895{
1896 struct mb86a20s_state *state = fe->demodulator_priv;
dd4493ef 1897 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
04fa725e 1898 int rc, if_freq;
f66d81b5 1899 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
dd4493ef 1900
04fa725e
MCC		 1901 if (!c->isdbt_layer_enabled)
1902 c->isdbt_layer_enabled = 7;
1903
1904 if (c->isdbt_layer_enabled == 1)
1905 state->bw = MB86A20S_1SEG;
1906 else if (c->isdbt_partial_reception)
1907 state->bw = MB86A20S_13SEG_PARTIAL;
1908 else
1909 state->bw = MB86A20S_13SEG;
1910
1911 if (c->inversion == INVERSION_ON)
1912 state->inversion = true;
1913 else
1914 state->inversion = false;
1915
1916 if (!c->isdbt_sb_mode) {
1917 state->subchannel = 0;
1918 } else {
41c6e9dd 1919 if (c->isdbt_sb_subchannel >= ARRAY_SIZE(mb86a20s_subchannel))
04fa725e
MCC		 1920 c->isdbt_sb_subchannel = 0;
1921
1922 state->subchannel = mb86a20s_subchannel[c->isdbt_sb_subchannel];
1923 }
1924
dd4493ef
MCC		 1925 /*
1926 * Gate should already be opened, but it doesn't hurt to
1927 * double-check
1928 */
1929 if (fe->ops.i2c_gate_ctrl)
1930 fe->ops.i2c_gate_ctrl(fe, 1);
dd4493ef
MCC		 1931 fe->ops.tuner_ops.set_params(fe);
1932
a78b41d5 1933 if (fe->ops.tuner_ops.get_if_frequency)
768e6dad
MCC		 1934 fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
1935
dd4493ef
MCC		 1936 /*
1937 * Make it more reliable: if, for some reason, the initial
1938 * device initialization doesn't happen, initialize it when
1939 * a SBTVD parameters are adjusted.
1940 *
1941 * Unfortunately, due to a hard to track bug at tda829x/tda18271,
1942 * the agc callback logic is not called during DVB attach time,
1943 * causing mb86a20s to not be initialized with Kworld SBTVD.
1944 * So, this hack is needed, in order to make Kworld SBTVD to work.
768e6dad
MCC		 1945 *
1946 * It is also needed to change the IF after the initial init.
a78b41d5
MCC		 1947 *
1948 * HACK: Always init the frontend when set_frontend is called:
1949 * it was noticed that, on some devices, it fails to lock on a
1950 * different channel. So, it is better to reset everything, even
1951 * wasting some time, than to loose channel lock.
dd4493ef 1952 */
a78b41d5 1953 mb86a20s_initfe(fe);
dd4493ef
MCC		 1954
1955 if (fe->ops.i2c_gate_ctrl)
1956 fe->ops.i2c_gate_ctrl(fe, 0);
d01a8ee3 1957
dd4493ef 1958 rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception);
09b6d21e 1959 mb86a20s_reset_counters(fe);
3a2e4751 1960 mb86a20s_stats_not_ready(fe);
d01a8ee3 1961
dd4493ef
MCC		 1962 if (fe->ops.i2c_gate_ctrl)
1963 fe->ops.i2c_gate_ctrl(fe, 1);
1964
1965 return rc;
1966}
1967
09b6d21e
MCC		 1968static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe,
1969 fe_status_t *status)
d36e418a 1970{
09b6d21e 1971 struct mb86a20s_state *state = fe->demodulator_priv;
15b1c5a0 1972 int rc, status_nr;
d36e418a 1973
09b6d21e 1974 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
d36e418a
MCC		 1975
1976 if (fe->ops.i2c_gate_ctrl)
1977 fe->ops.i2c_gate_ctrl(fe, 0);
1978
09b6d21e 1979 /* Get lock */
15b1c5a0
MCC		 1980 status_nr = mb86a20s_read_status(fe, status);
1981 if (status_nr < 7) {
09b6d21e
MCC		 1982 mb86a20s_stats_not_ready(fe);
1983 mb86a20s_reset_frontend_cache(fe);
1984 }
15b1c5a0 1985 if (status_nr < 0) {
149d518a
MCC		 1986 dev_err(&state->i2c->dev,
1987 "%s: Can't read frontend lock status\n", __func__);
09b6d21e 1988 goto error;
149d518a 1989 }
09b6d21e
MCC		 1990
1991 /* Get signal strength */
1992 rc = mb86a20s_read_signal_strength(fe);
1993 if (rc < 0) {
149d518a
MCC		 1994 dev_err(&state->i2c->dev,
1995 "%s: Can't reset VBER registers.\n", __func__);
09b6d21e
MCC		 1996 mb86a20s_stats_not_ready(fe);
1997 mb86a20s_reset_frontend_cache(fe);
149d518a
MCC		 1998
1999 rc = 0; /* Status is OK */
09b6d21e
MCC		 2000 goto error;
2001 }
09b6d21e 2002
15b1c5a0 2003 if (status_nr >= 7) {
09b6d21e
MCC		 2004 /* Get TMCC info*/
2005 rc = mb86a20s_get_frontend(fe);
149d518a
MCC		 2006 if (rc < 0) {
2007 dev_err(&state->i2c->dev,
2008 "%s: Can't get FE TMCC data.\n", __func__);
2009 rc = 0; /* Status is OK */
2010 goto error;
2011 }
2012
2013 /* Get statistics */
15b1c5a0 2014 rc = mb86a20s_get_stats(fe, status_nr);
149d518a
MCC		 2015 if (rc < 0 && rc != -EBUSY) {
2016 dev_err(&state->i2c->dev,
2017 "%s: Can't get FE statistics.\n", __func__);
2018 rc = 0;
09b6d21e 2019 goto error;
149d518a
MCC		 2020 }
2021 rc = 0; /* Don't return EBUSY to userspace */
09b6d21e 2022 }
149d518a 2023 goto ok;
09b6d21e 2024
149d518a 2025error:
09b6d21e 2026 mb86a20s_stats_not_ready(fe);
d36e418a 2027
149d518a 2028ok:
d36e418a
MCC		 2029 if (fe->ops.i2c_gate_ctrl)
2030 fe->ops.i2c_gate_ctrl(fe, 1);
149d518a 2031
09b6d21e
MCC		 2032 return rc;
2033}
2034
2035static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe,
2036 u16 *strength)
2037{
2038 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
2039
2040
2041 *strength = c->strength.stat[0].uvalue;
d36e418a 2042
09b6d21e 2043 return 0;
d36e418a
MCC		 2044}
2045
09b6d21e
MCC		 2046static int mb86a20s_get_frontend_dummy(struct dvb_frontend *fe)
2047{
2048 /*
2049 * get_frontend is now handled together with other stats
2050 * retrival, when read_status() is called, as some statistics
2051 * will depend on the layers detection.
2052 */
2053 return 0;
2054};
2055
b9ede79a 2056static int mb86a20s_tune(struct dvb_frontend *fe,
7e072221 2057 bool re_tune,
b9ede79a
MCC		 2058 unsigned int mode_flags,
2059 unsigned int *delay,
2060 fe_status_t *status)
2061{
f66d81b5 2062 struct mb86a20s_state *state = fe->demodulator_priv;
b9ede79a
MCC		 2063 int rc = 0;
2064
f66d81b5 2065 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
b9ede79a 2066
7e072221 2067 if (re_tune)
2d76e22b 2068 rc = mb86a20s_set_frontend(fe);
b9ede79a
MCC		 2069
2070 if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
09b6d21e 2071 mb86a20s_read_status_and_stats(fe, status);
b9ede79a
MCC		 2072
2073 return rc;
2074}
2075
2076static void mb86a20s_release(struct dvb_frontend *fe)
2077{
2078 struct mb86a20s_state *state = fe->demodulator_priv;
2079
f66d81b5 2080 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
b9ede79a
MCC		 2081
2082 kfree(state);
2083}
2084
2085static struct dvb_frontend_ops mb86a20s_ops;
2086
2087struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config,
2088 struct i2c_adapter *i2c)
2089{
f66d81b5 2090 struct mb86a20s_state *state;
b9ede79a
MCC		 2091 u8 rev;
2092
f167e302
MCC		 2093 dev_dbg(&i2c->dev, "%s called.\n", __func__);
2094
b9ede79a 2095 /* allocate memory for the internal state */
f66d81b5 2096 state = kzalloc(sizeof(struct mb86a20s_state), GFP_KERNEL);
b9ede79a 2097 if (state == NULL) {
f167e302 2098 dev_err(&i2c->dev,
f66d81b5 2099 "%s: unable to allocate memory for state\n", __func__);
b9ede79a
MCC		 2100 goto error;
2101 }
2102
2103 /* setup the state */
2104 state->config = config;
2105 state->i2c = i2c;
2106
2107 /* create dvb_frontend */
2108 memcpy(&state->frontend.ops, &mb86a20s_ops,
2109 sizeof(struct dvb_frontend_ops));
2110 state->frontend.demodulator_priv = state;
2111
2112 /* Check if it is a mb86a20s frontend */
2113 rev = mb86a20s_readreg(state, 0);
2114
2115 if (rev == 0x13) {
f167e302 2116 dev_info(&i2c->dev,
f66d81b5 2117 "Detected a Fujitsu mb86a20s frontend\n");
b9ede79a 2118 } else {
f167e302 2119 dev_dbg(&i2c->dev,
f66d81b5 2120 "Frontend revision %d is unknown - aborting.\n",
b9ede79a
MCC		 2121 rev);
2122 goto error;
2123 }
2124
2125 return &state->frontend;
2126
2127error:
2128 kfree(state);
2129 return NULL;
2130}
2131EXPORT_SYMBOL(mb86a20s_attach);
2132
2133static struct dvb_frontend_ops mb86a20s_ops = {
2d76e22b 2134 .delsys = { SYS_ISDBT },
b9ede79a
MCC		 2135 /* Use dib8000 values per default */
2136 .info = {
2137 .name = "Fujitsu mb86A20s",
04fa725e 2138 .caps = FE_CAN_RECOVER |
b9ede79a
MCC		 2139 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
2140 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
2141 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2142 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO |
2143 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
2144 /* Actually, those values depend on the used tuner */
2145 .frequency_min = 45000000,
2146 .frequency_max = 864000000,
2147 .frequency_stepsize = 62500,
2148 },
2149
2150 .release = mb86a20s_release,
2151
2152 .init = mb86a20s_initfe,
2d76e22b 2153 .set_frontend = mb86a20s_set_frontend,
09b6d21e
MCC		 2154 .get_frontend = mb86a20s_get_frontend_dummy,
2155 .read_status = mb86a20s_read_status_and_stats,
2156 .read_signal_strength = mb86a20s_read_signal_strength_from_cache,
b9ede79a
MCC		 2157 .tune = mb86a20s_tune,
2158};
2159
2160MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware");
2161MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
2162MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)