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[media] mb86a20s: Implement set_frontend cache logic
[linux-2.6-block.git] / drivers / media / dvb-frontends / mb86a20s.c
CommitLineData
b9ede79a
MCC		 1/*
2 * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver
3 *
a77cfcac 4 * Copyright (C) 2010-2013 Mauro Carvalho Chehab <mchehab@redhat.com>
b9ede79a
MCC		 5 * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com>
6 *
b9ede79a
MCC		 7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 */
16
17#include <linux/kernel.h>
18#include <asm/div64.h>
19
20#include "dvb_frontend.h"
21#include "mb86a20s.h"
22
23static int debug = 1;
24module_param(debug, int, 0644);
25MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
26
04fa725e
MCC		 27enum mb86a20s_bandwidth {
28 MB86A20S_13SEG = 0,
29 MB86A20S_13SEG_PARTIAL = 1,
30 MB86A20S_1SEG = 2,
31 MB86A20S_3SEG = 3,
32};
33
34u8 mb86a20s_subchannel[] = {
35 0xb0, 0xc0, 0xd0, 0xe0,
36 0xf0, 0x00, 0x10, 0x20,
37};
38
b9ede79a
MCC		 39struct mb86a20s_state {
40 struct i2c_adapter *i2c;
41 const struct mb86a20s_config *config;
09b6d21e 42 u32 last_frequency;
b9ede79a
MCC		 43
44 struct dvb_frontend frontend;
c736a5f2 45
768e6dad 46 u32 if_freq;
04fa725e
MCC		 47 enum mb86a20s_bandwidth bw;
48 bool inversion;
49 u32 subchannel;
768e6dad 50
d01a8ee3 51 u32 estimated_rate[3];
0921ecfd 52 unsigned long get_strength_time;
d01a8ee3 53
c736a5f2 54 bool need_init;
b9ede79a
MCC		 55};
56
57struct regdata {
58 u8 reg;
59 u8 data;
60};
61
d01a8ee3
MCC		 62#define BER_SAMPLING_RATE 1 /* Seconds */
63
b9ede79a
MCC		 64/*
65 * Initialization sequence: Use whatevere default values that PV SBTVD
66 * does on its initialisation, obtained via USB snoop
67 */
768e6dad 68static struct regdata mb86a20s_init1[] = {
b9ede79a
MCC		 69 { 0x70, 0x0f },
70 { 0x70, 0xff },
71 { 0x08, 0x01 },
17e67d4c 72 { 0x50, 0xd1 }, { 0x51, 0x20 },
a7025edf 73 { 0x28, 0x2a }, { 0x29, 0x00 }, { 0x2a, 0xff }, { 0x2b, 0x80 },
768e6dad
MCC		 74};
75
76static struct regdata mb86a20s_init2[] = {
ebe96749 77 { 0x28, 0x22 }, { 0x29, 0x00 }, { 0x2a, 0x1f }, { 0x2b, 0xf0 },
b9ede79a 78 { 0x3b, 0x21 },
17e67d4c 79 { 0x3c, 0x38 },
b9ede79a 80 { 0x01, 0x0d },
17e67d4c 81 { 0x04, 0x08 }, { 0x05, 0x03 },
a7025edf 82 { 0x04, 0x0e }, { 0x05, 0x00 },
17e67d4c
MCC		 83 { 0x04, 0x0f }, { 0x05, 0x37 },
84 { 0x04, 0x0b }, { 0x05, 0x78 },
a7025edf 85 { 0x04, 0x00 }, { 0x05, 0x00 },
17e67d4c
MCC		 86 { 0x04, 0x01 }, { 0x05, 0x1e },
87 { 0x04, 0x02 }, { 0x05, 0x07 },
88 { 0x04, 0x03 }, { 0x05, 0xd0 },
a7025edf
MCC		 89 { 0x04, 0x09 }, { 0x05, 0x00 },
90 { 0x04, 0x0a }, { 0x05, 0xff },
17e67d4c 91 { 0x04, 0x27 }, { 0x05, 0x00 },
a7025edf 92 { 0x04, 0x28 }, { 0x05, 0x00 },
17e67d4c
MCC		 93 { 0x04, 0x1e }, { 0x05, 0x00 },
94 { 0x04, 0x29 }, { 0x05, 0x64 },
95 { 0x04, 0x32 }, { 0x05, 0x02 },
a7025edf
MCC		 96 { 0x04, 0x14 }, { 0x05, 0x02 },
97 { 0x04, 0x04 }, { 0x05, 0x00 },
98 { 0x04, 0x05 }, { 0x05, 0x22 },
99 { 0x04, 0x06 }, { 0x05, 0x0e },
100 { 0x04, 0x07 }, { 0x05, 0xd8 },
101 { 0x04, 0x12 }, { 0x05, 0x00 },
102 { 0x04, 0x13 }, { 0x05, 0xff },
ebe96749
MCC		 103 { 0x04, 0x15 }, { 0x05, 0x4e },
104 { 0x04, 0x16 }, { 0x05, 0x20 },
09b6d21e
MCC		 105
106 /*
107 * On this demod, when the bit count reaches the count below,
108 * it collects the bit error count. The bit counters are initialized
109 * to 65535 here. This warrants that all of them will be quickly
110 * calculated when device gets locked. As TMCC is parsed, the values
d01a8ee3 111 * will be adjusted later in the driver's code.
09b6d21e
MCC		 112 */
113 { 0x52, 0x01 }, /* Turn on BER before Viterbi */
114 { 0x50, 0xa7 }, { 0x51, 0x00 },
a7025edf
MCC		 115 { 0x50, 0xa8 }, { 0x51, 0xff },
116 { 0x50, 0xa9 }, { 0x51, 0xff },
09b6d21e 117 { 0x50, 0xaa }, { 0x51, 0x00 },
a7025edf
MCC		 118 { 0x50, 0xab }, { 0x51, 0xff },
119 { 0x50, 0xac }, { 0x51, 0xff },
09b6d21e 120 { 0x50, 0xad }, { 0x51, 0x00 },
a7025edf
MCC		 121 { 0x50, 0xae }, { 0x51, 0xff },
122 { 0x50, 0xaf }, { 0x51, 0xff },
09b6d21e 123
d9b6f08a
MCC		 124 /*
125 * On this demod, post BER counts blocks. When the count reaches the
126 * value below, it collects the block error count. The block counters
127 * are initialized to 127 here. This warrants that all of them will be
128 * quickly calculated when device gets locked. As TMCC is parsed, the
129 * values will be adjusted later in the driver's code.
130 */
131 { 0x5e, 0x07 }, /* Turn on BER after Viterbi */
132 { 0x50, 0xdc }, { 0x51, 0x00 },
133 { 0x50, 0xdd }, { 0x51, 0x7f },
134 { 0x50, 0xde }, { 0x51, 0x00 },
135 { 0x50, 0xdf }, { 0x51, 0x7f },
136 { 0x50, 0xe0 }, { 0x51, 0x00 },
137 { 0x50, 0xe1 }, { 0x51, 0x7f },
593ae89a
MCC		 138
139 /*
140 * On this demod, when the block count reaches the count below,
141 * it collects the block error count. The block counters are initialized
142 * to 127 here. This warrants that all of them will be quickly
143 * calculated when device gets locked. As TMCC is parsed, the values
144 * will be adjusted later in the driver's code.
145 */
146 { 0x50, 0xb0 }, { 0x51, 0x07 }, /* Enable PER */
147 { 0x50, 0xb2 }, { 0x51, 0x00 },
148 { 0x50, 0xb3 }, { 0x51, 0x7f },
149 { 0x50, 0xb4 }, { 0x51, 0x00 },
150 { 0x50, 0xb5 }, { 0x51, 0x7f },
151 { 0x50, 0xb6 }, { 0x51, 0x00 },
152 { 0x50, 0xb7 }, { 0x51, 0x7f },
25188bd0
MCC		 153
154 { 0x50, 0x50 }, { 0x51, 0x02 }, /* MER manual mode */
09b6d21e
MCC		 155 { 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */
156 { 0x45, 0x04 }, /* CN symbol 4 */
25188bd0
MCC		 157 { 0x48, 0x04 }, /* CN manual mode */
158
a7025edf
MCC		 159 { 0x50, 0xd5 }, { 0x51, 0x01 }, /* Serial */
160 { 0x50, 0xd6 }, { 0x51, 0x1f },
161 { 0x50, 0xd2 }, { 0x51, 0x03 },
17e67d4c
MCC		 162 { 0x50, 0xd7 }, { 0x51, 0xbf },
163 { 0x28, 0x74 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0xff },
164 { 0x28, 0x46 }, { 0x29, 0x00 }, { 0x2a, 0x1a }, { 0x2b, 0x0c },
ce77d120
MCC		 165
166 { 0x04, 0x40 }, { 0x05, 0x00 },
17e67d4c
MCC		 167 { 0x28, 0x00 }, { 0x2b, 0x08 },
168 { 0x28, 0x05 }, { 0x2b, 0x00 },
b9ede79a 169 { 0x1c, 0x01 },
17e67d4c
MCC		 170 { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x1f },
171 { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x18 },
172 { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x12 },
173 { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x30 },
174 { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x37 },
175 { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 },
176 { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x09 },
177 { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x06 },
178 { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x7b },
179 { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x76 },
180 { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x7d },
181 { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x08 },
182 { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0b },
183 { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 },
184 { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xf2 },
185 { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xf3 },
186 { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x05 },
187 { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 },
188 { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f },
189 { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xef },
190 { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xd8 },
191 { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xf1 },
192 { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x3d },
193 { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x94 },
194 { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0xba },
a7025edf
MCC		 195 { 0x50, 0x1e }, { 0x51, 0x5d },
196 { 0x50, 0x22 }, { 0x51, 0x00 },
197 { 0x50, 0x23 }, { 0x51, 0xc8 },
198 { 0x50, 0x24 }, { 0x51, 0x00 },
199 { 0x50, 0x25 }, { 0x51, 0xf0 },
200 { 0x50, 0x26 }, { 0x51, 0x00 },
201 { 0x50, 0x27 }, { 0x51, 0xc3 },
202 { 0x50, 0x39 }, { 0x51, 0x02 },
17e67d4c
MCC		 203 { 0xec, 0x0f },
204 { 0xeb, 0x1f },
ebe96749 205 { 0x28, 0x6a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 },
b9ede79a
MCC		 206 { 0xd0, 0x00 },
207};
208
209static struct regdata mb86a20s_reset_reception[] = {
210 { 0x70, 0xf0 },
211 { 0x70, 0xff },
212 { 0x08, 0x01 },
213 { 0x08, 0x00 },
214};
215
d9b6f08a
MCC		 216static struct regdata mb86a20s_per_ber_reset[] = {
217 { 0x53, 0x00 }, /* pre BER Counter reset */
09b6d21e 218 { 0x53, 0x07 },
09b6d21e 219
d9b6f08a
MCC		 220 { 0x5f, 0x00 }, /* post BER Counter reset */
221 { 0x5f, 0x07 },
222
09b6d21e
MCC		 223 { 0x50, 0xb1 }, /* PER Counter reset */
224 { 0x51, 0x07 },
225 { 0x51, 0x00 },
226};
227
dd4493ef
MCC		 228/*
229 * I2C read/write functions and macros
230 */
231
b9ede79a 232static int mb86a20s_i2c_writereg(struct mb86a20s_state *state,
09b6d21e 233 u8 i2c_addr, u8 reg, u8 data)
b9ede79a
MCC		 234{
235 u8 buf[] = { reg, data };
236 struct i2c_msg msg = {
237 .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
238 };
239 int rc;
240
241 rc = i2c_transfer(state->i2c, &msg, 1);
242 if (rc != 1) {
f66d81b5
MCC		 243 dev_err(&state->i2c->dev,
244 "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n",
245 __func__, rc, reg, data);
b9ede79a
MCC		 246 return rc;
247 }
248
249 return 0;
250}
251
252static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state,
253 u8 i2c_addr, struct regdata *rd, int size)
254{
255 int i, rc;
256
257 for (i = 0; i < size; i++) {
258 rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg,
259 rd[i].data);
260 if (rc < 0)
261 return rc;
262 }
263 return 0;
264}
265
266static int mb86a20s_i2c_readreg(struct mb86a20s_state *state,
267 u8 i2c_addr, u8 reg)
268{
269 u8 val;
270 int rc;
271 struct i2c_msg msg[] = {
272 { .addr = i2c_addr, .flags = 0, .buf = &reg, .len = 1 },
273 { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 }
274 };
275
276 rc = i2c_transfer(state->i2c, msg, 2);
277
278 if (rc != 2) {
f66d81b5
MCC		 279 dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n",
280 __func__, reg, rc);
281 return (rc < 0) ? rc : -EIO;
b9ede79a
MCC		 282 }
283
284 return val;
285}
286
287#define mb86a20s_readreg(state, reg) \
288 mb86a20s_i2c_readreg(state, state->config->demod_address, reg)
289#define mb86a20s_writereg(state, reg, val) \
290 mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val)
291#define mb86a20s_writeregdata(state, regdata) \
292 mb86a20s_i2c_writeregdata(state, state->config->demod_address, \
293 regdata, ARRAY_SIZE(regdata))
294
09b6d21e
MCC		 295/*
296 * Ancillary internal routines (likely compiled inlined)
297 *
298 * The functions below assume that gateway lock has already obtained
299 */
300
dd4493ef 301static int mb86a20s_read_status(struct dvb_frontend *fe, fe_status_t *status)
b9ede79a
MCC		 302{
303 struct mb86a20s_state *state = fe->demodulator_priv;
dd4493ef 304 int val;
b9ede79a 305
dd4493ef 306 *status = 0;
b9ede79a 307
dd4493ef
MCC		 308 val = mb86a20s_readreg(state, 0x0a) & 0xf;
309 if (val < 0)
310 return val;
68541cda 311
dd4493ef
MCC		 312 if (val >= 2)
313 *status |= FE_HAS_SIGNAL;
b9ede79a 314
dd4493ef
MCC		 315 if (val >= 4)
316 *status |= FE_HAS_CARRIER;
7572f9c5 317
dd4493ef
MCC		 318 if (val >= 5)
319 *status |= FE_HAS_VITERBI;
7572f9c5 320
dd4493ef
MCC		 321 if (val >= 7)
322 *status |= FE_HAS_SYNC;
68541cda 323
dd4493ef
MCC		 324 if (val >= 8) /* Maybe 9? */
325 *status |= FE_HAS_LOCK;
326
f66d81b5
MCC		 327 dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n",
328 __func__, *status, val);
dd4493ef 329
15b1c5a0 330 return val;
b9ede79a
MCC		 331}
332
09b6d21e 333static int mb86a20s_read_signal_strength(struct dvb_frontend *fe)
b9ede79a
MCC		 334{
335 struct mb86a20s_state *state = fe->demodulator_priv;
0921ecfd 336 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
09b6d21e 337 int rc;
b9ede79a 338 unsigned rf_max, rf_min, rf;
68541cda 339
0921ecfd
MCC		 340 if (state->get_strength_time &&
341 (!time_after(jiffies, state->get_strength_time)))
342 return c->strength.stat[0].uvalue;
343
344 /* Reset its value if an error happen */
345 c->strength.stat[0].uvalue = 0;
346
b9ede79a
MCC		 347 /* Does a binary search to get RF strength */
348 rf_max = 0xfff;
349 rf_min = 0;
350 do {
351 rf = (rf_max + rf_min) / 2;
09b6d21e
MCC		 352 rc = mb86a20s_writereg(state, 0x04, 0x1f);
353 if (rc < 0)
354 return rc;
355 rc = mb86a20s_writereg(state, 0x05, rf >> 8);
356 if (rc < 0)
357 return rc;
358 rc = mb86a20s_writereg(state, 0x04, 0x20);
359 if (rc < 0)
360 return rc;
dad78c56 361 rc = mb86a20s_writereg(state, 0x05, rf);
09b6d21e
MCC		 362 if (rc < 0)
363 return rc;
b9ede79a 364
09b6d21e
MCC		 365 rc = mb86a20s_readreg(state, 0x02);
366 if (rc < 0)
367 return rc;
368 if (rc & 0x08)
b9ede79a
MCC		 369 rf_min = (rf_max + rf_min) / 2;
370 else
371 rf_max = (rf_max + rf_min) / 2;
372 if (rf_max - rf_min < 4) {
09b6d21e
MCC		 373 rf = (rf_max + rf_min) / 2;
374
375 /* Rescale it from 2^12 (4096) to 2^16 */
0921ecfd
MCC		 376 rf = rf << (16 - 12);
377 if (rf)
378 rf |= (1 << 12) - 1;
379
f66d81b5
MCC		 380 dev_dbg(&state->i2c->dev,
381 "%s: signal strength = %d (%d < RF=%d < %d)\n",
382 __func__, rf, rf_min, rf >> 4, rf_max);
0921ecfd
MCC		 383 c->strength.stat[0].uvalue = rf;
384 state->get_strength_time = jiffies +
385 msecs_to_jiffies(1000);
386 return 0;
b9ede79a
MCC		 387 }
388 } while (1);
b9ede79a
MCC		 389}
390
959a119f
MCC		 391static int mb86a20s_get_modulation(struct mb86a20s_state *state,
392 unsigned layer)
393{
394 int rc;
395 static unsigned char reg[] = {
396 [0] = 0x86, /* Layer A */
397 [1] = 0x8a, /* Layer B */
398 [2] = 0x8e, /* Layer C */
399 };
400
82033bc5 401 if (layer >= ARRAY_SIZE(reg))
959a119f
MCC		 402 return -EINVAL;
403 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
404 if (rc < 0)
405 return rc;
406 rc = mb86a20s_readreg(state, 0x6e);
407 if (rc < 0)
408 return rc;
04585921 409 switch ((rc >> 4) & 0x07) {
959a119f
MCC		 410 case 0:
411 return DQPSK;
412 case 1:
413 return QPSK;
414 case 2:
415 return QAM_16;
416 case 3:
417 return QAM_64;
418 default:
419 return QAM_AUTO;
420 }
421}
422
423static int mb86a20s_get_fec(struct mb86a20s_state *state,
424 unsigned layer)
425{
426 int rc;
427
428 static unsigned char reg[] = {
429 [0] = 0x87, /* Layer A */
430 [1] = 0x8b, /* Layer B */
431 [2] = 0x8f, /* Layer C */
432 };
433
82033bc5 434 if (layer >= ARRAY_SIZE(reg))
959a119f
MCC		 435 return -EINVAL;
436 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
437 if (rc < 0)
438 return rc;
439 rc = mb86a20s_readreg(state, 0x6e);
440 if (rc < 0)
441 return rc;
04585921 442 switch ((rc >> 4) & 0x07) {
959a119f
MCC		 443 case 0:
444 return FEC_1_2;
445 case 1:
446 return FEC_2_3;
447 case 2:
448 return FEC_3_4;
449 case 3:
450 return FEC_5_6;
451 case 4:
452 return FEC_7_8;
453 default:
454 return FEC_AUTO;
455 }
456}
457
458static int mb86a20s_get_interleaving(struct mb86a20s_state *state,
459 unsigned layer)
460{
461 int rc;
462
463 static unsigned char reg[] = {
464 [0] = 0x88, /* Layer A */
465 [1] = 0x8c, /* Layer B */
466 [2] = 0x90, /* Layer C */
467 };
468
82033bc5 469 if (layer >= ARRAY_SIZE(reg))
959a119f
MCC		 470 return -EINVAL;
471 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
472 if (rc < 0)
473 return rc;
474 rc = mb86a20s_readreg(state, 0x6e);
475 if (rc < 0)
476 return rc;
04585921
MCC		 477
478 switch ((rc >> 4) & 0x07) {
479 case 1:
480 return GUARD_INTERVAL_1_4;
481 case 2:
482 return GUARD_INTERVAL_1_8;
483 case 3:
484 return GUARD_INTERVAL_1_16;
485 case 4:
486 return GUARD_INTERVAL_1_32;
487
488 default:
489 case 0:
490 return GUARD_INTERVAL_AUTO;
491 }
959a119f
MCC		 492}
493
494static int mb86a20s_get_segment_count(struct mb86a20s_state *state,
495 unsigned layer)
496{
497 int rc, count;
959a119f
MCC		 498 static unsigned char reg[] = {
499 [0] = 0x89, /* Layer A */
500 [1] = 0x8d, /* Layer B */
501 [2] = 0x91, /* Layer C */
502 };
503
f66d81b5
MCC		 504 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
505
82033bc5 506 if (layer >= ARRAY_SIZE(reg))
959a119f 507 return -EINVAL;
f66d81b5 508
959a119f
MCC		 509 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
510 if (rc < 0)
511 return rc;
512 rc = mb86a20s_readreg(state, 0x6e);
513 if (rc < 0)
514 return rc;
515 count = (rc >> 4) & 0x0f;
516
f66d81b5
MCC		 517 dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count);
518
959a119f
MCC		 519 return count;
520}
521
a77cfcac
MCC		 522static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe)
523{
f66d81b5 524 struct mb86a20s_state *state = fe->demodulator_priv;
a77cfcac
MCC		 525 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
526
f66d81b5
MCC		 527 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
528
a77cfcac
MCC		 529 /* Fixed parameters */
530 c->delivery_system = SYS_ISDBT;
531 c->bandwidth_hz = 6000000;
532
533 /* Initialize values that will be later autodetected */
534 c->isdbt_layer_enabled = 0;
535 c->transmission_mode = TRANSMISSION_MODE_AUTO;
536 c->guard_interval = GUARD_INTERVAL_AUTO;
537 c->isdbt_sb_mode = 0;
538 c->isdbt_sb_segment_count = 0;
539}
540
d01a8ee3
MCC		 541/*
542 * Estimates the bit rate using the per-segment bit rate given by
543 * ABNT/NBR 15601 spec (table 4).
544 */
545static u32 isdbt_rate[3][5][4] = {
546 { /* DQPSK/QPSK */
547 { 280850, 312060, 330420, 340430 }, /* 1/2 */
548 { 374470, 416080, 440560, 453910 }, /* 2/3 */
549 { 421280, 468090, 495630, 510650 }, /* 3/4 */
550 { 468090, 520100, 550700, 567390 }, /* 5/6 */
551 { 491500, 546110, 578230, 595760 }, /* 7/8 */
552 }, { /* QAM16 */
553 { 561710, 624130, 660840, 680870 }, /* 1/2 */
554 { 748950, 832170, 881120, 907820 }, /* 2/3 */
555 { 842570, 936190, 991260, 1021300 }, /* 3/4 */
556 { 936190, 1040210, 1101400, 1134780 }, /* 5/6 */
557 { 983000, 1092220, 1156470, 1191520 }, /* 7/8 */
558 }, { /* QAM64 */
559 { 842570, 936190, 991260, 1021300 }, /* 1/2 */
560 { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */
561 { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */
562 { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */
563 { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */
564 }
565};
566
567static void mb86a20s_layer_bitrate(struct dvb_frontend *fe, u32 layer,
568 u32 modulation, u32 fec, u32 interleaving,
569 u32 segment)
570{
571 struct mb86a20s_state *state = fe->demodulator_priv;
572 u32 rate;
573 int m, f, i;
574
575 /*
576 * If modulation/fec/interleaving is not detected, the default is
577 * to consider the lowest bit rate, to avoid taking too long time
578 * to get BER.
579 */
580 switch (modulation) {
581 case DQPSK:
582 case QPSK:
583 default:
584 m = 0;
585 break;
586 case QAM_16:
587 m = 1;
588 break;
589 case QAM_64:
590 m = 2;
591 break;
592 }
593
594 switch (fec) {
595 default:
596 case FEC_1_2:
597 case FEC_AUTO:
598 f = 0;
599 break;
600 case FEC_2_3:
601 f = 1;
602 break;
603 case FEC_3_4:
604 f = 2;
605 break;
606 case FEC_5_6:
607 f = 3;
608 break;
609 case FEC_7_8:
610 f = 4;
611 break;
612 }
613
614 switch (interleaving) {
615 default:
616 case GUARD_INTERVAL_1_4:
617 i = 0;
618 break;
619 case GUARD_INTERVAL_1_8:
620 i = 1;
621 break;
622 case GUARD_INTERVAL_1_16:
623 i = 2;
624 break;
625 case GUARD_INTERVAL_1_32:
626 i = 3;
627 break;
628 }
629
630 /* Samples BER at BER_SAMPLING_RATE seconds */
631 rate = isdbt_rate[m][f][i] * segment * BER_SAMPLING_RATE;
632
633 /* Avoids sampling too quickly or to overflow the register */
634 if (rate < 256)
635 rate = 256;
636 else if (rate > (1 << 24) - 1)
637 rate = (1 << 24) - 1;
638
639 dev_dbg(&state->i2c->dev,
640 "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n",
641 __func__, 'A' + layer, segment * isdbt_rate[m][f][i]/1000,
642 rate, rate);
643
644 state->estimated_rate[i] = rate;
645}
646
647
7c61d80a 648static int mb86a20s_get_frontend(struct dvb_frontend *fe)
b9ede79a 649{
959a119f 650 struct mb86a20s_state *state = fe->demodulator_priv;
a77cfcac 651 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
959a119f 652 int i, rc;
b9ede79a 653
f66d81b5
MCC		 654 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
655
a77cfcac
MCC		 656 /* Reset frontend cache to default values */
657 mb86a20s_reset_frontend_cache(fe);
959a119f 658
959a119f
MCC		 659 /* Check for partial reception */
660 rc = mb86a20s_writereg(state, 0x6d, 0x85);
a77cfcac
MCC		 661 if (rc < 0)
662 return rc;
663 rc = mb86a20s_readreg(state, 0x6e);
664 if (rc < 0)
665 return rc;
666 c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0;
959a119f
MCC		 667
668 /* Get per-layer data */
a77cfcac 669
959a119f 670 for (i = 0; i < 3; i++) {
f66d81b5
MCC		 671 dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n",
672 __func__, 'A' + i);
673
959a119f 674 rc = mb86a20s_get_segment_count(state, i);
a77cfcac 675 if (rc < 0)
f66d81b5 676 goto noperlayer_error;
d01a8ee3 677 if (rc >= 0 && rc < 14) {
a77cfcac 678 c->layer[i].segment_count = rc;
d01a8ee3 679 } else {
a77cfcac 680 c->layer[i].segment_count = 0;
d01a8ee3 681 state->estimated_rate[i] = 0;
959a119f 682 continue;
a77cfcac
MCC		 683 }
684 c->isdbt_layer_enabled |= 1 << i;
959a119f 685 rc = mb86a20s_get_modulation(state, i);
a77cfcac 686 if (rc < 0)
f66d81b5
MCC		 687 goto noperlayer_error;
688 dev_dbg(&state->i2c->dev, "%s: modulation %d.\n",
689 __func__, rc);
a77cfcac 690 c->layer[i].modulation = rc;
959a119f 691 rc = mb86a20s_get_fec(state, i);
a77cfcac 692 if (rc < 0)
f66d81b5
MCC		 693 goto noperlayer_error;
694 dev_dbg(&state->i2c->dev, "%s: FEC %d.\n",
695 __func__, rc);
a77cfcac 696 c->layer[i].fec = rc;
959a119f 697 rc = mb86a20s_get_interleaving(state, i);
a77cfcac 698 if (rc < 0)
f66d81b5
MCC		 699 goto noperlayer_error;
700 dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n",
701 __func__, rc);
a77cfcac 702 c->layer[i].interleaving = rc;
d01a8ee3
MCC		 703 mb86a20s_layer_bitrate(fe, i, c->layer[i].modulation,
704 c->layer[i].fec,
705 c->layer[i].interleaving,
706 c->layer[i].segment_count);
959a119f
MCC		 707 }
708
959a119f 709 rc = mb86a20s_writereg(state, 0x6d, 0x84);
a77cfcac
MCC		 710 if (rc < 0)
711 return rc;
712 if ((rc & 0x60) == 0x20) {
713 c->isdbt_sb_mode = 1;
959a119f 714 /* At least, one segment should exist */
a77cfcac
MCC		 715 if (!c->isdbt_sb_segment_count)
716 c->isdbt_sb_segment_count = 1;
717 }
959a119f
MCC		 718
719 /* Get transmission mode and guard interval */
959a119f 720 rc = mb86a20s_readreg(state, 0x07);
a77cfcac
MCC		 721 if (rc < 0)
722 return rc;
723 if ((rc & 0x60) == 0x20) {
724 switch (rc & 0x0c >> 2) {
725 case 0:
726 c->transmission_mode = TRANSMISSION_MODE_2K;
727 break;
728 case 1:
729 c->transmission_mode = TRANSMISSION_MODE_4K;
730 break;
731 case 2:
732 c->transmission_mode = TRANSMISSION_MODE_8K;
733 break;
959a119f 734 }
a77cfcac
MCC		 735 }
736 if (!(rc & 0x10)) {
737 switch (rc & 0x3) {
738 case 0:
739 c->guard_interval = GUARD_INTERVAL_1_4;
740 break;
741 case 1:
742 c->guard_interval = GUARD_INTERVAL_1_8;
743 break;
744 case 2:
745 c->guard_interval = GUARD_INTERVAL_1_16;
746 break;
959a119f
MCC		 747 }
748 }
09b6d21e 749 return 0;
959a119f 750
f66d81b5 751noperlayer_error:
b9ede79a 752
09b6d21e
MCC		 753 /* per-layer info is incomplete; discard all per-layer */
754 c->isdbt_layer_enabled = 0;
755
756 return rc;
757}
758
759static int mb86a20s_reset_counters(struct dvb_frontend *fe)
760{
761 struct mb86a20s_state *state = fe->demodulator_priv;
762 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
763 int rc, val;
764
765 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
766
767 /* Reset the counters, if the channel changed */
768 if (state->last_frequency != c->frequency) {
09b6d21e
MCC		 769 memset(&c->cnr, 0, sizeof(c->cnr));
770 memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error));
771 memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count));
d9b6f08a
MCC		 772 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
773 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
09b6d21e
MCC		 774 memset(&c->block_error, 0, sizeof(c->block_error));
775 memset(&c->block_count, 0, sizeof(c->block_count));
776
777 state->last_frequency = c->frequency;
778 }
779
780 /* Clear status for most stats */
781
d9b6f08a
MCC		 782 /* BER/PER counter reset */
783 rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset);
09b6d21e
MCC		 784 if (rc < 0)
785 goto err;
786
787 /* CNR counter reset */
788 rc = mb86a20s_readreg(state, 0x45);
789 if (rc < 0)
790 goto err;
791 val = rc;
792 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
793 if (rc < 0)
794 goto err;
795 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
796 if (rc < 0)
797 goto err;
798
799 /* MER counter reset */
800 rc = mb86a20s_writereg(state, 0x50, 0x50);
801 if (rc < 0)
802 goto err;
803 rc = mb86a20s_readreg(state, 0x51);
804 if (rc < 0)
805 goto err;
806 val = rc;
807 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
808 if (rc < 0)
809 goto err;
810 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
811 if (rc < 0)
812 goto err;
813
149d518a 814 goto ok;
09b6d21e 815err:
149d518a
MCC		 816 dev_err(&state->i2c->dev,
817 "%s: Can't reset FE statistics (error %d).\n",
818 __func__, rc);
819ok:
a77cfcac 820 return rc;
09b6d21e
MCC		 821}
822
ad0abbf1
MCC		 823static int mb86a20s_get_pre_ber(struct dvb_frontend *fe,
824 unsigned layer,
825 u32 *error, u32 *count)
149d518a
MCC		 826{
827 struct mb86a20s_state *state = fe->demodulator_priv;
ad0abbf1 828 int rc, val;
149d518a
MCC		 829
830 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
831
832 if (layer >= 3)
833 return -EINVAL;
834
835 /* Check if the BER measures are already available */
836 rc = mb86a20s_readreg(state, 0x54);
837 if (rc < 0)
838 return rc;
839
840 /* Check if data is available for that layer */
841 if (!(rc & (1 << layer))) {
842 dev_dbg(&state->i2c->dev,
ad0abbf1 843 "%s: preBER for layer %c is not available yet.\n",
149d518a
MCC		 844 __func__, 'A' + layer);
845 return -EBUSY;
846 }
847
848 /* Read Bit Error Count */
849 rc = mb86a20s_readreg(state, 0x55 + layer * 3);
850 if (rc < 0)
851 return rc;
852 *error = rc << 16;
853 rc = mb86a20s_readreg(state, 0x56 + layer * 3);
854 if (rc < 0)
855 return rc;
856 *error |= rc << 8;
857 rc = mb86a20s_readreg(state, 0x57 + layer * 3);
858 if (rc < 0)
859 return rc;
860 *error |= rc;
861
862 dev_dbg(&state->i2c->dev,
863 "%s: bit error before Viterbi for layer %c: %d.\n",
864 __func__, 'A' + layer, *error);
865
866 /* Read Bit Count */
867 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
868 if (rc < 0)
869 return rc;
870 rc = mb86a20s_readreg(state, 0x51);
871 if (rc < 0)
872 return rc;
873 *count = rc << 16;
874 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
875 if (rc < 0)
876 return rc;
877 rc = mb86a20s_readreg(state, 0x51);
878 if (rc < 0)
879 return rc;
880 *count |= rc << 8;
881 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
882 if (rc < 0)
883 return rc;
884 rc = mb86a20s_readreg(state, 0x51);
885 if (rc < 0)
886 return rc;
887 *count |= rc;
888
889 dev_dbg(&state->i2c->dev,
890 "%s: bit count before Viterbi for layer %c: %d.\n",
891 __func__, 'A' + layer, *count);
892
893
d01a8ee3
MCC		 894 /*
895 * As we get TMCC data from the frontend, we can better estimate the
896 * BER bit counters, in order to do the BER measure during a longer
897 * time. Use those data, if available, to update the bit count
898 * measure.
899 */
900
901 if (state->estimated_rate[layer]
902 && state->estimated_rate[layer] != *count) {
903 dev_dbg(&state->i2c->dev,
ad0abbf1 904 "%s: updating layer %c preBER counter to %d.\n",
d01a8ee3 905 __func__, 'A' + layer, state->estimated_rate[layer]);
ad0abbf1
MCC		 906
907 /* Turn off BER before Viterbi */
908 rc = mb86a20s_writereg(state, 0x52, 0x00);
909
910 /* Update counter for this layer */
d01a8ee3
MCC		 911 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
912 if (rc < 0)
913 return rc;
914 rc = mb86a20s_writereg(state, 0x51,
915 state->estimated_rate[layer] >> 16);
916 if (rc < 0)
917 return rc;
918 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
919 if (rc < 0)
920 return rc;
921 rc = mb86a20s_writereg(state, 0x51,
922 state->estimated_rate[layer] >> 8);
923 if (rc < 0)
924 return rc;
925 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
926 if (rc < 0)
927 return rc;
928 rc = mb86a20s_writereg(state, 0x51,
929 state->estimated_rate[layer]);
930 if (rc < 0)
931 return rc;
ad0abbf1
MCC		 932
933 /* Turn on BER before Viterbi */
934 rc = mb86a20s_writereg(state, 0x52, 0x01);
935
936 /* Reset all preBER counters */
937 rc = mb86a20s_writereg(state, 0x53, 0x00);
938 if (rc < 0)
939 return rc;
940 rc = mb86a20s_writereg(state, 0x53, 0x07);
941 } else {
942 /* Reset counter to collect new data */
943 rc = mb86a20s_readreg(state, 0x53);
944 if (rc < 0)
945 return rc;
946 val = rc;
947 rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer));
948 if (rc < 0)
949 return rc;
950 rc = mb86a20s_writereg(state, 0x53, val | (1 << layer));
d01a8ee3
MCC		 951 }
952
d9b6f08a
MCC		 953 return rc;
954}
955
956static int mb86a20s_get_post_ber(struct dvb_frontend *fe,
957 unsigned layer,
958 u32 *error, u32 *count)
959{
960 struct mb86a20s_state *state = fe->demodulator_priv;
961 u32 counter, collect_rate;
962 int rc, val;
963
964 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
965
966 if (layer >= 3)
967 return -EINVAL;
968
969 /* Check if the BER measures are already available */
970 rc = mb86a20s_readreg(state, 0x60);
971 if (rc < 0)
972 return rc;
973
974 /* Check if data is available for that layer */
975 if (!(rc & (1 << layer))) {
976 dev_dbg(&state->i2c->dev,
977 "%s: post BER for layer %c is not available yet.\n",
978 __func__, 'A' + layer);
979 return -EBUSY;
980 }
d01a8ee3 981
d9b6f08a
MCC		 982 /* Read Bit Error Count */
983 rc = mb86a20s_readreg(state, 0x64 + layer * 3);
984 if (rc < 0)
985 return rc;
986 *error = rc << 16;
987 rc = mb86a20s_readreg(state, 0x65 + layer * 3);
988 if (rc < 0)
989 return rc;
990 *error |= rc << 8;
991 rc = mb86a20s_readreg(state, 0x66 + layer * 3);
992 if (rc < 0)
993 return rc;
994 *error |= rc;
995
996 dev_dbg(&state->i2c->dev,
997 "%s: post bit error for layer %c: %d.\n",
998 __func__, 'A' + layer, *error);
999
1000 /* Read Bit Count */
1001 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
1002 if (rc < 0)
1003 return rc;
1004 rc = mb86a20s_readreg(state, 0x51);
1005 if (rc < 0)
1006 return rc;
1007 counter = rc << 8;
1008 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
1009 if (rc < 0)
1010 return rc;
1011 rc = mb86a20s_readreg(state, 0x51);
1012 if (rc < 0)
1013 return rc;
1014 counter |= rc;
1015 *count = counter * 204 * 8;
1016
1017 dev_dbg(&state->i2c->dev,
1018 "%s: post bit count for layer %c: %d.\n",
1019 __func__, 'A' + layer, *count);
1020
1021 /*
1022 * As we get TMCC data from the frontend, we can better estimate the
1023 * BER bit counters, in order to do the BER measure during a longer
1024 * time. Use those data, if available, to update the bit count
1025 * measure.
1026 */
1027
1028 if (!state->estimated_rate[layer])
1029 goto reset_measurement;
1030
1031 collect_rate = state->estimated_rate[layer] / 204 / 8;
1032 if (collect_rate < 32)
1033 collect_rate = 32;
1034 if (collect_rate > 65535)
1035 collect_rate = 65535;
1036 if (collect_rate != counter) {
1037 dev_dbg(&state->i2c->dev,
1038 "%s: updating postBER counter on layer %c to %d.\n",
1039 __func__, 'A' + layer, collect_rate);
1040
1041 /* Turn off BER after Viterbi */
1042 rc = mb86a20s_writereg(state, 0x5e, 0x00);
1043
1044 /* Update counter for this layer */
1045 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
1046 if (rc < 0)
1047 return rc;
1048 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1049 if (rc < 0)
1050 return rc;
1051 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
1052 if (rc < 0)
1053 return rc;
1054 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1055 if (rc < 0)
1056 return rc;
1057
1058 /* Turn on BER after Viterbi */
1059 rc = mb86a20s_writereg(state, 0x5e, 0x07);
1060
1061 /* Reset all preBER counters */
1062 rc = mb86a20s_writereg(state, 0x5f, 0x00);
1063 if (rc < 0)
1064 return rc;
1065 rc = mb86a20s_writereg(state, 0x5f, 0x07);
1066
1067 return rc;
1068 }
1069
1070reset_measurement:
149d518a 1071 /* Reset counter to collect new data */
ad0abbf1
MCC		 1072 rc = mb86a20s_readreg(state, 0x5f);
1073 if (rc < 0)
1074 return rc;
1075 val = rc;
1076 rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer));
149d518a
MCC		 1077 if (rc < 0)
1078 return rc;
d9b6f08a 1079 rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer));
149d518a 1080
ad0abbf1 1081 return rc;
149d518a
MCC		 1082}
1083
593ae89a
MCC		 1084static int mb86a20s_get_blk_error(struct dvb_frontend *fe,
1085 unsigned layer,
1086 u32 *error, u32 *count)
1087{
1088 struct mb86a20s_state *state = fe->demodulator_priv;
313cf4ef 1089 int rc, val;
593ae89a
MCC		 1090 u32 collect_rate;
1091 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1092
1093 if (layer >= 3)
1094 return -EINVAL;
1095
1096 /* Check if the PER measures are already available */
1097 rc = mb86a20s_writereg(state, 0x50, 0xb8);
1098 if (rc < 0)
1099 return rc;
1100 rc = mb86a20s_readreg(state, 0x51);
1101 if (rc < 0)
1102 return rc;
1103
1104 /* Check if data is available for that layer */
1105
1106 if (!(rc & (1 << layer))) {
1107 dev_dbg(&state->i2c->dev,
1108 "%s: block counts for layer %c aren't available yet.\n",
1109 __func__, 'A' + layer);
1110 return -EBUSY;
1111 }
1112
1113 /* Read Packet error Count */
1114 rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2);
1115 if (rc < 0)
1116 return rc;
1117 rc = mb86a20s_readreg(state, 0x51);
1118 if (rc < 0)
1119 return rc;
1120 *error = rc << 8;
1121 rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2);
1122 if (rc < 0)
1123 return rc;
1124 rc = mb86a20s_readreg(state, 0x51);
1125 if (rc < 0)
1126 return rc;
1127 *error |= rc;
d56e326f 1128 dev_dbg(&state->i2c->dev, "%s: block error for layer %c: %d.\n",
593ae89a
MCC		 1129 __func__, 'A' + layer, *error);
1130
1131 /* Read Bit Count */
1132 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1133 if (rc < 0)
1134 return rc;
1135 rc = mb86a20s_readreg(state, 0x51);
1136 if (rc < 0)
1137 return rc;
1138 *count = rc << 8;
1139 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1140 if (rc < 0)
1141 return rc;
1142 rc = mb86a20s_readreg(state, 0x51);
1143 if (rc < 0)
1144 return rc;
1145 *count |= rc;
1146
1147 dev_dbg(&state->i2c->dev,
1148 "%s: block count for layer %c: %d.\n",
1149 __func__, 'A' + layer, *count);
1150
1151 /*
1152 * As we get TMCC data from the frontend, we can better estimate the
1153 * BER bit counters, in order to do the BER measure during a longer
1154 * time. Use those data, if available, to update the bit count
1155 * measure.
1156 */
1157
1158 if (!state->estimated_rate[layer])
1159 goto reset_measurement;
1160
1161 collect_rate = state->estimated_rate[layer] / 204 / 8;
593ae89a
MCC		 1162 if (collect_rate < 32)
1163 collect_rate = 32;
1164 if (collect_rate > 65535)
1165 collect_rate = 65535;
1166
1167 if (collect_rate != *count) {
1168 dev_dbg(&state->i2c->dev,
1169 "%s: updating PER counter on layer %c to %d.\n",
1170 __func__, 'A' + layer, collect_rate);
313cf4ef
MCC		 1171
1172 /* Stop PER measurement */
1173 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1174 if (rc < 0)
1175 return rc;
1176 rc = mb86a20s_writereg(state, 0x51, 0x00);
1177 if (rc < 0)
1178 return rc;
1179
1180 /* Update this layer's counter */
593ae89a
MCC		 1181 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1182 if (rc < 0)
1183 return rc;
1184 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1185 if (rc < 0)
1186 return rc;
1187 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1188 if (rc < 0)
1189 return rc;
1190 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1191 if (rc < 0)
1192 return rc;
313cf4ef
MCC		 1193
1194 /* start PER measurement */
1195 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1196 if (rc < 0)
1197 return rc;
1198 rc = mb86a20s_writereg(state, 0x51, 0x07);
1199 if (rc < 0)
1200 return rc;
1201
1202 /* Reset all counters to collect new data */
1203 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1204 if (rc < 0)
1205 return rc;
1206 rc = mb86a20s_writereg(state, 0x51, 0x07);
1207 if (rc < 0)
1208 return rc;
1209 rc = mb86a20s_writereg(state, 0x51, 0x00);
1210
1211 return rc;
593ae89a
MCC		 1212 }
1213
1214reset_measurement:
1215 /* Reset counter to collect new data */
1216 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1217 if (rc < 0)
1218 return rc;
313cf4ef 1219 rc = mb86a20s_readreg(state, 0x51);
593ae89a
MCC		 1220 if (rc < 0)
1221 return rc;
313cf4ef
MCC		 1222 val = rc;
1223 rc = mb86a20s_writereg(state, 0x51, val | (1 << layer));
593ae89a
MCC		 1224 if (rc < 0)
1225 return rc;
313cf4ef 1226 rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer));
593ae89a 1227
313cf4ef 1228 return rc;
593ae89a
MCC		 1229}
1230
25188bd0
MCC		 1231struct linear_segments {
1232 unsigned x, y;
1233};
1234
1235/*
1236 * All tables below return a dB/1000 measurement
1237 */
1238
1239static struct linear_segments cnr_to_db_table[] = {
1240 { 19648, 0},
1241 { 18187, 1000},
1242 { 16534, 2000},
1243 { 14823, 3000},
1244 { 13161, 4000},
1245 { 11622, 5000},
1246 { 10279, 6000},
1247 { 9089, 7000},
1248 { 8042, 8000},
1249 { 7137, 9000},
1250 { 6342, 10000},
1251 { 5641, 11000},
1252 { 5030, 12000},
1253 { 4474, 13000},
1254 { 3988, 14000},
1255 { 3556, 15000},
1256 { 3180, 16000},
1257 { 2841, 17000},
1258 { 2541, 18000},
1259 { 2276, 19000},
1260 { 2038, 20000},
1261 { 1800, 21000},
1262 { 1625, 22000},
1263 { 1462, 23000},
1264 { 1324, 24000},
1265 { 1175, 25000},
1266 { 1063, 26000},
1267 { 980, 27000},
1268 { 907, 28000},
1269 { 840, 29000},
1270 { 788, 30000},
1271};
1272
1273static struct linear_segments cnr_64qam_table[] = {
1274 { 3922688, 0},
1275 { 3920384, 1000},
1276 { 3902720, 2000},
1277 { 3894784, 3000},
1278 { 3882496, 4000},
1279 { 3872768, 5000},
1280 { 3858944, 6000},
1281 { 3851520, 7000},
1282 { 3838976, 8000},
1283 { 3829248, 9000},
1284 { 3818240, 10000},
1285 { 3806976, 11000},
1286 { 3791872, 12000},
1287 { 3767040, 13000},
1288 { 3720960, 14000},
1289 { 3637504, 15000},
1290 { 3498496, 16000},
1291 { 3296000, 17000},
1292 { 3031040, 18000},
1293 { 2715392, 19000},
1294 { 2362624, 20000},
1295 { 1963264, 21000},
1296 { 1649664, 22000},
1297 { 1366784, 23000},
1298 { 1120768, 24000},
1299 { 890880, 25000},
1300 { 723456, 26000},
1301 { 612096, 27000},
1302 { 518912, 28000},
1303 { 448256, 29000},
1304 { 388864, 30000},
1305};
1306
1307static struct linear_segments cnr_16qam_table[] = {
1308 { 5314816, 0},
1309 { 5219072, 1000},
1310 { 5118720, 2000},
1311 { 4998912, 3000},
1312 { 4875520, 4000},
1313 { 4736000, 5000},
1314 { 4604160, 6000},
1315 { 4458752, 7000},
1316 { 4300288, 8000},
1317 { 4092928, 9000},
1318 { 3836160, 10000},
1319 { 3521024, 11000},
1320 { 3155968, 12000},
1321 { 2756864, 13000},
1322 { 2347008, 14000},
1323 { 1955072, 15000},
1324 { 1593600, 16000},
1325 { 1297920, 17000},
1326 { 1043968, 18000},
1327 { 839680, 19000},
1328 { 672256, 20000},
1329 { 523008, 21000},
1330 { 424704, 22000},
1331 { 345088, 23000},
1332 { 280064, 24000},
1333 { 221440, 25000},
1334 { 179712, 26000},
1335 { 151040, 27000},
1336 { 128512, 28000},
1337 { 110080, 29000},
1338 { 95744, 30000},
1339};
1340
1341struct linear_segments cnr_qpsk_table[] = {
1342 { 2834176, 0},
1343 { 2683648, 1000},
1344 { 2536960, 2000},
1345 { 2391808, 3000},
1346 { 2133248, 4000},
1347 { 1906176, 5000},
1348 { 1666560, 6000},
1349 { 1422080, 7000},
1350 { 1189632, 8000},
1351 { 976384, 9000},
1352 { 790272, 10000},
1353 { 633344, 11000},
1354 { 505600, 12000},
1355 { 402944, 13000},
1356 { 320768, 14000},
1357 { 255488, 15000},
1358 { 204032, 16000},
1359 { 163072, 17000},
1360 { 130304, 18000},
1361 { 105216, 19000},
1362 { 83456, 20000},
1363 { 65024, 21000},
1364 { 52480, 22000},
1365 { 42752, 23000},
1366 { 34560, 24000},
1367 { 27136, 25000},
1368 { 22016, 26000},
1369 { 18432, 27000},
1370 { 15616, 28000},
1371 { 13312, 29000},
1372 { 11520, 30000},
1373};
1374
1375static u32 interpolate_value(u32 value, struct linear_segments *segments,
1376 unsigned len)
1377{
1378 u64 tmp64;
1379 u32 dx, dy;
1380 int i, ret;
1381
1382 if (value >= segments[0].x)
1383 return segments[0].y;
1384 if (value < segments[len-1].x)
1385 return segments[len-1].y;
1386
1387 for (i = 1; i < len - 1; i++) {
1388 /* If value is identical, no need to interpolate */
1389 if (value == segments[i].x)
1390 return segments[i].y;
1391 if (value > segments[i].x)
1392 break;
1393 }
1394
1395 /* Linear interpolation between the two (x,y) points */
1396 dy = segments[i].y - segments[i - 1].y;
1397 dx = segments[i - 1].x - segments[i].x;
1398 tmp64 = value - segments[i].x;
1399 tmp64 *= dy;
1400 do_div(tmp64, dx);
1401 ret = segments[i].y - tmp64;
1402
1403 return ret;
1404}
1405
1406static int mb86a20s_get_main_CNR(struct dvb_frontend *fe)
1407{
1408 struct mb86a20s_state *state = fe->demodulator_priv;
1409 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1410 u32 cnr_linear, cnr;
1411 int rc, val;
1412
1413 /* Check if CNR is available */
1414 rc = mb86a20s_readreg(state, 0x45);
1415 if (rc < 0)
1416 return rc;
1417
1418 if (!(rc & 0x40)) {
d56e326f 1419 dev_dbg(&state->i2c->dev, "%s: CNR is not available yet.\n",
25188bd0
MCC		 1420 __func__);
1421 return -EBUSY;
1422 }
1423 val = rc;
1424
1425 rc = mb86a20s_readreg(state, 0x46);
1426 if (rc < 0)
1427 return rc;
1428 cnr_linear = rc << 8;
1429
1430 rc = mb86a20s_readreg(state, 0x46);
1431 if (rc < 0)
1432 return rc;
1433 cnr_linear |= rc;
1434
1435 cnr = interpolate_value(cnr_linear,
1436 cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table));
1437
1438 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1439 c->cnr.stat[0].svalue = cnr;
1440
1441 dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n",
1442 __func__, cnr / 1000, cnr % 1000, cnr_linear);
1443
1444 /* CNR counter reset */
1445 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
1446 if (rc < 0)
1447 return rc;
1448 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
1449
1450 return rc;
1451}
1452
593ae89a 1453static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe)
25188bd0
MCC		 1454{
1455 struct mb86a20s_state *state = fe->demodulator_priv;
1456 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1457 u32 mer, cnr;
1458 int rc, val, i;
1459 struct linear_segments *segs;
1460 unsigned segs_len;
1461
1462 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1463
1464 /* Check if the measures are already available */
1465 rc = mb86a20s_writereg(state, 0x50, 0x5b);
1466 if (rc < 0)
1467 return rc;
1468 rc = mb86a20s_readreg(state, 0x51);
1469 if (rc < 0)
1470 return rc;
1471
1472 /* Check if data is available */
1473 if (!(rc & 0x01)) {
d56e326f 1474 dev_dbg(&state->i2c->dev,
25188bd0
MCC		 1475 "%s: MER measures aren't available yet.\n", __func__);
1476 return -EBUSY;
1477 }
1478
1479 /* Read all layers */
1480 for (i = 0; i < 3; i++) {
1481 if (!(c->isdbt_layer_enabled & (1 << i))) {
1482 c->cnr.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1483 continue;
1484 }
1485
1486 rc = mb86a20s_writereg(state, 0x50, 0x52 + i * 3);
1487 if (rc < 0)
1488 return rc;
1489 rc = mb86a20s_readreg(state, 0x51);
1490 if (rc < 0)
1491 return rc;
1492 mer = rc << 16;
1493 rc = mb86a20s_writereg(state, 0x50, 0x53 + i * 3);
1494 if (rc < 0)
1495 return rc;
1496 rc = mb86a20s_readreg(state, 0x51);
1497 if (rc < 0)
1498 return rc;
1499 mer |= rc << 8;
1500 rc = mb86a20s_writereg(state, 0x50, 0x54 + i * 3);
1501 if (rc < 0)
1502 return rc;
1503 rc = mb86a20s_readreg(state, 0x51);
1504 if (rc < 0)
1505 return rc;
1506 mer |= rc;
1507
1508 switch (c->layer[i].modulation) {
1509 case DQPSK:
1510 case QPSK:
1511 segs = cnr_qpsk_table;
1512 segs_len = ARRAY_SIZE(cnr_qpsk_table);
1513 break;
1514 case QAM_16:
1515 segs = cnr_16qam_table;
1516 segs_len = ARRAY_SIZE(cnr_16qam_table);
1517 break;
1518 default:
1519 case QAM_64:
1520 segs = cnr_64qam_table;
1521 segs_len = ARRAY_SIZE(cnr_64qam_table);
1522 break;
1523 }
1524 cnr = interpolate_value(mer, segs, segs_len);
1525
1526 c->cnr.stat[1 + i].scale = FE_SCALE_DECIBEL;
1527 c->cnr.stat[1 + i].svalue = cnr;
1528
1529 dev_dbg(&state->i2c->dev,
1530 "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n",
1531 __func__, 'A' + i, cnr / 1000, cnr % 1000, mer);
1532
1533 }
1534
1535 /* Start a new MER measurement */
1536 /* MER counter reset */
1537 rc = mb86a20s_writereg(state, 0x50, 0x50);
1538 if (rc < 0)
1539 return rc;
1540 rc = mb86a20s_readreg(state, 0x51);
1541 if (rc < 0)
1542 return rc;
1543 val = rc;
1544
1545 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
1546 if (rc < 0)
1547 return rc;
1548 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
1549 if (rc < 0)
1550 return rc;
1551
1552 return 0;
1553}
1554
09b6d21e
MCC		 1555static void mb86a20s_stats_not_ready(struct dvb_frontend *fe)
1556{
1557 struct mb86a20s_state *state = fe->demodulator_priv;
1558 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1559 int i;
1560
1561 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
a77cfcac 1562
09b6d21e
MCC		 1563 /* Fill the length of each status counter */
1564
1565 /* Only global stats */
1566 c->strength.len = 1;
1567
1568 /* Per-layer stats - 3 layers + global */
1569 c->cnr.len = 4;
1570 c->pre_bit_error.len = 4;
1571 c->pre_bit_count.len = 4;
d9b6f08a
MCC		 1572 c->post_bit_error.len = 4;
1573 c->post_bit_count.len = 4;
09b6d21e
MCC		 1574 c->block_error.len = 4;
1575 c->block_count.len = 4;
1576
1577 /* Signal is always available */
1578 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
1579 c->strength.stat[0].uvalue = 0;
1580
1581 /* Put all of them at FE_SCALE_NOT_AVAILABLE */
1582 for (i = 0; i < 4; i++) {
1583 c->cnr.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1584 c->pre_bit_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1585 c->pre_bit_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
d9b6f08a
MCC		 1586 c->post_bit_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1587 c->post_bit_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
09b6d21e
MCC		 1588 c->block_error.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1589 c->block_count.stat[i].scale = FE_SCALE_NOT_AVAILABLE;
1590 }
b9ede79a
MCC		 1591}
1592
15b1c5a0 1593static int mb86a20s_get_stats(struct dvb_frontend *fe, int status_nr)
149d518a
MCC		 1594{
1595 struct mb86a20s_state *state = fe->demodulator_priv;
1596 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1597 int rc = 0, i;
1598 u32 bit_error = 0, bit_count = 0;
1599 u32 t_pre_bit_error = 0, t_pre_bit_count = 0;
d9b6f08a 1600 u32 t_post_bit_error = 0, t_post_bit_count = 0;
593ae89a
MCC		 1601 u32 block_error = 0, block_count = 0;
1602 u32 t_block_error = 0, t_block_count = 0;
d9b6f08a
MCC		 1603 int active_layers = 0, pre_ber_layers = 0, post_ber_layers = 0;
1604 int per_layers = 0;
149d518a 1605
25188bd0
MCC		 1606 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1607
1608 mb86a20s_get_main_CNR(fe);
1609
149d518a 1610 /* Get per-layer stats */
593ae89a 1611 mb86a20s_get_blk_error_layer_CNR(fe);
25188bd0 1612
15b1c5a0
MCC		 1613 /*
1614 * At state 7, only CNR is available
1615 * For BER measures, state=9 is required
1616 * FIXME: we may get MER measures with state=8
1617 */
1618 if (status_nr < 9)
1619 return 0;
1620
149d518a
MCC		 1621 for (i = 0; i < 3; i++) {
1622 if (c->isdbt_layer_enabled & (1 << i)) {
1623 /* Layer is active and has rc segments */
1624 active_layers++;
1625
149d518a 1626 /* Handle BER before vterbi */
ad0abbf1
MCC		 1627 rc = mb86a20s_get_pre_ber(fe, i,
1628 &bit_error, &bit_count);
149d518a
MCC		 1629 if (rc >= 0) {
1630 c->pre_bit_error.stat[1 + i].scale = FE_SCALE_COUNTER;
1631 c->pre_bit_error.stat[1 + i].uvalue += bit_error;
1632 c->pre_bit_count.stat[1 + i].scale = FE_SCALE_COUNTER;
1633 c->pre_bit_count.stat[1 + i].uvalue += bit_count;
1634 } else if (rc != -EBUSY) {
1635 /*
1636 * If an I/O error happened,
1637 * measures are now unavailable
1638 */
1639 c->pre_bit_error.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1640 c->pre_bit_count.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1641 dev_err(&state->i2c->dev,
1642 "%s: Can't get BER for layer %c (error %d).\n",
1643 __func__, 'A' + i, rc);
1644 }
149d518a 1645 if (c->block_error.stat[1 + i].scale != FE_SCALE_NOT_AVAILABLE)
d9b6f08a
MCC		 1646 pre_ber_layers++;
1647
1648 /* Handle BER post vterbi */
1649 rc = mb86a20s_get_post_ber(fe, i,
1650 &bit_error, &bit_count);
1651 if (rc >= 0) {
1652 c->post_bit_error.stat[1 + i].scale = FE_SCALE_COUNTER;
1653 c->post_bit_error.stat[1 + i].uvalue += bit_error;
1654 c->post_bit_count.stat[1 + i].scale = FE_SCALE_COUNTER;
1655 c->post_bit_count.stat[1 + i].uvalue += bit_count;
1656 } else if (rc != -EBUSY) {
1657 /*
1658 * If an I/O error happened,
1659 * measures are now unavailable
1660 */
1661 c->post_bit_error.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1662 c->post_bit_count.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1663 dev_err(&state->i2c->dev,
1664 "%s: Can't get BER for layer %c (error %d).\n",
1665 __func__, 'A' + i, rc);
1666 }
d9b6f08a
MCC		 1667 if (c->block_error.stat[1 + i].scale != FE_SCALE_NOT_AVAILABLE)
1668 post_ber_layers++;
149d518a 1669
593ae89a
MCC		 1670 /* Handle Block errors for PER/UCB reports */
1671 rc = mb86a20s_get_blk_error(fe, i,
1672 &block_error,
1673 &block_count);
1674 if (rc >= 0) {
1675 c->block_error.stat[1 + i].scale = FE_SCALE_COUNTER;
1676 c->block_error.stat[1 + i].uvalue += block_error;
1677 c->block_count.stat[1 + i].scale = FE_SCALE_COUNTER;
1678 c->block_count.stat[1 + i].uvalue += block_count;
1679 } else if (rc != -EBUSY) {
1680 /*
1681 * If an I/O error happened,
1682 * measures are now unavailable
1683 */
1684 c->block_error.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1685 c->block_count.stat[1 + i].scale = FE_SCALE_NOT_AVAILABLE;
1686 dev_err(&state->i2c->dev,
1687 "%s: Can't get PER for layer %c (error %d).\n",
1688 __func__, 'A' + i, rc);
1689
1690 }
593ae89a
MCC		 1691 if (c->block_error.stat[1 + i].scale != FE_SCALE_NOT_AVAILABLE)
1692 per_layers++;
1693
d9b6f08a 1694 /* Update total preBER */
149d518a
MCC		 1695 t_pre_bit_error += c->pre_bit_error.stat[1 + i].uvalue;
1696 t_pre_bit_count += c->pre_bit_count.stat[1 + i].uvalue;
593ae89a 1697
d9b6f08a
MCC		 1698 /* Update total postBER */
1699 t_post_bit_error += c->post_bit_error.stat[1 + i].uvalue;
1700 t_post_bit_count += c->post_bit_count.stat[1 + i].uvalue;
1701
593ae89a
MCC		 1702 /* Update total PER */
1703 t_block_error += c->block_error.stat[1 + i].uvalue;
1704 t_block_count += c->block_count.stat[1 + i].uvalue;
149d518a
MCC		 1705 }
1706 }
1707
1708 /*
1709 * Start showing global count if at least one error count is
1710 * available.
1711 */
d9b6f08a 1712 if (pre_ber_layers) {
149d518a
MCC		 1713 /*
1714 * At least one per-layer BER measure was read. We can now
1715 * calculate the total BER
1716 *
1717 * Total Bit Error/Count is calculated as the sum of the
1718 * bit errors on all active layers.
1719 */
1720 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1721 c->pre_bit_error.stat[0].uvalue = t_pre_bit_error;
1722 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1723 c->pre_bit_count.stat[0].uvalue = t_pre_bit_count;
f67102c4
MCC		 1724 } else {
1725 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1726 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
149d518a
MCC		 1727 }
1728
d9b6f08a
MCC		 1729 /*
1730 * Start showing global count if at least one error count is
1731 * available.
1732 */
1733 if (post_ber_layers) {
1734 /*
1735 * At least one per-layer BER measure was read. We can now
1736 * calculate the total BER
1737 *
1738 * Total Bit Error/Count is calculated as the sum of the
1739 * bit errors on all active layers.
1740 */
1741 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1742 c->post_bit_error.stat[0].uvalue = t_post_bit_error;
1743 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1744 c->post_bit_count.stat[0].uvalue = t_post_bit_count;
f67102c4
MCC		 1745 } else {
1746 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1747 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
d9b6f08a
MCC		 1748 }
1749
593ae89a
MCC		 1750 if (per_layers) {
1751 /*
1752 * At least one per-layer UCB measure was read. We can now
1753 * calculate the total UCB
1754 *
1755 * Total block Error/Count is calculated as the sum of the
1756 * block errors on all active layers.
1757 */
1758 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
1759 c->block_error.stat[0].uvalue = t_block_error;
1760 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1761 c->block_count.stat[0].uvalue = t_block_count;
f67102c4
MCC		 1762 } else {
1763 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1764 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
593ae89a
MCC		 1765 }
1766
149d518a
MCC		 1767 return rc;
1768}
09b6d21e
MCC		 1769
1770/*
1771 * The functions below are called via DVB callbacks, so they need to
1772 * properly use the I2C gate control
1773 */
1774
dd4493ef
MCC		 1775static int mb86a20s_initfe(struct dvb_frontend *fe)
1776{
1777 struct mb86a20s_state *state = fe->demodulator_priv;
768e6dad 1778 u64 pll;
dd4493ef 1779 int rc;
04fa725e 1780 u8 regD5 = 1, reg71, reg09 = 0x3a;
dd4493ef 1781
f66d81b5 1782 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
dd4493ef
MCC		 1783
1784 if (fe->ops.i2c_gate_ctrl)
1785 fe->ops.i2c_gate_ctrl(fe, 0);
1786
1787 /* Initialize the frontend */
768e6dad 1788 rc = mb86a20s_writeregdata(state, mb86a20s_init1);
dd4493ef
MCC		 1789 if (rc < 0)
1790 goto err;
1791
04fa725e
MCC		 1792 if (!state->inversion)
1793 reg09 |= 0x04;
1794 rc = mb86a20s_writereg(state, 0x09, reg09);
1795 if (rc < 0)
1796 goto err;
1797 if (!state->bw)
1798 reg71 = 1;
1799 else
1800 reg71 = 0;
1801 rc = mb86a20s_writereg(state, 0x39, reg71);
1802 if (rc < 0)
1803 goto err;
1804 rc = mb86a20s_writereg(state, 0x71, state->bw);
1805 if (rc < 0)
1806 goto err;
1807 if (state->subchannel) {
1808 rc = mb86a20s_writereg(state, 0x44, state->subchannel);
1809 if (rc < 0)
1810 goto err;
1811 }
1812
768e6dad
MCC		 1813 /* Adjust IF frequency to match tuner */
1814 if (fe->ops.tuner_ops.get_if_frequency)
1815 fe->ops.tuner_ops.get_if_frequency(fe, &state->if_freq);
1816
1817 if (!state->if_freq)
1818 state->if_freq = 3300000;
1819
1820 /* pll = freq[Hz] * 2^24/10^6 / 16.285714286 */
1821 pll = state->if_freq * 1677721600L;
1822 do_div(pll, 1628571429L);
1823 rc = mb86a20s_writereg(state, 0x28, 0x20);
1824 if (rc < 0)
1825 goto err;
1826 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1827 if (rc < 0)
1828 goto err;
1829 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1830 if (rc < 0)
1831 goto err;
1832 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1833 if (rc < 0)
1834 goto err;
1835 dev_dbg(&state->i2c->dev, "%s: IF=%d, PLL=0x%06llx\n",
1836 __func__, state->if_freq, (long long)pll);
1837
dd4493ef
MCC		 1838 if (!state->config->is_serial) {
1839 regD5 &= ~1;
1840
1841 rc = mb86a20s_writereg(state, 0x50, 0xd5);
1842 if (rc < 0)
1843 goto err;
1844 rc = mb86a20s_writereg(state, 0x51, regD5);
1845 if (rc < 0)
1846 goto err;
1847 }
1848
768e6dad
MCC		 1849 rc = mb86a20s_writeregdata(state, mb86a20s_init2);
1850 if (rc < 0)
1851 goto err;
1852
1853
dd4493ef
MCC		 1854err:
1855 if (fe->ops.i2c_gate_ctrl)
1856 fe->ops.i2c_gate_ctrl(fe, 1);
1857
1858 if (rc < 0) {
1859 state->need_init = true;
f66d81b5
MCC		 1860 dev_info(&state->i2c->dev,
1861 "mb86a20s: Init failed. Will try again later\n");
dd4493ef
MCC		 1862 } else {
1863 state->need_init = false;
f66d81b5 1864 dev_dbg(&state->i2c->dev, "Initialization succeeded.\n");
dd4493ef
MCC		 1865 }
1866 return rc;
1867}
1868
1869static int mb86a20s_set_frontend(struct dvb_frontend *fe)
1870{
1871 struct mb86a20s_state *state = fe->demodulator_priv;
dd4493ef 1872 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
04fa725e 1873 int rc, if_freq;
f66d81b5 1874 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
dd4493ef 1875
04fa725e
MCC		 1876 if (!c->isdbt_layer_enabled)
1877 c->isdbt_layer_enabled = 7;
1878
1879 if (c->isdbt_layer_enabled == 1)
1880 state->bw = MB86A20S_1SEG;
1881 else if (c->isdbt_partial_reception)
1882 state->bw = MB86A20S_13SEG_PARTIAL;
1883 else
1884 state->bw = MB86A20S_13SEG;
1885
1886 if (c->inversion == INVERSION_ON)
1887 state->inversion = true;
1888 else
1889 state->inversion = false;
1890
1891 if (!c->isdbt_sb_mode) {
1892 state->subchannel = 0;
1893 } else {
1894 if (c->isdbt_sb_subchannel > ARRAY_SIZE(mb86a20s_subchannel))
1895 c->isdbt_sb_subchannel = 0;
1896
1897 state->subchannel = mb86a20s_subchannel[c->isdbt_sb_subchannel];
1898 }
1899
dd4493ef
MCC		 1900 /*
1901 * Gate should already be opened, but it doesn't hurt to
1902 * double-check
1903 */
1904 if (fe->ops.i2c_gate_ctrl)
1905 fe->ops.i2c_gate_ctrl(fe, 1);
dd4493ef
MCC		 1906 fe->ops.tuner_ops.set_params(fe);
1907
a78b41d5 1908 if (fe->ops.tuner_ops.get_if_frequency)
768e6dad
MCC		 1909 fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
1910
dd4493ef
MCC		 1911 /*
1912 * Make it more reliable: if, for some reason, the initial
1913 * device initialization doesn't happen, initialize it when
1914 * a SBTVD parameters are adjusted.
1915 *
1916 * Unfortunately, due to a hard to track bug at tda829x/tda18271,
1917 * the agc callback logic is not called during DVB attach time,
1918 * causing mb86a20s to not be initialized with Kworld SBTVD.
1919 * So, this hack is needed, in order to make Kworld SBTVD to work.
768e6dad
MCC		 1920 *
1921 * It is also needed to change the IF after the initial init.
a78b41d5
MCC		 1922 *
1923 * HACK: Always init the frontend when set_frontend is called:
1924 * it was noticed that, on some devices, it fails to lock on a
1925 * different channel. So, it is better to reset everything, even
1926 * wasting some time, than to loose channel lock.
dd4493ef 1927 */
a78b41d5 1928 mb86a20s_initfe(fe);
dd4493ef
MCC		 1929
1930 if (fe->ops.i2c_gate_ctrl)
1931 fe->ops.i2c_gate_ctrl(fe, 0);
d01a8ee3 1932
dd4493ef 1933 rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception);
09b6d21e 1934 mb86a20s_reset_counters(fe);
3a2e4751 1935 mb86a20s_stats_not_ready(fe);
d01a8ee3 1936
dd4493ef
MCC		 1937 if (fe->ops.i2c_gate_ctrl)
1938 fe->ops.i2c_gate_ctrl(fe, 1);
1939
1940 return rc;
1941}
1942
09b6d21e
MCC		 1943static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe,
1944 fe_status_t *status)
d36e418a 1945{
09b6d21e 1946 struct mb86a20s_state *state = fe->demodulator_priv;
15b1c5a0 1947 int rc, status_nr;
d36e418a 1948
09b6d21e 1949 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
d36e418a
MCC		 1950
1951 if (fe->ops.i2c_gate_ctrl)
1952 fe->ops.i2c_gate_ctrl(fe, 0);
1953
09b6d21e 1954 /* Get lock */
15b1c5a0
MCC		 1955 status_nr = mb86a20s_read_status(fe, status);
1956 if (status_nr < 7) {
09b6d21e
MCC		 1957 mb86a20s_stats_not_ready(fe);
1958 mb86a20s_reset_frontend_cache(fe);
1959 }
15b1c5a0 1960 if (status_nr < 0) {
149d518a
MCC		 1961 dev_err(&state->i2c->dev,
1962 "%s: Can't read frontend lock status\n", __func__);
09b6d21e 1963 goto error;
149d518a 1964 }
09b6d21e
MCC		 1965
1966 /* Get signal strength */
1967 rc = mb86a20s_read_signal_strength(fe);
1968 if (rc < 0) {
149d518a
MCC		 1969 dev_err(&state->i2c->dev,
1970 "%s: Can't reset VBER registers.\n", __func__);
09b6d21e
MCC		 1971 mb86a20s_stats_not_ready(fe);
1972 mb86a20s_reset_frontend_cache(fe);
149d518a
MCC		 1973
1974 rc = 0; /* Status is OK */
09b6d21e
MCC		 1975 goto error;
1976 }
09b6d21e 1977
15b1c5a0 1978 if (status_nr >= 7) {
09b6d21e
MCC		 1979 /* Get TMCC info*/
1980 rc = mb86a20s_get_frontend(fe);
149d518a
MCC		 1981 if (rc < 0) {
1982 dev_err(&state->i2c->dev,
1983 "%s: Can't get FE TMCC data.\n", __func__);
1984 rc = 0; /* Status is OK */
1985 goto error;
1986 }
1987
1988 /* Get statistics */
15b1c5a0 1989 rc = mb86a20s_get_stats(fe, status_nr);
149d518a
MCC		 1990 if (rc < 0 && rc != -EBUSY) {
1991 dev_err(&state->i2c->dev,
1992 "%s: Can't get FE statistics.\n", __func__);
1993 rc = 0;
09b6d21e 1994 goto error;
149d518a
MCC		 1995 }
1996 rc = 0; /* Don't return EBUSY to userspace */
09b6d21e 1997 }
149d518a 1998 goto ok;
09b6d21e 1999
149d518a 2000error:
09b6d21e 2001 mb86a20s_stats_not_ready(fe);
d36e418a 2002
149d518a 2003ok:
d36e418a
MCC		 2004 if (fe->ops.i2c_gate_ctrl)
2005 fe->ops.i2c_gate_ctrl(fe, 1);
149d518a 2006
09b6d21e
MCC		 2007 return rc;
2008}
2009
2010static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe,
2011 u16 *strength)
2012{
2013 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
2014
2015
2016 *strength = c->strength.stat[0].uvalue;
d36e418a 2017
09b6d21e 2018 return 0;
d36e418a
MCC		 2019}
2020
09b6d21e
MCC		 2021static int mb86a20s_get_frontend_dummy(struct dvb_frontend *fe)
2022{
2023 /*
2024 * get_frontend is now handled together with other stats
2025 * retrival, when read_status() is called, as some statistics
2026 * will depend on the layers detection.
2027 */
2028 return 0;
2029};
2030
b9ede79a 2031static int mb86a20s_tune(struct dvb_frontend *fe,
7e072221 2032 bool re_tune,
b9ede79a
MCC		 2033 unsigned int mode_flags,
2034 unsigned int *delay,
2035 fe_status_t *status)
2036{
f66d81b5 2037 struct mb86a20s_state *state = fe->demodulator_priv;
b9ede79a
MCC		 2038 int rc = 0;
2039
f66d81b5 2040 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
b9ede79a 2041
7e072221 2042 if (re_tune)
2d76e22b 2043 rc = mb86a20s_set_frontend(fe);
b9ede79a
MCC		 2044
2045 if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
09b6d21e 2046 mb86a20s_read_status_and_stats(fe, status);
b9ede79a
MCC		 2047
2048 return rc;
2049}
2050
2051static void mb86a20s_release(struct dvb_frontend *fe)
2052{
2053 struct mb86a20s_state *state = fe->demodulator_priv;
2054
f66d81b5 2055 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
b9ede79a
MCC		 2056
2057 kfree(state);
2058}
2059
2060static struct dvb_frontend_ops mb86a20s_ops;
2061
2062struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config,
2063 struct i2c_adapter *i2c)
2064{
f66d81b5 2065 struct mb86a20s_state *state;
b9ede79a
MCC		 2066 u8 rev;
2067
f167e302
MCC		 2068 dev_dbg(&i2c->dev, "%s called.\n", __func__);
2069
b9ede79a 2070 /* allocate memory for the internal state */
f66d81b5 2071 state = kzalloc(sizeof(struct mb86a20s_state), GFP_KERNEL);
b9ede79a 2072 if (state == NULL) {
f167e302 2073 dev_err(&i2c->dev,
f66d81b5 2074 "%s: unable to allocate memory for state\n", __func__);
b9ede79a
MCC		 2075 goto error;
2076 }
2077
2078 /* setup the state */
2079 state->config = config;
2080 state->i2c = i2c;
2081
2082 /* create dvb_frontend */
2083 memcpy(&state->frontend.ops, &mb86a20s_ops,
2084 sizeof(struct dvb_frontend_ops));
2085 state->frontend.demodulator_priv = state;
2086
2087 /* Check if it is a mb86a20s frontend */
2088 rev = mb86a20s_readreg(state, 0);
2089
2090 if (rev == 0x13) {
f167e302 2091 dev_info(&i2c->dev,
f66d81b5 2092 "Detected a Fujitsu mb86a20s frontend\n");
b9ede79a 2093 } else {
f167e302 2094 dev_dbg(&i2c->dev,
f66d81b5 2095 "Frontend revision %d is unknown - aborting.\n",
b9ede79a
MCC		 2096 rev);
2097 goto error;
2098 }
2099
2100 return &state->frontend;
2101
2102error:
2103 kfree(state);
2104 return NULL;
2105}
2106EXPORT_SYMBOL(mb86a20s_attach);
2107
2108static struct dvb_frontend_ops mb86a20s_ops = {
2d76e22b 2109 .delsys = { SYS_ISDBT },
b9ede79a
MCC		 2110 /* Use dib8000 values per default */
2111 .info = {
2112 .name = "Fujitsu mb86A20s",
04fa725e 2113 .caps = FE_CAN_RECOVER |
b9ede79a
MCC		 2114 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
2115 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
2116 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2117 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO |
2118 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
2119 /* Actually, those values depend on the used tuner */
2120 .frequency_min = 45000000,
2121 .frequency_max = 864000000,
2122 .frequency_stepsize = 62500,
2123 },
2124
2125 .release = mb86a20s_release,
2126
2127 .init = mb86a20s_initfe,
2d76e22b 2128 .set_frontend = mb86a20s_set_frontend,
09b6d21e
MCC		 2129 .get_frontend = mb86a20s_get_frontend_dummy,
2130 .read_status = mb86a20s_read_status_and_stats,
2131 .read_signal_strength = mb86a20s_read_signal_strength_from_cache,
b9ede79a
MCC		 2132 .tune = mb86a20s_tune,
2133};
2134
2135MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware");
2136MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
2137MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)