Commit | Line | Data |
---|---|---|
50acfb2b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
b9ede79a MCC |
2 | /* |
3 | * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver | |
4 | * | |
37e59f87 | 5 | * Copyright (C) 2010-2013 Mauro Carvalho Chehab |
b9ede79a | 6 | * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com> |
b9ede79a MCC |
7 | */ |
8 | ||
9 | #include <linux/kernel.h> | |
10 | #include <asm/div64.h> | |
11 | ||
fada1935 | 12 | #include <media/dvb_frontend.h> |
b9ede79a MCC |
13 | #include "mb86a20s.h" |
14 | ||
4f62a20d MCC |
15 | #define NUM_LAYERS 3 |
16 | ||
04fa725e MCC |
17 | enum mb86a20s_bandwidth { |
18 | MB86A20S_13SEG = 0, | |
19 | MB86A20S_13SEG_PARTIAL = 1, | |
20 | MB86A20S_1SEG = 2, | |
21 | MB86A20S_3SEG = 3, | |
22 | }; | |
23 | ||
ce08131c | 24 | static u8 mb86a20s_subchannel[] = { |
04fa725e MCC |
25 | 0xb0, 0xc0, 0xd0, 0xe0, |
26 | 0xf0, 0x00, 0x10, 0x20, | |
27 | }; | |
28 | ||
b9ede79a MCC |
29 | struct mb86a20s_state { |
30 | struct i2c_adapter *i2c; | |
31 | const struct mb86a20s_config *config; | |
09b6d21e | 32 | u32 last_frequency; |
b9ede79a MCC |
33 | |
34 | struct dvb_frontend frontend; | |
c736a5f2 | 35 | |
768e6dad | 36 | u32 if_freq; |
04fa725e MCC |
37 | enum mb86a20s_bandwidth bw; |
38 | bool inversion; | |
39 | u32 subchannel; | |
768e6dad | 40 | |
4f62a20d | 41 | u32 estimated_rate[NUM_LAYERS]; |
0921ecfd | 42 | unsigned long get_strength_time; |
d01a8ee3 | 43 | |
c736a5f2 | 44 | bool need_init; |
b9ede79a MCC |
45 | }; |
46 | ||
47 | struct regdata { | |
48 | u8 reg; | |
49 | u8 data; | |
50 | }; | |
51 | ||
d01a8ee3 MCC |
52 | #define BER_SAMPLING_RATE 1 /* Seconds */ |
53 | ||
b9ede79a MCC |
54 | /* |
55 | * Initialization sequence: Use whatevere default values that PV SBTVD | |
56 | * does on its initialisation, obtained via USB snoop | |
57 | */ | |
768e6dad | 58 | static struct regdata mb86a20s_init1[] = { |
b9ede79a MCC |
59 | { 0x70, 0x0f }, |
60 | { 0x70, 0xff }, | |
61 | { 0x08, 0x01 }, | |
17e67d4c | 62 | { 0x50, 0xd1 }, { 0x51, 0x20 }, |
768e6dad MCC |
63 | }; |
64 | ||
65 | static struct regdata mb86a20s_init2[] = { | |
505a0ea7 MCC |
66 | { 0x50, 0xd1 }, { 0x51, 0x22 }, |
67 | { 0x39, 0x01 }, | |
68 | { 0x71, 0x00 }, | |
b9ede79a | 69 | { 0x3b, 0x21 }, |
505a0ea7 | 70 | { 0x3c, 0x3a }, |
b9ede79a | 71 | { 0x01, 0x0d }, |
505a0ea7 | 72 | { 0x04, 0x08 }, { 0x05, 0x05 }, |
a7025edf | 73 | { 0x04, 0x0e }, { 0x05, 0x00 }, |
505a0ea7 MCC |
74 | { 0x04, 0x0f }, { 0x05, 0x14 }, |
75 | { 0x04, 0x0b }, { 0x05, 0x8c }, | |
a7025edf | 76 | { 0x04, 0x00 }, { 0x05, 0x00 }, |
505a0ea7 MCC |
77 | { 0x04, 0x01 }, { 0x05, 0x07 }, |
78 | { 0x04, 0x02 }, { 0x05, 0x0f }, | |
79 | { 0x04, 0x03 }, { 0x05, 0xa0 }, | |
a7025edf MCC |
80 | { 0x04, 0x09 }, { 0x05, 0x00 }, |
81 | { 0x04, 0x0a }, { 0x05, 0xff }, | |
505a0ea7 | 82 | { 0x04, 0x27 }, { 0x05, 0x64 }, |
a7025edf | 83 | { 0x04, 0x28 }, { 0x05, 0x00 }, |
505a0ea7 MCC |
84 | { 0x04, 0x1e }, { 0x05, 0xff }, |
85 | { 0x04, 0x29 }, { 0x05, 0x0a }, | |
86 | { 0x04, 0x32 }, { 0x05, 0x0a }, | |
a7025edf MCC |
87 | { 0x04, 0x14 }, { 0x05, 0x02 }, |
88 | { 0x04, 0x04 }, { 0x05, 0x00 }, | |
89 | { 0x04, 0x05 }, { 0x05, 0x22 }, | |
90 | { 0x04, 0x06 }, { 0x05, 0x0e }, | |
91 | { 0x04, 0x07 }, { 0x05, 0xd8 }, | |
92 | { 0x04, 0x12 }, { 0x05, 0x00 }, | |
93 | { 0x04, 0x13 }, { 0x05, 0xff }, | |
09b6d21e MCC |
94 | |
95 | /* | |
96 | * On this demod, when the bit count reaches the count below, | |
97 | * it collects the bit error count. The bit counters are initialized | |
98 | * to 65535 here. This warrants that all of them will be quickly | |
99 | * calculated when device gets locked. As TMCC is parsed, the values | |
d01a8ee3 | 100 | * will be adjusted later in the driver's code. |
09b6d21e MCC |
101 | */ |
102 | { 0x52, 0x01 }, /* Turn on BER before Viterbi */ | |
103 | { 0x50, 0xa7 }, { 0x51, 0x00 }, | |
a7025edf MCC |
104 | { 0x50, 0xa8 }, { 0x51, 0xff }, |
105 | { 0x50, 0xa9 }, { 0x51, 0xff }, | |
09b6d21e | 106 | { 0x50, 0xaa }, { 0x51, 0x00 }, |
a7025edf MCC |
107 | { 0x50, 0xab }, { 0x51, 0xff }, |
108 | { 0x50, 0xac }, { 0x51, 0xff }, | |
09b6d21e | 109 | { 0x50, 0xad }, { 0x51, 0x00 }, |
a7025edf MCC |
110 | { 0x50, 0xae }, { 0x51, 0xff }, |
111 | { 0x50, 0xaf }, { 0x51, 0xff }, | |
09b6d21e | 112 | |
d9b6f08a MCC |
113 | /* |
114 | * On this demod, post BER counts blocks. When the count reaches the | |
115 | * value below, it collects the block error count. The block counters | |
116 | * are initialized to 127 here. This warrants that all of them will be | |
117 | * quickly calculated when device gets locked. As TMCC is parsed, the | |
118 | * values will be adjusted later in the driver's code. | |
119 | */ | |
120 | { 0x5e, 0x07 }, /* Turn on BER after Viterbi */ | |
121 | { 0x50, 0xdc }, { 0x51, 0x00 }, | |
122 | { 0x50, 0xdd }, { 0x51, 0x7f }, | |
123 | { 0x50, 0xde }, { 0x51, 0x00 }, | |
124 | { 0x50, 0xdf }, { 0x51, 0x7f }, | |
125 | { 0x50, 0xe0 }, { 0x51, 0x00 }, | |
126 | { 0x50, 0xe1 }, { 0x51, 0x7f }, | |
593ae89a MCC |
127 | |
128 | /* | |
129 | * On this demod, when the block count reaches the count below, | |
130 | * it collects the block error count. The block counters are initialized | |
131 | * to 127 here. This warrants that all of them will be quickly | |
132 | * calculated when device gets locked. As TMCC is parsed, the values | |
133 | * will be adjusted later in the driver's code. | |
134 | */ | |
135 | { 0x50, 0xb0 }, { 0x51, 0x07 }, /* Enable PER */ | |
136 | { 0x50, 0xb2 }, { 0x51, 0x00 }, | |
137 | { 0x50, 0xb3 }, { 0x51, 0x7f }, | |
138 | { 0x50, 0xb4 }, { 0x51, 0x00 }, | |
139 | { 0x50, 0xb5 }, { 0x51, 0x7f }, | |
140 | { 0x50, 0xb6 }, { 0x51, 0x00 }, | |
141 | { 0x50, 0xb7 }, { 0x51, 0x7f }, | |
25188bd0 MCC |
142 | |
143 | { 0x50, 0x50 }, { 0x51, 0x02 }, /* MER manual mode */ | |
09b6d21e MCC |
144 | { 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */ |
145 | { 0x45, 0x04 }, /* CN symbol 4 */ | |
25188bd0 | 146 | { 0x48, 0x04 }, /* CN manual mode */ |
505a0ea7 | 147 | { 0x50, 0xd5 }, { 0x51, 0x01 }, |
a7025edf MCC |
148 | { 0x50, 0xd6 }, { 0x51, 0x1f }, |
149 | { 0x50, 0xd2 }, { 0x51, 0x03 }, | |
505a0ea7 | 150 | { 0x50, 0xd7 }, { 0x51, 0x3f }, |
b9ede79a | 151 | { 0x1c, 0x01 }, |
505a0ea7 MCC |
152 | { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x03 }, |
153 | { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0d }, | |
154 | { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 }, | |
155 | { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x01 }, | |
156 | { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x21 }, | |
157 | { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x29 }, | |
158 | { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 }, | |
159 | { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x31 }, | |
160 | { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0e }, | |
161 | { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x4e }, | |
162 | { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x46 }, | |
163 | { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f }, | |
164 | { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x56 }, | |
165 | { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x35 }, | |
166 | { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbe }, | |
167 | { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0x84 }, | |
168 | { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x03 }, { 0x2b, 0xee }, | |
169 | { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x98 }, | |
170 | { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x9f }, | |
171 | { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xb2 }, | |
172 | { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0xc2 }, | |
173 | { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0x4a }, | |
174 | { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbc }, | |
175 | { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x04 }, { 0x2b, 0xba }, | |
176 | { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0x14 }, | |
a7025edf MCC |
177 | { 0x50, 0x1e }, { 0x51, 0x5d }, |
178 | { 0x50, 0x22 }, { 0x51, 0x00 }, | |
179 | { 0x50, 0x23 }, { 0x51, 0xc8 }, | |
180 | { 0x50, 0x24 }, { 0x51, 0x00 }, | |
181 | { 0x50, 0x25 }, { 0x51, 0xf0 }, | |
182 | { 0x50, 0x26 }, { 0x51, 0x00 }, | |
183 | { 0x50, 0x27 }, { 0x51, 0xc3 }, | |
184 | { 0x50, 0x39 }, { 0x51, 0x02 }, | |
505a0ea7 | 185 | { 0x50, 0xd5 }, { 0x51, 0x01 }, |
b9ede79a MCC |
186 | { 0xd0, 0x00 }, |
187 | }; | |
188 | ||
189 | static struct regdata mb86a20s_reset_reception[] = { | |
190 | { 0x70, 0xf0 }, | |
191 | { 0x70, 0xff }, | |
192 | { 0x08, 0x01 }, | |
193 | { 0x08, 0x00 }, | |
194 | }; | |
195 | ||
d9b6f08a MCC |
196 | static struct regdata mb86a20s_per_ber_reset[] = { |
197 | { 0x53, 0x00 }, /* pre BER Counter reset */ | |
09b6d21e | 198 | { 0x53, 0x07 }, |
09b6d21e | 199 | |
d9b6f08a MCC |
200 | { 0x5f, 0x00 }, /* post BER Counter reset */ |
201 | { 0x5f, 0x07 }, | |
202 | ||
09b6d21e MCC |
203 | { 0x50, 0xb1 }, /* PER Counter reset */ |
204 | { 0x51, 0x07 }, | |
205 | { 0x51, 0x00 }, | |
206 | }; | |
207 | ||
dd4493ef MCC |
208 | /* |
209 | * I2C read/write functions and macros | |
210 | */ | |
211 | ||
b9ede79a | 212 | static int mb86a20s_i2c_writereg(struct mb86a20s_state *state, |
09b6d21e | 213 | u8 i2c_addr, u8 reg, u8 data) |
b9ede79a MCC |
214 | { |
215 | u8 buf[] = { reg, data }; | |
216 | struct i2c_msg msg = { | |
217 | .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2 | |
218 | }; | |
219 | int rc; | |
220 | ||
221 | rc = i2c_transfer(state->i2c, &msg, 1); | |
222 | if (rc != 1) { | |
f66d81b5 MCC |
223 | dev_err(&state->i2c->dev, |
224 | "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n", | |
225 | __func__, rc, reg, data); | |
b9ede79a MCC |
226 | return rc; |
227 | } | |
228 | ||
229 | return 0; | |
230 | } | |
231 | ||
232 | static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state, | |
233 | u8 i2c_addr, struct regdata *rd, int size) | |
234 | { | |
235 | int i, rc; | |
236 | ||
237 | for (i = 0; i < size; i++) { | |
238 | rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg, | |
239 | rd[i].data); | |
240 | if (rc < 0) | |
241 | return rc; | |
242 | } | |
243 | return 0; | |
244 | } | |
245 | ||
246 | static int mb86a20s_i2c_readreg(struct mb86a20s_state *state, | |
247 | u8 i2c_addr, u8 reg) | |
248 | { | |
249 | u8 val; | |
250 | int rc; | |
251 | struct i2c_msg msg[] = { | |
252 | { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 }, | |
253 | { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 } | |
254 | }; | |
255 | ||
256 | rc = i2c_transfer(state->i2c, msg, 2); | |
257 | ||
258 | if (rc != 2) { | |
f66d81b5 MCC |
259 | dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n", |
260 | __func__, reg, rc); | |
261 | return (rc < 0) ? rc : -EIO; | |
b9ede79a MCC |
262 | } |
263 | ||
264 | return val; | |
265 | } | |
266 | ||
267 | #define mb86a20s_readreg(state, reg) \ | |
268 | mb86a20s_i2c_readreg(state, state->config->demod_address, reg) | |
269 | #define mb86a20s_writereg(state, reg, val) \ | |
270 | mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val) | |
271 | #define mb86a20s_writeregdata(state, regdata) \ | |
272 | mb86a20s_i2c_writeregdata(state, state->config->demod_address, \ | |
273 | regdata, ARRAY_SIZE(regdata)) | |
274 | ||
09b6d21e MCC |
275 | /* |
276 | * Ancillary internal routines (likely compiled inlined) | |
277 | * | |
278 | * The functions below assume that gateway lock has already obtained | |
279 | */ | |
280 | ||
0df289a2 | 281 | static int mb86a20s_read_status(struct dvb_frontend *fe, enum fe_status *status) |
b9ede79a MCC |
282 | { |
283 | struct mb86a20s_state *state = fe->demodulator_priv; | |
dd4493ef | 284 | int val; |
b9ede79a | 285 | |
dd4493ef | 286 | *status = 0; |
b9ede79a | 287 | |
eca2d34b | 288 | val = mb86a20s_readreg(state, 0x0a); |
dd4493ef MCC |
289 | if (val < 0) |
290 | return val; | |
68541cda | 291 | |
eca2d34b | 292 | val &= 0xf; |
dd4493ef MCC |
293 | if (val >= 2) |
294 | *status |= FE_HAS_SIGNAL; | |
b9ede79a | 295 | |
dd4493ef MCC |
296 | if (val >= 4) |
297 | *status |= FE_HAS_CARRIER; | |
7572f9c5 | 298 | |
dd4493ef MCC |
299 | if (val >= 5) |
300 | *status |= FE_HAS_VITERBI; | |
7572f9c5 | 301 | |
dd4493ef MCC |
302 | if (val >= 7) |
303 | *status |= FE_HAS_SYNC; | |
68541cda | 304 | |
dafb65fb MCC |
305 | /* |
306 | * Actually, on state S8, it starts receiving TS, but the TS | |
307 | * output is only on normal state after the transition to S9. | |
308 | */ | |
309 | if (val >= 9) | |
dd4493ef MCC |
310 | *status |= FE_HAS_LOCK; |
311 | ||
f66d81b5 MCC |
312 | dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n", |
313 | __func__, *status, val); | |
dd4493ef | 314 | |
15b1c5a0 | 315 | return val; |
b9ede79a MCC |
316 | } |
317 | ||
09b6d21e | 318 | static int mb86a20s_read_signal_strength(struct dvb_frontend *fe) |
b9ede79a MCC |
319 | { |
320 | struct mb86a20s_state *state = fe->demodulator_priv; | |
0921ecfd | 321 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
09b6d21e | 322 | int rc; |
b9ede79a | 323 | unsigned rf_max, rf_min, rf; |
68541cda | 324 | |
0921ecfd MCC |
325 | if (state->get_strength_time && |
326 | (!time_after(jiffies, state->get_strength_time))) | |
327 | return c->strength.stat[0].uvalue; | |
328 | ||
329 | /* Reset its value if an error happen */ | |
330 | c->strength.stat[0].uvalue = 0; | |
331 | ||
b9ede79a MCC |
332 | /* Does a binary search to get RF strength */ |
333 | rf_max = 0xfff; | |
334 | rf_min = 0; | |
335 | do { | |
336 | rf = (rf_max + rf_min) / 2; | |
09b6d21e MCC |
337 | rc = mb86a20s_writereg(state, 0x04, 0x1f); |
338 | if (rc < 0) | |
339 | return rc; | |
340 | rc = mb86a20s_writereg(state, 0x05, rf >> 8); | |
341 | if (rc < 0) | |
342 | return rc; | |
343 | rc = mb86a20s_writereg(state, 0x04, 0x20); | |
344 | if (rc < 0) | |
345 | return rc; | |
dad78c56 | 346 | rc = mb86a20s_writereg(state, 0x05, rf); |
09b6d21e MCC |
347 | if (rc < 0) |
348 | return rc; | |
b9ede79a | 349 | |
09b6d21e MCC |
350 | rc = mb86a20s_readreg(state, 0x02); |
351 | if (rc < 0) | |
352 | return rc; | |
353 | if (rc & 0x08) | |
b9ede79a MCC |
354 | rf_min = (rf_max + rf_min) / 2; |
355 | else | |
356 | rf_max = (rf_max + rf_min) / 2; | |
357 | if (rf_max - rf_min < 4) { | |
09b6d21e MCC |
358 | rf = (rf_max + rf_min) / 2; |
359 | ||
360 | /* Rescale it from 2^12 (4096) to 2^16 */ | |
0921ecfd MCC |
361 | rf = rf << (16 - 12); |
362 | if (rf) | |
363 | rf |= (1 << 12) - 1; | |
364 | ||
f66d81b5 MCC |
365 | dev_dbg(&state->i2c->dev, |
366 | "%s: signal strength = %d (%d < RF=%d < %d)\n", | |
367 | __func__, rf, rf_min, rf >> 4, rf_max); | |
0921ecfd MCC |
368 | c->strength.stat[0].uvalue = rf; |
369 | state->get_strength_time = jiffies + | |
370 | msecs_to_jiffies(1000); | |
371 | return 0; | |
b9ede79a MCC |
372 | } |
373 | } while (1); | |
b9ede79a MCC |
374 | } |
375 | ||
959a119f MCC |
376 | static int mb86a20s_get_modulation(struct mb86a20s_state *state, |
377 | unsigned layer) | |
378 | { | |
379 | int rc; | |
380 | static unsigned char reg[] = { | |
381 | [0] = 0x86, /* Layer A */ | |
382 | [1] = 0x8a, /* Layer B */ | |
383 | [2] = 0x8e, /* Layer C */ | |
384 | }; | |
385 | ||
82033bc5 | 386 | if (layer >= ARRAY_SIZE(reg)) |
959a119f MCC |
387 | return -EINVAL; |
388 | rc = mb86a20s_writereg(state, 0x6d, reg[layer]); | |
389 | if (rc < 0) | |
390 | return rc; | |
391 | rc = mb86a20s_readreg(state, 0x6e); | |
392 | if (rc < 0) | |
393 | return rc; | |
04585921 | 394 | switch ((rc >> 4) & 0x07) { |
959a119f MCC |
395 | case 0: |
396 | return DQPSK; | |
397 | case 1: | |
398 | return QPSK; | |
399 | case 2: | |
400 | return QAM_16; | |
401 | case 3: | |
402 | return QAM_64; | |
403 | default: | |
404 | return QAM_AUTO; | |
405 | } | |
406 | } | |
407 | ||
408 | static int mb86a20s_get_fec(struct mb86a20s_state *state, | |
409 | unsigned layer) | |
410 | { | |
411 | int rc; | |
412 | ||
413 | static unsigned char reg[] = { | |
414 | [0] = 0x87, /* Layer A */ | |
415 | [1] = 0x8b, /* Layer B */ | |
416 | [2] = 0x8f, /* Layer C */ | |
417 | }; | |
418 | ||
82033bc5 | 419 | if (layer >= ARRAY_SIZE(reg)) |
959a119f MCC |
420 | return -EINVAL; |
421 | rc = mb86a20s_writereg(state, 0x6d, reg[layer]); | |
422 | if (rc < 0) | |
423 | return rc; | |
424 | rc = mb86a20s_readreg(state, 0x6e); | |
425 | if (rc < 0) | |
426 | return rc; | |
04585921 | 427 | switch ((rc >> 4) & 0x07) { |
959a119f MCC |
428 | case 0: |
429 | return FEC_1_2; | |
430 | case 1: | |
431 | return FEC_2_3; | |
432 | case 2: | |
433 | return FEC_3_4; | |
434 | case 3: | |
435 | return FEC_5_6; | |
436 | case 4: | |
437 | return FEC_7_8; | |
438 | default: | |
439 | return FEC_AUTO; | |
440 | } | |
441 | } | |
442 | ||
443 | static int mb86a20s_get_interleaving(struct mb86a20s_state *state, | |
444 | unsigned layer) | |
445 | { | |
446 | int rc; | |
4247368b MCC |
447 | int interleaving[] = { |
448 | 0, 1, 2, 4, 8 | |
449 | }; | |
959a119f MCC |
450 | |
451 | static unsigned char reg[] = { | |
452 | [0] = 0x88, /* Layer A */ | |
453 | [1] = 0x8c, /* Layer B */ | |
454 | [2] = 0x90, /* Layer C */ | |
455 | }; | |
456 | ||
82033bc5 | 457 | if (layer >= ARRAY_SIZE(reg)) |
959a119f MCC |
458 | return -EINVAL; |
459 | rc = mb86a20s_writereg(state, 0x6d, reg[layer]); | |
460 | if (rc < 0) | |
461 | return rc; | |
462 | rc = mb86a20s_readreg(state, 0x6e); | |
463 | if (rc < 0) | |
464 | return rc; | |
04585921 | 465 | |
4247368b | 466 | return interleaving[(rc >> 4) & 0x07]; |
959a119f MCC |
467 | } |
468 | ||
469 | static int mb86a20s_get_segment_count(struct mb86a20s_state *state, | |
470 | unsigned layer) | |
471 | { | |
472 | int rc, count; | |
959a119f MCC |
473 | static unsigned char reg[] = { |
474 | [0] = 0x89, /* Layer A */ | |
475 | [1] = 0x8d, /* Layer B */ | |
476 | [2] = 0x91, /* Layer C */ | |
477 | }; | |
478 | ||
f66d81b5 MCC |
479 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); |
480 | ||
82033bc5 | 481 | if (layer >= ARRAY_SIZE(reg)) |
959a119f | 482 | return -EINVAL; |
f66d81b5 | 483 | |
959a119f MCC |
484 | rc = mb86a20s_writereg(state, 0x6d, reg[layer]); |
485 | if (rc < 0) | |
486 | return rc; | |
487 | rc = mb86a20s_readreg(state, 0x6e); | |
488 | if (rc < 0) | |
489 | return rc; | |
490 | count = (rc >> 4) & 0x0f; | |
491 | ||
f66d81b5 MCC |
492 | dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count); |
493 | ||
959a119f MCC |
494 | return count; |
495 | } | |
496 | ||
a77cfcac MCC |
497 | static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe) |
498 | { | |
f66d81b5 | 499 | struct mb86a20s_state *state = fe->demodulator_priv; |
a77cfcac MCC |
500 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
501 | ||
f66d81b5 MCC |
502 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); |
503 | ||
a77cfcac MCC |
504 | /* Fixed parameters */ |
505 | c->delivery_system = SYS_ISDBT; | |
506 | c->bandwidth_hz = 6000000; | |
507 | ||
508 | /* Initialize values that will be later autodetected */ | |
509 | c->isdbt_layer_enabled = 0; | |
510 | c->transmission_mode = TRANSMISSION_MODE_AUTO; | |
511 | c->guard_interval = GUARD_INTERVAL_AUTO; | |
512 | c->isdbt_sb_mode = 0; | |
513 | c->isdbt_sb_segment_count = 0; | |
514 | } | |
515 | ||
d01a8ee3 MCC |
516 | /* |
517 | * Estimates the bit rate using the per-segment bit rate given by | |
518 | * ABNT/NBR 15601 spec (table 4). | |
519 | */ | |
520 | static u32 isdbt_rate[3][5][4] = { | |
521 | { /* DQPSK/QPSK */ | |
522 | { 280850, 312060, 330420, 340430 }, /* 1/2 */ | |
523 | { 374470, 416080, 440560, 453910 }, /* 2/3 */ | |
524 | { 421280, 468090, 495630, 510650 }, /* 3/4 */ | |
525 | { 468090, 520100, 550700, 567390 }, /* 5/6 */ | |
526 | { 491500, 546110, 578230, 595760 }, /* 7/8 */ | |
527 | }, { /* QAM16 */ | |
528 | { 561710, 624130, 660840, 680870 }, /* 1/2 */ | |
529 | { 748950, 832170, 881120, 907820 }, /* 2/3 */ | |
530 | { 842570, 936190, 991260, 1021300 }, /* 3/4 */ | |
531 | { 936190, 1040210, 1101400, 1134780 }, /* 5/6 */ | |
532 | { 983000, 1092220, 1156470, 1191520 }, /* 7/8 */ | |
533 | }, { /* QAM64 */ | |
534 | { 842570, 936190, 991260, 1021300 }, /* 1/2 */ | |
535 | { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */ | |
536 | { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */ | |
537 | { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */ | |
538 | { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */ | |
539 | } | |
540 | }; | |
541 | ||
542 | static void mb86a20s_layer_bitrate(struct dvb_frontend *fe, u32 layer, | |
0562aef2 | 543 | u32 modulation, u32 forward_error_correction, |
277bfd2f | 544 | u32 guard_interval, |
d01a8ee3 MCC |
545 | u32 segment) |
546 | { | |
547 | struct mb86a20s_state *state = fe->demodulator_priv; | |
548 | u32 rate; | |
0562aef2 | 549 | int mod, fec, guard; |
d01a8ee3 MCC |
550 | |
551 | /* | |
277bfd2f | 552 | * If modulation/fec/guard is not detected, the default is |
d01a8ee3 MCC |
553 | * to consider the lowest bit rate, to avoid taking too long time |
554 | * to get BER. | |
555 | */ | |
556 | switch (modulation) { | |
557 | case DQPSK: | |
558 | case QPSK: | |
559 | default: | |
0562aef2 | 560 | mod = 0; |
d01a8ee3 MCC |
561 | break; |
562 | case QAM_16: | |
0562aef2 | 563 | mod = 1; |
d01a8ee3 MCC |
564 | break; |
565 | case QAM_64: | |
0562aef2 | 566 | mod = 2; |
d01a8ee3 MCC |
567 | break; |
568 | } | |
569 | ||
0562aef2 | 570 | switch (forward_error_correction) { |
d01a8ee3 MCC |
571 | default: |
572 | case FEC_1_2: | |
573 | case FEC_AUTO: | |
0562aef2 | 574 | fec = 0; |
d01a8ee3 MCC |
575 | break; |
576 | case FEC_2_3: | |
0562aef2 | 577 | fec = 1; |
d01a8ee3 MCC |
578 | break; |
579 | case FEC_3_4: | |
0562aef2 | 580 | fec = 2; |
d01a8ee3 MCC |
581 | break; |
582 | case FEC_5_6: | |
0562aef2 | 583 | fec = 3; |
d01a8ee3 MCC |
584 | break; |
585 | case FEC_7_8: | |
0562aef2 | 586 | fec = 4; |
d01a8ee3 MCC |
587 | break; |
588 | } | |
589 | ||
277bfd2f | 590 | switch (guard_interval) { |
d01a8ee3 MCC |
591 | default: |
592 | case GUARD_INTERVAL_1_4: | |
0562aef2 | 593 | guard = 0; |
d01a8ee3 MCC |
594 | break; |
595 | case GUARD_INTERVAL_1_8: | |
0562aef2 | 596 | guard = 1; |
d01a8ee3 MCC |
597 | break; |
598 | case GUARD_INTERVAL_1_16: | |
0562aef2 | 599 | guard = 2; |
d01a8ee3 MCC |
600 | break; |
601 | case GUARD_INTERVAL_1_32: | |
0562aef2 | 602 | guard = 3; |
d01a8ee3 MCC |
603 | break; |
604 | } | |
605 | ||
606 | /* Samples BER at BER_SAMPLING_RATE seconds */ | |
0562aef2 | 607 | rate = isdbt_rate[mod][fec][guard] * segment * BER_SAMPLING_RATE; |
d01a8ee3 MCC |
608 | |
609 | /* Avoids sampling too quickly or to overflow the register */ | |
610 | if (rate < 256) | |
611 | rate = 256; | |
612 | else if (rate > (1 << 24) - 1) | |
613 | rate = (1 << 24) - 1; | |
614 | ||
615 | dev_dbg(&state->i2c->dev, | |
616 | "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n", | |
0562aef2 MCC |
617 | __func__, 'A' + layer, |
618 | segment * isdbt_rate[mod][fec][guard]/1000, | |
d01a8ee3 MCC |
619 | rate, rate); |
620 | ||
b1f89331 | 621 | state->estimated_rate[layer] = rate; |
d01a8ee3 MCC |
622 | } |
623 | ||
7c61d80a | 624 | static int mb86a20s_get_frontend(struct dvb_frontend *fe) |
b9ede79a | 625 | { |
959a119f | 626 | struct mb86a20s_state *state = fe->demodulator_priv; |
a77cfcac | 627 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
5cb88ca8 | 628 | int layer, rc; |
b9ede79a | 629 | |
f66d81b5 MCC |
630 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); |
631 | ||
a77cfcac MCC |
632 | /* Reset frontend cache to default values */ |
633 | mb86a20s_reset_frontend_cache(fe); | |
959a119f | 634 | |
959a119f MCC |
635 | /* Check for partial reception */ |
636 | rc = mb86a20s_writereg(state, 0x6d, 0x85); | |
a77cfcac MCC |
637 | if (rc < 0) |
638 | return rc; | |
639 | rc = mb86a20s_readreg(state, 0x6e); | |
640 | if (rc < 0) | |
641 | return rc; | |
642 | c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0; | |
959a119f MCC |
643 | |
644 | /* Get per-layer data */ | |
a77cfcac | 645 | |
5cb88ca8 | 646 | for (layer = 0; layer < NUM_LAYERS; layer++) { |
f66d81b5 | 647 | dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n", |
5cb88ca8 | 648 | __func__, 'A' + layer); |
f66d81b5 | 649 | |
5cb88ca8 | 650 | rc = mb86a20s_get_segment_count(state, layer); |
a77cfcac | 651 | if (rc < 0) |
f66d81b5 | 652 | goto noperlayer_error; |
d01a8ee3 | 653 | if (rc >= 0 && rc < 14) { |
5cb88ca8 | 654 | c->layer[layer].segment_count = rc; |
d01a8ee3 | 655 | } else { |
5cb88ca8 MCC |
656 | c->layer[layer].segment_count = 0; |
657 | state->estimated_rate[layer] = 0; | |
959a119f | 658 | continue; |
a77cfcac | 659 | } |
5cb88ca8 MCC |
660 | c->isdbt_layer_enabled |= 1 << layer; |
661 | rc = mb86a20s_get_modulation(state, layer); | |
a77cfcac | 662 | if (rc < 0) |
f66d81b5 MCC |
663 | goto noperlayer_error; |
664 | dev_dbg(&state->i2c->dev, "%s: modulation %d.\n", | |
665 | __func__, rc); | |
5cb88ca8 MCC |
666 | c->layer[layer].modulation = rc; |
667 | rc = mb86a20s_get_fec(state, layer); | |
a77cfcac | 668 | if (rc < 0) |
f66d81b5 MCC |
669 | goto noperlayer_error; |
670 | dev_dbg(&state->i2c->dev, "%s: FEC %d.\n", | |
671 | __func__, rc); | |
5cb88ca8 MCC |
672 | c->layer[layer].fec = rc; |
673 | rc = mb86a20s_get_interleaving(state, layer); | |
a77cfcac | 674 | if (rc < 0) |
f66d81b5 MCC |
675 | goto noperlayer_error; |
676 | dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n", | |
677 | __func__, rc); | |
5cb88ca8 MCC |
678 | c->layer[layer].interleaving = rc; |
679 | mb86a20s_layer_bitrate(fe, layer, c->layer[layer].modulation, | |
680 | c->layer[layer].fec, | |
277bfd2f | 681 | c->guard_interval, |
5cb88ca8 | 682 | c->layer[layer].segment_count); |
959a119f MCC |
683 | } |
684 | ||
959a119f | 685 | rc = mb86a20s_writereg(state, 0x6d, 0x84); |
a77cfcac MCC |
686 | if (rc < 0) |
687 | return rc; | |
688 | if ((rc & 0x60) == 0x20) { | |
689 | c->isdbt_sb_mode = 1; | |
959a119f | 690 | /* At least, one segment should exist */ |
a77cfcac MCC |
691 | if (!c->isdbt_sb_segment_count) |
692 | c->isdbt_sb_segment_count = 1; | |
693 | } | |
959a119f MCC |
694 | |
695 | /* Get transmission mode and guard interval */ | |
959a119f | 696 | rc = mb86a20s_readreg(state, 0x07); |
a77cfcac MCC |
697 | if (rc < 0) |
698 | return rc; | |
276dfc4b | 699 | c->transmission_mode = TRANSMISSION_MODE_AUTO; |
a77cfcac | 700 | if ((rc & 0x60) == 0x20) { |
276dfc4b MCC |
701 | /* Only modes 2 and 3 are supported */ |
702 | switch ((rc >> 2) & 0x03) { | |
a77cfcac MCC |
703 | case 1: |
704 | c->transmission_mode = TRANSMISSION_MODE_4K; | |
705 | break; | |
706 | case 2: | |
707 | c->transmission_mode = TRANSMISSION_MODE_8K; | |
708 | break; | |
959a119f | 709 | } |
a77cfcac | 710 | } |
276dfc4b | 711 | c->guard_interval = GUARD_INTERVAL_AUTO; |
a77cfcac | 712 | if (!(rc & 0x10)) { |
276dfc4b | 713 | /* Guard interval 1/32 is not supported */ |
a77cfcac MCC |
714 | switch (rc & 0x3) { |
715 | case 0: | |
716 | c->guard_interval = GUARD_INTERVAL_1_4; | |
717 | break; | |
718 | case 1: | |
719 | c->guard_interval = GUARD_INTERVAL_1_8; | |
720 | break; | |
721 | case 2: | |
722 | c->guard_interval = GUARD_INTERVAL_1_16; | |
723 | break; | |
959a119f MCC |
724 | } |
725 | } | |
09b6d21e | 726 | return 0; |
959a119f | 727 | |
f66d81b5 | 728 | noperlayer_error: |
b9ede79a | 729 | |
09b6d21e MCC |
730 | /* per-layer info is incomplete; discard all per-layer */ |
731 | c->isdbt_layer_enabled = 0; | |
732 | ||
733 | return rc; | |
734 | } | |
735 | ||
736 | static int mb86a20s_reset_counters(struct dvb_frontend *fe) | |
737 | { | |
738 | struct mb86a20s_state *state = fe->demodulator_priv; | |
739 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; | |
740 | int rc, val; | |
741 | ||
742 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); | |
743 | ||
744 | /* Reset the counters, if the channel changed */ | |
745 | if (state->last_frequency != c->frequency) { | |
09b6d21e MCC |
746 | memset(&c->cnr, 0, sizeof(c->cnr)); |
747 | memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error)); | |
748 | memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count)); | |
d9b6f08a MCC |
749 | memset(&c->post_bit_error, 0, sizeof(c->post_bit_error)); |
750 | memset(&c->post_bit_count, 0, sizeof(c->post_bit_count)); | |
09b6d21e MCC |
751 | memset(&c->block_error, 0, sizeof(c->block_error)); |
752 | memset(&c->block_count, 0, sizeof(c->block_count)); | |
753 | ||
754 | state->last_frequency = c->frequency; | |
755 | } | |
756 | ||
757 | /* Clear status for most stats */ | |
758 | ||
d9b6f08a MCC |
759 | /* BER/PER counter reset */ |
760 | rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset); | |
09b6d21e MCC |
761 | if (rc < 0) |
762 | goto err; | |
763 | ||
764 | /* CNR counter reset */ | |
765 | rc = mb86a20s_readreg(state, 0x45); | |
766 | if (rc < 0) | |
767 | goto err; | |
768 | val = rc; | |
769 | rc = mb86a20s_writereg(state, 0x45, val | 0x10); | |
770 | if (rc < 0) | |
771 | goto err; | |
772 | rc = mb86a20s_writereg(state, 0x45, val & 0x6f); | |
773 | if (rc < 0) | |
774 | goto err; | |
775 | ||
776 | /* MER counter reset */ | |
777 | rc = mb86a20s_writereg(state, 0x50, 0x50); | |
778 | if (rc < 0) | |
779 | goto err; | |
780 | rc = mb86a20s_readreg(state, 0x51); | |
781 | if (rc < 0) | |
782 | goto err; | |
783 | val = rc; | |
784 | rc = mb86a20s_writereg(state, 0x51, val | 0x01); | |
785 | if (rc < 0) | |
786 | goto err; | |
787 | rc = mb86a20s_writereg(state, 0x51, val & 0x06); | |
788 | if (rc < 0) | |
789 | goto err; | |
790 | ||
149d518a | 791 | goto ok; |
09b6d21e | 792 | err: |
149d518a MCC |
793 | dev_err(&state->i2c->dev, |
794 | "%s: Can't reset FE statistics (error %d).\n", | |
795 | __func__, rc); | |
796 | ok: | |
a77cfcac | 797 | return rc; |
09b6d21e MCC |
798 | } |
799 | ||
ad0abbf1 MCC |
800 | static int mb86a20s_get_pre_ber(struct dvb_frontend *fe, |
801 | unsigned layer, | |
802 | u32 *error, u32 *count) | |
149d518a MCC |
803 | { |
804 | struct mb86a20s_state *state = fe->demodulator_priv; | |
ad0abbf1 | 805 | int rc, val; |
149d518a MCC |
806 | |
807 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); | |
808 | ||
4f62a20d | 809 | if (layer >= NUM_LAYERS) |
149d518a MCC |
810 | return -EINVAL; |
811 | ||
812 | /* Check if the BER measures are already available */ | |
813 | rc = mb86a20s_readreg(state, 0x54); | |
814 | if (rc < 0) | |
815 | return rc; | |
816 | ||
817 | /* Check if data is available for that layer */ | |
818 | if (!(rc & (1 << layer))) { | |
819 | dev_dbg(&state->i2c->dev, | |
ad0abbf1 | 820 | "%s: preBER for layer %c is not available yet.\n", |
149d518a MCC |
821 | __func__, 'A' + layer); |
822 | return -EBUSY; | |
823 | } | |
824 | ||
825 | /* Read Bit Error Count */ | |
826 | rc = mb86a20s_readreg(state, 0x55 + layer * 3); | |
827 | if (rc < 0) | |
828 | return rc; | |
829 | *error = rc << 16; | |
830 | rc = mb86a20s_readreg(state, 0x56 + layer * 3); | |
831 | if (rc < 0) | |
832 | return rc; | |
833 | *error |= rc << 8; | |
834 | rc = mb86a20s_readreg(state, 0x57 + layer * 3); | |
835 | if (rc < 0) | |
836 | return rc; | |
837 | *error |= rc; | |
838 | ||
839 | dev_dbg(&state->i2c->dev, | |
840 | "%s: bit error before Viterbi for layer %c: %d.\n", | |
841 | __func__, 'A' + layer, *error); | |
842 | ||
843 | /* Read Bit Count */ | |
844 | rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3); | |
845 | if (rc < 0) | |
846 | return rc; | |
847 | rc = mb86a20s_readreg(state, 0x51); | |
848 | if (rc < 0) | |
849 | return rc; | |
850 | *count = rc << 16; | |
851 | rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3); | |
852 | if (rc < 0) | |
853 | return rc; | |
854 | rc = mb86a20s_readreg(state, 0x51); | |
855 | if (rc < 0) | |
856 | return rc; | |
857 | *count |= rc << 8; | |
858 | rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3); | |
859 | if (rc < 0) | |
860 | return rc; | |
861 | rc = mb86a20s_readreg(state, 0x51); | |
862 | if (rc < 0) | |
863 | return rc; | |
864 | *count |= rc; | |
865 | ||
866 | dev_dbg(&state->i2c->dev, | |
867 | "%s: bit count before Viterbi for layer %c: %d.\n", | |
868 | __func__, 'A' + layer, *count); | |
869 | ||
870 | ||
d01a8ee3 MCC |
871 | /* |
872 | * As we get TMCC data from the frontend, we can better estimate the | |
873 | * BER bit counters, in order to do the BER measure during a longer | |
874 | * time. Use those data, if available, to update the bit count | |
875 | * measure. | |
876 | */ | |
877 | ||
878 | if (state->estimated_rate[layer] | |
879 | && state->estimated_rate[layer] != *count) { | |
880 | dev_dbg(&state->i2c->dev, | |
ad0abbf1 | 881 | "%s: updating layer %c preBER counter to %d.\n", |
d01a8ee3 | 882 | __func__, 'A' + layer, state->estimated_rate[layer]); |
ad0abbf1 MCC |
883 | |
884 | /* Turn off BER before Viterbi */ | |
885 | rc = mb86a20s_writereg(state, 0x52, 0x00); | |
886 | ||
887 | /* Update counter for this layer */ | |
d01a8ee3 MCC |
888 | rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3); |
889 | if (rc < 0) | |
890 | return rc; | |
891 | rc = mb86a20s_writereg(state, 0x51, | |
892 | state->estimated_rate[layer] >> 16); | |
893 | if (rc < 0) | |
894 | return rc; | |
895 | rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3); | |
896 | if (rc < 0) | |
897 | return rc; | |
898 | rc = mb86a20s_writereg(state, 0x51, | |
899 | state->estimated_rate[layer] >> 8); | |
900 | if (rc < 0) | |
901 | return rc; | |
902 | rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3); | |
903 | if (rc < 0) | |
904 | return rc; | |
905 | rc = mb86a20s_writereg(state, 0x51, | |
906 | state->estimated_rate[layer]); | |
907 | if (rc < 0) | |
908 | return rc; | |
ad0abbf1 MCC |
909 | |
910 | /* Turn on BER before Viterbi */ | |
911 | rc = mb86a20s_writereg(state, 0x52, 0x01); | |
912 | ||
913 | /* Reset all preBER counters */ | |
914 | rc = mb86a20s_writereg(state, 0x53, 0x00); | |
915 | if (rc < 0) | |
916 | return rc; | |
917 | rc = mb86a20s_writereg(state, 0x53, 0x07); | |
918 | } else { | |
919 | /* Reset counter to collect new data */ | |
920 | rc = mb86a20s_readreg(state, 0x53); | |
921 | if (rc < 0) | |
922 | return rc; | |
923 | val = rc; | |
924 | rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer)); | |
925 | if (rc < 0) | |
926 | return rc; | |
927 | rc = mb86a20s_writereg(state, 0x53, val | (1 << layer)); | |
d01a8ee3 MCC |
928 | } |
929 | ||
d9b6f08a MCC |
930 | return rc; |
931 | } | |
932 | ||
933 | static int mb86a20s_get_post_ber(struct dvb_frontend *fe, | |
934 | unsigned layer, | |
935 | u32 *error, u32 *count) | |
936 | { | |
937 | struct mb86a20s_state *state = fe->demodulator_priv; | |
938 | u32 counter, collect_rate; | |
939 | int rc, val; | |
940 | ||
941 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); | |
942 | ||
4f62a20d | 943 | if (layer >= NUM_LAYERS) |
d9b6f08a MCC |
944 | return -EINVAL; |
945 | ||
946 | /* Check if the BER measures are already available */ | |
947 | rc = mb86a20s_readreg(state, 0x60); | |
948 | if (rc < 0) | |
949 | return rc; | |
950 | ||
951 | /* Check if data is available for that layer */ | |
952 | if (!(rc & (1 << layer))) { | |
953 | dev_dbg(&state->i2c->dev, | |
954 | "%s: post BER for layer %c is not available yet.\n", | |
955 | __func__, 'A' + layer); | |
956 | return -EBUSY; | |
957 | } | |
d01a8ee3 | 958 | |
d9b6f08a MCC |
959 | /* Read Bit Error Count */ |
960 | rc = mb86a20s_readreg(state, 0x64 + layer * 3); | |
961 | if (rc < 0) | |
962 | return rc; | |
963 | *error = rc << 16; | |
964 | rc = mb86a20s_readreg(state, 0x65 + layer * 3); | |
965 | if (rc < 0) | |
966 | return rc; | |
967 | *error |= rc << 8; | |
968 | rc = mb86a20s_readreg(state, 0x66 + layer * 3); | |
969 | if (rc < 0) | |
970 | return rc; | |
971 | *error |= rc; | |
972 | ||
973 | dev_dbg(&state->i2c->dev, | |
974 | "%s: post bit error for layer %c: %d.\n", | |
975 | __func__, 'A' + layer, *error); | |
976 | ||
977 | /* Read Bit Count */ | |
978 | rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2); | |
979 | if (rc < 0) | |
980 | return rc; | |
981 | rc = mb86a20s_readreg(state, 0x51); | |
982 | if (rc < 0) | |
983 | return rc; | |
984 | counter = rc << 8; | |
985 | rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2); | |
986 | if (rc < 0) | |
987 | return rc; | |
988 | rc = mb86a20s_readreg(state, 0x51); | |
989 | if (rc < 0) | |
990 | return rc; | |
991 | counter |= rc; | |
992 | *count = counter * 204 * 8; | |
993 | ||
994 | dev_dbg(&state->i2c->dev, | |
995 | "%s: post bit count for layer %c: %d.\n", | |
996 | __func__, 'A' + layer, *count); | |
997 | ||
998 | /* | |
999 | * As we get TMCC data from the frontend, we can better estimate the | |
1000 | * BER bit counters, in order to do the BER measure during a longer | |
1001 | * time. Use those data, if available, to update the bit count | |
1002 | * measure. | |
1003 | */ | |
1004 | ||
1005 | if (!state->estimated_rate[layer]) | |
1006 | goto reset_measurement; | |
1007 | ||
1008 | collect_rate = state->estimated_rate[layer] / 204 / 8; | |
1009 | if (collect_rate < 32) | |
1010 | collect_rate = 32; | |
1011 | if (collect_rate > 65535) | |
1012 | collect_rate = 65535; | |
1013 | if (collect_rate != counter) { | |
1014 | dev_dbg(&state->i2c->dev, | |
1015 | "%s: updating postBER counter on layer %c to %d.\n", | |
1016 | __func__, 'A' + layer, collect_rate); | |
1017 | ||
1018 | /* Turn off BER after Viterbi */ | |
1019 | rc = mb86a20s_writereg(state, 0x5e, 0x00); | |
1020 | ||
1021 | /* Update counter for this layer */ | |
1022 | rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2); | |
1023 | if (rc < 0) | |
1024 | return rc; | |
1025 | rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8); | |
1026 | if (rc < 0) | |
1027 | return rc; | |
1028 | rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2); | |
1029 | if (rc < 0) | |
1030 | return rc; | |
1031 | rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff); | |
1032 | if (rc < 0) | |
1033 | return rc; | |
1034 | ||
1035 | /* Turn on BER after Viterbi */ | |
1036 | rc = mb86a20s_writereg(state, 0x5e, 0x07); | |
1037 | ||
1038 | /* Reset all preBER counters */ | |
1039 | rc = mb86a20s_writereg(state, 0x5f, 0x00); | |
1040 | if (rc < 0) | |
1041 | return rc; | |
1042 | rc = mb86a20s_writereg(state, 0x5f, 0x07); | |
1043 | ||
1044 | return rc; | |
1045 | } | |
1046 | ||
1047 | reset_measurement: | |
149d518a | 1048 | /* Reset counter to collect new data */ |
ad0abbf1 MCC |
1049 | rc = mb86a20s_readreg(state, 0x5f); |
1050 | if (rc < 0) | |
1051 | return rc; | |
1052 | val = rc; | |
1053 | rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer)); | |
149d518a MCC |
1054 | if (rc < 0) |
1055 | return rc; | |
d9b6f08a | 1056 | rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer)); |
149d518a | 1057 | |
ad0abbf1 | 1058 | return rc; |
149d518a MCC |
1059 | } |
1060 | ||
593ae89a MCC |
1061 | static int mb86a20s_get_blk_error(struct dvb_frontend *fe, |
1062 | unsigned layer, | |
1063 | u32 *error, u32 *count) | |
1064 | { | |
1065 | struct mb86a20s_state *state = fe->demodulator_priv; | |
313cf4ef | 1066 | int rc, val; |
593ae89a MCC |
1067 | u32 collect_rate; |
1068 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); | |
1069 | ||
4f62a20d | 1070 | if (layer >= NUM_LAYERS) |
593ae89a MCC |
1071 | return -EINVAL; |
1072 | ||
1073 | /* Check if the PER measures are already available */ | |
1074 | rc = mb86a20s_writereg(state, 0x50, 0xb8); | |
1075 | if (rc < 0) | |
1076 | return rc; | |
1077 | rc = mb86a20s_readreg(state, 0x51); | |
1078 | if (rc < 0) | |
1079 | return rc; | |
1080 | ||
1081 | /* Check if data is available for that layer */ | |
1082 | ||
1083 | if (!(rc & (1 << layer))) { | |
1084 | dev_dbg(&state->i2c->dev, | |
1085 | "%s: block counts for layer %c aren't available yet.\n", | |
1086 | __func__, 'A' + layer); | |
1087 | return -EBUSY; | |
1088 | } | |
1089 | ||
1090 | /* Read Packet error Count */ | |
1091 | rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2); | |
1092 | if (rc < 0) | |
1093 | return rc; | |
1094 | rc = mb86a20s_readreg(state, 0x51); | |
1095 | if (rc < 0) | |
1096 | return rc; | |
1097 | *error = rc << 8; | |
1098 | rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2); | |
1099 | if (rc < 0) | |
1100 | return rc; | |
1101 | rc = mb86a20s_readreg(state, 0x51); | |
1102 | if (rc < 0) | |
1103 | return rc; | |
1104 | *error |= rc; | |
d56e326f | 1105 | dev_dbg(&state->i2c->dev, "%s: block error for layer %c: %d.\n", |
593ae89a MCC |
1106 | __func__, 'A' + layer, *error); |
1107 | ||
1108 | /* Read Bit Count */ | |
1109 | rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2); | |
1110 | if (rc < 0) | |
1111 | return rc; | |
1112 | rc = mb86a20s_readreg(state, 0x51); | |
1113 | if (rc < 0) | |
1114 | return rc; | |
1115 | *count = rc << 8; | |
1116 | rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2); | |
1117 | if (rc < 0) | |
1118 | return rc; | |
1119 | rc = mb86a20s_readreg(state, 0x51); | |
1120 | if (rc < 0) | |
1121 | return rc; | |
1122 | *count |= rc; | |
1123 | ||
1124 | dev_dbg(&state->i2c->dev, | |
1125 | "%s: block count for layer %c: %d.\n", | |
1126 | __func__, 'A' + layer, *count); | |
1127 | ||
1128 | /* | |
1129 | * As we get TMCC data from the frontend, we can better estimate the | |
1130 | * BER bit counters, in order to do the BER measure during a longer | |
1131 | * time. Use those data, if available, to update the bit count | |
1132 | * measure. | |
1133 | */ | |
1134 | ||
1135 | if (!state->estimated_rate[layer]) | |
1136 | goto reset_measurement; | |
1137 | ||
1138 | collect_rate = state->estimated_rate[layer] / 204 / 8; | |
593ae89a MCC |
1139 | if (collect_rate < 32) |
1140 | collect_rate = 32; | |
1141 | if (collect_rate > 65535) | |
1142 | collect_rate = 65535; | |
1143 | ||
1144 | if (collect_rate != *count) { | |
1145 | dev_dbg(&state->i2c->dev, | |
1146 | "%s: updating PER counter on layer %c to %d.\n", | |
1147 | __func__, 'A' + layer, collect_rate); | |
313cf4ef MCC |
1148 | |
1149 | /* Stop PER measurement */ | |
1150 | rc = mb86a20s_writereg(state, 0x50, 0xb0); | |
1151 | if (rc < 0) | |
1152 | return rc; | |
1153 | rc = mb86a20s_writereg(state, 0x51, 0x00); | |
1154 | if (rc < 0) | |
1155 | return rc; | |
1156 | ||
1157 | /* Update this layer's counter */ | |
593ae89a MCC |
1158 | rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2); |
1159 | if (rc < 0) | |
1160 | return rc; | |
1161 | rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8); | |
1162 | if (rc < 0) | |
1163 | return rc; | |
1164 | rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2); | |
1165 | if (rc < 0) | |
1166 | return rc; | |
1167 | rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff); | |
1168 | if (rc < 0) | |
1169 | return rc; | |
313cf4ef MCC |
1170 | |
1171 | /* start PER measurement */ | |
1172 | rc = mb86a20s_writereg(state, 0x50, 0xb0); | |
1173 | if (rc < 0) | |
1174 | return rc; | |
1175 | rc = mb86a20s_writereg(state, 0x51, 0x07); | |
1176 | if (rc < 0) | |
1177 | return rc; | |
1178 | ||
1179 | /* Reset all counters to collect new data */ | |
1180 | rc = mb86a20s_writereg(state, 0x50, 0xb1); | |
1181 | if (rc < 0) | |
1182 | return rc; | |
1183 | rc = mb86a20s_writereg(state, 0x51, 0x07); | |
1184 | if (rc < 0) | |
1185 | return rc; | |
1186 | rc = mb86a20s_writereg(state, 0x51, 0x00); | |
1187 | ||
1188 | return rc; | |
593ae89a MCC |
1189 | } |
1190 | ||
1191 | reset_measurement: | |
1192 | /* Reset counter to collect new data */ | |
1193 | rc = mb86a20s_writereg(state, 0x50, 0xb1); | |
1194 | if (rc < 0) | |
1195 | return rc; | |
313cf4ef | 1196 | rc = mb86a20s_readreg(state, 0x51); |
593ae89a MCC |
1197 | if (rc < 0) |
1198 | return rc; | |
313cf4ef MCC |
1199 | val = rc; |
1200 | rc = mb86a20s_writereg(state, 0x51, val | (1 << layer)); | |
593ae89a MCC |
1201 | if (rc < 0) |
1202 | return rc; | |
313cf4ef | 1203 | rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer)); |
593ae89a | 1204 | |
313cf4ef | 1205 | return rc; |
593ae89a MCC |
1206 | } |
1207 | ||
25188bd0 MCC |
1208 | struct linear_segments { |
1209 | unsigned x, y; | |
1210 | }; | |
1211 | ||
1212 | /* | |
1213 | * All tables below return a dB/1000 measurement | |
1214 | */ | |
1215 | ||
ce08131c | 1216 | static const struct linear_segments cnr_to_db_table[] = { |
25188bd0 MCC |
1217 | { 19648, 0}, |
1218 | { 18187, 1000}, | |
1219 | { 16534, 2000}, | |
1220 | { 14823, 3000}, | |
1221 | { 13161, 4000}, | |
1222 | { 11622, 5000}, | |
1223 | { 10279, 6000}, | |
1224 | { 9089, 7000}, | |
1225 | { 8042, 8000}, | |
1226 | { 7137, 9000}, | |
1227 | { 6342, 10000}, | |
1228 | { 5641, 11000}, | |
1229 | { 5030, 12000}, | |
1230 | { 4474, 13000}, | |
1231 | { 3988, 14000}, | |
1232 | { 3556, 15000}, | |
1233 | { 3180, 16000}, | |
1234 | { 2841, 17000}, | |
1235 | { 2541, 18000}, | |
1236 | { 2276, 19000}, | |
1237 | { 2038, 20000}, | |
1238 | { 1800, 21000}, | |
1239 | { 1625, 22000}, | |
1240 | { 1462, 23000}, | |
1241 | { 1324, 24000}, | |
1242 | { 1175, 25000}, | |
1243 | { 1063, 26000}, | |
1244 | { 980, 27000}, | |
1245 | { 907, 28000}, | |
1246 | { 840, 29000}, | |
1247 | { 788, 30000}, | |
1248 | }; | |
1249 | ||
ce08131c | 1250 | static const struct linear_segments cnr_64qam_table[] = { |
25188bd0 MCC |
1251 | { 3922688, 0}, |
1252 | { 3920384, 1000}, | |
1253 | { 3902720, 2000}, | |
1254 | { 3894784, 3000}, | |
1255 | { 3882496, 4000}, | |
1256 | { 3872768, 5000}, | |
1257 | { 3858944, 6000}, | |
1258 | { 3851520, 7000}, | |
1259 | { 3838976, 8000}, | |
1260 | { 3829248, 9000}, | |
1261 | { 3818240, 10000}, | |
1262 | { 3806976, 11000}, | |
1263 | { 3791872, 12000}, | |
1264 | { 3767040, 13000}, | |
1265 | { 3720960, 14000}, | |
1266 | { 3637504, 15000}, | |
1267 | { 3498496, 16000}, | |
1268 | { 3296000, 17000}, | |
1269 | { 3031040, 18000}, | |
1270 | { 2715392, 19000}, | |
1271 | { 2362624, 20000}, | |
1272 | { 1963264, 21000}, | |
1273 | { 1649664, 22000}, | |
1274 | { 1366784, 23000}, | |
1275 | { 1120768, 24000}, | |
1276 | { 890880, 25000}, | |
1277 | { 723456, 26000}, | |
1278 | { 612096, 27000}, | |
1279 | { 518912, 28000}, | |
1280 | { 448256, 29000}, | |
1281 | { 388864, 30000}, | |
1282 | }; | |
1283 | ||
ce08131c | 1284 | static const struct linear_segments cnr_16qam_table[] = { |
25188bd0 MCC |
1285 | { 5314816, 0}, |
1286 | { 5219072, 1000}, | |
1287 | { 5118720, 2000}, | |
1288 | { 4998912, 3000}, | |
1289 | { 4875520, 4000}, | |
1290 | { 4736000, 5000}, | |
1291 | { 4604160, 6000}, | |
1292 | { 4458752, 7000}, | |
1293 | { 4300288, 8000}, | |
1294 | { 4092928, 9000}, | |
1295 | { 3836160, 10000}, | |
1296 | { 3521024, 11000}, | |
1297 | { 3155968, 12000}, | |
1298 | { 2756864, 13000}, | |
1299 | { 2347008, 14000}, | |
1300 | { 1955072, 15000}, | |
1301 | { 1593600, 16000}, | |
1302 | { 1297920, 17000}, | |
1303 | { 1043968, 18000}, | |
1304 | { 839680, 19000}, | |
1305 | { 672256, 20000}, | |
1306 | { 523008, 21000}, | |
1307 | { 424704, 22000}, | |
1308 | { 345088, 23000}, | |
1309 | { 280064, 24000}, | |
1310 | { 221440, 25000}, | |
1311 | { 179712, 26000}, | |
1312 | { 151040, 27000}, | |
1313 | { 128512, 28000}, | |
1314 | { 110080, 29000}, | |
1315 | { 95744, 30000}, | |
1316 | }; | |
1317 | ||
ce08131c | 1318 | static const struct linear_segments cnr_qpsk_table[] = { |
25188bd0 MCC |
1319 | { 2834176, 0}, |
1320 | { 2683648, 1000}, | |
1321 | { 2536960, 2000}, | |
1322 | { 2391808, 3000}, | |
1323 | { 2133248, 4000}, | |
1324 | { 1906176, 5000}, | |
1325 | { 1666560, 6000}, | |
1326 | { 1422080, 7000}, | |
1327 | { 1189632, 8000}, | |
1328 | { 976384, 9000}, | |
1329 | { 790272, 10000}, | |
1330 | { 633344, 11000}, | |
1331 | { 505600, 12000}, | |
1332 | { 402944, 13000}, | |
1333 | { 320768, 14000}, | |
1334 | { 255488, 15000}, | |
1335 | { 204032, 16000}, | |
1336 | { 163072, 17000}, | |
1337 | { 130304, 18000}, | |
1338 | { 105216, 19000}, | |
1339 | { 83456, 20000}, | |
1340 | { 65024, 21000}, | |
1341 | { 52480, 22000}, | |
1342 | { 42752, 23000}, | |
1343 | { 34560, 24000}, | |
1344 | { 27136, 25000}, | |
1345 | { 22016, 26000}, | |
1346 | { 18432, 27000}, | |
1347 | { 15616, 28000}, | |
1348 | { 13312, 29000}, | |
1349 | { 11520, 30000}, | |
1350 | }; | |
1351 | ||
ce08131c | 1352 | static u32 interpolate_value(u32 value, const struct linear_segments *segments, |
25188bd0 MCC |
1353 | unsigned len) |
1354 | { | |
1355 | u64 tmp64; | |
1356 | u32 dx, dy; | |
1357 | int i, ret; | |
1358 | ||
1359 | if (value >= segments[0].x) | |
1360 | return segments[0].y; | |
1361 | if (value < segments[len-1].x) | |
1362 | return segments[len-1].y; | |
1363 | ||
1364 | for (i = 1; i < len - 1; i++) { | |
1365 | /* If value is identical, no need to interpolate */ | |
1366 | if (value == segments[i].x) | |
1367 | return segments[i].y; | |
1368 | if (value > segments[i].x) | |
1369 | break; | |
1370 | } | |
1371 | ||
1372 | /* Linear interpolation between the two (x,y) points */ | |
1373 | dy = segments[i].y - segments[i - 1].y; | |
1374 | dx = segments[i - 1].x - segments[i].x; | |
1375 | tmp64 = value - segments[i].x; | |
1376 | tmp64 *= dy; | |
1377 | do_div(tmp64, dx); | |
1378 | ret = segments[i].y - tmp64; | |
1379 | ||
1380 | return ret; | |
1381 | } | |
1382 | ||
1383 | static int mb86a20s_get_main_CNR(struct dvb_frontend *fe) | |
1384 | { | |
1385 | struct mb86a20s_state *state = fe->demodulator_priv; | |
1386 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; | |
1387 | u32 cnr_linear, cnr; | |
1388 | int rc, val; | |
1389 | ||
1390 | /* Check if CNR is available */ | |
1391 | rc = mb86a20s_readreg(state, 0x45); | |
1392 | if (rc < 0) | |
1393 | return rc; | |
1394 | ||
1395 | if (!(rc & 0x40)) { | |
d56e326f | 1396 | dev_dbg(&state->i2c->dev, "%s: CNR is not available yet.\n", |
25188bd0 MCC |
1397 | __func__); |
1398 | return -EBUSY; | |
1399 | } | |
1400 | val = rc; | |
1401 | ||
1402 | rc = mb86a20s_readreg(state, 0x46); | |
1403 | if (rc < 0) | |
1404 | return rc; | |
1405 | cnr_linear = rc << 8; | |
1406 | ||
1407 | rc = mb86a20s_readreg(state, 0x46); | |
1408 | if (rc < 0) | |
1409 | return rc; | |
1410 | cnr_linear |= rc; | |
1411 | ||
1412 | cnr = interpolate_value(cnr_linear, | |
1413 | cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table)); | |
1414 | ||
1415 | c->cnr.stat[0].scale = FE_SCALE_DECIBEL; | |
1416 | c->cnr.stat[0].svalue = cnr; | |
1417 | ||
1418 | dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n", | |
1419 | __func__, cnr / 1000, cnr % 1000, cnr_linear); | |
1420 | ||
1421 | /* CNR counter reset */ | |
1422 | rc = mb86a20s_writereg(state, 0x45, val | 0x10); | |
1423 | if (rc < 0) | |
1424 | return rc; | |
1425 | rc = mb86a20s_writereg(state, 0x45, val & 0x6f); | |
1426 | ||
1427 | return rc; | |
1428 | } | |
1429 | ||
593ae89a | 1430 | static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe) |
25188bd0 MCC |
1431 | { |
1432 | struct mb86a20s_state *state = fe->demodulator_priv; | |
1433 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; | |
1434 | u32 mer, cnr; | |
5cb88ca8 | 1435 | int rc, val, layer; |
ce08131c | 1436 | const struct linear_segments *segs; |
25188bd0 MCC |
1437 | unsigned segs_len; |
1438 | ||
1439 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); | |
1440 | ||
1441 | /* Check if the measures are already available */ | |
1442 | rc = mb86a20s_writereg(state, 0x50, 0x5b); | |
1443 | if (rc < 0) | |
1444 | return rc; | |
1445 | rc = mb86a20s_readreg(state, 0x51); | |
1446 | if (rc < 0) | |
1447 | return rc; | |
1448 | ||
1449 | /* Check if data is available */ | |
1450 | if (!(rc & 0x01)) { | |
d56e326f | 1451 | dev_dbg(&state->i2c->dev, |
25188bd0 MCC |
1452 | "%s: MER measures aren't available yet.\n", __func__); |
1453 | return -EBUSY; | |
1454 | } | |
1455 | ||
1456 | /* Read all layers */ | |
5cb88ca8 MCC |
1457 | for (layer = 0; layer < NUM_LAYERS; layer++) { |
1458 | if (!(c->isdbt_layer_enabled & (1 << layer))) { | |
1459 | c->cnr.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; | |
25188bd0 MCC |
1460 | continue; |
1461 | } | |
1462 | ||
5cb88ca8 | 1463 | rc = mb86a20s_writereg(state, 0x50, 0x52 + layer * 3); |
25188bd0 MCC |
1464 | if (rc < 0) |
1465 | return rc; | |
1466 | rc = mb86a20s_readreg(state, 0x51); | |
1467 | if (rc < 0) | |
1468 | return rc; | |
1469 | mer = rc << 16; | |
5cb88ca8 | 1470 | rc = mb86a20s_writereg(state, 0x50, 0x53 + layer * 3); |
25188bd0 MCC |
1471 | if (rc < 0) |
1472 | return rc; | |
1473 | rc = mb86a20s_readreg(state, 0x51); | |
1474 | if (rc < 0) | |
1475 | return rc; | |
1476 | mer |= rc << 8; | |
5cb88ca8 | 1477 | rc = mb86a20s_writereg(state, 0x50, 0x54 + layer * 3); |
25188bd0 MCC |
1478 | if (rc < 0) |
1479 | return rc; | |
1480 | rc = mb86a20s_readreg(state, 0x51); | |
1481 | if (rc < 0) | |
1482 | return rc; | |
1483 | mer |= rc; | |
1484 | ||
5cb88ca8 | 1485 | switch (c->layer[layer].modulation) { |
25188bd0 MCC |
1486 | case DQPSK: |
1487 | case QPSK: | |
1488 | segs = cnr_qpsk_table; | |
1489 | segs_len = ARRAY_SIZE(cnr_qpsk_table); | |
1490 | break; | |
1491 | case QAM_16: | |
1492 | segs = cnr_16qam_table; | |
1493 | segs_len = ARRAY_SIZE(cnr_16qam_table); | |
1494 | break; | |
1495 | default: | |
1496 | case QAM_64: | |
1497 | segs = cnr_64qam_table; | |
1498 | segs_len = ARRAY_SIZE(cnr_64qam_table); | |
1499 | break; | |
1500 | } | |
1501 | cnr = interpolate_value(mer, segs, segs_len); | |
1502 | ||
5cb88ca8 MCC |
1503 | c->cnr.stat[1 + layer].scale = FE_SCALE_DECIBEL; |
1504 | c->cnr.stat[1 + layer].svalue = cnr; | |
25188bd0 MCC |
1505 | |
1506 | dev_dbg(&state->i2c->dev, | |
1507 | "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n", | |
5cb88ca8 | 1508 | __func__, 'A' + layer, cnr / 1000, cnr % 1000, mer); |
25188bd0 MCC |
1509 | |
1510 | } | |
1511 | ||
1512 | /* Start a new MER measurement */ | |
1513 | /* MER counter reset */ | |
1514 | rc = mb86a20s_writereg(state, 0x50, 0x50); | |
1515 | if (rc < 0) | |
1516 | return rc; | |
1517 | rc = mb86a20s_readreg(state, 0x51); | |
1518 | if (rc < 0) | |
1519 | return rc; | |
1520 | val = rc; | |
1521 | ||
1522 | rc = mb86a20s_writereg(state, 0x51, val | 0x01); | |
1523 | if (rc < 0) | |
1524 | return rc; | |
1525 | rc = mb86a20s_writereg(state, 0x51, val & 0x06); | |
1526 | if (rc < 0) | |
1527 | return rc; | |
1528 | ||
1529 | return 0; | |
1530 | } | |
1531 | ||
09b6d21e MCC |
1532 | static void mb86a20s_stats_not_ready(struct dvb_frontend *fe) |
1533 | { | |
1534 | struct mb86a20s_state *state = fe->demodulator_priv; | |
1535 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; | |
5cb88ca8 | 1536 | int layer; |
09b6d21e MCC |
1537 | |
1538 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); | |
a77cfcac | 1539 | |
09b6d21e MCC |
1540 | /* Fill the length of each status counter */ |
1541 | ||
1542 | /* Only global stats */ | |
1543 | c->strength.len = 1; | |
1544 | ||
1545 | /* Per-layer stats - 3 layers + global */ | |
4f62a20d MCC |
1546 | c->cnr.len = NUM_LAYERS + 1; |
1547 | c->pre_bit_error.len = NUM_LAYERS + 1; | |
1548 | c->pre_bit_count.len = NUM_LAYERS + 1; | |
1549 | c->post_bit_error.len = NUM_LAYERS + 1; | |
1550 | c->post_bit_count.len = NUM_LAYERS + 1; | |
1551 | c->block_error.len = NUM_LAYERS + 1; | |
1552 | c->block_count.len = NUM_LAYERS + 1; | |
09b6d21e MCC |
1553 | |
1554 | /* Signal is always available */ | |
1555 | c->strength.stat[0].scale = FE_SCALE_RELATIVE; | |
1556 | c->strength.stat[0].uvalue = 0; | |
1557 | ||
1558 | /* Put all of them at FE_SCALE_NOT_AVAILABLE */ | |
5cb88ca8 MCC |
1559 | for (layer = 0; layer < NUM_LAYERS + 1; layer++) { |
1560 | c->cnr.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; | |
1561 | c->pre_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; | |
1562 | c->pre_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; | |
1563 | c->post_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; | |
1564 | c->post_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; | |
1565 | c->block_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; | |
1566 | c->block_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; | |
09b6d21e | 1567 | } |
b9ede79a MCC |
1568 | } |
1569 | ||
15b1c5a0 | 1570 | static int mb86a20s_get_stats(struct dvb_frontend *fe, int status_nr) |
149d518a MCC |
1571 | { |
1572 | struct mb86a20s_state *state = fe->demodulator_priv; | |
1573 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; | |
5cb88ca8 | 1574 | int rc = 0, layer; |
149d518a MCC |
1575 | u32 bit_error = 0, bit_count = 0; |
1576 | u32 t_pre_bit_error = 0, t_pre_bit_count = 0; | |
d9b6f08a | 1577 | u32 t_post_bit_error = 0, t_post_bit_count = 0; |
593ae89a MCC |
1578 | u32 block_error = 0, block_count = 0; |
1579 | u32 t_block_error = 0, t_block_count = 0; | |
d9b6f08a MCC |
1580 | int active_layers = 0, pre_ber_layers = 0, post_ber_layers = 0; |
1581 | int per_layers = 0; | |
149d518a | 1582 | |
25188bd0 MCC |
1583 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); |
1584 | ||
1585 | mb86a20s_get_main_CNR(fe); | |
1586 | ||
149d518a | 1587 | /* Get per-layer stats */ |
593ae89a | 1588 | mb86a20s_get_blk_error_layer_CNR(fe); |
25188bd0 | 1589 | |
15b1c5a0 MCC |
1590 | /* |
1591 | * At state 7, only CNR is available | |
1592 | * For BER measures, state=9 is required | |
1593 | * FIXME: we may get MER measures with state=8 | |
1594 | */ | |
1595 | if (status_nr < 9) | |
1596 | return 0; | |
1597 | ||
5cb88ca8 MCC |
1598 | for (layer = 0; layer < NUM_LAYERS; layer++) { |
1599 | if (c->isdbt_layer_enabled & (1 << layer)) { | |
149d518a MCC |
1600 | /* Layer is active and has rc segments */ |
1601 | active_layers++; | |
1602 | ||
149d518a | 1603 | /* Handle BER before vterbi */ |
5cb88ca8 | 1604 | rc = mb86a20s_get_pre_ber(fe, layer, |
ad0abbf1 | 1605 | &bit_error, &bit_count); |
149d518a | 1606 | if (rc >= 0) { |
5cb88ca8 MCC |
1607 | c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER; |
1608 | c->pre_bit_error.stat[1 + layer].uvalue += bit_error; | |
1609 | c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER; | |
1610 | c->pre_bit_count.stat[1 + layer].uvalue += bit_count; | |
149d518a MCC |
1611 | } else if (rc != -EBUSY) { |
1612 | /* | |
1613 | * If an I/O error happened, | |
1614 | * measures are now unavailable | |
1615 | */ | |
5cb88ca8 MCC |
1616 | c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; |
1617 | c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; | |
149d518a MCC |
1618 | dev_err(&state->i2c->dev, |
1619 | "%s: Can't get BER for layer %c (error %d).\n", | |
5cb88ca8 | 1620 | __func__, 'A' + layer, rc); |
149d518a | 1621 | } |
5cb88ca8 | 1622 | if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE) |
d9b6f08a MCC |
1623 | pre_ber_layers++; |
1624 | ||
1625 | /* Handle BER post vterbi */ | |
5cb88ca8 | 1626 | rc = mb86a20s_get_post_ber(fe, layer, |
d9b6f08a MCC |
1627 | &bit_error, &bit_count); |
1628 | if (rc >= 0) { | |
5cb88ca8 MCC |
1629 | c->post_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER; |
1630 | c->post_bit_error.stat[1 + layer].uvalue += bit_error; | |
1631 | c->post_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER; | |
1632 | c->post_bit_count.stat[1 + layer].uvalue += bit_count; | |
d9b6f08a MCC |
1633 | } else if (rc != -EBUSY) { |
1634 | /* | |
1635 | * If an I/O error happened, | |
1636 | * measures are now unavailable | |
1637 | */ | |
5cb88ca8 MCC |
1638 | c->post_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; |
1639 | c->post_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; | |
d9b6f08a MCC |
1640 | dev_err(&state->i2c->dev, |
1641 | "%s: Can't get BER for layer %c (error %d).\n", | |
5cb88ca8 | 1642 | __func__, 'A' + layer, rc); |
d9b6f08a | 1643 | } |
5cb88ca8 | 1644 | if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE) |
d9b6f08a | 1645 | post_ber_layers++; |
149d518a | 1646 | |
593ae89a | 1647 | /* Handle Block errors for PER/UCB reports */ |
5cb88ca8 | 1648 | rc = mb86a20s_get_blk_error(fe, layer, |
593ae89a MCC |
1649 | &block_error, |
1650 | &block_count); | |
1651 | if (rc >= 0) { | |
5cb88ca8 MCC |
1652 | c->block_error.stat[1 + layer].scale = FE_SCALE_COUNTER; |
1653 | c->block_error.stat[1 + layer].uvalue += block_error; | |
1654 | c->block_count.stat[1 + layer].scale = FE_SCALE_COUNTER; | |
1655 | c->block_count.stat[1 + layer].uvalue += block_count; | |
593ae89a MCC |
1656 | } else if (rc != -EBUSY) { |
1657 | /* | |
1658 | * If an I/O error happened, | |
1659 | * measures are now unavailable | |
1660 | */ | |
5cb88ca8 MCC |
1661 | c->block_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; |
1662 | c->block_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; | |
593ae89a MCC |
1663 | dev_err(&state->i2c->dev, |
1664 | "%s: Can't get PER for layer %c (error %d).\n", | |
5cb88ca8 | 1665 | __func__, 'A' + layer, rc); |
593ae89a MCC |
1666 | |
1667 | } | |
5cb88ca8 | 1668 | if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE) |
593ae89a MCC |
1669 | per_layers++; |
1670 | ||
d9b6f08a | 1671 | /* Update total preBER */ |
5cb88ca8 MCC |
1672 | t_pre_bit_error += c->pre_bit_error.stat[1 + layer].uvalue; |
1673 | t_pre_bit_count += c->pre_bit_count.stat[1 + layer].uvalue; | |
593ae89a | 1674 | |
d9b6f08a | 1675 | /* Update total postBER */ |
5cb88ca8 MCC |
1676 | t_post_bit_error += c->post_bit_error.stat[1 + layer].uvalue; |
1677 | t_post_bit_count += c->post_bit_count.stat[1 + layer].uvalue; | |
d9b6f08a | 1678 | |
593ae89a | 1679 | /* Update total PER */ |
5cb88ca8 MCC |
1680 | t_block_error += c->block_error.stat[1 + layer].uvalue; |
1681 | t_block_count += c->block_count.stat[1 + layer].uvalue; | |
149d518a MCC |
1682 | } |
1683 | } | |
1684 | ||
1685 | /* | |
1686 | * Start showing global count if at least one error count is | |
1687 | * available. | |
1688 | */ | |
d9b6f08a | 1689 | if (pre_ber_layers) { |
149d518a MCC |
1690 | /* |
1691 | * At least one per-layer BER measure was read. We can now | |
1692 | * calculate the total BER | |
1693 | * | |
1694 | * Total Bit Error/Count is calculated as the sum of the | |
1695 | * bit errors on all active layers. | |
1696 | */ | |
1697 | c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; | |
1698 | c->pre_bit_error.stat[0].uvalue = t_pre_bit_error; | |
1699 | c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; | |
1700 | c->pre_bit_count.stat[0].uvalue = t_pre_bit_count; | |
f67102c4 MCC |
1701 | } else { |
1702 | c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
1703 | c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; | |
149d518a MCC |
1704 | } |
1705 | ||
d9b6f08a MCC |
1706 | /* |
1707 | * Start showing global count if at least one error count is | |
1708 | * available. | |
1709 | */ | |
1710 | if (post_ber_layers) { | |
1711 | /* | |
1712 | * At least one per-layer BER measure was read. We can now | |
1713 | * calculate the total BER | |
1714 | * | |
1715 | * Total Bit Error/Count is calculated as the sum of the | |
1716 | * bit errors on all active layers. | |
1717 | */ | |
1718 | c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; | |
1719 | c->post_bit_error.stat[0].uvalue = t_post_bit_error; | |
1720 | c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; | |
1721 | c->post_bit_count.stat[0].uvalue = t_post_bit_count; | |
f67102c4 MCC |
1722 | } else { |
1723 | c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
1724 | c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; | |
d9b6f08a MCC |
1725 | } |
1726 | ||
593ae89a MCC |
1727 | if (per_layers) { |
1728 | /* | |
1729 | * At least one per-layer UCB measure was read. We can now | |
1730 | * calculate the total UCB | |
1731 | * | |
1732 | * Total block Error/Count is calculated as the sum of the | |
1733 | * block errors on all active layers. | |
1734 | */ | |
1735 | c->block_error.stat[0].scale = FE_SCALE_COUNTER; | |
1736 | c->block_error.stat[0].uvalue = t_block_error; | |
1737 | c->block_count.stat[0].scale = FE_SCALE_COUNTER; | |
1738 | c->block_count.stat[0].uvalue = t_block_count; | |
f67102c4 MCC |
1739 | } else { |
1740 | c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
1741 | c->block_count.stat[0].scale = FE_SCALE_COUNTER; | |
593ae89a MCC |
1742 | } |
1743 | ||
149d518a MCC |
1744 | return rc; |
1745 | } | |
09b6d21e MCC |
1746 | |
1747 | /* | |
1748 | * The functions below are called via DVB callbacks, so they need to | |
1749 | * properly use the I2C gate control | |
1750 | */ | |
1751 | ||
dd4493ef MCC |
1752 | static int mb86a20s_initfe(struct dvb_frontend *fe) |
1753 | { | |
1754 | struct mb86a20s_state *state = fe->demodulator_priv; | |
768e6dad | 1755 | u64 pll; |
0e4bbedd | 1756 | u32 fclk; |
dd4493ef | 1757 | int rc; |
04fa725e | 1758 | u8 regD5 = 1, reg71, reg09 = 0x3a; |
dd4493ef | 1759 | |
f66d81b5 | 1760 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); |
dd4493ef MCC |
1761 | |
1762 | if (fe->ops.i2c_gate_ctrl) | |
1763 | fe->ops.i2c_gate_ctrl(fe, 0); | |
1764 | ||
1765 | /* Initialize the frontend */ | |
768e6dad | 1766 | rc = mb86a20s_writeregdata(state, mb86a20s_init1); |
dd4493ef MCC |
1767 | if (rc < 0) |
1768 | goto err; | |
1769 | ||
04fa725e MCC |
1770 | if (!state->inversion) |
1771 | reg09 |= 0x04; | |
1772 | rc = mb86a20s_writereg(state, 0x09, reg09); | |
1773 | if (rc < 0) | |
1774 | goto err; | |
1775 | if (!state->bw) | |
1776 | reg71 = 1; | |
1777 | else | |
1778 | reg71 = 0; | |
1779 | rc = mb86a20s_writereg(state, 0x39, reg71); | |
1780 | if (rc < 0) | |
1781 | goto err; | |
1782 | rc = mb86a20s_writereg(state, 0x71, state->bw); | |
1783 | if (rc < 0) | |
1784 | goto err; | |
1785 | if (state->subchannel) { | |
1786 | rc = mb86a20s_writereg(state, 0x44, state->subchannel); | |
1787 | if (rc < 0) | |
1788 | goto err; | |
1789 | } | |
1790 | ||
0e4bbedd MCC |
1791 | fclk = state->config->fclk; |
1792 | if (!fclk) | |
1793 | fclk = 32571428; | |
1794 | ||
768e6dad MCC |
1795 | /* Adjust IF frequency to match tuner */ |
1796 | if (fe->ops.tuner_ops.get_if_frequency) | |
1797 | fe->ops.tuner_ops.get_if_frequency(fe, &state->if_freq); | |
1798 | ||
1799 | if (!state->if_freq) | |
1800 | state->if_freq = 3300000; | |
1801 | ||
0e4bbedd MCC |
1802 | pll = (((u64)1) << 34) * state->if_freq; |
1803 | do_div(pll, 63 * fclk); | |
1804 | pll = (1 << 25) - pll; | |
1805 | rc = mb86a20s_writereg(state, 0x28, 0x2a); | |
1806 | if (rc < 0) | |
1807 | goto err; | |
1808 | rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff); | |
1809 | if (rc < 0) | |
1810 | goto err; | |
1811 | rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff); | |
1812 | if (rc < 0) | |
1813 | goto err; | |
1814 | rc = mb86a20s_writereg(state, 0x2b, pll & 0xff); | |
1815 | if (rc < 0) | |
1816 | goto err; | |
1817 | dev_dbg(&state->i2c->dev, "%s: fclk=%d, IF=%d, clock reg=0x%06llx\n", | |
1818 | __func__, fclk, state->if_freq, (long long)pll); | |
1819 | ||
768e6dad MCC |
1820 | /* pll = freq[Hz] * 2^24/10^6 / 16.285714286 */ |
1821 | pll = state->if_freq * 1677721600L; | |
1822 | do_div(pll, 1628571429L); | |
1823 | rc = mb86a20s_writereg(state, 0x28, 0x20); | |
1824 | if (rc < 0) | |
1825 | goto err; | |
1826 | rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff); | |
1827 | if (rc < 0) | |
1828 | goto err; | |
1829 | rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff); | |
1830 | if (rc < 0) | |
1831 | goto err; | |
1832 | rc = mb86a20s_writereg(state, 0x2b, pll & 0xff); | |
1833 | if (rc < 0) | |
1834 | goto err; | |
0e4bbedd | 1835 | dev_dbg(&state->i2c->dev, "%s: IF=%d, IF reg=0x%06llx\n", |
768e6dad MCC |
1836 | __func__, state->if_freq, (long long)pll); |
1837 | ||
9d32069f | 1838 | if (!state->config->is_serial) |
dd4493ef MCC |
1839 | regD5 &= ~1; |
1840 | ||
9d32069f MCC |
1841 | rc = mb86a20s_writereg(state, 0x50, 0xd5); |
1842 | if (rc < 0) | |
1843 | goto err; | |
1844 | rc = mb86a20s_writereg(state, 0x51, regD5); | |
1845 | if (rc < 0) | |
1846 | goto err; | |
dd4493ef | 1847 | |
768e6dad MCC |
1848 | rc = mb86a20s_writeregdata(state, mb86a20s_init2); |
1849 | if (rc < 0) | |
1850 | goto err; | |
1851 | ||
1852 | ||
dd4493ef MCC |
1853 | err: |
1854 | if (fe->ops.i2c_gate_ctrl) | |
1855 | fe->ops.i2c_gate_ctrl(fe, 1); | |
1856 | ||
1857 | if (rc < 0) { | |
1858 | state->need_init = true; | |
f66d81b5 MCC |
1859 | dev_info(&state->i2c->dev, |
1860 | "mb86a20s: Init failed. Will try again later\n"); | |
dd4493ef MCC |
1861 | } else { |
1862 | state->need_init = false; | |
f66d81b5 | 1863 | dev_dbg(&state->i2c->dev, "Initialization succeeded.\n"); |
dd4493ef MCC |
1864 | } |
1865 | return rc; | |
1866 | } | |
1867 | ||
1868 | static int mb86a20s_set_frontend(struct dvb_frontend *fe) | |
1869 | { | |
1870 | struct mb86a20s_state *state = fe->demodulator_priv; | |
dd4493ef | 1871 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
04fa725e | 1872 | int rc, if_freq; |
f66d81b5 | 1873 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); |
dd4493ef | 1874 | |
04fa725e MCC |
1875 | if (!c->isdbt_layer_enabled) |
1876 | c->isdbt_layer_enabled = 7; | |
1877 | ||
1878 | if (c->isdbt_layer_enabled == 1) | |
1879 | state->bw = MB86A20S_1SEG; | |
1880 | else if (c->isdbt_partial_reception) | |
1881 | state->bw = MB86A20S_13SEG_PARTIAL; | |
1882 | else | |
1883 | state->bw = MB86A20S_13SEG; | |
1884 | ||
1885 | if (c->inversion == INVERSION_ON) | |
1886 | state->inversion = true; | |
1887 | else | |
1888 | state->inversion = false; | |
1889 | ||
1890 | if (!c->isdbt_sb_mode) { | |
1891 | state->subchannel = 0; | |
1892 | } else { | |
41c6e9dd | 1893 | if (c->isdbt_sb_subchannel >= ARRAY_SIZE(mb86a20s_subchannel)) |
04fa725e MCC |
1894 | c->isdbt_sb_subchannel = 0; |
1895 | ||
1896 | state->subchannel = mb86a20s_subchannel[c->isdbt_sb_subchannel]; | |
1897 | } | |
1898 | ||
dd4493ef MCC |
1899 | /* |
1900 | * Gate should already be opened, but it doesn't hurt to | |
1901 | * double-check | |
1902 | */ | |
1903 | if (fe->ops.i2c_gate_ctrl) | |
1904 | fe->ops.i2c_gate_ctrl(fe, 1); | |
dd4493ef MCC |
1905 | fe->ops.tuner_ops.set_params(fe); |
1906 | ||
a78b41d5 | 1907 | if (fe->ops.tuner_ops.get_if_frequency) |
768e6dad MCC |
1908 | fe->ops.tuner_ops.get_if_frequency(fe, &if_freq); |
1909 | ||
dd4493ef MCC |
1910 | /* |
1911 | * Make it more reliable: if, for some reason, the initial | |
1912 | * device initialization doesn't happen, initialize it when | |
1913 | * a SBTVD parameters are adjusted. | |
1914 | * | |
1915 | * Unfortunately, due to a hard to track bug at tda829x/tda18271, | |
1916 | * the agc callback logic is not called during DVB attach time, | |
1917 | * causing mb86a20s to not be initialized with Kworld SBTVD. | |
1918 | * So, this hack is needed, in order to make Kworld SBTVD to work. | |
768e6dad MCC |
1919 | * |
1920 | * It is also needed to change the IF after the initial init. | |
a78b41d5 MCC |
1921 | * |
1922 | * HACK: Always init the frontend when set_frontend is called: | |
1923 | * it was noticed that, on some devices, it fails to lock on a | |
1924 | * different channel. So, it is better to reset everything, even | |
1925 | * wasting some time, than to loose channel lock. | |
dd4493ef | 1926 | */ |
a78b41d5 | 1927 | mb86a20s_initfe(fe); |
dd4493ef MCC |
1928 | |
1929 | if (fe->ops.i2c_gate_ctrl) | |
1930 | fe->ops.i2c_gate_ctrl(fe, 0); | |
d01a8ee3 | 1931 | |
dd4493ef | 1932 | rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception); |
09b6d21e | 1933 | mb86a20s_reset_counters(fe); |
3a2e4751 | 1934 | mb86a20s_stats_not_ready(fe); |
d01a8ee3 | 1935 | |
dd4493ef MCC |
1936 | if (fe->ops.i2c_gate_ctrl) |
1937 | fe->ops.i2c_gate_ctrl(fe, 1); | |
1938 | ||
1939 | return rc; | |
1940 | } | |
1941 | ||
09b6d21e | 1942 | static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe, |
0df289a2 | 1943 | enum fe_status *status) |
d36e418a | 1944 | { |
09b6d21e | 1945 | struct mb86a20s_state *state = fe->demodulator_priv; |
15b1c5a0 | 1946 | int rc, status_nr; |
d36e418a | 1947 | |
09b6d21e | 1948 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); |
d36e418a MCC |
1949 | |
1950 | if (fe->ops.i2c_gate_ctrl) | |
1951 | fe->ops.i2c_gate_ctrl(fe, 0); | |
1952 | ||
09b6d21e | 1953 | /* Get lock */ |
15b1c5a0 MCC |
1954 | status_nr = mb86a20s_read_status(fe, status); |
1955 | if (status_nr < 7) { | |
09b6d21e MCC |
1956 | mb86a20s_stats_not_ready(fe); |
1957 | mb86a20s_reset_frontend_cache(fe); | |
1958 | } | |
15b1c5a0 | 1959 | if (status_nr < 0) { |
149d518a MCC |
1960 | dev_err(&state->i2c->dev, |
1961 | "%s: Can't read frontend lock status\n", __func__); | |
19157003 | 1962 | rc = status_nr; |
09b6d21e | 1963 | goto error; |
149d518a | 1964 | } |
09b6d21e MCC |
1965 | |
1966 | /* Get signal strength */ | |
1967 | rc = mb86a20s_read_signal_strength(fe); | |
1968 | if (rc < 0) { | |
149d518a MCC |
1969 | dev_err(&state->i2c->dev, |
1970 | "%s: Can't reset VBER registers.\n", __func__); | |
09b6d21e MCC |
1971 | mb86a20s_stats_not_ready(fe); |
1972 | mb86a20s_reset_frontend_cache(fe); | |
149d518a MCC |
1973 | |
1974 | rc = 0; /* Status is OK */ | |
09b6d21e MCC |
1975 | goto error; |
1976 | } | |
09b6d21e | 1977 | |
15b1c5a0 | 1978 | if (status_nr >= 7) { |
09b6d21e MCC |
1979 | /* Get TMCC info*/ |
1980 | rc = mb86a20s_get_frontend(fe); | |
149d518a MCC |
1981 | if (rc < 0) { |
1982 | dev_err(&state->i2c->dev, | |
1983 | "%s: Can't get FE TMCC data.\n", __func__); | |
1984 | rc = 0; /* Status is OK */ | |
1985 | goto error; | |
1986 | } | |
1987 | ||
1988 | /* Get statistics */ | |
15b1c5a0 | 1989 | rc = mb86a20s_get_stats(fe, status_nr); |
149d518a MCC |
1990 | if (rc < 0 && rc != -EBUSY) { |
1991 | dev_err(&state->i2c->dev, | |
1992 | "%s: Can't get FE statistics.\n", __func__); | |
1993 | rc = 0; | |
09b6d21e | 1994 | goto error; |
149d518a MCC |
1995 | } |
1996 | rc = 0; /* Don't return EBUSY to userspace */ | |
09b6d21e | 1997 | } |
149d518a | 1998 | goto ok; |
09b6d21e | 1999 | |
149d518a | 2000 | error: |
09b6d21e | 2001 | mb86a20s_stats_not_ready(fe); |
d36e418a | 2002 | |
149d518a | 2003 | ok: |
d36e418a MCC |
2004 | if (fe->ops.i2c_gate_ctrl) |
2005 | fe->ops.i2c_gate_ctrl(fe, 1); | |
149d518a | 2006 | |
09b6d21e MCC |
2007 | return rc; |
2008 | } | |
2009 | ||
2010 | static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe, | |
2011 | u16 *strength) | |
2012 | { | |
2013 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; | |
2014 | ||
2015 | ||
2016 | *strength = c->strength.stat[0].uvalue; | |
d36e418a | 2017 | |
09b6d21e | 2018 | return 0; |
d36e418a MCC |
2019 | } |
2020 | ||
b9ede79a | 2021 | static int mb86a20s_tune(struct dvb_frontend *fe, |
7e072221 | 2022 | bool re_tune, |
b9ede79a MCC |
2023 | unsigned int mode_flags, |
2024 | unsigned int *delay, | |
0df289a2 | 2025 | enum fe_status *status) |
b9ede79a | 2026 | { |
f66d81b5 | 2027 | struct mb86a20s_state *state = fe->demodulator_priv; |
b9ede79a MCC |
2028 | int rc = 0; |
2029 | ||
f66d81b5 | 2030 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); |
b9ede79a | 2031 | |
7e072221 | 2032 | if (re_tune) |
2d76e22b | 2033 | rc = mb86a20s_set_frontend(fe); |
b9ede79a MCC |
2034 | |
2035 | if (!(mode_flags & FE_TUNE_MODE_ONESHOT)) | |
09b6d21e | 2036 | mb86a20s_read_status_and_stats(fe, status); |
b9ede79a MCC |
2037 | |
2038 | return rc; | |
2039 | } | |
2040 | ||
2041 | static void mb86a20s_release(struct dvb_frontend *fe) | |
2042 | { | |
2043 | struct mb86a20s_state *state = fe->demodulator_priv; | |
2044 | ||
f66d81b5 | 2045 | dev_dbg(&state->i2c->dev, "%s called.\n", __func__); |
b9ede79a MCC |
2046 | |
2047 | kfree(state); | |
2048 | } | |
2049 | ||
8d718e53 | 2050 | static enum dvbfe_algo mb86a20s_get_frontend_algo(struct dvb_frontend *fe) |
dafb65fb | 2051 | { |
4a3fad70 | 2052 | return DVBFE_ALGO_HW; |
dafb65fb MCC |
2053 | } |
2054 | ||
bd336e63 | 2055 | static const struct dvb_frontend_ops mb86a20s_ops; |
b9ede79a MCC |
2056 | |
2057 | struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config, | |
2058 | struct i2c_adapter *i2c) | |
2059 | { | |
f66d81b5 | 2060 | struct mb86a20s_state *state; |
b9ede79a MCC |
2061 | u8 rev; |
2062 | ||
f167e302 MCC |
2063 | dev_dbg(&i2c->dev, "%s called.\n", __func__); |
2064 | ||
b9ede79a | 2065 | /* allocate memory for the internal state */ |
2d3da59f | 2066 | state = kzalloc(sizeof(*state), GFP_KERNEL); |
c38e8657 | 2067 | if (!state) |
9722e569 | 2068 | return NULL; |
b9ede79a MCC |
2069 | |
2070 | /* setup the state */ | |
2071 | state->config = config; | |
2072 | state->i2c = i2c; | |
2073 | ||
2074 | /* create dvb_frontend */ | |
2075 | memcpy(&state->frontend.ops, &mb86a20s_ops, | |
2076 | sizeof(struct dvb_frontend_ops)); | |
2077 | state->frontend.demodulator_priv = state; | |
2078 | ||
2079 | /* Check if it is a mb86a20s frontend */ | |
2080 | rev = mb86a20s_readreg(state, 0); | |
9722e569 ME |
2081 | if (rev != 0x13) { |
2082 | kfree(state); | |
f167e302 | 2083 | dev_dbg(&i2c->dev, |
f66d81b5 | 2084 | "Frontend revision %d is unknown - aborting.\n", |
b9ede79a | 2085 | rev); |
9722e569 | 2086 | return NULL; |
b9ede79a MCC |
2087 | } |
2088 | ||
9722e569 | 2089 | dev_info(&i2c->dev, "Detected a Fujitsu mb86a20s frontend\n"); |
b9ede79a | 2090 | return &state->frontend; |
b9ede79a MCC |
2091 | } |
2092 | EXPORT_SYMBOL(mb86a20s_attach); | |
2093 | ||
bd336e63 | 2094 | static const struct dvb_frontend_ops mb86a20s_ops = { |
2d76e22b | 2095 | .delsys = { SYS_ISDBT }, |
b9ede79a MCC |
2096 | /* Use dib8000 values per default */ |
2097 | .info = { | |
2098 | .name = "Fujitsu mb86A20s", | |
04fa725e | 2099 | .caps = FE_CAN_RECOVER | |
b9ede79a MCC |
2100 | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | |
2101 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | | |
2102 | FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | | |
2103 | FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO | | |
2104 | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO, | |
2105 | /* Actually, those values depend on the used tuner */ | |
f1b1eabf MCC |
2106 | .frequency_min_hz = 45 * MHz, |
2107 | .frequency_max_hz = 864 * MHz, | |
2108 | .frequency_stepsize_hz = 62500, | |
b9ede79a MCC |
2109 | }, |
2110 | ||
2111 | .release = mb86a20s_release, | |
2112 | ||
2113 | .init = mb86a20s_initfe, | |
2d76e22b | 2114 | .set_frontend = mb86a20s_set_frontend, |
09b6d21e MCC |
2115 | .read_status = mb86a20s_read_status_and_stats, |
2116 | .read_signal_strength = mb86a20s_read_signal_strength_from_cache, | |
b9ede79a | 2117 | .tune = mb86a20s_tune, |
dafb65fb | 2118 | .get_frontend_algo = mb86a20s_get_frontend_algo, |
b9ede79a MCC |
2119 | }; |
2120 | ||
2121 | MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware"); | |
37e59f87 | 2122 | MODULE_AUTHOR("Mauro Carvalho Chehab"); |
b9ede79a | 2123 | MODULE_LICENSE("GPL"); |