Commit | Line | Data |
---|---|---|
395d00d1 | 1 | /* |
7978b8a1 | 2 | * Montage Technology M88DS3103/M88RS6000 demodulator driver |
395d00d1 AP |
3 | * |
4 | * Copyright (C) 2013 Antti Palosaari <crope@iki.fi> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
395d00d1 AP |
15 | */ |
16 | ||
17 | #include "m88ds3103_priv.h" | |
18 | ||
bd336e63 | 19 | static const struct dvb_frontend_ops m88ds3103_ops; |
395d00d1 | 20 | |
56ea37da AP |
21 | /* write single register with mask */ |
22 | static int m88ds3103_update_bits(struct m88ds3103_dev *dev, | |
23 | u8 reg, u8 mask, u8 val) | |
24 | { | |
25 | int ret; | |
26 | u8 tmp; | |
27 | ||
28 | /* no need for read if whole reg is written */ | |
29 | if (mask != 0xff) { | |
30 | ret = regmap_bulk_read(dev->regmap, reg, &tmp, 1); | |
31 | if (ret) | |
32 | return ret; | |
33 | ||
34 | val &= mask; | |
35 | tmp &= ~mask; | |
36 | val |= tmp; | |
37 | } | |
38 | ||
39 | return regmap_bulk_write(dev->regmap, reg, &val, 1); | |
40 | } | |
41 | ||
06487dee | 42 | /* write reg val table using reg addr auto increment */ |
7978b8a1 | 43 | static int m88ds3103_wr_reg_val_tab(struct m88ds3103_dev *dev, |
06487dee AP |
44 | const struct m88ds3103_reg_val *tab, int tab_len) |
45 | { | |
7978b8a1 | 46 | struct i2c_client *client = dev->client; |
06487dee AP |
47 | int ret, i, j; |
48 | u8 buf[83]; | |
41b9aa00 | 49 | |
7978b8a1 | 50 | dev_dbg(&client->dev, "tab_len=%d\n", tab_len); |
06487dee | 51 | |
f4df95bc | 52 | if (tab_len > 86) { |
06487dee AP |
53 | ret = -EINVAL; |
54 | goto err; | |
55 | } | |
56 | ||
57 | for (i = 0, j = 0; i < tab_len; i++, j++) { | |
58 | buf[j] = tab[i].val; | |
59 | ||
60 | if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 || | |
7978b8a1 | 61 | !((j + 1) % (dev->cfg->i2c_wr_max - 1))) { |
478932b1 | 62 | ret = regmap_bulk_write(dev->regmap, tab[i].reg - j, buf, j + 1); |
06487dee AP |
63 | if (ret) |
64 | goto err; | |
65 | ||
66 | j = -1; | |
67 | } | |
68 | } | |
69 | ||
70 | return 0; | |
71 | err: | |
7978b8a1 | 72 | dev_dbg(&client->dev, "failed=%d\n", ret); |
06487dee AP |
73 | return ret; |
74 | } | |
75 | ||
0f91c9d6 DH |
76 | /* |
77 | * Get the demodulator AGC PWM voltage setting supplied to the tuner. | |
78 | */ | |
79 | int m88ds3103_get_agc_pwm(struct dvb_frontend *fe, u8 *_agc_pwm) | |
80 | { | |
81 | struct m88ds3103_dev *dev = fe->demodulator_priv; | |
82 | unsigned tmp; | |
83 | int ret; | |
84 | ||
85 | ret = regmap_read(dev->regmap, 0x3f, &tmp); | |
86 | if (ret == 0) | |
87 | *_agc_pwm = tmp; | |
88 | return ret; | |
89 | } | |
90 | EXPORT_SYMBOL(m88ds3103_get_agc_pwm); | |
91 | ||
0df289a2 MCC |
92 | static int m88ds3103_read_status(struct dvb_frontend *fe, |
93 | enum fe_status *status) | |
395d00d1 | 94 | { |
7978b8a1 AP |
95 | struct m88ds3103_dev *dev = fe->demodulator_priv; |
96 | struct i2c_client *client = dev->client; | |
395d00d1 | 97 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
c1daf651 | 98 | int ret, i, itmp; |
478932b1 | 99 | unsigned int utmp; |
c1daf651 | 100 | u8 buf[3]; |
395d00d1 AP |
101 | |
102 | *status = 0; | |
103 | ||
7978b8a1 | 104 | if (!dev->warm) { |
395d00d1 AP |
105 | ret = -EAGAIN; |
106 | goto err; | |
107 | } | |
108 | ||
109 | switch (c->delivery_system) { | |
110 | case SYS_DVBS: | |
478932b1 | 111 | ret = regmap_read(dev->regmap, 0xd1, &utmp); |
395d00d1 AP |
112 | if (ret) |
113 | goto err; | |
114 | ||
478932b1 | 115 | if ((utmp & 0x07) == 0x07) |
395d00d1 AP |
116 | *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | |
117 | FE_HAS_VITERBI | FE_HAS_SYNC | | |
118 | FE_HAS_LOCK; | |
119 | break; | |
120 | case SYS_DVBS2: | |
478932b1 | 121 | ret = regmap_read(dev->regmap, 0x0d, &utmp); |
395d00d1 AP |
122 | if (ret) |
123 | goto err; | |
124 | ||
478932b1 | 125 | if ((utmp & 0x8f) == 0x8f) |
395d00d1 AP |
126 | *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | |
127 | FE_HAS_VITERBI | FE_HAS_SYNC | | |
128 | FE_HAS_LOCK; | |
129 | break; | |
130 | default: | |
7978b8a1 | 131 | dev_dbg(&client->dev, "invalid delivery_system\n"); |
395d00d1 AP |
132 | ret = -EINVAL; |
133 | goto err; | |
134 | } | |
135 | ||
7978b8a1 | 136 | dev->fe_status = *status; |
478932b1 | 137 | dev_dbg(&client->dev, "lock=%02x status=%02x\n", utmp, *status); |
395d00d1 | 138 | |
c1daf651 | 139 | /* CNR */ |
7978b8a1 | 140 | if (dev->fe_status & FE_HAS_VITERBI) { |
c1daf651 AP |
141 | unsigned int cnr, noise, signal, noise_tot, signal_tot; |
142 | ||
143 | cnr = 0; | |
144 | /* more iterations for more accurate estimation */ | |
145 | #define M88DS3103_SNR_ITERATIONS 3 | |
146 | ||
147 | switch (c->delivery_system) { | |
148 | case SYS_DVBS: | |
149 | itmp = 0; | |
150 | ||
151 | for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) { | |
478932b1 | 152 | ret = regmap_read(dev->regmap, 0xff, &utmp); |
c1daf651 AP |
153 | if (ret) |
154 | goto err; | |
155 | ||
478932b1 | 156 | itmp += utmp; |
c1daf651 AP |
157 | } |
158 | ||
159 | /* use of single register limits max value to 15 dB */ | |
160 | /* SNR(X) dB = 10 * ln(X) / ln(10) dB */ | |
161 | itmp = DIV_ROUND_CLOSEST(itmp, 8 * M88DS3103_SNR_ITERATIONS); | |
162 | if (itmp) | |
163 | cnr = div_u64((u64) 10000 * intlog2(itmp), intlog2(10)); | |
164 | break; | |
165 | case SYS_DVBS2: | |
166 | noise_tot = 0; | |
167 | signal_tot = 0; | |
168 | ||
169 | for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) { | |
478932b1 | 170 | ret = regmap_bulk_read(dev->regmap, 0x8c, buf, 3); |
c1daf651 AP |
171 | if (ret) |
172 | goto err; | |
173 | ||
174 | noise = buf[1] << 6; /* [13:6] */ | |
175 | noise |= buf[0] & 0x3f; /* [5:0] */ | |
176 | noise >>= 2; | |
177 | signal = buf[2] * buf[2]; | |
178 | signal >>= 1; | |
179 | ||
180 | noise_tot += noise; | |
181 | signal_tot += signal; | |
182 | } | |
183 | ||
184 | noise = noise_tot / M88DS3103_SNR_ITERATIONS; | |
185 | signal = signal_tot / M88DS3103_SNR_ITERATIONS; | |
186 | ||
187 | /* SNR(X) dB = 10 * log10(X) dB */ | |
188 | if (signal > noise) { | |
189 | itmp = signal / noise; | |
190 | cnr = div_u64((u64) 10000 * intlog10(itmp), (1 << 24)); | |
191 | } | |
192 | break; | |
193 | default: | |
7978b8a1 | 194 | dev_dbg(&client->dev, "invalid delivery_system\n"); |
c1daf651 AP |
195 | ret = -EINVAL; |
196 | goto err; | |
197 | } | |
198 | ||
199 | if (cnr) { | |
200 | c->cnr.stat[0].scale = FE_SCALE_DECIBEL; | |
201 | c->cnr.stat[0].svalue = cnr; | |
202 | } else { | |
203 | c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
204 | } | |
205 | } else { | |
206 | c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
207 | } | |
208 | ||
ce80d713 | 209 | /* BER */ |
7978b8a1 | 210 | if (dev->fe_status & FE_HAS_LOCK) { |
ce80d713 AP |
211 | unsigned int utmp, post_bit_error, post_bit_count; |
212 | ||
213 | switch (c->delivery_system) { | |
214 | case SYS_DVBS: | |
478932b1 | 215 | ret = regmap_write(dev->regmap, 0xf9, 0x04); |
ce80d713 AP |
216 | if (ret) |
217 | goto err; | |
218 | ||
478932b1 | 219 | ret = regmap_read(dev->regmap, 0xf8, &utmp); |
ce80d713 AP |
220 | if (ret) |
221 | goto err; | |
222 | ||
223 | /* measurement ready? */ | |
478932b1 AP |
224 | if (!(utmp & 0x10)) { |
225 | ret = regmap_bulk_read(dev->regmap, 0xf6, buf, 2); | |
ce80d713 AP |
226 | if (ret) |
227 | goto err; | |
228 | ||
229 | post_bit_error = buf[1] << 8 | buf[0] << 0; | |
230 | post_bit_count = 0x800000; | |
7978b8a1 AP |
231 | dev->post_bit_error += post_bit_error; |
232 | dev->post_bit_count += post_bit_count; | |
233 | dev->dvbv3_ber = post_bit_error; | |
ce80d713 AP |
234 | |
235 | /* restart measurement */ | |
478932b1 AP |
236 | utmp |= 0x10; |
237 | ret = regmap_write(dev->regmap, 0xf8, utmp); | |
ce80d713 AP |
238 | if (ret) |
239 | goto err; | |
240 | } | |
241 | break; | |
242 | case SYS_DVBS2: | |
478932b1 | 243 | ret = regmap_bulk_read(dev->regmap, 0xd5, buf, 3); |
ce80d713 AP |
244 | if (ret) |
245 | goto err; | |
246 | ||
247 | utmp = buf[2] << 16 | buf[1] << 8 | buf[0] << 0; | |
248 | ||
249 | /* enough data? */ | |
250 | if (utmp > 4000) { | |
478932b1 | 251 | ret = regmap_bulk_read(dev->regmap, 0xf7, buf, 2); |
ce80d713 AP |
252 | if (ret) |
253 | goto err; | |
254 | ||
255 | post_bit_error = buf[1] << 8 | buf[0] << 0; | |
256 | post_bit_count = 32 * utmp; /* TODO: FEC */ | |
7978b8a1 AP |
257 | dev->post_bit_error += post_bit_error; |
258 | dev->post_bit_count += post_bit_count; | |
259 | dev->dvbv3_ber = post_bit_error; | |
ce80d713 AP |
260 | |
261 | /* restart measurement */ | |
478932b1 | 262 | ret = regmap_write(dev->regmap, 0xd1, 0x01); |
ce80d713 AP |
263 | if (ret) |
264 | goto err; | |
265 | ||
478932b1 | 266 | ret = regmap_write(dev->regmap, 0xf9, 0x01); |
ce80d713 AP |
267 | if (ret) |
268 | goto err; | |
269 | ||
478932b1 | 270 | ret = regmap_write(dev->regmap, 0xf9, 0x00); |
ce80d713 AP |
271 | if (ret) |
272 | goto err; | |
273 | ||
478932b1 | 274 | ret = regmap_write(dev->regmap, 0xd1, 0x00); |
ce80d713 AP |
275 | if (ret) |
276 | goto err; | |
277 | } | |
278 | break; | |
279 | default: | |
7978b8a1 | 280 | dev_dbg(&client->dev, "invalid delivery_system\n"); |
ce80d713 AP |
281 | ret = -EINVAL; |
282 | goto err; | |
283 | } | |
284 | ||
285 | c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; | |
7978b8a1 | 286 | c->post_bit_error.stat[0].uvalue = dev->post_bit_error; |
ce80d713 | 287 | c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; |
7978b8a1 | 288 | c->post_bit_count.stat[0].uvalue = dev->post_bit_count; |
ce80d713 AP |
289 | } else { |
290 | c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
291 | c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
292 | } | |
293 | ||
395d00d1 AP |
294 | return 0; |
295 | err: | |
7978b8a1 | 296 | dev_dbg(&client->dev, "failed=%d\n", ret); |
395d00d1 AP |
297 | return ret; |
298 | } | |
299 | ||
300 | static int m88ds3103_set_frontend(struct dvb_frontend *fe) | |
301 | { | |
7978b8a1 AP |
302 | struct m88ds3103_dev *dev = fe->demodulator_priv; |
303 | struct i2c_client *client = dev->client; | |
395d00d1 | 304 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
06487dee | 305 | int ret, len; |
395d00d1 | 306 | const struct m88ds3103_reg_val *init; |
b6851419 | 307 | u8 u8tmp, u8tmp1 = 0, u8tmp2 = 0; /* silence compiler warning */ |
f4df95bc | 308 | u8 buf[3]; |
334ef18e | 309 | u16 u16tmp; |
f5d9b88d | 310 | u32 tuner_frequency_khz, target_mclk; |
395d00d1 | 311 | s32 s32tmp; |
41b9aa00 | 312 | |
7978b8a1 AP |
313 | dev_dbg(&client->dev, |
314 | "delivery_system=%d modulation=%d frequency=%u symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n", | |
315 | c->delivery_system, c->modulation, c->frequency, c->symbol_rate, | |
316 | c->inversion, c->pilot, c->rolloff); | |
395d00d1 | 317 | |
7978b8a1 | 318 | if (!dev->warm) { |
395d00d1 AP |
319 | ret = -EAGAIN; |
320 | goto err; | |
321 | } | |
322 | ||
f4df95bc | 323 | /* reset */ |
478932b1 | 324 | ret = regmap_write(dev->regmap, 0x07, 0x80); |
f4df95bc | 325 | if (ret) |
326 | goto err; | |
327 | ||
478932b1 | 328 | ret = regmap_write(dev->regmap, 0x07, 0x00); |
f4df95bc | 329 | if (ret) |
330 | goto err; | |
331 | ||
332 | /* Disable demod clock path */ | |
7978b8a1 | 333 | if (dev->chip_id == M88RS6000_CHIP_ID) { |
478932b1 | 334 | ret = regmap_write(dev->regmap, 0x06, 0xe0); |
f4df95bc | 335 | if (ret) |
336 | goto err; | |
337 | } | |
338 | ||
395d00d1 AP |
339 | /* program tuner */ |
340 | if (fe->ops.tuner_ops.set_params) { | |
341 | ret = fe->ops.tuner_ops.set_params(fe); | |
342 | if (ret) | |
343 | goto err; | |
344 | } | |
345 | ||
346 | if (fe->ops.tuner_ops.get_frequency) { | |
f5d9b88d | 347 | ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency_khz); |
395d00d1 AP |
348 | if (ret) |
349 | goto err; | |
2f9dff3f AP |
350 | } else { |
351 | /* | |
352 | * Use nominal target frequency as tuner driver does not provide | |
353 | * actual frequency used. Carrier offset calculation is not | |
354 | * valid. | |
355 | */ | |
f5d9b88d | 356 | tuner_frequency_khz = c->frequency; |
395d00d1 AP |
357 | } |
358 | ||
f4df95bc | 359 | /* select M88RS6000 demod main mclk and ts mclk from tuner die. */ |
7978b8a1 | 360 | if (dev->chip_id == M88RS6000_CHIP_ID) { |
f4df95bc | 361 | if (c->symbol_rate > 45010000) |
f5d9b88d | 362 | dev->mclk = 110250000; |
f4df95bc | 363 | else |
f5d9b88d | 364 | dev->mclk = 96000000; |
395d00d1 | 365 | |
f4df95bc | 366 | if (c->delivery_system == SYS_DVBS) |
f5d9b88d | 367 | target_mclk = 96000000; |
f4df95bc | 368 | else |
f5d9b88d | 369 | target_mclk = 144000000; |
f4df95bc | 370 | |
371 | /* Enable demod clock path */ | |
478932b1 | 372 | ret = regmap_write(dev->regmap, 0x06, 0x00); |
f4df95bc | 373 | if (ret) |
374 | goto err; | |
375 | usleep_range(10000, 20000); | |
376 | } else { | |
377 | /* set M88DS3103 mclk and ts mclk. */ | |
f5d9b88d | 378 | dev->mclk = 96000000; |
f4df95bc | 379 | |
7978b8a1 | 380 | switch (dev->cfg->ts_mode) { |
b6851419 | 381 | case M88DS3103_TS_SERIAL: |
382 | case M88DS3103_TS_SERIAL_D7: | |
7978b8a1 | 383 | target_mclk = dev->cfg->ts_clk; |
b6851419 | 384 | break; |
385 | case M88DS3103_TS_PARALLEL: | |
386 | case M88DS3103_TS_CI: | |
387 | if (c->delivery_system == SYS_DVBS) | |
f5d9b88d | 388 | target_mclk = 96000000; |
b6851419 | 389 | else { |
f4df95bc | 390 | if (c->symbol_rate < 18000000) |
f5d9b88d | 391 | target_mclk = 96000000; |
f4df95bc | 392 | else if (c->symbol_rate < 28000000) |
f5d9b88d | 393 | target_mclk = 144000000; |
f4df95bc | 394 | else |
f5d9b88d | 395 | target_mclk = 192000000; |
f4df95bc | 396 | } |
b6851419 | 397 | break; |
398 | default: | |
7978b8a1 | 399 | dev_dbg(&client->dev, "invalid ts_mode\n"); |
b6851419 | 400 | ret = -EINVAL; |
401 | goto err; | |
f4df95bc | 402 | } |
403 | ||
404 | switch (target_mclk) { | |
f5d9b88d | 405 | case 96000000: |
f4df95bc | 406 | u8tmp1 = 0x02; /* 0b10 */ |
407 | u8tmp2 = 0x01; /* 0b01 */ | |
408 | break; | |
f5d9b88d | 409 | case 144000000: |
f4df95bc | 410 | u8tmp1 = 0x00; /* 0b00 */ |
411 | u8tmp2 = 0x01; /* 0b01 */ | |
412 | break; | |
f5d9b88d | 413 | case 192000000: |
f4df95bc | 414 | u8tmp1 = 0x03; /* 0b11 */ |
415 | u8tmp2 = 0x00; /* 0b00 */ | |
416 | break; | |
417 | } | |
56ea37da | 418 | ret = m88ds3103_update_bits(dev, 0x22, 0xc0, u8tmp1 << 6); |
f4df95bc | 419 | if (ret) |
420 | goto err; | |
56ea37da | 421 | ret = m88ds3103_update_bits(dev, 0x24, 0xc0, u8tmp2 << 6); |
f4df95bc | 422 | if (ret) |
423 | goto err; | |
424 | } | |
395d00d1 | 425 | |
478932b1 | 426 | ret = regmap_write(dev->regmap, 0xb2, 0x01); |
395d00d1 AP |
427 | if (ret) |
428 | goto err; | |
429 | ||
478932b1 | 430 | ret = regmap_write(dev->regmap, 0x00, 0x01); |
395d00d1 AP |
431 | if (ret) |
432 | goto err; | |
433 | ||
434 | switch (c->delivery_system) { | |
435 | case SYS_DVBS: | |
7978b8a1 | 436 | if (dev->chip_id == M88RS6000_CHIP_ID) { |
f4df95bc | 437 | len = ARRAY_SIZE(m88rs6000_dvbs_init_reg_vals); |
438 | init = m88rs6000_dvbs_init_reg_vals; | |
439 | } else { | |
440 | len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals); | |
441 | init = m88ds3103_dvbs_init_reg_vals; | |
442 | } | |
395d00d1 AP |
443 | break; |
444 | case SYS_DVBS2: | |
7978b8a1 | 445 | if (dev->chip_id == M88RS6000_CHIP_ID) { |
f4df95bc | 446 | len = ARRAY_SIZE(m88rs6000_dvbs2_init_reg_vals); |
447 | init = m88rs6000_dvbs2_init_reg_vals; | |
448 | } else { | |
449 | len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals); | |
450 | init = m88ds3103_dvbs2_init_reg_vals; | |
395d00d1 AP |
451 | } |
452 | break; | |
453 | default: | |
7978b8a1 | 454 | dev_dbg(&client->dev, "invalid delivery_system\n"); |
395d00d1 AP |
455 | ret = -EINVAL; |
456 | goto err; | |
457 | } | |
458 | ||
459 | /* program init table */ | |
7978b8a1 AP |
460 | if (c->delivery_system != dev->delivery_system) { |
461 | ret = m88ds3103_wr_reg_val_tab(dev, init, len); | |
06487dee AP |
462 | if (ret) |
463 | goto err; | |
395d00d1 AP |
464 | } |
465 | ||
7978b8a1 | 466 | if (dev->chip_id == M88RS6000_CHIP_ID) { |
f5d9b88d AP |
467 | if (c->delivery_system == SYS_DVBS2 && |
468 | c->symbol_rate <= 5000000) { | |
478932b1 | 469 | ret = regmap_write(dev->regmap, 0xc0, 0x04); |
f4df95bc | 470 | if (ret) |
471 | goto err; | |
472 | buf[0] = 0x09; | |
473 | buf[1] = 0x22; | |
474 | buf[2] = 0x88; | |
478932b1 | 475 | ret = regmap_bulk_write(dev->regmap, 0x8a, buf, 3); |
f4df95bc | 476 | if (ret) |
477 | goto err; | |
478 | } | |
56ea37da | 479 | ret = m88ds3103_update_bits(dev, 0x9d, 0x08, 0x08); |
f4df95bc | 480 | if (ret) |
481 | goto err; | |
478932b1 | 482 | ret = regmap_write(dev->regmap, 0xf1, 0x01); |
f4df95bc | 483 | if (ret) |
484 | goto err; | |
56ea37da | 485 | ret = m88ds3103_update_bits(dev, 0x30, 0x80, 0x80); |
f4df95bc | 486 | if (ret) |
487 | goto err; | |
488 | } | |
489 | ||
7978b8a1 | 490 | switch (dev->cfg->ts_mode) { |
395d00d1 AP |
491 | case M88DS3103_TS_SERIAL: |
492 | u8tmp1 = 0x00; | |
79d09330 | 493 | u8tmp = 0x06; |
395d00d1 AP |
494 | break; |
495 | case M88DS3103_TS_SERIAL_D7: | |
496 | u8tmp1 = 0x20; | |
79d09330 | 497 | u8tmp = 0x06; |
395d00d1 AP |
498 | break; |
499 | case M88DS3103_TS_PARALLEL: | |
79d09330 | 500 | u8tmp = 0x02; |
395d00d1 AP |
501 | break; |
502 | case M88DS3103_TS_CI: | |
79d09330 | 503 | u8tmp = 0x03; |
395d00d1 AP |
504 | break; |
505 | default: | |
7978b8a1 | 506 | dev_dbg(&client->dev, "invalid ts_mode\n"); |
395d00d1 AP |
507 | ret = -EINVAL; |
508 | goto err; | |
509 | } | |
510 | ||
7978b8a1 | 511 | if (dev->cfg->ts_clk_pol) |
79d09330 | 512 | u8tmp |= 0x40; |
513 | ||
395d00d1 | 514 | /* TS mode */ |
478932b1 | 515 | ret = regmap_write(dev->regmap, 0xfd, u8tmp); |
395d00d1 AP |
516 | if (ret) |
517 | goto err; | |
518 | ||
7978b8a1 | 519 | switch (dev->cfg->ts_mode) { |
395d00d1 AP |
520 | case M88DS3103_TS_SERIAL: |
521 | case M88DS3103_TS_SERIAL_D7: | |
56ea37da | 522 | ret = m88ds3103_update_bits(dev, 0x29, 0x20, u8tmp1); |
395d00d1 AP |
523 | if (ret) |
524 | goto err; | |
334ef18e AP |
525 | u16tmp = 0; |
526 | u8tmp1 = 0x3f; | |
527 | u8tmp2 = 0x3f; | |
b6851419 | 528 | break; |
529 | default: | |
334ef18e AP |
530 | u16tmp = DIV_ROUND_UP(target_mclk, dev->cfg->ts_clk); |
531 | u8tmp1 = u16tmp / 2 - 1; | |
532 | u8tmp2 = DIV_ROUND_UP(u16tmp, 2) - 1; | |
395d00d1 AP |
533 | } |
534 | ||
f5d9b88d | 535 | dev_dbg(&client->dev, "target_mclk=%u ts_clk=%u ts_clk_divide_ratio=%u\n", |
334ef18e | 536 | target_mclk, dev->cfg->ts_clk, u16tmp); |
395d00d1 | 537 | |
395d00d1 | 538 | /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */ |
395d00d1 | 539 | /* u8tmp2[5:0] => ea[5:0] */ |
334ef18e AP |
540 | u8tmp = (u8tmp1 >> 2) & 0x0f; |
541 | ret = regmap_update_bits(dev->regmap, 0xfe, 0x0f, u8tmp); | |
395d00d1 AP |
542 | if (ret) |
543 | goto err; | |
395d00d1 | 544 | u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0; |
478932b1 | 545 | ret = regmap_write(dev->regmap, 0xea, u8tmp); |
395d00d1 AP |
546 | if (ret) |
547 | goto err; | |
548 | ||
395d00d1 AP |
549 | if (c->symbol_rate <= 3000000) |
550 | u8tmp = 0x20; | |
551 | else if (c->symbol_rate <= 10000000) | |
552 | u8tmp = 0x10; | |
553 | else | |
554 | u8tmp = 0x06; | |
555 | ||
478932b1 | 556 | ret = regmap_write(dev->regmap, 0xc3, 0x08); |
395d00d1 AP |
557 | if (ret) |
558 | goto err; | |
559 | ||
478932b1 | 560 | ret = regmap_write(dev->regmap, 0xc8, u8tmp); |
395d00d1 AP |
561 | if (ret) |
562 | goto err; | |
563 | ||
478932b1 | 564 | ret = regmap_write(dev->regmap, 0xc4, 0x08); |
395d00d1 AP |
565 | if (ret) |
566 | goto err; | |
567 | ||
478932b1 | 568 | ret = regmap_write(dev->regmap, 0xc7, 0x00); |
395d00d1 AP |
569 | if (ret) |
570 | goto err; | |
571 | ||
f5d9b88d | 572 | u16tmp = DIV_ROUND_CLOSEST_ULL((u64)c->symbol_rate * 0x10000, dev->mclk); |
395d00d1 AP |
573 | buf[0] = (u16tmp >> 0) & 0xff; |
574 | buf[1] = (u16tmp >> 8) & 0xff; | |
478932b1 | 575 | ret = regmap_bulk_write(dev->regmap, 0x61, buf, 2); |
395d00d1 AP |
576 | if (ret) |
577 | goto err; | |
578 | ||
56ea37da | 579 | ret = m88ds3103_update_bits(dev, 0x4d, 0x02, dev->cfg->spec_inv << 1); |
395d00d1 AP |
580 | if (ret) |
581 | goto err; | |
582 | ||
56ea37da | 583 | ret = m88ds3103_update_bits(dev, 0x30, 0x10, dev->cfg->agc_inv << 4); |
395d00d1 AP |
584 | if (ret) |
585 | goto err; | |
586 | ||
478932b1 | 587 | ret = regmap_write(dev->regmap, 0x33, dev->cfg->agc); |
395d00d1 AP |
588 | if (ret) |
589 | goto err; | |
590 | ||
7978b8a1 | 591 | dev_dbg(&client->dev, "carrier offset=%d\n", |
f5d9b88d | 592 | (tuner_frequency_khz - c->frequency)); |
395d00d1 | 593 | |
f5d9b88d AP |
594 | /* Use 32-bit calc as there is no s64 version of DIV_ROUND_CLOSEST() */ |
595 | s32tmp = 0x10000 * (tuner_frequency_khz - c->frequency); | |
596 | s32tmp = DIV_ROUND_CLOSEST(s32tmp, dev->mclk / 1000); | |
395d00d1 AP |
597 | buf[0] = (s32tmp >> 0) & 0xff; |
598 | buf[1] = (s32tmp >> 8) & 0xff; | |
478932b1 | 599 | ret = regmap_bulk_write(dev->regmap, 0x5e, buf, 2); |
395d00d1 AP |
600 | if (ret) |
601 | goto err; | |
602 | ||
478932b1 | 603 | ret = regmap_write(dev->regmap, 0x00, 0x00); |
395d00d1 AP |
604 | if (ret) |
605 | goto err; | |
606 | ||
478932b1 | 607 | ret = regmap_write(dev->regmap, 0xb2, 0x00); |
395d00d1 AP |
608 | if (ret) |
609 | goto err; | |
610 | ||
7978b8a1 | 611 | dev->delivery_system = c->delivery_system; |
395d00d1 AP |
612 | |
613 | return 0; | |
614 | err: | |
7978b8a1 | 615 | dev_dbg(&client->dev, "failed=%d\n", ret); |
395d00d1 AP |
616 | return ret; |
617 | } | |
618 | ||
619 | static int m88ds3103_init(struct dvb_frontend *fe) | |
620 | { | |
7978b8a1 AP |
621 | struct m88ds3103_dev *dev = fe->demodulator_priv; |
622 | struct i2c_client *client = dev->client; | |
c1daf651 | 623 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
60701d5f | 624 | int ret, len, rem; |
478932b1 | 625 | unsigned int utmp; |
60701d5f AP |
626 | const struct firmware *firmware; |
627 | const char *name; | |
41b9aa00 | 628 | |
7978b8a1 | 629 | dev_dbg(&client->dev, "\n"); |
395d00d1 AP |
630 | |
631 | /* set cold state by default */ | |
7978b8a1 | 632 | dev->warm = false; |
395d00d1 AP |
633 | |
634 | /* wake up device from sleep */ | |
56ea37da | 635 | ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x01); |
395d00d1 AP |
636 | if (ret) |
637 | goto err; | |
56ea37da | 638 | ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x00); |
395d00d1 AP |
639 | if (ret) |
640 | goto err; | |
56ea37da | 641 | ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x00); |
395d00d1 AP |
642 | if (ret) |
643 | goto err; | |
644 | ||
395d00d1 | 645 | /* firmware status */ |
478932b1 | 646 | ret = regmap_read(dev->regmap, 0xb9, &utmp); |
395d00d1 AP |
647 | if (ret) |
648 | goto err; | |
649 | ||
478932b1 | 650 | dev_dbg(&client->dev, "firmware=%02x\n", utmp); |
395d00d1 | 651 | |
478932b1 | 652 | if (utmp) |
60701d5f | 653 | goto warm; |
395d00d1 | 654 | |
f4df95bc | 655 | /* global reset, global diseqc reset, golbal fec reset */ |
478932b1 | 656 | ret = regmap_write(dev->regmap, 0x07, 0xe0); |
f4df95bc | 657 | if (ret) |
658 | goto err; | |
478932b1 | 659 | ret = regmap_write(dev->regmap, 0x07, 0x00); |
f4df95bc | 660 | if (ret) |
661 | goto err; | |
662 | ||
395d00d1 | 663 | /* cold state - try to download firmware */ |
7978b8a1 AP |
664 | dev_info(&client->dev, "found a '%s' in cold state\n", |
665 | m88ds3103_ops.info.name); | |
395d00d1 | 666 | |
7978b8a1 | 667 | if (dev->chip_id == M88RS6000_CHIP_ID) |
60701d5f | 668 | name = M88RS6000_FIRMWARE; |
f4df95bc | 669 | else |
60701d5f | 670 | name = M88DS3103_FIRMWARE; |
395d00d1 | 671 | /* request the firmware, this will block and timeout */ |
60701d5f | 672 | ret = request_firmware(&firmware, name, &client->dev); |
395d00d1 | 673 | if (ret) { |
60701d5f | 674 | dev_err(&client->dev, "firmware file '%s' not found\n", name); |
395d00d1 AP |
675 | goto err; |
676 | } | |
677 | ||
60701d5f | 678 | dev_info(&client->dev, "downloading firmware from file '%s'\n", name); |
395d00d1 | 679 | |
478932b1 | 680 | ret = regmap_write(dev->regmap, 0xb2, 0x01); |
395d00d1 | 681 | if (ret) |
60701d5f | 682 | goto err_release_firmware; |
395d00d1 | 683 | |
60701d5f AP |
684 | for (rem = firmware->size; rem > 0; rem -= (dev->cfg->i2c_wr_max - 1)) { |
685 | len = min(dev->cfg->i2c_wr_max - 1, rem); | |
478932b1 | 686 | ret = regmap_bulk_write(dev->regmap, 0xb0, |
60701d5f AP |
687 | &firmware->data[firmware->size - rem], |
688 | len); | |
395d00d1 | 689 | if (ret) { |
60701d5f | 690 | dev_err(&client->dev, "firmware download failed %d\n", |
7978b8a1 | 691 | ret); |
60701d5f | 692 | goto err_release_firmware; |
395d00d1 AP |
693 | } |
694 | } | |
695 | ||
478932b1 | 696 | ret = regmap_write(dev->regmap, 0xb2, 0x00); |
395d00d1 | 697 | if (ret) |
60701d5f | 698 | goto err_release_firmware; |
395d00d1 | 699 | |
60701d5f | 700 | release_firmware(firmware); |
395d00d1 | 701 | |
478932b1 | 702 | ret = regmap_read(dev->regmap, 0xb9, &utmp); |
395d00d1 AP |
703 | if (ret) |
704 | goto err; | |
705 | ||
478932b1 | 706 | if (!utmp) { |
60701d5f | 707 | ret = -EINVAL; |
7978b8a1 | 708 | dev_info(&client->dev, "firmware did not run\n"); |
395d00d1 AP |
709 | goto err; |
710 | } | |
711 | ||
7978b8a1 AP |
712 | dev_info(&client->dev, "found a '%s' in warm state\n", |
713 | m88ds3103_ops.info.name); | |
714 | dev_info(&client->dev, "firmware version: %X.%X\n", | |
478932b1 | 715 | (utmp >> 4) & 0xf, (utmp >> 0 & 0xf)); |
395d00d1 | 716 | |
60701d5f | 717 | warm: |
395d00d1 | 718 | /* warm state */ |
7978b8a1 AP |
719 | dev->warm = true; |
720 | ||
c1daf651 AP |
721 | /* init stats here in order signal app which stats are supported */ |
722 | c->cnr.len = 1; | |
723 | c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
ce80d713 AP |
724 | c->post_bit_error.len = 1; |
725 | c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
726 | c->post_bit_count.len = 1; | |
727 | c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; | |
395d00d1 | 728 | |
7978b8a1 | 729 | return 0; |
60701d5f AP |
730 | err_release_firmware: |
731 | release_firmware(firmware); | |
5ed0cf88 | 732 | err: |
7978b8a1 | 733 | dev_dbg(&client->dev, "failed=%d\n", ret); |
395d00d1 AP |
734 | return ret; |
735 | } | |
736 | ||
737 | static int m88ds3103_sleep(struct dvb_frontend *fe) | |
738 | { | |
7978b8a1 AP |
739 | struct m88ds3103_dev *dev = fe->demodulator_priv; |
740 | struct i2c_client *client = dev->client; | |
395d00d1 | 741 | int ret; |
478932b1 | 742 | unsigned int utmp; |
41b9aa00 | 743 | |
7978b8a1 | 744 | dev_dbg(&client->dev, "\n"); |
395d00d1 | 745 | |
7978b8a1 AP |
746 | dev->fe_status = 0; |
747 | dev->delivery_system = SYS_UNDEFINED; | |
395d00d1 AP |
748 | |
749 | /* TS Hi-Z */ | |
7978b8a1 | 750 | if (dev->chip_id == M88RS6000_CHIP_ID) |
478932b1 | 751 | utmp = 0x29; |
f4df95bc | 752 | else |
478932b1 | 753 | utmp = 0x27; |
56ea37da | 754 | ret = m88ds3103_update_bits(dev, utmp, 0x01, 0x00); |
395d00d1 AP |
755 | if (ret) |
756 | goto err; | |
757 | ||
758 | /* sleep */ | |
56ea37da | 759 | ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x00); |
395d00d1 AP |
760 | if (ret) |
761 | goto err; | |
56ea37da | 762 | ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x01); |
395d00d1 AP |
763 | if (ret) |
764 | goto err; | |
56ea37da | 765 | ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x10); |
395d00d1 AP |
766 | if (ret) |
767 | goto err; | |
768 | ||
769 | return 0; | |
770 | err: | |
7978b8a1 | 771 | dev_dbg(&client->dev, "failed=%d\n", ret); |
395d00d1 AP |
772 | return ret; |
773 | } | |
774 | ||
7e3e68bc MCC |
775 | static int m88ds3103_get_frontend(struct dvb_frontend *fe, |
776 | struct dtv_frontend_properties *c) | |
395d00d1 | 777 | { |
7978b8a1 AP |
778 | struct m88ds3103_dev *dev = fe->demodulator_priv; |
779 | struct i2c_client *client = dev->client; | |
395d00d1 AP |
780 | int ret; |
781 | u8 buf[3]; | |
41b9aa00 | 782 | |
7978b8a1 | 783 | dev_dbg(&client->dev, "\n"); |
395d00d1 | 784 | |
7978b8a1 | 785 | if (!dev->warm || !(dev->fe_status & FE_HAS_LOCK)) { |
9240c384 | 786 | ret = 0; |
395d00d1 AP |
787 | goto err; |
788 | } | |
789 | ||
790 | switch (c->delivery_system) { | |
791 | case SYS_DVBS: | |
478932b1 | 792 | ret = regmap_bulk_read(dev->regmap, 0xe0, &buf[0], 1); |
395d00d1 AP |
793 | if (ret) |
794 | goto err; | |
795 | ||
478932b1 | 796 | ret = regmap_bulk_read(dev->regmap, 0xe6, &buf[1], 1); |
395d00d1 AP |
797 | if (ret) |
798 | goto err; | |
799 | ||
800 | switch ((buf[0] >> 2) & 0x01) { | |
801 | case 0: | |
802 | c->inversion = INVERSION_OFF; | |
803 | break; | |
804 | case 1: | |
805 | c->inversion = INVERSION_ON; | |
806 | break; | |
395d00d1 AP |
807 | } |
808 | ||
809 | switch ((buf[1] >> 5) & 0x07) { | |
810 | case 0: | |
811 | c->fec_inner = FEC_7_8; | |
812 | break; | |
813 | case 1: | |
814 | c->fec_inner = FEC_5_6; | |
815 | break; | |
816 | case 2: | |
817 | c->fec_inner = FEC_3_4; | |
818 | break; | |
819 | case 3: | |
820 | c->fec_inner = FEC_2_3; | |
821 | break; | |
822 | case 4: | |
823 | c->fec_inner = FEC_1_2; | |
824 | break; | |
825 | default: | |
7978b8a1 | 826 | dev_dbg(&client->dev, "invalid fec_inner\n"); |
395d00d1 AP |
827 | } |
828 | ||
829 | c->modulation = QPSK; | |
830 | ||
831 | break; | |
832 | case SYS_DVBS2: | |
478932b1 | 833 | ret = regmap_bulk_read(dev->regmap, 0x7e, &buf[0], 1); |
395d00d1 AP |
834 | if (ret) |
835 | goto err; | |
836 | ||
478932b1 | 837 | ret = regmap_bulk_read(dev->regmap, 0x89, &buf[1], 1); |
395d00d1 AP |
838 | if (ret) |
839 | goto err; | |
840 | ||
478932b1 | 841 | ret = regmap_bulk_read(dev->regmap, 0xf2, &buf[2], 1); |
395d00d1 AP |
842 | if (ret) |
843 | goto err; | |
844 | ||
845 | switch ((buf[0] >> 0) & 0x0f) { | |
846 | case 2: | |
847 | c->fec_inner = FEC_2_5; | |
848 | break; | |
849 | case 3: | |
850 | c->fec_inner = FEC_1_2; | |
851 | break; | |
852 | case 4: | |
853 | c->fec_inner = FEC_3_5; | |
854 | break; | |
855 | case 5: | |
856 | c->fec_inner = FEC_2_3; | |
857 | break; | |
858 | case 6: | |
859 | c->fec_inner = FEC_3_4; | |
860 | break; | |
861 | case 7: | |
862 | c->fec_inner = FEC_4_5; | |
863 | break; | |
864 | case 8: | |
865 | c->fec_inner = FEC_5_6; | |
866 | break; | |
867 | case 9: | |
868 | c->fec_inner = FEC_8_9; | |
869 | break; | |
870 | case 10: | |
871 | c->fec_inner = FEC_9_10; | |
872 | break; | |
873 | default: | |
7978b8a1 | 874 | dev_dbg(&client->dev, "invalid fec_inner\n"); |
395d00d1 AP |
875 | } |
876 | ||
877 | switch ((buf[0] >> 5) & 0x01) { | |
878 | case 0: | |
879 | c->pilot = PILOT_OFF; | |
880 | break; | |
881 | case 1: | |
882 | c->pilot = PILOT_ON; | |
883 | break; | |
395d00d1 AP |
884 | } |
885 | ||
886 | switch ((buf[0] >> 6) & 0x07) { | |
887 | case 0: | |
888 | c->modulation = QPSK; | |
889 | break; | |
890 | case 1: | |
891 | c->modulation = PSK_8; | |
892 | break; | |
893 | case 2: | |
894 | c->modulation = APSK_16; | |
895 | break; | |
896 | case 3: | |
897 | c->modulation = APSK_32; | |
898 | break; | |
899 | default: | |
7978b8a1 | 900 | dev_dbg(&client->dev, "invalid modulation\n"); |
395d00d1 AP |
901 | } |
902 | ||
903 | switch ((buf[1] >> 7) & 0x01) { | |
904 | case 0: | |
905 | c->inversion = INVERSION_OFF; | |
906 | break; | |
907 | case 1: | |
908 | c->inversion = INVERSION_ON; | |
909 | break; | |
395d00d1 AP |
910 | } |
911 | ||
912 | switch ((buf[2] >> 0) & 0x03) { | |
913 | case 0: | |
914 | c->rolloff = ROLLOFF_35; | |
915 | break; | |
916 | case 1: | |
917 | c->rolloff = ROLLOFF_25; | |
918 | break; | |
919 | case 2: | |
920 | c->rolloff = ROLLOFF_20; | |
921 | break; | |
922 | default: | |
7978b8a1 | 923 | dev_dbg(&client->dev, "invalid rolloff\n"); |
395d00d1 AP |
924 | } |
925 | break; | |
926 | default: | |
7978b8a1 | 927 | dev_dbg(&client->dev, "invalid delivery_system\n"); |
395d00d1 AP |
928 | ret = -EINVAL; |
929 | goto err; | |
930 | } | |
931 | ||
478932b1 | 932 | ret = regmap_bulk_read(dev->regmap, 0x6d, buf, 2); |
395d00d1 AP |
933 | if (ret) |
934 | goto err; | |
935 | ||
f5d9b88d | 936 | c->symbol_rate = DIV_ROUND_CLOSEST_ULL((u64)(buf[1] << 8 | buf[0] << 0) * dev->mclk, 0x10000); |
395d00d1 AP |
937 | |
938 | return 0; | |
939 | err: | |
7978b8a1 | 940 | dev_dbg(&client->dev, "failed=%d\n", ret); |
395d00d1 AP |
941 | return ret; |
942 | } | |
943 | ||
944 | static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr) | |
945 | { | |
395d00d1 | 946 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
41b9aa00 | 947 | |
c1daf651 AP |
948 | if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL) |
949 | *snr = div_s64(c->cnr.stat[0].svalue, 100); | |
950 | else | |
951 | *snr = 0; | |
395d00d1 AP |
952 | |
953 | return 0; | |
395d00d1 AP |
954 | } |
955 | ||
4423a2ba AP |
956 | static int m88ds3103_read_ber(struct dvb_frontend *fe, u32 *ber) |
957 | { | |
7978b8a1 | 958 | struct m88ds3103_dev *dev = fe->demodulator_priv; |
41b9aa00 | 959 | |
7978b8a1 | 960 | *ber = dev->dvbv3_ber; |
4423a2ba AP |
961 | |
962 | return 0; | |
4423a2ba | 963 | } |
395d00d1 AP |
964 | |
965 | static int m88ds3103_set_tone(struct dvb_frontend *fe, | |
0df289a2 | 966 | enum fe_sec_tone_mode fe_sec_tone_mode) |
395d00d1 | 967 | { |
7978b8a1 AP |
968 | struct m88ds3103_dev *dev = fe->demodulator_priv; |
969 | struct i2c_client *client = dev->client; | |
395d00d1 | 970 | int ret; |
478932b1 | 971 | unsigned int utmp, tone, reg_a1_mask; |
41b9aa00 | 972 | |
7978b8a1 | 973 | dev_dbg(&client->dev, "fe_sec_tone_mode=%d\n", fe_sec_tone_mode); |
395d00d1 | 974 | |
7978b8a1 | 975 | if (!dev->warm) { |
395d00d1 AP |
976 | ret = -EAGAIN; |
977 | goto err; | |
978 | } | |
979 | ||
980 | switch (fe_sec_tone_mode) { | |
981 | case SEC_TONE_ON: | |
982 | tone = 0; | |
418a97cb | 983 | reg_a1_mask = 0x47; |
395d00d1 AP |
984 | break; |
985 | case SEC_TONE_OFF: | |
986 | tone = 1; | |
987 | reg_a1_mask = 0x00; | |
988 | break; | |
989 | default: | |
7978b8a1 | 990 | dev_dbg(&client->dev, "invalid fe_sec_tone_mode\n"); |
395d00d1 AP |
991 | ret = -EINVAL; |
992 | goto err; | |
993 | } | |
994 | ||
478932b1 | 995 | utmp = tone << 7 | dev->cfg->envelope_mode << 5; |
56ea37da | 996 | ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp); |
395d00d1 AP |
997 | if (ret) |
998 | goto err; | |
999 | ||
478932b1 | 1000 | utmp = 1 << 2; |
56ea37da | 1001 | ret = m88ds3103_update_bits(dev, 0xa1, reg_a1_mask, utmp); |
395d00d1 AP |
1002 | if (ret) |
1003 | goto err; | |
1004 | ||
1005 | return 0; | |
1006 | err: | |
7978b8a1 | 1007 | dev_dbg(&client->dev, "failed=%d\n", ret); |
395d00d1 AP |
1008 | return ret; |
1009 | } | |
1010 | ||
79d09330 | 1011 | static int m88ds3103_set_voltage(struct dvb_frontend *fe, |
0df289a2 | 1012 | enum fe_sec_voltage fe_sec_voltage) |
79d09330 | 1013 | { |
7978b8a1 AP |
1014 | struct m88ds3103_dev *dev = fe->demodulator_priv; |
1015 | struct i2c_client *client = dev->client; | |
d28677ff | 1016 | int ret; |
478932b1 | 1017 | unsigned int utmp; |
d28677ff | 1018 | bool voltage_sel, voltage_dis; |
79d09330 | 1019 | |
7978b8a1 | 1020 | dev_dbg(&client->dev, "fe_sec_voltage=%d\n", fe_sec_voltage); |
79d09330 | 1021 | |
7978b8a1 | 1022 | if (!dev->warm) { |
d28677ff AP |
1023 | ret = -EAGAIN; |
1024 | goto err; | |
1025 | } | |
79d09330 | 1026 | |
d28677ff | 1027 | switch (fe_sec_voltage) { |
79d09330 | 1028 | case SEC_VOLTAGE_18: |
afbd6eb4 MCC |
1029 | voltage_sel = true; |
1030 | voltage_dis = false; | |
79d09330 | 1031 | break; |
1032 | case SEC_VOLTAGE_13: | |
afbd6eb4 MCC |
1033 | voltage_sel = false; |
1034 | voltage_dis = false; | |
79d09330 | 1035 | break; |
1036 | case SEC_VOLTAGE_OFF: | |
afbd6eb4 MCC |
1037 | voltage_sel = false; |
1038 | voltage_dis = true; | |
79d09330 | 1039 | break; |
d28677ff | 1040 | default: |
7978b8a1 | 1041 | dev_dbg(&client->dev, "invalid fe_sec_voltage\n"); |
d28677ff AP |
1042 | ret = -EINVAL; |
1043 | goto err; | |
79d09330 | 1044 | } |
d28677ff AP |
1045 | |
1046 | /* output pin polarity */ | |
7978b8a1 AP |
1047 | voltage_sel ^= dev->cfg->lnb_hv_pol; |
1048 | voltage_dis ^= dev->cfg->lnb_en_pol; | |
d28677ff | 1049 | |
478932b1 | 1050 | utmp = voltage_dis << 1 | voltage_sel << 0; |
56ea37da | 1051 | ret = m88ds3103_update_bits(dev, 0xa2, 0x03, utmp); |
d28677ff AP |
1052 | if (ret) |
1053 | goto err; | |
79d09330 | 1054 | |
1055 | return 0; | |
d28677ff | 1056 | err: |
7978b8a1 | 1057 | dev_dbg(&client->dev, "failed=%d\n", ret); |
d28677ff | 1058 | return ret; |
79d09330 | 1059 | } |
1060 | ||
395d00d1 AP |
1061 | static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe, |
1062 | struct dvb_diseqc_master_cmd *diseqc_cmd) | |
1063 | { | |
7978b8a1 AP |
1064 | struct m88ds3103_dev *dev = fe->demodulator_priv; |
1065 | struct i2c_client *client = dev->client; | |
befa0cc1 | 1066 | int ret; |
478932b1 | 1067 | unsigned int utmp; |
befa0cc1 | 1068 | unsigned long timeout; |
41b9aa00 | 1069 | |
7978b8a1 AP |
1070 | dev_dbg(&client->dev, "msg=%*ph\n", |
1071 | diseqc_cmd->msg_len, diseqc_cmd->msg); | |
395d00d1 | 1072 | |
7978b8a1 | 1073 | if (!dev->warm) { |
395d00d1 AP |
1074 | ret = -EAGAIN; |
1075 | goto err; | |
1076 | } | |
1077 | ||
1078 | if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) { | |
1079 | ret = -EINVAL; | |
1080 | goto err; | |
1081 | } | |
1082 | ||
478932b1 | 1083 | utmp = dev->cfg->envelope_mode << 5; |
56ea37da | 1084 | ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp); |
395d00d1 AP |
1085 | if (ret) |
1086 | goto err; | |
1087 | ||
478932b1 | 1088 | ret = regmap_bulk_write(dev->regmap, 0xa3, diseqc_cmd->msg, |
395d00d1 AP |
1089 | diseqc_cmd->msg_len); |
1090 | if (ret) | |
1091 | goto err; | |
1092 | ||
478932b1 | 1093 | ret = regmap_write(dev->regmap, 0xa1, |
395d00d1 AP |
1094 | (diseqc_cmd->msg_len - 1) << 3 | 0x07); |
1095 | if (ret) | |
1096 | goto err; | |
1097 | ||
395d00d1 | 1098 | /* wait DiSEqC TX ready */ |
befa0cc1 AP |
1099 | #define SEND_MASTER_CMD_TIMEOUT 120 |
1100 | timeout = jiffies + msecs_to_jiffies(SEND_MASTER_CMD_TIMEOUT); | |
1101 | ||
9ef3cdc1 AP |
1102 | /* DiSEqC message period is 13.5 ms per byte */ |
1103 | utmp = diseqc_cmd->msg_len * 13500; | |
1104 | usleep_range(utmp - 4000, utmp); | |
395d00d1 | 1105 | |
478932b1 AP |
1106 | for (utmp = 1; !time_after(jiffies, timeout) && utmp;) { |
1107 | ret = regmap_read(dev->regmap, 0xa1, &utmp); | |
395d00d1 AP |
1108 | if (ret) |
1109 | goto err; | |
478932b1 | 1110 | utmp = (utmp >> 6) & 0x1; |
395d00d1 AP |
1111 | } |
1112 | ||
478932b1 | 1113 | if (utmp == 0) { |
7978b8a1 | 1114 | dev_dbg(&client->dev, "diseqc tx took %u ms\n", |
befa0cc1 AP |
1115 | jiffies_to_msecs(jiffies) - |
1116 | (jiffies_to_msecs(timeout) - SEND_MASTER_CMD_TIMEOUT)); | |
1117 | } else { | |
7978b8a1 | 1118 | dev_dbg(&client->dev, "diseqc tx timeout\n"); |
395d00d1 | 1119 | |
56ea37da | 1120 | ret = m88ds3103_update_bits(dev, 0xa1, 0xc0, 0x40); |
395d00d1 AP |
1121 | if (ret) |
1122 | goto err; | |
1123 | } | |
1124 | ||
56ea37da | 1125 | ret = m88ds3103_update_bits(dev, 0xa2, 0xc0, 0x80); |
395d00d1 AP |
1126 | if (ret) |
1127 | goto err; | |
1128 | ||
478932b1 | 1129 | if (utmp == 1) { |
395d00d1 AP |
1130 | ret = -ETIMEDOUT; |
1131 | goto err; | |
1132 | } | |
1133 | ||
1134 | return 0; | |
1135 | err: | |
7978b8a1 | 1136 | dev_dbg(&client->dev, "failed=%d\n", ret); |
395d00d1 AP |
1137 | return ret; |
1138 | } | |
1139 | ||
1140 | static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe, | |
0df289a2 | 1141 | enum fe_sec_mini_cmd fe_sec_mini_cmd) |
395d00d1 | 1142 | { |
7978b8a1 AP |
1143 | struct m88ds3103_dev *dev = fe->demodulator_priv; |
1144 | struct i2c_client *client = dev->client; | |
befa0cc1 | 1145 | int ret; |
478932b1 | 1146 | unsigned int utmp, burst; |
befa0cc1 | 1147 | unsigned long timeout; |
41b9aa00 | 1148 | |
7978b8a1 | 1149 | dev_dbg(&client->dev, "fe_sec_mini_cmd=%d\n", fe_sec_mini_cmd); |
395d00d1 | 1150 | |
7978b8a1 | 1151 | if (!dev->warm) { |
395d00d1 AP |
1152 | ret = -EAGAIN; |
1153 | goto err; | |
1154 | } | |
1155 | ||
478932b1 | 1156 | utmp = dev->cfg->envelope_mode << 5; |
56ea37da | 1157 | ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp); |
395d00d1 AP |
1158 | if (ret) |
1159 | goto err; | |
1160 | ||
1161 | switch (fe_sec_mini_cmd) { | |
1162 | case SEC_MINI_A: | |
1163 | burst = 0x02; | |
1164 | break; | |
1165 | case SEC_MINI_B: | |
1166 | burst = 0x01; | |
1167 | break; | |
1168 | default: | |
7978b8a1 | 1169 | dev_dbg(&client->dev, "invalid fe_sec_mini_cmd\n"); |
395d00d1 AP |
1170 | ret = -EINVAL; |
1171 | goto err; | |
1172 | } | |
1173 | ||
478932b1 | 1174 | ret = regmap_write(dev->regmap, 0xa1, burst); |
395d00d1 AP |
1175 | if (ret) |
1176 | goto err; | |
1177 | ||
395d00d1 | 1178 | /* wait DiSEqC TX ready */ |
befa0cc1 AP |
1179 | #define SEND_BURST_TIMEOUT 40 |
1180 | timeout = jiffies + msecs_to_jiffies(SEND_BURST_TIMEOUT); | |
1181 | ||
1182 | /* DiSEqC ToneBurst period is 12.5 ms */ | |
1183 | usleep_range(8500, 12500); | |
395d00d1 | 1184 | |
478932b1 AP |
1185 | for (utmp = 1; !time_after(jiffies, timeout) && utmp;) { |
1186 | ret = regmap_read(dev->regmap, 0xa1, &utmp); | |
395d00d1 AP |
1187 | if (ret) |
1188 | goto err; | |
478932b1 | 1189 | utmp = (utmp >> 6) & 0x1; |
395d00d1 AP |
1190 | } |
1191 | ||
478932b1 | 1192 | if (utmp == 0) { |
7978b8a1 | 1193 | dev_dbg(&client->dev, "diseqc tx took %u ms\n", |
befa0cc1 AP |
1194 | jiffies_to_msecs(jiffies) - |
1195 | (jiffies_to_msecs(timeout) - SEND_BURST_TIMEOUT)); | |
1196 | } else { | |
7978b8a1 | 1197 | dev_dbg(&client->dev, "diseqc tx timeout\n"); |
befa0cc1 | 1198 | |
56ea37da | 1199 | ret = m88ds3103_update_bits(dev, 0xa1, 0xc0, 0x40); |
befa0cc1 AP |
1200 | if (ret) |
1201 | goto err; | |
1202 | } | |
395d00d1 | 1203 | |
56ea37da | 1204 | ret = m88ds3103_update_bits(dev, 0xa2, 0xc0, 0x80); |
395d00d1 AP |
1205 | if (ret) |
1206 | goto err; | |
1207 | ||
478932b1 | 1208 | if (utmp == 1) { |
395d00d1 AP |
1209 | ret = -ETIMEDOUT; |
1210 | goto err; | |
1211 | } | |
1212 | ||
1213 | return 0; | |
1214 | err: | |
7978b8a1 | 1215 | dev_dbg(&client->dev, "failed=%d\n", ret); |
395d00d1 AP |
1216 | return ret; |
1217 | } | |
1218 | ||
1219 | static int m88ds3103_get_tune_settings(struct dvb_frontend *fe, | |
1220 | struct dvb_frontend_tune_settings *s) | |
1221 | { | |
1222 | s->min_delay_ms = 3000; | |
1223 | ||
1224 | return 0; | |
1225 | } | |
1226 | ||
44b9055b | 1227 | static void m88ds3103_release(struct dvb_frontend *fe) |
395d00d1 | 1228 | { |
7978b8a1 AP |
1229 | struct m88ds3103_dev *dev = fe->demodulator_priv; |
1230 | struct i2c_client *client = dev->client; | |
41b9aa00 | 1231 | |
f01919e8 | 1232 | i2c_unregister_device(client); |
395d00d1 AP |
1233 | } |
1234 | ||
e00fed40 | 1235 | static int m88ds3103_select(struct i2c_mux_core *muxc, u32 chan) |
395d00d1 | 1236 | { |
e00fed40 | 1237 | struct m88ds3103_dev *dev = i2c_mux_priv(muxc); |
7978b8a1 | 1238 | struct i2c_client *client = dev->client; |
395d00d1 | 1239 | int ret; |
478932b1 AP |
1240 | struct i2c_msg msg = { |
1241 | .addr = client->addr, | |
1242 | .flags = 0, | |
1243 | .len = 2, | |
1244 | .buf = "\x03\x11", | |
395d00d1 | 1245 | }; |
395d00d1 | 1246 | |
478932b1 AP |
1247 | /* Open tuner I2C repeater for 1 xfer, closes automatically */ |
1248 | ret = __i2c_transfer(client->adapter, &msg, 1); | |
395d00d1 | 1249 | if (ret != 1) { |
7978b8a1 | 1250 | dev_warn(&client->dev, "i2c wr failed=%d\n", ret); |
44b9055b AP |
1251 | if (ret >= 0) |
1252 | ret = -EREMOTEIO; | |
44b9055b AP |
1253 | return ret; |
1254 | } | |
395d00d1 | 1255 | |
44b9055b | 1256 | return 0; |
395d00d1 AP |
1257 | } |
1258 | ||
f01919e8 AP |
1259 | /* |
1260 | * XXX: That is wrapper to m88ds3103_probe() via driver core in order to provide | |
1261 | * proper I2C client for legacy media attach binding. | |
1262 | * New users must use I2C client binding directly! | |
1263 | */ | |
395d00d1 AP |
1264 | struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg, |
1265 | struct i2c_adapter *i2c, struct i2c_adapter **tuner_i2c_adapter) | |
1266 | { | |
f01919e8 AP |
1267 | struct i2c_client *client; |
1268 | struct i2c_board_info board_info; | |
1269 | struct m88ds3103_platform_data pdata; | |
1270 | ||
1271 | pdata.clk = cfg->clock; | |
1272 | pdata.i2c_wr_max = cfg->i2c_wr_max; | |
1273 | pdata.ts_mode = cfg->ts_mode; | |
1274 | pdata.ts_clk = cfg->ts_clk; | |
1275 | pdata.ts_clk_pol = cfg->ts_clk_pol; | |
1276 | pdata.spec_inv = cfg->spec_inv; | |
1277 | pdata.agc = cfg->agc; | |
1278 | pdata.agc_inv = cfg->agc_inv; | |
1279 | pdata.clk_out = cfg->clock_out; | |
1280 | pdata.envelope_mode = cfg->envelope_mode; | |
1281 | pdata.lnb_hv_pol = cfg->lnb_hv_pol; | |
1282 | pdata.lnb_en_pol = cfg->lnb_en_pol; | |
1283 | pdata.attach_in_use = true; | |
1284 | ||
1285 | memset(&board_info, 0, sizeof(board_info)); | |
1286 | strlcpy(board_info.type, "m88ds3103", I2C_NAME_SIZE); | |
1287 | board_info.addr = cfg->i2c_addr; | |
1288 | board_info.platform_data = &pdata; | |
1289 | client = i2c_new_device(i2c, &board_info); | |
1290 | if (!client || !client->dev.driver) | |
1291 | return NULL; | |
1292 | ||
1293 | *tuner_i2c_adapter = pdata.get_i2c_adapter(client); | |
1294 | return pdata.get_dvb_frontend(client); | |
1295 | } | |
1296 | EXPORT_SYMBOL(m88ds3103_attach); | |
1297 | ||
bd336e63 | 1298 | static const struct dvb_frontend_ops m88ds3103_ops = { |
7978b8a1 | 1299 | .delsys = {SYS_DVBS, SYS_DVBS2}, |
f01919e8 | 1300 | .info = { |
7978b8a1 | 1301 | .name = "Montage Technology M88DS3103", |
f01919e8 AP |
1302 | .frequency_min = 950000, |
1303 | .frequency_max = 2150000, | |
1304 | .frequency_tolerance = 5000, | |
1305 | .symbol_rate_min = 1000000, | |
1306 | .symbol_rate_max = 45000000, | |
1307 | .caps = FE_CAN_INVERSION_AUTO | | |
1308 | FE_CAN_FEC_1_2 | | |
1309 | FE_CAN_FEC_2_3 | | |
1310 | FE_CAN_FEC_3_4 | | |
1311 | FE_CAN_FEC_4_5 | | |
1312 | FE_CAN_FEC_5_6 | | |
1313 | FE_CAN_FEC_6_7 | | |
1314 | FE_CAN_FEC_7_8 | | |
1315 | FE_CAN_FEC_8_9 | | |
1316 | FE_CAN_FEC_AUTO | | |
1317 | FE_CAN_QPSK | | |
1318 | FE_CAN_RECOVER | | |
1319 | FE_CAN_2G_MODULATION | |
1320 | }, | |
1321 | ||
1322 | .release = m88ds3103_release, | |
1323 | ||
1324 | .get_tune_settings = m88ds3103_get_tune_settings, | |
1325 | ||
1326 | .init = m88ds3103_init, | |
1327 | .sleep = m88ds3103_sleep, | |
1328 | ||
1329 | .set_frontend = m88ds3103_set_frontend, | |
1330 | .get_frontend = m88ds3103_get_frontend, | |
1331 | ||
1332 | .read_status = m88ds3103_read_status, | |
1333 | .read_snr = m88ds3103_read_snr, | |
1334 | .read_ber = m88ds3103_read_ber, | |
1335 | ||
1336 | .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd, | |
1337 | .diseqc_send_burst = m88ds3103_diseqc_send_burst, | |
1338 | ||
1339 | .set_tone = m88ds3103_set_tone, | |
1340 | .set_voltage = m88ds3103_set_voltage, | |
1341 | }; | |
1342 | ||
1343 | static struct dvb_frontend *m88ds3103_get_dvb_frontend(struct i2c_client *client) | |
1344 | { | |
7978b8a1 | 1345 | struct m88ds3103_dev *dev = i2c_get_clientdata(client); |
f01919e8 AP |
1346 | |
1347 | dev_dbg(&client->dev, "\n"); | |
1348 | ||
1349 | return &dev->fe; | |
1350 | } | |
1351 | ||
1352 | static struct i2c_adapter *m88ds3103_get_i2c_adapter(struct i2c_client *client) | |
1353 | { | |
7978b8a1 | 1354 | struct m88ds3103_dev *dev = i2c_get_clientdata(client); |
f01919e8 AP |
1355 | |
1356 | dev_dbg(&client->dev, "\n"); | |
1357 | ||
e00fed40 | 1358 | return dev->muxc->adapter[0]; |
f01919e8 AP |
1359 | } |
1360 | ||
1361 | static int m88ds3103_probe(struct i2c_client *client, | |
1362 | const struct i2c_device_id *id) | |
1363 | { | |
7978b8a1 | 1364 | struct m88ds3103_dev *dev; |
f01919e8 | 1365 | struct m88ds3103_platform_data *pdata = client->dev.platform_data; |
395d00d1 | 1366 | int ret; |
478932b1 | 1367 | unsigned int utmp; |
395d00d1 | 1368 | |
f01919e8 AP |
1369 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); |
1370 | if (!dev) { | |
395d00d1 | 1371 | ret = -ENOMEM; |
395d00d1 AP |
1372 | goto err; |
1373 | } | |
1374 | ||
f01919e8 | 1375 | dev->client = client; |
f01919e8 AP |
1376 | dev->config.clock = pdata->clk; |
1377 | dev->config.i2c_wr_max = pdata->i2c_wr_max; | |
1378 | dev->config.ts_mode = pdata->ts_mode; | |
f5d9b88d | 1379 | dev->config.ts_clk = pdata->ts_clk * 1000; |
f01919e8 AP |
1380 | dev->config.ts_clk_pol = pdata->ts_clk_pol; |
1381 | dev->config.spec_inv = pdata->spec_inv; | |
1382 | dev->config.agc_inv = pdata->agc_inv; | |
1383 | dev->config.clock_out = pdata->clk_out; | |
1384 | dev->config.envelope_mode = pdata->envelope_mode; | |
1385 | dev->config.agc = pdata->agc; | |
1386 | dev->config.lnb_hv_pol = pdata->lnb_hv_pol; | |
1387 | dev->config.lnb_en_pol = pdata->lnb_en_pol; | |
1388 | dev->cfg = &dev->config; | |
478932b1 AP |
1389 | /* create regmap */ |
1390 | dev->regmap_config.reg_bits = 8, | |
1391 | dev->regmap_config.val_bits = 8, | |
1392 | dev->regmap_config.lock_arg = dev, | |
1393 | dev->regmap = devm_regmap_init_i2c(client, &dev->regmap_config); | |
1394 | if (IS_ERR(dev->regmap)) { | |
1395 | ret = PTR_ERR(dev->regmap); | |
1396 | goto err_kfree; | |
1397 | } | |
395d00d1 | 1398 | |
f4df95bc | 1399 | /* 0x00: chip id[6:0], 0x01: chip ver[7:0], 0x02: chip ver[15:8] */ |
478932b1 | 1400 | ret = regmap_read(dev->regmap, 0x00, &utmp); |
395d00d1 | 1401 | if (ret) |
f01919e8 | 1402 | goto err_kfree; |
395d00d1 | 1403 | |
478932b1 AP |
1404 | dev->chip_id = utmp >> 1; |
1405 | dev_dbg(&client->dev, "chip_id=%02x\n", dev->chip_id); | |
395d00d1 | 1406 | |
478932b1 | 1407 | switch (dev->chip_id) { |
f4df95bc | 1408 | case M88RS6000_CHIP_ID: |
1409 | case M88DS3103_CHIP_ID: | |
395d00d1 AP |
1410 | break; |
1411 | default: | |
f01919e8 | 1412 | goto err_kfree; |
395d00d1 AP |
1413 | } |
1414 | ||
f01919e8 | 1415 | switch (dev->cfg->clock_out) { |
395d00d1 | 1416 | case M88DS3103_CLOCK_OUT_DISABLED: |
478932b1 | 1417 | utmp = 0x80; |
395d00d1 AP |
1418 | break; |
1419 | case M88DS3103_CLOCK_OUT_ENABLED: | |
478932b1 | 1420 | utmp = 0x00; |
395d00d1 AP |
1421 | break; |
1422 | case M88DS3103_CLOCK_OUT_ENABLED_DIV2: | |
478932b1 | 1423 | utmp = 0x10; |
395d00d1 AP |
1424 | break; |
1425 | default: | |
4347df6a | 1426 | ret = -EINVAL; |
f01919e8 | 1427 | goto err_kfree; |
395d00d1 AP |
1428 | } |
1429 | ||
334ef18e AP |
1430 | if (!pdata->ts_clk) { |
1431 | ret = -EINVAL; | |
1432 | goto err_kfree; | |
1433 | } | |
1434 | ||
f4df95bc | 1435 | /* 0x29 register is defined differently for m88rs6000. */ |
1436 | /* set internal tuner address to 0x21 */ | |
478932b1 AP |
1437 | if (dev->chip_id == M88RS6000_CHIP_ID) |
1438 | utmp = 0x00; | |
f4df95bc | 1439 | |
478932b1 | 1440 | ret = regmap_write(dev->regmap, 0x29, utmp); |
395d00d1 | 1441 | if (ret) |
f01919e8 | 1442 | goto err_kfree; |
395d00d1 AP |
1443 | |
1444 | /* sleep */ | |
56ea37da | 1445 | ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x00); |
395d00d1 | 1446 | if (ret) |
f01919e8 | 1447 | goto err_kfree; |
56ea37da | 1448 | ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x01); |
395d00d1 | 1449 | if (ret) |
f01919e8 | 1450 | goto err_kfree; |
56ea37da | 1451 | ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x10); |
395d00d1 | 1452 | if (ret) |
f01919e8 | 1453 | goto err_kfree; |
395d00d1 | 1454 | |
44b9055b | 1455 | /* create mux i2c adapter for tuner */ |
e00fed40 PR |
1456 | dev->muxc = i2c_mux_alloc(client->adapter, &client->dev, 1, 0, 0, |
1457 | m88ds3103_select, NULL); | |
1458 | if (!dev->muxc) { | |
4347df6a | 1459 | ret = -ENOMEM; |
f01919e8 | 1460 | goto err_kfree; |
4347df6a | 1461 | } |
e00fed40 PR |
1462 | dev->muxc->priv = dev; |
1463 | ret = i2c_mux_add_adapter(dev->muxc, 0, 0, 0); | |
1464 | if (ret) | |
1465 | goto err_kfree; | |
44b9055b | 1466 | |
395d00d1 | 1467 | /* create dvb_frontend */ |
f01919e8 AP |
1468 | memcpy(&dev->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops)); |
1469 | if (dev->chip_id == M88RS6000_CHIP_ID) | |
7978b8a1 AP |
1470 | strncpy(dev->fe.ops.info.name, "Montage Technology M88RS6000", |
1471 | sizeof(dev->fe.ops.info.name)); | |
f01919e8 AP |
1472 | if (!pdata->attach_in_use) |
1473 | dev->fe.ops.release = NULL; | |
1474 | dev->fe.demodulator_priv = dev; | |
1475 | i2c_set_clientdata(client, dev); | |
1476 | ||
1477 | /* setup callbacks */ | |
1478 | pdata->get_dvb_frontend = m88ds3103_get_dvb_frontend; | |
1479 | pdata->get_i2c_adapter = m88ds3103_get_i2c_adapter; | |
1480 | return 0; | |
1481 | err_kfree: | |
1482 | kfree(dev); | |
395d00d1 | 1483 | err: |
f01919e8 AP |
1484 | dev_dbg(&client->dev, "failed=%d\n", ret); |
1485 | return ret; | |
395d00d1 | 1486 | } |
395d00d1 | 1487 | |
f01919e8 AP |
1488 | static int m88ds3103_remove(struct i2c_client *client) |
1489 | { | |
7978b8a1 | 1490 | struct m88ds3103_dev *dev = i2c_get_clientdata(client); |
395d00d1 | 1491 | |
f01919e8 | 1492 | dev_dbg(&client->dev, "\n"); |
395d00d1 | 1493 | |
e00fed40 | 1494 | i2c_mux_del_adapters(dev->muxc); |
395d00d1 | 1495 | |
f01919e8 AP |
1496 | kfree(dev); |
1497 | return 0; | |
1498 | } | |
395d00d1 | 1499 | |
f01919e8 AP |
1500 | static const struct i2c_device_id m88ds3103_id_table[] = { |
1501 | {"m88ds3103", 0}, | |
1502 | {} | |
1503 | }; | |
1504 | MODULE_DEVICE_TABLE(i2c, m88ds3103_id_table); | |
395d00d1 | 1505 | |
f01919e8 AP |
1506 | static struct i2c_driver m88ds3103_driver = { |
1507 | .driver = { | |
f01919e8 AP |
1508 | .name = "m88ds3103", |
1509 | .suppress_bind_attrs = true, | |
1510 | }, | |
1511 | .probe = m88ds3103_probe, | |
1512 | .remove = m88ds3103_remove, | |
1513 | .id_table = m88ds3103_id_table, | |
395d00d1 AP |
1514 | }; |
1515 | ||
f01919e8 AP |
1516 | module_i2c_driver(m88ds3103_driver); |
1517 | ||
395d00d1 | 1518 | MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>"); |
7978b8a1 | 1519 | MODULE_DESCRIPTION("Montage Technology M88DS3103 DVB-S/S2 demodulator driver"); |
395d00d1 AP |
1520 | MODULE_LICENSE("GPL"); |
1521 | MODULE_FIRMWARE(M88DS3103_FIRMWARE); | |
f4df95bc | 1522 | MODULE_FIRMWARE(M88RS6000_FIRMWARE); |