media: move dvb kAPI headers to include/media
[linux-2.6-block.git] / drivers / media / dvb-frontends / lgdt330x.c
CommitLineData
d8667cbb 1/*
1963c907 2 * Support for LGDT3302 and LGDT3303 - VSB/QAM
d8667cbb
MM
3 *
4 * Copyright (C) 2005 Wilson Michaels <wilsonmichaels@earthlink.net>
5 *
d8667cbb
MM
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
d8667cbb
MM
16 */
17
18/*
19 * NOTES ABOUT THIS DRIVER
20 *
1963c907
MK
21 * This Linux driver supports:
22 * DViCO FusionHDTV 3 Gold-Q
23 * DViCO FusionHDTV 3 Gold-T
24 * DViCO FusionHDTV 5 Gold
3cff00d9 25 * DViCO FusionHDTV 5 Lite
d8e6acf2 26 * DViCO FusionHDTV 5 USB Gold
c0b11b91 27 * Air2PC/AirStar 2 ATSC 3rd generation (HD5000)
20fe4f65 28 * pcHDTV HD5500
d8667cbb 29 *
d8667cbb
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30 */
31
d8667cbb
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32#include <linux/kernel.h>
33#include <linux/module.h>
d8667cbb
MM
34#include <linux/init.h>
35#include <linux/delay.h>
4e57b681
TS
36#include <linux/string.h>
37#include <linux/slab.h>
d8667cbb
MM
38#include <asm/byteorder.h>
39
fada1935
MCC
40#include <media/dvb_frontend.h>
41#include <media/dvb_math.h>
6ddcc919
MK
42#include "lgdt330x_priv.h"
43#include "lgdt330x.h"
d8667cbb 44
19be685a
TP
45/* Use Equalizer Mean Squared Error instead of Phaser Tracker MSE */
46/* #define USE_EQMSE */
47
ff699e6b 48static int debug;
d8667cbb 49module_param(debug, int, 0644);
6ddcc919 50MODULE_PARM_DESC(debug,"Turn on/off lgdt330x frontend debugging (default:off).");
d8667cbb
MM
51#define dprintk(args...) \
52do { \
6ddcc919 53if (debug) printk(KERN_DEBUG "lgdt330x: " args); \
d8667cbb
MM
54} while (0)
55
6ddcc919 56struct lgdt330x_state
d8667cbb
MM
57{
58 struct i2c_adapter* i2c;
d8667cbb
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59
60 /* Configuration settings */
6ddcc919 61 const struct lgdt330x_config* config;
d8667cbb
MM
62
63 struct dvb_frontend frontend;
64
65 /* Demodulator private data */
0df289a2 66 enum fe_modulation current_modulation;
19be685a 67 u32 snr; /* Result of last SNR calculation */
d8667cbb
MM
68
69 /* Tuner private data */
70 u32 current_frequency;
71};
72
1963c907 73static int i2c_write_demod_bytes (struct lgdt330x_state* state,
dc9ca2af
MK
74 u8 *buf, /* data bytes to send */
75 int len /* number of bytes to send */ )
d8667cbb 76{
b6aef071 77 struct i2c_msg msg =
1963c907
MK
78 { .addr = state->config->demod_address,
79 .flags = 0,
80 .buf = buf,
81 .len = 2 };
b6aef071 82 int i;
1963c907 83 int err;
d8667cbb 84
1963c907 85 for (i=0; i<len-1; i+=2){
d8667cbb 86 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
271ddbf7 87 printk(KERN_WARNING "lgdt330x: %s error (addr %02x <- %02x, err = %i)\n", __func__, msg.buf[0], msg.buf[1], err);
58ba006b
MK
88 if (err < 0)
89 return err;
90 else
91 return -EREMOTEIO;
d8667cbb 92 }
1963c907 93 msg.buf += 2;
d8667cbb
MM
94 }
95 return 0;
96}
97
98/*
99 * This routine writes the register (reg) to the demod bus
100 * then reads the data returned for (len) bytes.
101 */
102
34817174
XW
103static int i2c_read_demod_bytes(struct lgdt330x_state *state,
104 enum I2C_REG reg, u8 *buf, int len)
d8667cbb
MM
105{
106 u8 wr [] = { reg };
107 struct i2c_msg msg [] = {
108 { .addr = state->config->demod_address,
109 .flags = 0, .buf = wr, .len = 1 },
110 { .addr = state->config->demod_address,
111 .flags = I2C_M_RD, .buf = buf, .len = len },
112 };
113 int ret;
114 ret = i2c_transfer(state->i2c, msg, 2);
115 if (ret != 2) {
271ddbf7 116 printk(KERN_WARNING "lgdt330x: %s: addr 0x%02x select 0x%02x error (ret == %i)\n", __func__, state->config->demod_address, reg, ret);
34817174
XW
117 if (ret >= 0)
118 ret = -EIO;
d8667cbb
MM
119 } else {
120 ret = 0;
121 }
122 return ret;
123}
124
125/* Software reset */
1963c907 126static int lgdt3302_SwReset(struct lgdt330x_state* state)
d8667cbb
MM
127{
128 u8 ret;
129 u8 reset[] = {
130 IRQ_MASK,
131 0x00 /* bit 6 is active low software reset
132 * bits 5-0 are 1 to mask interrupts */
133 };
134
1963c907 135 ret = i2c_write_demod_bytes(state,
dc9ca2af 136 reset, sizeof(reset));
d8667cbb 137 if (ret == 0) {
1963c907
MK
138
139 /* force reset high (inactive) and unmask interrupts */
140 reset[1] = 0x7f;
141 ret = i2c_write_demod_bytes(state,
dc9ca2af 142 reset, sizeof(reset));
d8667cbb 143 }
d8667cbb
MM
144 return ret;
145}
146
1963c907
MK
147static int lgdt3303_SwReset(struct lgdt330x_state* state)
148{
149 u8 ret;
150 u8 reset[] = {
151 0x02,
152 0x00 /* bit 0 is active low software reset */
153 };
154
155 ret = i2c_write_demod_bytes(state,
dc9ca2af 156 reset, sizeof(reset));
1963c907
MK
157 if (ret == 0) {
158
159 /* force reset high (inactive) */
160 reset[1] = 0x01;
161 ret = i2c_write_demod_bytes(state,
dc9ca2af 162 reset, sizeof(reset));
1963c907
MK
163 }
164 return ret;
165}
166
167static int lgdt330x_SwReset(struct lgdt330x_state* state)
168{
169 switch (state->config->demod_chip) {
170 case LGDT3302:
171 return lgdt3302_SwReset(state);
172 case LGDT3303:
173 return lgdt3303_SwReset(state);
174 default:
175 return -ENODEV;
176 }
177}
178
6ddcc919 179static int lgdt330x_init(struct dvb_frontend* fe)
d8667cbb
MM
180{
181 /* Hardware reset is done using gpio[0] of cx23880x chip.
182 * I'd like to do it here, but don't know how to find chip address.
183 * cx88-cards.c arranges for the reset bit to be inactive (high).
184 * Maybe there needs to be a callable function in cx88-core or
185 * the caller of this function needs to do it. */
186
1963c907
MK
187 /*
188 * Array of byte pairs <address, value>
189 * to initialize each different chip
190 */
191 static u8 lgdt3302_init_data[] = {
192 /* Use 50MHz parameter values from spec sheet since xtal is 50 */
193 /* Change the value of NCOCTFV[25:0] of carrier
194 recovery center frequency register */
195 VSB_CARRIER_FREQ0, 0x00,
196 VSB_CARRIER_FREQ1, 0x87,
197 VSB_CARRIER_FREQ2, 0x8e,
198 VSB_CARRIER_FREQ3, 0x01,
199 /* Change the TPCLK pin polarity
200 data is valid on falling clock */
201 DEMUX_CONTROL, 0xfb,
202 /* Change the value of IFBW[11:0] of
203 AGC IF/RF loop filter bandwidth register */
204 AGC_RF_BANDWIDTH0, 0x40,
205 AGC_RF_BANDWIDTH1, 0x93,
206 AGC_RF_BANDWIDTH2, 0x00,
207 /* Change the value of bit 6, 'nINAGCBY' and
208 'NSSEL[1:0] of ACG function control register 2 */
209 AGC_FUNC_CTRL2, 0xc6,
210 /* Change the value of bit 6 'RFFIX'
211 of AGC function control register 3 */
212 AGC_FUNC_CTRL3, 0x40,
213 /* Set the value of 'INLVTHD' register 0x2a/0x2c
214 to 0x7fe */
215 AGC_DELAY0, 0x07,
216 AGC_DELAY2, 0xfe,
217 /* Change the value of IAGCBW[15:8]
9aaeded7 218 of inner AGC loop filter bandwidth */
1963c907
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219 AGC_LOOP_BANDWIDTH0, 0x08,
220 AGC_LOOP_BANDWIDTH1, 0x9a
221 };
222
223 static u8 lgdt3303_init_data[] = {
224 0x4c, 0x14
225 };
226
c0f4c0ad 227 static u8 flip_1_lgdt3303_init_data[] = {
c0b11b91
MK
228 0x4c, 0x14,
229 0x87, 0xf3
230 };
231
c0f4c0ad
MK
232 static u8 flip_2_lgdt3303_init_data[] = {
233 0x4c, 0x14,
234 0x87, 0xda
235 };
236
1963c907
MK
237 struct lgdt330x_state* state = fe->demodulator_priv;
238 char *chip_name;
239 int err;
240
241 switch (state->config->demod_chip) {
242 case LGDT3302:
243 chip_name = "LGDT3302";
244 err = i2c_write_demod_bytes(state, lgdt3302_init_data,
dc9ca2af
MK
245 sizeof(lgdt3302_init_data));
246 break;
1963c907
MK
247 case LGDT3303:
248 chip_name = "LGDT3303";
c0f4c0ad
MK
249 switch (state->config->clock_polarity_flip) {
250 case 2:
251 err = i2c_write_demod_bytes(state,
252 flip_2_lgdt3303_init_data,
253 sizeof(flip_2_lgdt3303_init_data));
254 break;
255 case 1:
256 err = i2c_write_demod_bytes(state,
257 flip_1_lgdt3303_init_data,
258 sizeof(flip_1_lgdt3303_init_data));
259 break;
260 case 0:
261 default:
c0b11b91
MK
262 err = i2c_write_demod_bytes(state, lgdt3303_init_data,
263 sizeof(lgdt3303_init_data));
264 }
dc9ca2af 265 break;
1963c907
MK
266 default:
267 chip_name = "undefined";
268 printk (KERN_WARNING "Only LGDT3302 and LGDT3303 are supported chips.\n");
269 err = -ENODEV;
270 }
271ddbf7 271 dprintk("%s entered as %s\n", __func__, chip_name);
1963c907
MK
272 if (err < 0)
273 return err;
274 return lgdt330x_SwReset(state);
d8667cbb
MM
275}
276
6ddcc919 277static int lgdt330x_read_ber(struct dvb_frontend* fe, u32* ber)
d8667cbb 278{
1963c907 279 *ber = 0; /* Not supplied by the demod chips */
d8667cbb
MM
280 return 0;
281}
282
6ddcc919 283static int lgdt330x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
d8667cbb 284{
1963c907
MK
285 struct lgdt330x_state* state = fe->demodulator_priv;
286 int err;
d8667cbb
MM
287 u8 buf[2];
288
26110dac
MK
289 *ucblocks = 0;
290
1963c907
MK
291 switch (state->config->demod_chip) {
292 case LGDT3302:
293 err = i2c_read_demod_bytes(state, LGDT3302_PACKET_ERR_COUNTER1,
dc9ca2af
MK
294 buf, sizeof(buf));
295 break;
1963c907
MK
296 case LGDT3303:
297 err = i2c_read_demod_bytes(state, LGDT3303_PACKET_ERR_COUNTER1,
dc9ca2af
MK
298 buf, sizeof(buf));
299 break;
1963c907
MK
300 default:
301 printk(KERN_WARNING
dc9ca2af 302 "Only LGDT3302 and LGDT3303 are supported chips.\n");
1963c907
MK
303 err = -ENODEV;
304 }
26110dac
MK
305 if (err < 0)
306 return err;
d8667cbb
MM
307
308 *ucblocks = (buf[0] << 8) | buf[1];
309 return 0;
310}
311
ca7072dd 312static int lgdt330x_set_parameters(struct dvb_frontend *fe)
d8667cbb 313{
ca7072dd 314 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1963c907
MK
315 /*
316 * Array of byte pairs <address, value>
317 * to initialize 8VSB for lgdt3303 chip 50 MHz IF
318 */
319 static u8 lgdt3303_8vsb_44_data[] = {
320 0x04, 0x00,
321 0x0d, 0x40,
0b6389ff
MK
322 0x0e, 0x87,
323 0x0f, 0x8e,
324 0x10, 0x01,
325 0x47, 0x8b };
1963c907
MK
326
327 /*
328 * Array of byte pairs <address, value>
329 * to initialize QAM for lgdt3303 chip
330 */
331 static u8 lgdt3303_qam_data[] = {
332 0x04, 0x00,
333 0x0d, 0x00,
334 0x0e, 0x00,
335 0x0f, 0x00,
336 0x10, 0x00,
337 0x51, 0x63,
338 0x47, 0x66,
339 0x48, 0x66,
340 0x4d, 0x1a,
341 0x49, 0x08,
342 0x4a, 0x9b };
343
344 struct lgdt330x_state* state = fe->demodulator_priv;
d8667cbb 345
d8667cbb 346 static u8 top_ctrl_cfg[] = { TOP_CONTROL, 0x03 };
d8667cbb 347
54828d19 348 int err = 0;
d8667cbb 349 /* Change only if we are actually changing the modulation */
ca7072dd
MCC
350 if (state->current_modulation != p->modulation) {
351 switch (p->modulation) {
d8667cbb 352 case VSB_8:
271ddbf7 353 dprintk("%s: VSB_8 MODE\n", __func__);
d8667cbb 354
1963c907
MK
355 /* Select VSB mode */
356 top_ctrl_cfg[1] = 0x03;
0ccef6db
MK
357
358 /* Select ANT connector if supported by card */
359 if (state->config->pll_rf_set)
360 state->config->pll_rf_set(fe, 1);
1963c907
MK
361
362 if (state->config->demod_chip == LGDT3303) {
363 err = i2c_write_demod_bytes(state, lgdt3303_8vsb_44_data,
dc9ca2af 364 sizeof(lgdt3303_8vsb_44_data));
1963c907 365 }
d8667cbb
MM
366 break;
367
368 case QAM_64:
271ddbf7 369 dprintk("%s: QAM_64 MODE\n", __func__);
d8667cbb 370
1963c907
MK
371 /* Select QAM_64 mode */
372 top_ctrl_cfg[1] = 0x00;
0ccef6db
MK
373
374 /* Select CABLE connector if supported by card */
375 if (state->config->pll_rf_set)
376 state->config->pll_rf_set(fe, 0);
1963c907
MK
377
378 if (state->config->demod_chip == LGDT3303) {
379 err = i2c_write_demod_bytes(state, lgdt3303_qam_data,
380 sizeof(lgdt3303_qam_data));
381 }
d8667cbb
MM
382 break;
383
384 case QAM_256:
271ddbf7 385 dprintk("%s: QAM_256 MODE\n", __func__);
d8667cbb 386
1963c907
MK
387 /* Select QAM_256 mode */
388 top_ctrl_cfg[1] = 0x01;
0ccef6db
MK
389
390 /* Select CABLE connector if supported by card */
391 if (state->config->pll_rf_set)
392 state->config->pll_rf_set(fe, 0);
1963c907
MK
393
394 if (state->config->demod_chip == LGDT3303) {
395 err = i2c_write_demod_bytes(state, lgdt3303_qam_data,
396 sizeof(lgdt3303_qam_data));
397 }
d8667cbb
MM
398 break;
399 default:
ca7072dd 400 printk(KERN_WARNING "lgdt330x: %s: Modulation type(%d) UNSUPPORTED\n", __func__, p->modulation);
d8667cbb
MM
401 return -1;
402 }
54828d19 403 if (err < 0)
4bd69e7b 404 printk(KERN_WARNING "lgdt330x: %s: error blasting bytes to lgdt3303 for modulation type(%d)\n",
ca7072dd 405 __func__, p->modulation);
54828d19 406
1963c907
MK
407 /*
408 * select serial or parallel MPEG harware interface
409 * Serial: 0x04 for LGDT3302 or 0x40 for LGDT3303
410 * Parallel: 0x00
411 */
412 top_ctrl_cfg[1] |= state->config->serial_mpeg;
d8667cbb
MM
413
414 /* Select the requested mode */
1963c907 415 i2c_write_demod_bytes(state, top_ctrl_cfg,
dc9ca2af
MK
416 sizeof(top_ctrl_cfg));
417 if (state->config->set_ts_params)
418 state->config->set_ts_params(fe, 0);
ca7072dd 419 state->current_modulation = p->modulation;
d8667cbb 420 }
d8667cbb 421
dc9ca2af 422 /* Tune to the specified frequency */
dea74869 423 if (fe->ops.tuner_ops.set_params) {
14d24d14 424 fe->ops.tuner_ops.set_params(fe);
dea74869 425 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
02269f37 426 }
dc9ca2af
MK
427
428 /* Keep track of the new frequency */
4302c15e
MCC
429 /* FIXME this is the wrong way to do this... */
430 /* The tuner is shared with the video4linux analog API */
ca7072dd 431 state->current_frequency = p->frequency;
dc9ca2af 432
6ddcc919 433 lgdt330x_SwReset(state);
d8667cbb
MM
434 return 0;
435}
436
7e3e68bc
MCC
437static int lgdt330x_get_frontend(struct dvb_frontend *fe,
438 struct dtv_frontend_properties *p)
d8667cbb 439{
6ddcc919 440 struct lgdt330x_state *state = fe->demodulator_priv;
7e3e68bc 441
ca7072dd 442 p->frequency = state->current_frequency;
d8667cbb
MM
443 return 0;
444}
445
0df289a2
MCC
446static int lgdt3302_read_status(struct dvb_frontend *fe,
447 enum fe_status *status)
d8667cbb 448{
1963c907 449 struct lgdt330x_state* state = fe->demodulator_priv;
d8667cbb
MM
450 u8 buf[3];
451
452 *status = 0; /* Reset status result */
453
08d80525 454 /* AGC status register */
1963c907 455 i2c_read_demod_bytes(state, AGC_STATUS, buf, 1);
271ddbf7 456 dprintk("%s: AGC_STATUS = 0x%02x\n", __func__, buf[0]);
08d80525
MK
457 if ((buf[0] & 0x0c) == 0x8){
458 /* Test signal does not exist flag */
459 /* as well as the AGC lock flag. */
460 *status |= FE_HAS_SIGNAL;
08d80525
MK
461 }
462
1963c907
MK
463 /*
464 * You must set the Mask bits to 1 in the IRQ_MASK in order
465 * to see that status bit in the IRQ_STATUS register.
466 * This is done in SwReset();
467 */
d8667cbb 468 /* signal status */
1963c907 469 i2c_read_demod_bytes(state, TOP_CONTROL, buf, sizeof(buf));
271ddbf7 470 dprintk("%s: TOP_CONTROL = 0x%02x, IRO_MASK = 0x%02x, IRQ_STATUS = 0x%02x\n", __func__, buf[0], buf[1], buf[2]);
08d80525 471
d8667cbb
MM
472
473 /* sync status */
474 if ((buf[2] & 0x03) == 0x01) {
475 *status |= FE_HAS_SYNC;
476 }
477
478 /* FEC error status */
479 if ((buf[2] & 0x0c) == 0x08) {
480 *status |= FE_HAS_LOCK;
481 *status |= FE_HAS_VITERBI;
482 }
483
d8667cbb 484 /* Carrier Recovery Lock Status Register */
1963c907 485 i2c_read_demod_bytes(state, CARRIER_LOCK, buf, 1);
271ddbf7 486 dprintk("%s: CARRIER_LOCK = 0x%02x\n", __func__, buf[0]);
d8667cbb
MM
487 switch (state->current_modulation) {
488 case QAM_256:
489 case QAM_64:
af901ca1 490 /* Need to understand why there are 3 lock levels here */
d8667cbb
MM
491 if ((buf[0] & 0x07) == 0x07)
492 *status |= FE_HAS_CARRIER;
d8667cbb 493 break;
d8667cbb
MM
494 case VSB_8:
495 if ((buf[0] & 0x80) == 0x80)
496 *status |= FE_HAS_CARRIER;
d8667cbb 497 break;
d8667cbb 498 default:
271ddbf7 499 printk(KERN_WARNING "lgdt330x: %s: Modulation set to unsupported value\n", __func__);
d8667cbb 500 }
d8667cbb
MM
501
502 return 0;
503}
504
0df289a2
MCC
505static int lgdt3303_read_status(struct dvb_frontend *fe,
506 enum fe_status *status)
1963c907
MK
507{
508 struct lgdt330x_state* state = fe->demodulator_priv;
509 int err;
510 u8 buf[3];
511
512 *status = 0; /* Reset status result */
513
514 /* lgdt3303 AGC status register */
515 err = i2c_read_demod_bytes(state, 0x58, buf, 1);
516 if (err < 0)
517 return err;
518
271ddbf7 519 dprintk("%s: AGC_STATUS = 0x%02x\n", __func__, buf[0]);
1963c907
MK
520 if ((buf[0] & 0x21) == 0x01){
521 /* Test input signal does not exist flag */
522 /* as well as the AGC lock flag. */
523 *status |= FE_HAS_SIGNAL;
1963c907
MK
524 }
525
526 /* Carrier Recovery Lock Status Register */
527 i2c_read_demod_bytes(state, CARRIER_LOCK, buf, 1);
271ddbf7 528 dprintk("%s: CARRIER_LOCK = 0x%02x\n", __func__, buf[0]);
1963c907
MK
529 switch (state->current_modulation) {
530 case QAM_256:
531 case QAM_64:
af901ca1 532 /* Need to understand why there are 3 lock levels here */
1963c907
MK
533 if ((buf[0] & 0x07) == 0x07)
534 *status |= FE_HAS_CARRIER;
535 else
536 break;
537 i2c_read_demod_bytes(state, 0x8a, buf, 1);
538 if ((buf[0] & 0x04) == 0x04)
539 *status |= FE_HAS_SYNC;
540 if ((buf[0] & 0x01) == 0x01)
541 *status |= FE_HAS_LOCK;
542 if ((buf[0] & 0x08) == 0x08)
543 *status |= FE_HAS_VITERBI;
544 break;
545 case VSB_8:
546 if ((buf[0] & 0x80) == 0x80)
547 *status |= FE_HAS_CARRIER;
548 else
549 break;
550 i2c_read_demod_bytes(state, 0x38, buf, 1);
551 if ((buf[0] & 0x02) == 0x00)
552 *status |= FE_HAS_SYNC;
553 if ((buf[0] & 0x01) == 0x01) {
554 *status |= FE_HAS_LOCK;
555 *status |= FE_HAS_VITERBI;
556 }
557 break;
558 default:
271ddbf7 559 printk(KERN_WARNING "lgdt330x: %s: Modulation set to unsupported value\n", __func__);
1963c907
MK
560 }
561 return 0;
562}
563
19be685a
TP
564/* Calculate SNR estimation (scaled by 2^24)
565
566 8-VSB SNR equations from LGDT3302 and LGDT3303 datasheets, QAM
567 equations from LGDT3303 datasheet. VSB is the same between the '02
568 and '03, so maybe QAM is too? Perhaps someone with a newer datasheet
569 that has QAM information could verify?
570
571 For 8-VSB: (two ways, take your pick)
572 LGDT3302:
573 SNR_EQ = 10 * log10(25 * 24^2 / EQ_MSE)
574 LGDT3303:
575 SNR_EQ = 10 * log10(25 * 32^2 / EQ_MSE)
576 LGDT3302 & LGDT3303:
577 SNR_PT = 10 * log10(25 * 32^2 / PT_MSE) (we use this one)
578 For 64-QAM:
579 SNR = 10 * log10( 688128 / MSEQAM)
580 For 256-QAM:
581 SNR = 10 * log10( 696320 / MSEQAM)
582
583 We re-write the snr equation as:
584 SNR * 2^24 = 10*(c - intlog10(MSE))
585 Where for 256-QAM, c = log10(696320) * 2^24, and so on. */
586
587static u32 calculate_snr(u32 mse, u32 c)
d8667cbb 588{
19be685a
TP
589 if (mse == 0) /* No signal */
590 return 0;
591
592 mse = intlog10(mse);
593 if (mse > c) {
594 /* Negative SNR, which is possible, but realisticly the
595 demod will lose lock before the signal gets this bad. The
596 API only allows for unsigned values, so just return 0 */
597 return 0;
598 }
599 return 10*(c - mse);
d8667cbb
MM
600}
601
1963c907 602static int lgdt3302_read_snr(struct dvb_frontend* fe, u16* snr)
d8667cbb 603{
6ddcc919 604 struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv;
19be685a
TP
605 u8 buf[5]; /* read data buffer */
606 u32 noise; /* noise value */
607 u32 c; /* per-modulation SNR calculation constant */
d8667cbb 608
19be685a
TP
609 switch(state->current_modulation) {
610 case VSB_8:
611 i2c_read_demod_bytes(state, LGDT3302_EQPH_ERR0, buf, 5);
612#ifdef USE_EQMSE
613 /* Use Equalizer Mean-Square Error Register */
614 /* SNR for ranges from -15.61 to +41.58 */
d8667cbb 615 noise = ((buf[0] & 7) << 16) | (buf[1] << 8) | buf[2];
19be685a 616 c = 69765745; /* log10(25*24^2)*2^24 */
d8667cbb 617#else
19be685a
TP
618 /* Use Phase Tracker Mean-Square Error Register */
619 /* SNR for ranges from -13.11 to +44.08 */
d8667cbb 620 noise = ((buf[0] & 7<<3) << 13) | (buf[3] << 8) | buf[4];
19be685a
TP
621 c = 73957994; /* log10(25*32^2)*2^24 */
622#endif
623 break;
624 case QAM_64:
625 case QAM_256:
626 i2c_read_demod_bytes(state, CARRIER_MSEQAM1, buf, 2);
1963c907 627 noise = ((buf[0] & 3) << 8) | buf[1];
19be685a
TP
628 c = state->current_modulation == QAM_64 ? 97939837 : 98026066;
629 /* log10(688128)*2^24 and log10(696320)*2^24 */
630 break;
631 default:
632 printk(KERN_ERR "lgdt330x: %s: Modulation set to unsupported value\n",
271ddbf7 633 __func__);
19be685a 634 return -EREMOTEIO; /* return -EDRIVER_IS_GIBBERED; */
d8667cbb
MM
635 }
636
19be685a
TP
637 state->snr = calculate_snr(noise, c);
638 *snr = (state->snr) >> 16; /* Convert from 8.24 fixed-point to 8.8 */
d8667cbb 639
271ddbf7 640 dprintk("%s: noise = 0x%08x, snr = %d.%02d dB\n", __func__, noise,
19be685a 641 state->snr >> 24, (((state->snr>>8) & 0xffff) * 100) >> 16);
d8667cbb
MM
642
643 return 0;
644}
645
1963c907
MK
646static int lgdt3303_read_snr(struct dvb_frontend* fe, u16* snr)
647{
1963c907 648 struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv;
19be685a
TP
649 u8 buf[5]; /* read data buffer */
650 u32 noise; /* noise value */
651 u32 c; /* per-modulation SNR calculation constant */
1963c907 652
19be685a
TP
653 switch(state->current_modulation) {
654 case VSB_8:
655 i2c_read_demod_bytes(state, LGDT3303_EQPH_ERR0, buf, 5);
656#ifdef USE_EQMSE
657 /* Use Equalizer Mean-Square Error Register */
658 /* SNR for ranges from -16.12 to +44.08 */
659 noise = ((buf[0] & 0x78) << 13) | (buf[1] << 8) | buf[2];
660 c = 73957994; /* log10(25*32^2)*2^24 */
661#else
662 /* Use Phase Tracker Mean-Square Error Register */
663 /* SNR for ranges from -13.11 to +44.08 */
1963c907 664 noise = ((buf[0] & 7) << 16) | (buf[3] << 8) | buf[4];
19be685a
TP
665 c = 73957994; /* log10(25*32^2)*2^24 */
666#endif
667 break;
668 case QAM_64:
669 case QAM_256:
670 i2c_read_demod_bytes(state, CARRIER_MSEQAM1, buf, 2);
1963c907 671 noise = (buf[0] << 8) | buf[1];
19be685a
TP
672 c = state->current_modulation == QAM_64 ? 97939837 : 98026066;
673 /* log10(688128)*2^24 and log10(696320)*2^24 */
674 break;
675 default:
676 printk(KERN_ERR "lgdt330x: %s: Modulation set to unsupported value\n",
271ddbf7 677 __func__);
19be685a 678 return -EREMOTEIO; /* return -EDRIVER_IS_GIBBERED; */
1963c907
MK
679 }
680
19be685a
TP
681 state->snr = calculate_snr(noise, c);
682 *snr = (state->snr) >> 16; /* Convert from 8.24 fixed-point to 8.8 */
683
271ddbf7 684 dprintk("%s: noise = 0x%08x, snr = %d.%02d dB\n", __func__, noise,
19be685a
TP
685 state->snr >> 24, (((state->snr >> 8) & 0xffff) * 100) >> 16);
686
687 return 0;
688}
689
690static int lgdt330x_read_signal_strength(struct dvb_frontend* fe, u16* strength)
691{
692 /* Calculate Strength from SNR up to 35dB */
693 /* Even though the SNR can go higher than 35dB, there is some comfort */
694 /* factor in having a range of strong signals that can show at 100% */
695 struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv;
696 u16 snr;
697 int ret;
1963c907 698
19be685a
TP
699 ret = fe->ops.read_snr(fe, &snr);
700 if (ret != 0)
701 return ret;
702 /* Rather than use the 8.8 value snr, use state->snr which is 8.24 */
703 /* scale the range 0 - 35*2^24 into 0 - 65535 */
704 if (state->snr >= 8960 * 0x10000)
705 *strength = 0xffff;
706 else
707 *strength = state->snr / 8960;
1963c907
MK
708
709 return 0;
710}
711
6ddcc919 712static int lgdt330x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
d8667cbb
MM
713{
714 /* I have no idea about this - it may not be needed */
715 fe_tune_settings->min_delay_ms = 500;
716 fe_tune_settings->step_size = 0;
717 fe_tune_settings->max_drift = 0;
718 return 0;
719}
720
6ddcc919 721static void lgdt330x_release(struct dvb_frontend* fe)
d8667cbb 722{
6ddcc919 723 struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv;
d8667cbb
MM
724 kfree(state);
725}
726
bd336e63
MK
727static const struct dvb_frontend_ops lgdt3302_ops;
728static const struct dvb_frontend_ops lgdt3303_ops;
d8667cbb 729
6ddcc919 730struct dvb_frontend* lgdt330x_attach(const struct lgdt330x_config* config,
d8667cbb
MM
731 struct i2c_adapter* i2c)
732{
6ddcc919 733 struct lgdt330x_state* state = NULL;
d8667cbb
MM
734 u8 buf[1];
735
736 /* Allocate memory for the internal state */
7408187d 737 state = kzalloc(sizeof(struct lgdt330x_state), GFP_KERNEL);
d8667cbb
MM
738 if (state == NULL)
739 goto error;
d8667cbb
MM
740
741 /* Setup the state */
742 state->config = config;
743 state->i2c = i2c;
dea74869
PB
744
745 /* Create dvb_frontend */
1963c907
MK
746 switch (config->demod_chip) {
747 case LGDT3302:
dea74869 748 memcpy(&state->frontend.ops, &lgdt3302_ops, sizeof(struct dvb_frontend_ops));
1963c907
MK
749 break;
750 case LGDT3303:
dea74869 751 memcpy(&state->frontend.ops, &lgdt3303_ops, sizeof(struct dvb_frontend_ops));
1963c907
MK
752 break;
753 default:
754 goto error;
755 }
dea74869 756 state->frontend.demodulator_priv = state;
1963c907 757
d8667cbb 758 /* Verify communication with demod chip */
1963c907 759 if (i2c_read_demod_bytes(state, 2, buf, 1))
d8667cbb
MM
760 goto error;
761
762 state->current_frequency = -1;
763 state->current_modulation = -1;
764
d8667cbb
MM
765 return &state->frontend;
766
767error:
2ea75330 768 kfree(state);
271ddbf7 769 dprintk("%s: ERROR\n",__func__);
d8667cbb
MM
770 return NULL;
771}
772
bd336e63 773static const struct dvb_frontend_ops lgdt3302_ops = {
ca7072dd 774 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
1963c907 775 .info = {
e179d8b0 776 .name= "LG Electronics LGDT3302 VSB/QAM Frontend",
1963c907
MK
777 .frequency_min= 54000000,
778 .frequency_max= 858000000,
779 .frequency_stepsize= 62500,
66944e99
MK
780 .symbol_rate_min = 5056941, /* QAM 64 */
781 .symbol_rate_max = 10762000, /* VSB 8 */
1963c907
MK
782 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
783 },
784 .init = lgdt330x_init,
ca7072dd
MCC
785 .set_frontend = lgdt330x_set_parameters,
786 .get_frontend = lgdt330x_get_frontend,
1963c907
MK
787 .get_tune_settings = lgdt330x_get_tune_settings,
788 .read_status = lgdt3302_read_status,
789 .read_ber = lgdt330x_read_ber,
790 .read_signal_strength = lgdt330x_read_signal_strength,
791 .read_snr = lgdt3302_read_snr,
792 .read_ucblocks = lgdt330x_read_ucblocks,
793 .release = lgdt330x_release,
794};
795
bd336e63 796static const struct dvb_frontend_ops lgdt3303_ops = {
ca7072dd 797 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
d8667cbb 798 .info = {
1963c907 799 .name= "LG Electronics LGDT3303 VSB/QAM Frontend",
d8667cbb
MM
800 .frequency_min= 54000000,
801 .frequency_max= 858000000,
802 .frequency_stepsize= 62500,
66944e99
MK
803 .symbol_rate_min = 5056941, /* QAM 64 */
804 .symbol_rate_max = 10762000, /* VSB 8 */
d8667cbb
MM
805 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
806 },
6ddcc919 807 .init = lgdt330x_init,
ca7072dd
MCC
808 .set_frontend = lgdt330x_set_parameters,
809 .get_frontend = lgdt330x_get_frontend,
6ddcc919 810 .get_tune_settings = lgdt330x_get_tune_settings,
1963c907 811 .read_status = lgdt3303_read_status,
6ddcc919
MK
812 .read_ber = lgdt330x_read_ber,
813 .read_signal_strength = lgdt330x_read_signal_strength,
1963c907 814 .read_snr = lgdt3303_read_snr,
6ddcc919
MK
815 .read_ucblocks = lgdt330x_read_ucblocks,
816 .release = lgdt330x_release,
d8667cbb
MM
817};
818
1963c907 819MODULE_DESCRIPTION("LGDT330X (ATSC 8VSB & ITU-T J.83 AnnexB 64/256 QAM) Demodulator Driver");
d8667cbb
MM
820MODULE_AUTHOR("Wilson Michaels");
821MODULE_LICENSE("GPL");
822
6ddcc919 823EXPORT_SYMBOL(lgdt330x_attach);