Merge tag 'v4.10-rc1' into docs-next
[linux-block.git] / drivers / media / dvb-frontends / lgdt330x.c
CommitLineData
d8667cbb 1/*
1963c907 2 * Support for LGDT3302 and LGDT3303 - VSB/QAM
d8667cbb
MM
3 *
4 * Copyright (C) 2005 Wilson Michaels <wilsonmichaels@earthlink.net>
5 *
d8667cbb
MM
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 *
20 */
21
22/*
23 * NOTES ABOUT THIS DRIVER
24 *
1963c907
MK
25 * This Linux driver supports:
26 * DViCO FusionHDTV 3 Gold-Q
27 * DViCO FusionHDTV 3 Gold-T
28 * DViCO FusionHDTV 5 Gold
3cff00d9 29 * DViCO FusionHDTV 5 Lite
d8e6acf2 30 * DViCO FusionHDTV 5 USB Gold
c0b11b91 31 * Air2PC/AirStar 2 ATSC 3rd generation (HD5000)
20fe4f65 32 * pcHDTV HD5500
d8667cbb 33 *
d8667cbb
MM
34 */
35
d8667cbb
MM
36#include <linux/kernel.h>
37#include <linux/module.h>
d8667cbb
MM
38#include <linux/init.h>
39#include <linux/delay.h>
4e57b681
TS
40#include <linux/string.h>
41#include <linux/slab.h>
d8667cbb
MM
42#include <asm/byteorder.h>
43
44#include "dvb_frontend.h"
19be685a 45#include "dvb_math.h"
6ddcc919
MK
46#include "lgdt330x_priv.h"
47#include "lgdt330x.h"
d8667cbb 48
19be685a
TP
49/* Use Equalizer Mean Squared Error instead of Phaser Tracker MSE */
50/* #define USE_EQMSE */
51
ff699e6b 52static int debug;
d8667cbb 53module_param(debug, int, 0644);
6ddcc919 54MODULE_PARM_DESC(debug,"Turn on/off lgdt330x frontend debugging (default:off).");
d8667cbb
MM
55#define dprintk(args...) \
56do { \
6ddcc919 57if (debug) printk(KERN_DEBUG "lgdt330x: " args); \
d8667cbb
MM
58} while (0)
59
6ddcc919 60struct lgdt330x_state
d8667cbb
MM
61{
62 struct i2c_adapter* i2c;
d8667cbb
MM
63
64 /* Configuration settings */
6ddcc919 65 const struct lgdt330x_config* config;
d8667cbb
MM
66
67 struct dvb_frontend frontend;
68
69 /* Demodulator private data */
0df289a2 70 enum fe_modulation current_modulation;
19be685a 71 u32 snr; /* Result of last SNR calculation */
d8667cbb
MM
72
73 /* Tuner private data */
74 u32 current_frequency;
75};
76
1963c907 77static int i2c_write_demod_bytes (struct lgdt330x_state* state,
dc9ca2af
MK
78 u8 *buf, /* data bytes to send */
79 int len /* number of bytes to send */ )
d8667cbb 80{
b6aef071 81 struct i2c_msg msg =
1963c907
MK
82 { .addr = state->config->demod_address,
83 .flags = 0,
84 .buf = buf,
85 .len = 2 };
b6aef071 86 int i;
1963c907 87 int err;
d8667cbb 88
1963c907 89 for (i=0; i<len-1; i+=2){
d8667cbb 90 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
271ddbf7 91 printk(KERN_WARNING "lgdt330x: %s error (addr %02x <- %02x, err = %i)\n", __func__, msg.buf[0], msg.buf[1], err);
58ba006b
MK
92 if (err < 0)
93 return err;
94 else
95 return -EREMOTEIO;
d8667cbb 96 }
1963c907 97 msg.buf += 2;
d8667cbb
MM
98 }
99 return 0;
100}
101
102/*
103 * This routine writes the register (reg) to the demod bus
104 * then reads the data returned for (len) bytes.
105 */
106
34817174
XW
107static int i2c_read_demod_bytes(struct lgdt330x_state *state,
108 enum I2C_REG reg, u8 *buf, int len)
d8667cbb
MM
109{
110 u8 wr [] = { reg };
111 struct i2c_msg msg [] = {
112 { .addr = state->config->demod_address,
113 .flags = 0, .buf = wr, .len = 1 },
114 { .addr = state->config->demod_address,
115 .flags = I2C_M_RD, .buf = buf, .len = len },
116 };
117 int ret;
118 ret = i2c_transfer(state->i2c, msg, 2);
119 if (ret != 2) {
271ddbf7 120 printk(KERN_WARNING "lgdt330x: %s: addr 0x%02x select 0x%02x error (ret == %i)\n", __func__, state->config->demod_address, reg, ret);
34817174
XW
121 if (ret >= 0)
122 ret = -EIO;
d8667cbb
MM
123 } else {
124 ret = 0;
125 }
126 return ret;
127}
128
129/* Software reset */
1963c907 130static int lgdt3302_SwReset(struct lgdt330x_state* state)
d8667cbb
MM
131{
132 u8 ret;
133 u8 reset[] = {
134 IRQ_MASK,
135 0x00 /* bit 6 is active low software reset
136 * bits 5-0 are 1 to mask interrupts */
137 };
138
1963c907 139 ret = i2c_write_demod_bytes(state,
dc9ca2af 140 reset, sizeof(reset));
d8667cbb 141 if (ret == 0) {
1963c907
MK
142
143 /* force reset high (inactive) and unmask interrupts */
144 reset[1] = 0x7f;
145 ret = i2c_write_demod_bytes(state,
dc9ca2af 146 reset, sizeof(reset));
d8667cbb 147 }
d8667cbb
MM
148 return ret;
149}
150
1963c907
MK
151static int lgdt3303_SwReset(struct lgdt330x_state* state)
152{
153 u8 ret;
154 u8 reset[] = {
155 0x02,
156 0x00 /* bit 0 is active low software reset */
157 };
158
159 ret = i2c_write_demod_bytes(state,
dc9ca2af 160 reset, sizeof(reset));
1963c907
MK
161 if (ret == 0) {
162
163 /* force reset high (inactive) */
164 reset[1] = 0x01;
165 ret = i2c_write_demod_bytes(state,
dc9ca2af 166 reset, sizeof(reset));
1963c907
MK
167 }
168 return ret;
169}
170
171static int lgdt330x_SwReset(struct lgdt330x_state* state)
172{
173 switch (state->config->demod_chip) {
174 case LGDT3302:
175 return lgdt3302_SwReset(state);
176 case LGDT3303:
177 return lgdt3303_SwReset(state);
178 default:
179 return -ENODEV;
180 }
181}
182
6ddcc919 183static int lgdt330x_init(struct dvb_frontend* fe)
d8667cbb
MM
184{
185 /* Hardware reset is done using gpio[0] of cx23880x chip.
186 * I'd like to do it here, but don't know how to find chip address.
187 * cx88-cards.c arranges for the reset bit to be inactive (high).
188 * Maybe there needs to be a callable function in cx88-core or
189 * the caller of this function needs to do it. */
190
1963c907
MK
191 /*
192 * Array of byte pairs <address, value>
193 * to initialize each different chip
194 */
195 static u8 lgdt3302_init_data[] = {
196 /* Use 50MHz parameter values from spec sheet since xtal is 50 */
197 /* Change the value of NCOCTFV[25:0] of carrier
198 recovery center frequency register */
199 VSB_CARRIER_FREQ0, 0x00,
200 VSB_CARRIER_FREQ1, 0x87,
201 VSB_CARRIER_FREQ2, 0x8e,
202 VSB_CARRIER_FREQ3, 0x01,
203 /* Change the TPCLK pin polarity
204 data is valid on falling clock */
205 DEMUX_CONTROL, 0xfb,
206 /* Change the value of IFBW[11:0] of
207 AGC IF/RF loop filter bandwidth register */
208 AGC_RF_BANDWIDTH0, 0x40,
209 AGC_RF_BANDWIDTH1, 0x93,
210 AGC_RF_BANDWIDTH2, 0x00,
211 /* Change the value of bit 6, 'nINAGCBY' and
212 'NSSEL[1:0] of ACG function control register 2 */
213 AGC_FUNC_CTRL2, 0xc6,
214 /* Change the value of bit 6 'RFFIX'
215 of AGC function control register 3 */
216 AGC_FUNC_CTRL3, 0x40,
217 /* Set the value of 'INLVTHD' register 0x2a/0x2c
218 to 0x7fe */
219 AGC_DELAY0, 0x07,
220 AGC_DELAY2, 0xfe,
221 /* Change the value of IAGCBW[15:8]
9aaeded7 222 of inner AGC loop filter bandwidth */
1963c907
MK
223 AGC_LOOP_BANDWIDTH0, 0x08,
224 AGC_LOOP_BANDWIDTH1, 0x9a
225 };
226
227 static u8 lgdt3303_init_data[] = {
228 0x4c, 0x14
229 };
230
c0f4c0ad 231 static u8 flip_1_lgdt3303_init_data[] = {
c0b11b91
MK
232 0x4c, 0x14,
233 0x87, 0xf3
234 };
235
c0f4c0ad
MK
236 static u8 flip_2_lgdt3303_init_data[] = {
237 0x4c, 0x14,
238 0x87, 0xda
239 };
240
1963c907
MK
241 struct lgdt330x_state* state = fe->demodulator_priv;
242 char *chip_name;
243 int err;
244
245 switch (state->config->demod_chip) {
246 case LGDT3302:
247 chip_name = "LGDT3302";
248 err = i2c_write_demod_bytes(state, lgdt3302_init_data,
dc9ca2af
MK
249 sizeof(lgdt3302_init_data));
250 break;
1963c907
MK
251 case LGDT3303:
252 chip_name = "LGDT3303";
c0f4c0ad
MK
253 switch (state->config->clock_polarity_flip) {
254 case 2:
255 err = i2c_write_demod_bytes(state,
256 flip_2_lgdt3303_init_data,
257 sizeof(flip_2_lgdt3303_init_data));
258 break;
259 case 1:
260 err = i2c_write_demod_bytes(state,
261 flip_1_lgdt3303_init_data,
262 sizeof(flip_1_lgdt3303_init_data));
263 break;
264 case 0:
265 default:
c0b11b91
MK
266 err = i2c_write_demod_bytes(state, lgdt3303_init_data,
267 sizeof(lgdt3303_init_data));
268 }
dc9ca2af 269 break;
1963c907
MK
270 default:
271 chip_name = "undefined";
272 printk (KERN_WARNING "Only LGDT3302 and LGDT3303 are supported chips.\n");
273 err = -ENODEV;
274 }
271ddbf7 275 dprintk("%s entered as %s\n", __func__, chip_name);
1963c907
MK
276 if (err < 0)
277 return err;
278 return lgdt330x_SwReset(state);
d8667cbb
MM
279}
280
6ddcc919 281static int lgdt330x_read_ber(struct dvb_frontend* fe, u32* ber)
d8667cbb 282{
1963c907 283 *ber = 0; /* Not supplied by the demod chips */
d8667cbb
MM
284 return 0;
285}
286
6ddcc919 287static int lgdt330x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
d8667cbb 288{
1963c907
MK
289 struct lgdt330x_state* state = fe->demodulator_priv;
290 int err;
d8667cbb
MM
291 u8 buf[2];
292
26110dac
MK
293 *ucblocks = 0;
294
1963c907
MK
295 switch (state->config->demod_chip) {
296 case LGDT3302:
297 err = i2c_read_demod_bytes(state, LGDT3302_PACKET_ERR_COUNTER1,
dc9ca2af
MK
298 buf, sizeof(buf));
299 break;
1963c907
MK
300 case LGDT3303:
301 err = i2c_read_demod_bytes(state, LGDT3303_PACKET_ERR_COUNTER1,
dc9ca2af
MK
302 buf, sizeof(buf));
303 break;
1963c907
MK
304 default:
305 printk(KERN_WARNING
dc9ca2af 306 "Only LGDT3302 and LGDT3303 are supported chips.\n");
1963c907
MK
307 err = -ENODEV;
308 }
26110dac
MK
309 if (err < 0)
310 return err;
d8667cbb
MM
311
312 *ucblocks = (buf[0] << 8) | buf[1];
313 return 0;
314}
315
ca7072dd 316static int lgdt330x_set_parameters(struct dvb_frontend *fe)
d8667cbb 317{
ca7072dd 318 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1963c907
MK
319 /*
320 * Array of byte pairs <address, value>
321 * to initialize 8VSB for lgdt3303 chip 50 MHz IF
322 */
323 static u8 lgdt3303_8vsb_44_data[] = {
324 0x04, 0x00,
325 0x0d, 0x40,
0b6389ff
MK
326 0x0e, 0x87,
327 0x0f, 0x8e,
328 0x10, 0x01,
329 0x47, 0x8b };
1963c907
MK
330
331 /*
332 * Array of byte pairs <address, value>
333 * to initialize QAM for lgdt3303 chip
334 */
335 static u8 lgdt3303_qam_data[] = {
336 0x04, 0x00,
337 0x0d, 0x00,
338 0x0e, 0x00,
339 0x0f, 0x00,
340 0x10, 0x00,
341 0x51, 0x63,
342 0x47, 0x66,
343 0x48, 0x66,
344 0x4d, 0x1a,
345 0x49, 0x08,
346 0x4a, 0x9b };
347
348 struct lgdt330x_state* state = fe->demodulator_priv;
d8667cbb 349
d8667cbb 350 static u8 top_ctrl_cfg[] = { TOP_CONTROL, 0x03 };
d8667cbb 351
54828d19 352 int err = 0;
d8667cbb 353 /* Change only if we are actually changing the modulation */
ca7072dd
MCC
354 if (state->current_modulation != p->modulation) {
355 switch (p->modulation) {
d8667cbb 356 case VSB_8:
271ddbf7 357 dprintk("%s: VSB_8 MODE\n", __func__);
d8667cbb 358
1963c907
MK
359 /* Select VSB mode */
360 top_ctrl_cfg[1] = 0x03;
0ccef6db
MK
361
362 /* Select ANT connector if supported by card */
363 if (state->config->pll_rf_set)
364 state->config->pll_rf_set(fe, 1);
1963c907
MK
365
366 if (state->config->demod_chip == LGDT3303) {
367 err = i2c_write_demod_bytes(state, lgdt3303_8vsb_44_data,
dc9ca2af 368 sizeof(lgdt3303_8vsb_44_data));
1963c907 369 }
d8667cbb
MM
370 break;
371
372 case QAM_64:
271ddbf7 373 dprintk("%s: QAM_64 MODE\n", __func__);
d8667cbb 374
1963c907
MK
375 /* Select QAM_64 mode */
376 top_ctrl_cfg[1] = 0x00;
0ccef6db
MK
377
378 /* Select CABLE connector if supported by card */
379 if (state->config->pll_rf_set)
380 state->config->pll_rf_set(fe, 0);
1963c907
MK
381
382 if (state->config->demod_chip == LGDT3303) {
383 err = i2c_write_demod_bytes(state, lgdt3303_qam_data,
384 sizeof(lgdt3303_qam_data));
385 }
d8667cbb
MM
386 break;
387
388 case QAM_256:
271ddbf7 389 dprintk("%s: QAM_256 MODE\n", __func__);
d8667cbb 390
1963c907
MK
391 /* Select QAM_256 mode */
392 top_ctrl_cfg[1] = 0x01;
0ccef6db
MK
393
394 /* Select CABLE connector if supported by card */
395 if (state->config->pll_rf_set)
396 state->config->pll_rf_set(fe, 0);
1963c907
MK
397
398 if (state->config->demod_chip == LGDT3303) {
399 err = i2c_write_demod_bytes(state, lgdt3303_qam_data,
400 sizeof(lgdt3303_qam_data));
401 }
d8667cbb
MM
402 break;
403 default:
ca7072dd 404 printk(KERN_WARNING "lgdt330x: %s: Modulation type(%d) UNSUPPORTED\n", __func__, p->modulation);
d8667cbb
MM
405 return -1;
406 }
54828d19 407 if (err < 0)
4bd69e7b 408 printk(KERN_WARNING "lgdt330x: %s: error blasting bytes to lgdt3303 for modulation type(%d)\n",
ca7072dd 409 __func__, p->modulation);
54828d19 410
1963c907
MK
411 /*
412 * select serial or parallel MPEG harware interface
413 * Serial: 0x04 for LGDT3302 or 0x40 for LGDT3303
414 * Parallel: 0x00
415 */
416 top_ctrl_cfg[1] |= state->config->serial_mpeg;
d8667cbb
MM
417
418 /* Select the requested mode */
1963c907 419 i2c_write_demod_bytes(state, top_ctrl_cfg,
dc9ca2af
MK
420 sizeof(top_ctrl_cfg));
421 if (state->config->set_ts_params)
422 state->config->set_ts_params(fe, 0);
ca7072dd 423 state->current_modulation = p->modulation;
d8667cbb 424 }
d8667cbb 425
dc9ca2af 426 /* Tune to the specified frequency */
dea74869 427 if (fe->ops.tuner_ops.set_params) {
14d24d14 428 fe->ops.tuner_ops.set_params(fe);
dea74869 429 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
02269f37 430 }
dc9ca2af
MK
431
432 /* Keep track of the new frequency */
4302c15e
MCC
433 /* FIXME this is the wrong way to do this... */
434 /* The tuner is shared with the video4linux analog API */
ca7072dd 435 state->current_frequency = p->frequency;
dc9ca2af 436
6ddcc919 437 lgdt330x_SwReset(state);
d8667cbb
MM
438 return 0;
439}
440
7e3e68bc
MCC
441static int lgdt330x_get_frontend(struct dvb_frontend *fe,
442 struct dtv_frontend_properties *p)
d8667cbb 443{
6ddcc919 444 struct lgdt330x_state *state = fe->demodulator_priv;
7e3e68bc 445
ca7072dd 446 p->frequency = state->current_frequency;
d8667cbb
MM
447 return 0;
448}
449
0df289a2
MCC
450static int lgdt3302_read_status(struct dvb_frontend *fe,
451 enum fe_status *status)
d8667cbb 452{
1963c907 453 struct lgdt330x_state* state = fe->demodulator_priv;
d8667cbb
MM
454 u8 buf[3];
455
456 *status = 0; /* Reset status result */
457
08d80525 458 /* AGC status register */
1963c907 459 i2c_read_demod_bytes(state, AGC_STATUS, buf, 1);
271ddbf7 460 dprintk("%s: AGC_STATUS = 0x%02x\n", __func__, buf[0]);
08d80525
MK
461 if ((buf[0] & 0x0c) == 0x8){
462 /* Test signal does not exist flag */
463 /* as well as the AGC lock flag. */
464 *status |= FE_HAS_SIGNAL;
08d80525
MK
465 }
466
1963c907
MK
467 /*
468 * You must set the Mask bits to 1 in the IRQ_MASK in order
469 * to see that status bit in the IRQ_STATUS register.
470 * This is done in SwReset();
471 */
d8667cbb 472 /* signal status */
1963c907 473 i2c_read_demod_bytes(state, TOP_CONTROL, buf, sizeof(buf));
271ddbf7 474 dprintk("%s: TOP_CONTROL = 0x%02x, IRO_MASK = 0x%02x, IRQ_STATUS = 0x%02x\n", __func__, buf[0], buf[1], buf[2]);
08d80525 475
d8667cbb
MM
476
477 /* sync status */
478 if ((buf[2] & 0x03) == 0x01) {
479 *status |= FE_HAS_SYNC;
480 }
481
482 /* FEC error status */
483 if ((buf[2] & 0x0c) == 0x08) {
484 *status |= FE_HAS_LOCK;
485 *status |= FE_HAS_VITERBI;
486 }
487
d8667cbb 488 /* Carrier Recovery Lock Status Register */
1963c907 489 i2c_read_demod_bytes(state, CARRIER_LOCK, buf, 1);
271ddbf7 490 dprintk("%s: CARRIER_LOCK = 0x%02x\n", __func__, buf[0]);
d8667cbb
MM
491 switch (state->current_modulation) {
492 case QAM_256:
493 case QAM_64:
af901ca1 494 /* Need to understand why there are 3 lock levels here */
d8667cbb
MM
495 if ((buf[0] & 0x07) == 0x07)
496 *status |= FE_HAS_CARRIER;
d8667cbb 497 break;
d8667cbb
MM
498 case VSB_8:
499 if ((buf[0] & 0x80) == 0x80)
500 *status |= FE_HAS_CARRIER;
d8667cbb 501 break;
d8667cbb 502 default:
271ddbf7 503 printk(KERN_WARNING "lgdt330x: %s: Modulation set to unsupported value\n", __func__);
d8667cbb 504 }
d8667cbb
MM
505
506 return 0;
507}
508
0df289a2
MCC
509static int lgdt3303_read_status(struct dvb_frontend *fe,
510 enum fe_status *status)
1963c907
MK
511{
512 struct lgdt330x_state* state = fe->demodulator_priv;
513 int err;
514 u8 buf[3];
515
516 *status = 0; /* Reset status result */
517
518 /* lgdt3303 AGC status register */
519 err = i2c_read_demod_bytes(state, 0x58, buf, 1);
520 if (err < 0)
521 return err;
522
271ddbf7 523 dprintk("%s: AGC_STATUS = 0x%02x\n", __func__, buf[0]);
1963c907
MK
524 if ((buf[0] & 0x21) == 0x01){
525 /* Test input signal does not exist flag */
526 /* as well as the AGC lock flag. */
527 *status |= FE_HAS_SIGNAL;
1963c907
MK
528 }
529
530 /* Carrier Recovery Lock Status Register */
531 i2c_read_demod_bytes(state, CARRIER_LOCK, buf, 1);
271ddbf7 532 dprintk("%s: CARRIER_LOCK = 0x%02x\n", __func__, buf[0]);
1963c907
MK
533 switch (state->current_modulation) {
534 case QAM_256:
535 case QAM_64:
af901ca1 536 /* Need to understand why there are 3 lock levels here */
1963c907
MK
537 if ((buf[0] & 0x07) == 0x07)
538 *status |= FE_HAS_CARRIER;
539 else
540 break;
541 i2c_read_demod_bytes(state, 0x8a, buf, 1);
542 if ((buf[0] & 0x04) == 0x04)
543 *status |= FE_HAS_SYNC;
544 if ((buf[0] & 0x01) == 0x01)
545 *status |= FE_HAS_LOCK;
546 if ((buf[0] & 0x08) == 0x08)
547 *status |= FE_HAS_VITERBI;
548 break;
549 case VSB_8:
550 if ((buf[0] & 0x80) == 0x80)
551 *status |= FE_HAS_CARRIER;
552 else
553 break;
554 i2c_read_demod_bytes(state, 0x38, buf, 1);
555 if ((buf[0] & 0x02) == 0x00)
556 *status |= FE_HAS_SYNC;
557 if ((buf[0] & 0x01) == 0x01) {
558 *status |= FE_HAS_LOCK;
559 *status |= FE_HAS_VITERBI;
560 }
561 break;
562 default:
271ddbf7 563 printk(KERN_WARNING "lgdt330x: %s: Modulation set to unsupported value\n", __func__);
1963c907
MK
564 }
565 return 0;
566}
567
19be685a
TP
568/* Calculate SNR estimation (scaled by 2^24)
569
570 8-VSB SNR equations from LGDT3302 and LGDT3303 datasheets, QAM
571 equations from LGDT3303 datasheet. VSB is the same between the '02
572 and '03, so maybe QAM is too? Perhaps someone with a newer datasheet
573 that has QAM information could verify?
574
575 For 8-VSB: (two ways, take your pick)
576 LGDT3302:
577 SNR_EQ = 10 * log10(25 * 24^2 / EQ_MSE)
578 LGDT3303:
579 SNR_EQ = 10 * log10(25 * 32^2 / EQ_MSE)
580 LGDT3302 & LGDT3303:
581 SNR_PT = 10 * log10(25 * 32^2 / PT_MSE) (we use this one)
582 For 64-QAM:
583 SNR = 10 * log10( 688128 / MSEQAM)
584 For 256-QAM:
585 SNR = 10 * log10( 696320 / MSEQAM)
586
587 We re-write the snr equation as:
588 SNR * 2^24 = 10*(c - intlog10(MSE))
589 Where for 256-QAM, c = log10(696320) * 2^24, and so on. */
590
591static u32 calculate_snr(u32 mse, u32 c)
d8667cbb 592{
19be685a
TP
593 if (mse == 0) /* No signal */
594 return 0;
595
596 mse = intlog10(mse);
597 if (mse > c) {
598 /* Negative SNR, which is possible, but realisticly the
599 demod will lose lock before the signal gets this bad. The
600 API only allows for unsigned values, so just return 0 */
601 return 0;
602 }
603 return 10*(c - mse);
d8667cbb
MM
604}
605
1963c907 606static int lgdt3302_read_snr(struct dvb_frontend* fe, u16* snr)
d8667cbb 607{
6ddcc919 608 struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv;
19be685a
TP
609 u8 buf[5]; /* read data buffer */
610 u32 noise; /* noise value */
611 u32 c; /* per-modulation SNR calculation constant */
d8667cbb 612
19be685a
TP
613 switch(state->current_modulation) {
614 case VSB_8:
615 i2c_read_demod_bytes(state, LGDT3302_EQPH_ERR0, buf, 5);
616#ifdef USE_EQMSE
617 /* Use Equalizer Mean-Square Error Register */
618 /* SNR for ranges from -15.61 to +41.58 */
d8667cbb 619 noise = ((buf[0] & 7) << 16) | (buf[1] << 8) | buf[2];
19be685a 620 c = 69765745; /* log10(25*24^2)*2^24 */
d8667cbb 621#else
19be685a
TP
622 /* Use Phase Tracker Mean-Square Error Register */
623 /* SNR for ranges from -13.11 to +44.08 */
d8667cbb 624 noise = ((buf[0] & 7<<3) << 13) | (buf[3] << 8) | buf[4];
19be685a
TP
625 c = 73957994; /* log10(25*32^2)*2^24 */
626#endif
627 break;
628 case QAM_64:
629 case QAM_256:
630 i2c_read_demod_bytes(state, CARRIER_MSEQAM1, buf, 2);
1963c907 631 noise = ((buf[0] & 3) << 8) | buf[1];
19be685a
TP
632 c = state->current_modulation == QAM_64 ? 97939837 : 98026066;
633 /* log10(688128)*2^24 and log10(696320)*2^24 */
634 break;
635 default:
636 printk(KERN_ERR "lgdt330x: %s: Modulation set to unsupported value\n",
271ddbf7 637 __func__);
19be685a 638 return -EREMOTEIO; /* return -EDRIVER_IS_GIBBERED; */
d8667cbb
MM
639 }
640
19be685a
TP
641 state->snr = calculate_snr(noise, c);
642 *snr = (state->snr) >> 16; /* Convert from 8.24 fixed-point to 8.8 */
d8667cbb 643
271ddbf7 644 dprintk("%s: noise = 0x%08x, snr = %d.%02d dB\n", __func__, noise,
19be685a 645 state->snr >> 24, (((state->snr>>8) & 0xffff) * 100) >> 16);
d8667cbb
MM
646
647 return 0;
648}
649
1963c907
MK
650static int lgdt3303_read_snr(struct dvb_frontend* fe, u16* snr)
651{
1963c907 652 struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv;
19be685a
TP
653 u8 buf[5]; /* read data buffer */
654 u32 noise; /* noise value */
655 u32 c; /* per-modulation SNR calculation constant */
1963c907 656
19be685a
TP
657 switch(state->current_modulation) {
658 case VSB_8:
659 i2c_read_demod_bytes(state, LGDT3303_EQPH_ERR0, buf, 5);
660#ifdef USE_EQMSE
661 /* Use Equalizer Mean-Square Error Register */
662 /* SNR for ranges from -16.12 to +44.08 */
663 noise = ((buf[0] & 0x78) << 13) | (buf[1] << 8) | buf[2];
664 c = 73957994; /* log10(25*32^2)*2^24 */
665#else
666 /* Use Phase Tracker Mean-Square Error Register */
667 /* SNR for ranges from -13.11 to +44.08 */
1963c907 668 noise = ((buf[0] & 7) << 16) | (buf[3] << 8) | buf[4];
19be685a
TP
669 c = 73957994; /* log10(25*32^2)*2^24 */
670#endif
671 break;
672 case QAM_64:
673 case QAM_256:
674 i2c_read_demod_bytes(state, CARRIER_MSEQAM1, buf, 2);
1963c907 675 noise = (buf[0] << 8) | buf[1];
19be685a
TP
676 c = state->current_modulation == QAM_64 ? 97939837 : 98026066;
677 /* log10(688128)*2^24 and log10(696320)*2^24 */
678 break;
679 default:
680 printk(KERN_ERR "lgdt330x: %s: Modulation set to unsupported value\n",
271ddbf7 681 __func__);
19be685a 682 return -EREMOTEIO; /* return -EDRIVER_IS_GIBBERED; */
1963c907
MK
683 }
684
19be685a
TP
685 state->snr = calculate_snr(noise, c);
686 *snr = (state->snr) >> 16; /* Convert from 8.24 fixed-point to 8.8 */
687
271ddbf7 688 dprintk("%s: noise = 0x%08x, snr = %d.%02d dB\n", __func__, noise,
19be685a
TP
689 state->snr >> 24, (((state->snr >> 8) & 0xffff) * 100) >> 16);
690
691 return 0;
692}
693
694static int lgdt330x_read_signal_strength(struct dvb_frontend* fe, u16* strength)
695{
696 /* Calculate Strength from SNR up to 35dB */
697 /* Even though the SNR can go higher than 35dB, there is some comfort */
698 /* factor in having a range of strong signals that can show at 100% */
699 struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv;
700 u16 snr;
701 int ret;
1963c907 702
19be685a
TP
703 ret = fe->ops.read_snr(fe, &snr);
704 if (ret != 0)
705 return ret;
706 /* Rather than use the 8.8 value snr, use state->snr which is 8.24 */
707 /* scale the range 0 - 35*2^24 into 0 - 65535 */
708 if (state->snr >= 8960 * 0x10000)
709 *strength = 0xffff;
710 else
711 *strength = state->snr / 8960;
1963c907
MK
712
713 return 0;
714}
715
6ddcc919 716static int lgdt330x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
d8667cbb
MM
717{
718 /* I have no idea about this - it may not be needed */
719 fe_tune_settings->min_delay_ms = 500;
720 fe_tune_settings->step_size = 0;
721 fe_tune_settings->max_drift = 0;
722 return 0;
723}
724
6ddcc919 725static void lgdt330x_release(struct dvb_frontend* fe)
d8667cbb 726{
6ddcc919 727 struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv;
d8667cbb
MM
728 kfree(state);
729}
730
bd336e63
MK
731static const struct dvb_frontend_ops lgdt3302_ops;
732static const struct dvb_frontend_ops lgdt3303_ops;
d8667cbb 733
6ddcc919 734struct dvb_frontend* lgdt330x_attach(const struct lgdt330x_config* config,
d8667cbb
MM
735 struct i2c_adapter* i2c)
736{
6ddcc919 737 struct lgdt330x_state* state = NULL;
d8667cbb
MM
738 u8 buf[1];
739
740 /* Allocate memory for the internal state */
7408187d 741 state = kzalloc(sizeof(struct lgdt330x_state), GFP_KERNEL);
d8667cbb
MM
742 if (state == NULL)
743 goto error;
d8667cbb
MM
744
745 /* Setup the state */
746 state->config = config;
747 state->i2c = i2c;
dea74869
PB
748
749 /* Create dvb_frontend */
1963c907
MK
750 switch (config->demod_chip) {
751 case LGDT3302:
dea74869 752 memcpy(&state->frontend.ops, &lgdt3302_ops, sizeof(struct dvb_frontend_ops));
1963c907
MK
753 break;
754 case LGDT3303:
dea74869 755 memcpy(&state->frontend.ops, &lgdt3303_ops, sizeof(struct dvb_frontend_ops));
1963c907
MK
756 break;
757 default:
758 goto error;
759 }
dea74869 760 state->frontend.demodulator_priv = state;
1963c907 761
d8667cbb 762 /* Verify communication with demod chip */
1963c907 763 if (i2c_read_demod_bytes(state, 2, buf, 1))
d8667cbb
MM
764 goto error;
765
766 state->current_frequency = -1;
767 state->current_modulation = -1;
768
d8667cbb
MM
769 return &state->frontend;
770
771error:
2ea75330 772 kfree(state);
271ddbf7 773 dprintk("%s: ERROR\n",__func__);
d8667cbb
MM
774 return NULL;
775}
776
bd336e63 777static const struct dvb_frontend_ops lgdt3302_ops = {
ca7072dd 778 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
1963c907 779 .info = {
e179d8b0 780 .name= "LG Electronics LGDT3302 VSB/QAM Frontend",
1963c907
MK
781 .frequency_min= 54000000,
782 .frequency_max= 858000000,
783 .frequency_stepsize= 62500,
66944e99
MK
784 .symbol_rate_min = 5056941, /* QAM 64 */
785 .symbol_rate_max = 10762000, /* VSB 8 */
1963c907
MK
786 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
787 },
788 .init = lgdt330x_init,
ca7072dd
MCC
789 .set_frontend = lgdt330x_set_parameters,
790 .get_frontend = lgdt330x_get_frontend,
1963c907
MK
791 .get_tune_settings = lgdt330x_get_tune_settings,
792 .read_status = lgdt3302_read_status,
793 .read_ber = lgdt330x_read_ber,
794 .read_signal_strength = lgdt330x_read_signal_strength,
795 .read_snr = lgdt3302_read_snr,
796 .read_ucblocks = lgdt330x_read_ucblocks,
797 .release = lgdt330x_release,
798};
799
bd336e63 800static const struct dvb_frontend_ops lgdt3303_ops = {
ca7072dd 801 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
d8667cbb 802 .info = {
1963c907 803 .name= "LG Electronics LGDT3303 VSB/QAM Frontend",
d8667cbb
MM
804 .frequency_min= 54000000,
805 .frequency_max= 858000000,
806 .frequency_stepsize= 62500,
66944e99
MK
807 .symbol_rate_min = 5056941, /* QAM 64 */
808 .symbol_rate_max = 10762000, /* VSB 8 */
d8667cbb
MM
809 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
810 },
6ddcc919 811 .init = lgdt330x_init,
ca7072dd
MCC
812 .set_frontend = lgdt330x_set_parameters,
813 .get_frontend = lgdt330x_get_frontend,
6ddcc919 814 .get_tune_settings = lgdt330x_get_tune_settings,
1963c907 815 .read_status = lgdt3303_read_status,
6ddcc919
MK
816 .read_ber = lgdt330x_read_ber,
817 .read_signal_strength = lgdt330x_read_signal_strength,
1963c907 818 .read_snr = lgdt3303_read_snr,
6ddcc919
MK
819 .read_ucblocks = lgdt330x_read_ucblocks,
820 .release = lgdt330x_release,
d8667cbb
MM
821};
822
1963c907 823MODULE_DESCRIPTION("LGDT330X (ATSC 8VSB & ITU-T J.83 AnnexB 64/256 QAM) Demodulator Driver");
d8667cbb
MM
824MODULE_AUTHOR("Wilson Michaels");
825MODULE_LICENSE("GPL");
826
6ddcc919 827EXPORT_SYMBOL(lgdt330x_attach);