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media: dvb-frontends/mxl5xx: declare LIST_HEAD(mxllist) static
[linux-2.6-block.git] / drivers / media / dvb-frontends / lgdt3306a.c
CommitLineData
b63b36fa
FR		 1/*
2 * Support for LGDT3306A - 8VSB/QAM-B
3 *
4 * Copyright (C) 2013 Fred Richter <frichter@hauppauge.com>
5 * - driver structure based on lgdt3305.[ch] by Michael Krufky
6 * - code based on LG3306_V0.35 API by LG Electronics Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
b63b36fa
FR		 17 */
18
097117ca
MCC		 19#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
b63b36fa
FR		 21#include <asm/div64.h>
22#include <linux/dvb/frontend.h>
23#include "dvb_math.h"
24#include "lgdt3306a.h"
4f751890 25#include <linux/i2c-mux.h>
b63b36fa
FR		 26
27
28static int debug;
29module_param(debug, int, 0644);
30MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))");
31
32#define DBG_INFO 1
33#define DBG_REG 2
8e8cd34e 34#define DBG_DUMP 4 /* FGR - comment out to remove dump code */
b63b36fa 35
097117ca
MCC		 36#define lg_debug(fmt, arg...) \
37 printk(KERN_DEBUG pr_fmt(fmt), ## arg)
38
39#define dbg_info(fmt, arg...) \
40 do { \
41 if (debug & DBG_INFO) \
42 lg_debug(fmt, ## arg); \
43 } while (0)
b63b36fa 44
097117ca
MCC		 45#define dbg_reg(fmt, arg...) \
46 do { \
47 if (debug & DBG_REG) \
48 lg_debug(fmt, ## arg); \
49 } while (0)
b63b36fa
FR		 50
51#define lg_chkerr(ret) \
52({ \
53 int __ret; \
54 __ret = (ret < 0); \
55 if (__ret) \
097117ca 56 pr_err("error %d on line %d\n", ret, __LINE__); \
b63b36fa
FR		 57 __ret; \
58})
59
60struct lgdt3306a_state {
61 struct i2c_adapter *i2c_adap;
62 const struct lgdt3306a_config *cfg;
63
64 struct dvb_frontend frontend;
65
0df289a2 66 enum fe_modulation current_modulation;
b63b36fa
FR		 67 u32 current_frequency;
68 u32 snr;
4f751890
KC		 69
70 struct i2c_mux_core *muxc;
b63b36fa
FR		 71};
72
95f22c5a
MCC		 73/*
74 * LG3306A Register Usage
75 * (LG does not really name the registers, so this code does not either)
76 *
77 * 0000 -> 00FF Common control and status
78 * 1000 -> 10FF Synchronizer control and status
79 * 1F00 -> 1FFF Smart Antenna control and status
80 * 2100 -> 21FF VSB Equalizer control and status
81 * 2800 -> 28FF QAM Equalizer control and status
82 * 3000 -> 30FF FEC control and status
83 */
b63b36fa 84
f883d603
MIK		 85enum lgdt3306a_lock_status {
86 LG3306_UNLOCK = 0x00,
87 LG3306_LOCK = 0x01,
4937ba94 88 LG3306_UNKNOWN_LOCK = 0xff
f883d603 89};
b63b36fa 90
f883d603 91enum lgdt3306a_neverlock_status {
b63b36fa
FR		 92 LG3306_NL_INIT = 0x00,
93 LG3306_NL_PROCESS = 0x01,
94 LG3306_NL_LOCK = 0x02,
95 LG3306_NL_FAIL = 0x03,
4937ba94 96 LG3306_NL_UNKNOWN = 0xff
f883d603 97};
b63b36fa 98
f883d603
MIK		 99enum lgdt3306a_modulation {
100 LG3306_VSB = 0x00,
101 LG3306_QAM64 = 0x01,
102 LG3306_QAM256 = 0x02,
4937ba94 103 LG3306_UNKNOWN_MODE = 0xff
f883d603 104};
b63b36fa 105
f883d603 106enum lgdt3306a_lock_check {
b63b36fa
FR		 107 LG3306_SYNC_LOCK,
108 LG3306_FEC_LOCK,
109 LG3306_TR_LOCK,
110 LG3306_AGC_LOCK,
f883d603 111};
b63b36fa
FR		 112
113
114#ifdef DBG_DUMP
115static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state);
116static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state);
117#endif
118
119
120static int lgdt3306a_write_reg(struct lgdt3306a_state *state, u16 reg, u8 val)
121{
122 int ret;
123 u8 buf[] = { reg >> 8, reg & 0xff, val };
124 struct i2c_msg msg = {
125 .addr = state->cfg->i2c_addr, .flags = 0,
126 .buf = buf, .len = 3,
127 };
128
097117ca 129 dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
b63b36fa
FR		 130
131 ret = i2c_transfer(state->i2c_adap, &msg, 1);
132
133 if (ret != 1) {
097117ca 134 pr_err("error (addr %02x %02x <- %02x, err = %i)\n",
b63b36fa
FR		 135 msg.buf[0], msg.buf[1], msg.buf[2], ret);
136 if (ret < 0)
137 return ret;
138 else
139 return -EREMOTEIO;
140 }
141 return 0;
142}
143
144static int lgdt3306a_read_reg(struct lgdt3306a_state *state, u16 reg, u8 *val)
145{
146 int ret;
147 u8 reg_buf[] = { reg >> 8, reg & 0xff };
148 struct i2c_msg msg[] = {
149 { .addr = state->cfg->i2c_addr,
150 .flags = 0, .buf = reg_buf, .len = 2 },
151 { .addr = state->cfg->i2c_addr,
152 .flags = I2C_M_RD, .buf = val, .len = 1 },
153 };
154
155 ret = i2c_transfer(state->i2c_adap, msg, 2);
156
157 if (ret != 2) {
097117ca 158 pr_err("error (addr %02x reg %04x error (ret == %i)\n",
b63b36fa
FR		 159 state->cfg->i2c_addr, reg, ret);
160 if (ret < 0)
161 return ret;
162 else
163 return -EREMOTEIO;
164 }
097117ca 165 dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, *val);
b63b36fa
FR		 166
167 return 0;
168}
169
170#define read_reg(state, reg) \
171({ \
172 u8 __val; \
173 int ret = lgdt3306a_read_reg(state, reg, &__val); \
174 if (lg_chkerr(ret)) \
175 __val = 0; \
176 __val; \
177})
178
179static int lgdt3306a_set_reg_bit(struct lgdt3306a_state *state,
180 u16 reg, int bit, int onoff)
181{
182 u8 val;
183 int ret;
184
097117ca 185 dbg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
b63b36fa
FR		 186
187 ret = lgdt3306a_read_reg(state, reg, &val);
188 if (lg_chkerr(ret))
189 goto fail;
190
191 val &= ~(1 << bit);
192 val |= (onoff & 1) << bit;
193
194 ret = lgdt3306a_write_reg(state, reg, val);
195 lg_chkerr(ret);
196fail:
197 return ret;
198}
199
200/* ------------------------------------------------------------------------ */
201
202static int lgdt3306a_soft_reset(struct lgdt3306a_state *state)
203{
204 int ret;
205
097117ca 206 dbg_info("\n");
b63b36fa
FR		 207
208 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
209 if (lg_chkerr(ret))
210 goto fail;
211
212 msleep(20);
213 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
214 lg_chkerr(ret);
215
216fail:
217 return ret;
218}
219
220static int lgdt3306a_mpeg_mode(struct lgdt3306a_state *state,
221 enum lgdt3306a_mpeg_mode mode)
222{
223 u8 val;
224 int ret;
225
097117ca 226 dbg_info("(%d)\n", mode);
534f4364
MCC		 227 /* transport packet format - TPSENB=0x80 */
228 ret = lgdt3306a_set_reg_bit(state, 0x0071, 7,
229 mode == LGDT3306A_MPEG_PARALLEL ? 1 : 0);
b63b36fa
FR		 230 if (lg_chkerr(ret))
231 goto fail;
232
534f4364
MCC		 233 /*
234 * start of packet signal duration
235 * TPSSOPBITEN=0x40; 0=byte duration, 1=bit duration
236 */
237 ret = lgdt3306a_set_reg_bit(state, 0x0071, 6, 0);
b63b36fa
FR		 238 if (lg_chkerr(ret))
239 goto fail;
240
241 ret = lgdt3306a_read_reg(state, 0x0070, &val);
242 if (lg_chkerr(ret))
243 goto fail;
244
8e8cd34e 245 val |= 0x10; /* TPCLKSUPB=0x10 */
b63b36fa 246
8e8cd34e 247 if (mode == LGDT3306A_MPEG_PARALLEL)
b63b36fa
FR		 248 val &= ~0x10;
249
250 ret = lgdt3306a_write_reg(state, 0x0070, val);
251 lg_chkerr(ret);
252
253fail:
254 return ret;
255}
256
257static int lgdt3306a_mpeg_mode_polarity(struct lgdt3306a_state *state,
258 enum lgdt3306a_tp_clock_edge edge,
259 enum lgdt3306a_tp_valid_polarity valid)
260{
261 u8 val;
262 int ret;
263
097117ca 264 dbg_info("edge=%d, valid=%d\n", edge, valid);
b63b36fa
FR		 265
266 ret = lgdt3306a_read_reg(state, 0x0070, &val);
267 if (lg_chkerr(ret))
268 goto fail;
269
8e8cd34e 270 val &= ~0x06; /* TPCLKPOL=0x04, TPVALPOL=0x02 */
b63b36fa 271
8e8cd34e 272 if (edge == LGDT3306A_TPCLK_RISING_EDGE)
b63b36fa 273 val |= 0x04;
8e8cd34e 274 if (valid == LGDT3306A_TP_VALID_HIGH)
b63b36fa
FR		 275 val |= 0x02;
276
277 ret = lgdt3306a_write_reg(state, 0x0070, val);
278 lg_chkerr(ret);
279
280fail:
281 return ret;
282}
283
284static int lgdt3306a_mpeg_tristate(struct lgdt3306a_state *state,
285 int mode)
286{
287 u8 val;
288 int ret;
289
097117ca 290 dbg_info("(%d)\n", mode);
b63b36fa 291
8e8cd34e 292 if (mode) {
b63b36fa
FR		 293 ret = lgdt3306a_read_reg(state, 0x0070, &val);
294 if (lg_chkerr(ret))
295 goto fail;
534f4364
MCC		 296 /*
297 * Tristate bus; TPOUTEN=0x80, TPCLKOUTEN=0x20,
298 * TPDATAOUTEN=0x08
299 */
300 val &= ~0xa8;
b63b36fa
FR		 301 ret = lgdt3306a_write_reg(state, 0x0070, val);
302 if (lg_chkerr(ret))
303 goto fail;
304
534f4364
MCC		 305 /* AGCIFOUTENB=0x40; 1=Disable IFAGC pin */
306 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 1);
b63b36fa
FR		 307 if (lg_chkerr(ret))
308 goto fail;
309
310 } else {
534f4364
MCC		 311 /* enable IFAGC pin */
312 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 0);
b63b36fa
FR		 313 if (lg_chkerr(ret))
314 goto fail;
315
316 ret = lgdt3306a_read_reg(state, 0x0070, &val);
317 if (lg_chkerr(ret))
318 goto fail;
319
4937ba94 320 val |= 0xa8; /* enable bus */
b63b36fa
FR		 321 ret = lgdt3306a_write_reg(state, 0x0070, val);
322 if (lg_chkerr(ret))
323 goto fail;
324 }
325
326fail:
327 return ret;
328}
329
8e8cd34e 330static int lgdt3306a_ts_bus_ctrl(struct dvb_frontend *fe, int acquire)
b63b36fa
FR		 331{
332 struct lgdt3306a_state *state = fe->demodulator_priv;
333
097117ca 334 dbg_info("acquire=%d\n", acquire);
b63b36fa
FR		 335
336 return lgdt3306a_mpeg_tristate(state, acquire ? 0 : 1);
337
338}
339
340static int lgdt3306a_power(struct lgdt3306a_state *state,
341 int mode)
342{
343 int ret;
344
097117ca 345 dbg_info("(%d)\n", mode);
b63b36fa 346
8e8cd34e 347 if (mode == 0) {
534f4364
MCC		 348 /* into reset */
349 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
b63b36fa
FR		 350 if (lg_chkerr(ret))
351 goto fail;
352
534f4364
MCC		 353 /* power down */
354 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 0);
b63b36fa
FR		 355 if (lg_chkerr(ret))
356 goto fail;
357
358 } else {
534f4364
MCC		 359 /* out of reset */
360 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
b63b36fa
FR		 361 if (lg_chkerr(ret))
362 goto fail;
363
534f4364
MCC		 364 /* power up */
365 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 1);
b63b36fa
FR		 366 if (lg_chkerr(ret))
367 goto fail;
368 }
369
370#ifdef DBG_DUMP
371 lgdt3306a_DumpAllRegs(state);
372#endif
373fail:
374 return ret;
375}
376
377
378static int lgdt3306a_set_vsb(struct lgdt3306a_state *state)
379{
380 u8 val;
381 int ret;
382
097117ca 383 dbg_info("\n");
b63b36fa 384
8e8cd34e 385 /* 0. Spectrum inversion detection manual; spectrum inverted */
b63b36fa 386 ret = lgdt3306a_read_reg(state, 0x0002, &val);
4937ba94 387 val &= 0xf7; /* SPECINVAUTO Off */
8e8cd34e 388 val |= 0x04; /* SPECINV On */
b63b36fa
FR		 389 ret = lgdt3306a_write_reg(state, 0x0002, val);
390 if (lg_chkerr(ret))
391 goto fail;
392
8e8cd34e 393 /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
b63b36fa
FR		 394 ret = lgdt3306a_write_reg(state, 0x0008, 0x80);
395 if (lg_chkerr(ret))
396 goto fail;
397
8e8cd34e 398 /* 2. Bandwidth mode for VSB(6MHz) */
b63b36fa 399 ret = lgdt3306a_read_reg(state, 0x0009, &val);
4937ba94
MCC		 400 val &= 0xe3;
401 val |= 0x0c; /* STDOPDETTMODE[2:0]=3 */
b63b36fa
FR		 402 ret = lgdt3306a_write_reg(state, 0x0009, val);
403 if (lg_chkerr(ret))
404 goto fail;
405
8e8cd34e 406 /* 3. QAM mode detection mode(None) */
b63b36fa 407 ret = lgdt3306a_read_reg(state, 0x0009, &val);
4937ba94 408 val &= 0xfc; /* STDOPDETCMODE[1:0]=0 */
b63b36fa
FR		 409 ret = lgdt3306a_write_reg(state, 0x0009, val);
410 if (lg_chkerr(ret))
411 goto fail;
412
8e8cd34e 413 /* 4. ADC sampling frequency rate(2x sampling) */
4937ba94
MCC		 414 ret = lgdt3306a_read_reg(state, 0x000d, &val);
415 val &= 0xbf; /* SAMPLING4XFEN=0 */
416 ret = lgdt3306a_write_reg(state, 0x000d, val);
b63b36fa
FR		 417 if (lg_chkerr(ret))
418 goto fail;
419
8e8cd34e
MIK		 420#if 0
421 /* FGR - disable any AICC filtering, testing only */
422
b63b36fa
FR		 423 ret = lgdt3306a_write_reg(state, 0x0024, 0x00);
424 if (lg_chkerr(ret))
425 goto fail;
426
8e8cd34e 427 /* AICCFIXFREQ0 NT N-1(Video rejection) */
4937ba94
MCC		 428 ret = lgdt3306a_write_reg(state, 0x002e, 0x00);
429 ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
b63b36fa
FR		 430 ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
431
8e8cd34e 432 /* AICCFIXFREQ1 NT N-1(Audio rejection) */
4937ba94
MCC		 433 ret = lgdt3306a_write_reg(state, 0x002b, 0x00);
434 ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
435 ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
b63b36fa 436
8e8cd34e 437 /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
b63b36fa
FR		 438 ret = lgdt3306a_write_reg(state, 0x0028, 0x00);
439 ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
4937ba94 440 ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
b63b36fa 441
8e8cd34e 442 /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
b63b36fa
FR		 443 ret = lgdt3306a_write_reg(state, 0x0025, 0x00);
444 ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
445 ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
446
8e8cd34e
MIK		 447#else
448 /* FGR - this works well for HVR-1955,1975 */
449
450 /* 5. AICCOPMODE NT N-1 Adj. */
b63b36fa
FR		 451 ret = lgdt3306a_write_reg(state, 0x0024, 0x5A);
452 if (lg_chkerr(ret))
453 goto fail;
454
8e8cd34e 455 /* AICCFIXFREQ0 NT N-1(Video rejection) */
4937ba94
MCC		 456 ret = lgdt3306a_write_reg(state, 0x002e, 0x5A);
457 ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
b63b36fa
FR		 458 ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
459
8e8cd34e 460 /* AICCFIXFREQ1 NT N-1(Audio rejection) */
4937ba94
MCC		 461 ret = lgdt3306a_write_reg(state, 0x002b, 0x36);
462 ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
463 ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
b63b36fa 464
8e8cd34e 465 /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
b63b36fa
FR		 466 ret = lgdt3306a_write_reg(state, 0x0028, 0x2A);
467 ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
4937ba94 468 ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
b63b36fa 469
8e8cd34e 470 /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
b63b36fa
FR		 471 ret = lgdt3306a_write_reg(state, 0x0025, 0x06);
472 ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
473 ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
474#endif
475
4937ba94
MCC		 476 ret = lgdt3306a_read_reg(state, 0x001e, &val);
477 val &= 0x0f;
478 val |= 0xa0;
479 ret = lgdt3306a_write_reg(state, 0x001e, val);
b63b36fa
FR		 480
481 ret = lgdt3306a_write_reg(state, 0x0022, 0x08);
482
483 ret = lgdt3306a_write_reg(state, 0x0023, 0xFF);
484
4937ba94
MCC		 485 ret = lgdt3306a_read_reg(state, 0x211f, &val);
486 val &= 0xef;
487 ret = lgdt3306a_write_reg(state, 0x211f, val);
b63b36fa
FR		 488
489 ret = lgdt3306a_write_reg(state, 0x2173, 0x01);
490
491 ret = lgdt3306a_read_reg(state, 0x1061, &val);
4937ba94 492 val &= 0xf8;
b63b36fa
FR		 493 val |= 0x04;
494 ret = lgdt3306a_write_reg(state, 0x1061, val);
495
4937ba94
MCC		 496 ret = lgdt3306a_read_reg(state, 0x103d, &val);
497 val &= 0xcf;
498 ret = lgdt3306a_write_reg(state, 0x103d, val);
b63b36fa
FR		 499
500 ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
501
502 ret = lgdt3306a_read_reg(state, 0x2141, &val);
4937ba94 503 val &= 0x3f;
b63b36fa
FR		 504 ret = lgdt3306a_write_reg(state, 0x2141, val);
505
506 ret = lgdt3306a_read_reg(state, 0x2135, &val);
4937ba94 507 val &= 0x0f;
b63b36fa
FR		 508 val |= 0x70;
509 ret = lgdt3306a_write_reg(state, 0x2135, val);
510
511 ret = lgdt3306a_read_reg(state, 0x0003, &val);
4937ba94 512 val &= 0xf7;
b63b36fa
FR		 513 ret = lgdt3306a_write_reg(state, 0x0003, val);
514
4937ba94
MCC		 515 ret = lgdt3306a_read_reg(state, 0x001c, &val);
516 val &= 0x7f;
517 ret = lgdt3306a_write_reg(state, 0x001c, val);
b63b36fa 518
8e8cd34e 519 /* 6. EQ step size */
b63b36fa 520 ret = lgdt3306a_read_reg(state, 0x2179, &val);
4937ba94 521 val &= 0xf8;
b63b36fa
FR		 522 ret = lgdt3306a_write_reg(state, 0x2179, val);
523
4937ba94
MCC		 524 ret = lgdt3306a_read_reg(state, 0x217a, &val);
525 val &= 0xf8;
526 ret = lgdt3306a_write_reg(state, 0x217a, val);
b63b36fa 527
8e8cd34e 528 /* 7. Reset */
b63b36fa
FR		 529 ret = lgdt3306a_soft_reset(state);
530 if (lg_chkerr(ret))
531 goto fail;
532
097117ca 533 dbg_info("complete\n");
b63b36fa
FR		 534fail:
535 return ret;
536}
537
538static int lgdt3306a_set_qam(struct lgdt3306a_state *state, int modulation)
539{
540 u8 val;
541 int ret;
542
097117ca 543 dbg_info("modulation=%d\n", modulation);
b63b36fa 544
8e8cd34e 545 /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
b63b36fa
FR		 546 ret = lgdt3306a_write_reg(state, 0x0008, 0x08);
547 if (lg_chkerr(ret))
548 goto fail;
549
8e8cd34e 550 /* 1a. Spectrum inversion detection to Auto */
b63b36fa 551 ret = lgdt3306a_read_reg(state, 0x0002, &val);
4937ba94 552 val &= 0xfb; /* SPECINV Off */
8e8cd34e 553 val |= 0x08; /* SPECINVAUTO On */
b63b36fa
FR		 554 ret = lgdt3306a_write_reg(state, 0x0002, val);
555 if (lg_chkerr(ret))
556 goto fail;
557
8e8cd34e 558 /* 2. Bandwidth mode for QAM */
b63b36fa 559 ret = lgdt3306a_read_reg(state, 0x0009, &val);
4937ba94 560 val &= 0xe3; /* STDOPDETTMODE[2:0]=0 VSB Off */
b63b36fa
FR		 561 ret = lgdt3306a_write_reg(state, 0x0009, val);
562 if (lg_chkerr(ret))
563 goto fail;
564
8e8cd34e 565 /* 3. : 64QAM/256QAM detection(manual, auto) */
b63b36fa 566 ret = lgdt3306a_read_reg(state, 0x0009, &val);
4937ba94 567 val &= 0xfc;
8e8cd34e 568 val |= 0x02; /* STDOPDETCMODE[1:0]=1=Manual 2=Auto */
b63b36fa
FR		 569 ret = lgdt3306a_write_reg(state, 0x0009, val);
570 if (lg_chkerr(ret))
571 goto fail;
572
8e8cd34e 573 /* 3a. : 64QAM/256QAM selection for manual */
b63b36fa 574 ret = lgdt3306a_read_reg(state, 0x101a, &val);
4937ba94 575 val &= 0xf8;
8e8cd34e
MIK		 576 if (modulation == QAM_64)
577 val |= 0x02; /* QMDQMODE[2:0]=2=QAM64 */
578 else
579 val |= 0x04; /* QMDQMODE[2:0]=4=QAM256 */
580
b63b36fa
FR		 581 ret = lgdt3306a_write_reg(state, 0x101a, val);
582 if (lg_chkerr(ret))
583 goto fail;
584
8e8cd34e 585 /* 4. ADC sampling frequency rate(4x sampling) */
4937ba94
MCC		 586 ret = lgdt3306a_read_reg(state, 0x000d, &val);
587 val &= 0xbf;
8e8cd34e 588 val |= 0x40; /* SAMPLING4XFEN=1 */
4937ba94 589 ret = lgdt3306a_write_reg(state, 0x000d, val);
b63b36fa
FR		 590 if (lg_chkerr(ret))
591 goto fail;
592
8e8cd34e 593 /* 5. No AICC operation in QAM mode */
b63b36fa
FR		 594 ret = lgdt3306a_read_reg(state, 0x0024, &val);
595 val &= 0x00;
596 ret = lgdt3306a_write_reg(state, 0x0024, val);
597 if (lg_chkerr(ret))
598 goto fail;
599
8e8cd34e 600 /* 6. Reset */
b63b36fa
FR		 601 ret = lgdt3306a_soft_reset(state);
602 if (lg_chkerr(ret))
603 goto fail;
604
097117ca 605 dbg_info("complete\n");
b63b36fa
FR		 606fail:
607 return ret;
608}
609
610static int lgdt3306a_set_modulation(struct lgdt3306a_state *state,
611 struct dtv_frontend_properties *p)
612{
613 int ret;
614
097117ca 615 dbg_info("\n");
b63b36fa
FR		 616
617 switch (p->modulation) {
618 case VSB_8:
619 ret = lgdt3306a_set_vsb(state);
620 break;
621 case QAM_64:
622 ret = lgdt3306a_set_qam(state, QAM_64);
623 break;
624 case QAM_256:
625 ret = lgdt3306a_set_qam(state, QAM_256);
626 break;
627 default:
628 return -EINVAL;
629 }
630 if (lg_chkerr(ret))
631 goto fail;
632
633 state->current_modulation = p->modulation;
634
635fail:
636 return ret;
637}
638
639/* ------------------------------------------------------------------------ */
640
641static int lgdt3306a_agc_setup(struct lgdt3306a_state *state,
642 struct dtv_frontend_properties *p)
643{
8e8cd34e 644 /* TODO: anything we want to do here??? */
097117ca 645 dbg_info("\n");
b63b36fa
FR		 646
647 switch (p->modulation) {
648 case VSB_8:
649 break;
650 case QAM_64:
651 case QAM_256:
652 break;
653 default:
654 return -EINVAL;
655 }
656 return 0;
657}
658
659/* ------------------------------------------------------------------------ */
660
661static int lgdt3306a_set_inversion(struct lgdt3306a_state *state,
662 int inversion)
663{
664 int ret;
665
097117ca 666 dbg_info("(%d)\n", inversion);
b63b36fa 667
8e8cd34e 668 ret = lgdt3306a_set_reg_bit(state, 0x0002, 2, inversion ? 1 : 0);
b63b36fa
FR		 669 return ret;
670}
671
672static int lgdt3306a_set_inversion_auto(struct lgdt3306a_state *state,
673 int enabled)
674{
675 int ret;
676
097117ca 677 dbg_info("(%d)\n", enabled);
b63b36fa 678
534f4364
MCC		 679 /* 0=Manual 1=Auto(QAM only) - SPECINVAUTO=0x04 */
680 ret = lgdt3306a_set_reg_bit(state, 0x0002, 3, enabled);
b63b36fa
FR		 681 return ret;
682}
683
684static int lgdt3306a_spectral_inversion(struct lgdt3306a_state *state,
685 struct dtv_frontend_properties *p,
686 int inversion)
687{
688 int ret = 0;
689
097117ca 690 dbg_info("(%d)\n", inversion);
8e8cd34e 691#if 0
534f4364
MCC		 692 /*
693 * FGR - spectral_inversion defaults already set for VSB and QAM;
694 * can enable later if desired
695 */
b63b36fa
FR		 696
697 ret = lgdt3306a_set_inversion(state, inversion);
698
699 switch (p->modulation) {
700 case VSB_8:
534f4364
MCC		 701 /* Manual only for VSB */
702 ret = lgdt3306a_set_inversion_auto(state, 0);
b63b36fa
FR		 703 break;
704 case QAM_64:
705 case QAM_256:
534f4364
MCC		 706 /* Auto ok for QAM */
707 ret = lgdt3306a_set_inversion_auto(state, 1);
b63b36fa
FR		 708 break;
709 default:
710 ret = -EINVAL;
711 }
712#endif
713 return ret;
714}
715
716static int lgdt3306a_set_if(struct lgdt3306a_state *state,
717 struct dtv_frontend_properties *p)
718{
719 int ret;
720 u16 if_freq_khz;
721 u8 nco1, nco2;
722
723 switch (p->modulation) {
724 case VSB_8:
725 if_freq_khz = state->cfg->vsb_if_khz;
726 break;
727 case QAM_64:
728 case QAM_256:
729 if_freq_khz = state->cfg->qam_if_khz;
730 break;
731 default:
732 return -EINVAL;
733 }
734
8e8cd34e 735 switch (if_freq_khz) {
b63b36fa 736 default:
f86548cf 737 pr_warn("IF=%d KHz is not supported, 3250 assumed\n",
534f4364 738 if_freq_khz);
8e8cd34e 739 /* fallthrough */
34a5a2f8 740 case 3250: /* 3.25Mhz */
b63b36fa
FR		 741 nco1 = 0x34;
742 nco2 = 0x00;
743 break;
34a5a2f8 744 case 3500: /* 3.50Mhz */
b63b36fa
FR		 745 nco1 = 0x38;
746 nco2 = 0x00;
747 break;
34a5a2f8 748 case 4000: /* 4.00Mhz */
b63b36fa
FR		 749 nco1 = 0x40;
750 nco2 = 0x00;
751 break;
34a5a2f8 752 case 5000: /* 5.00Mhz */
b63b36fa
FR		 753 nco1 = 0x50;
754 nco2 = 0x00;
755 break;
8e8cd34e 756 case 5380: /* 5.38Mhz */
b63b36fa
FR		 757 nco1 = 0x56;
758 nco2 = 0x14;
759 break;
760 }
761 ret = lgdt3306a_write_reg(state, 0x0010, nco1);
ee0133ee
MCC		 762 if (ret)
763 return ret;
b63b36fa 764 ret = lgdt3306a_write_reg(state, 0x0011, nco2);
ee0133ee
MCC		 765 if (ret)
766 return ret;
b63b36fa 767
097117ca 768 dbg_info("if_freq=%d KHz->[%04x]\n", if_freq_khz, nco1<<8 | nco2);
b63b36fa
FR		 769
770 return 0;
771}
772
773/* ------------------------------------------------------------------------ */
774
775static int lgdt3306a_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
776{
777 struct lgdt3306a_state *state = fe->demodulator_priv;
778
8e8cd34e 779 if (state->cfg->deny_i2c_rptr) {
097117ca 780 dbg_info("deny_i2c_rptr=%d\n", state->cfg->deny_i2c_rptr);
b63b36fa
FR		 781 return 0;
782 }
097117ca 783 dbg_info("(%d)\n", enable);
b63b36fa 784
534f4364
MCC		 785 /* NI2CRPTEN=0x80 */
786 return lgdt3306a_set_reg_bit(state, 0x0002, 7, enable ? 0 : 1);
b63b36fa
FR		 787}
788
789static int lgdt3306a_sleep(struct lgdt3306a_state *state)
790{
791 int ret;
792
097117ca 793 dbg_info("\n");
8e8cd34e 794 state->current_frequency = -1; /* force re-tune, when we wake */
b63b36fa 795
8e8cd34e 796 ret = lgdt3306a_mpeg_tristate(state, 1); /* disable data bus */
b63b36fa
FR		 797 if (lg_chkerr(ret))
798 goto fail;
799
8e8cd34e 800 ret = lgdt3306a_power(state, 0); /* power down */
b63b36fa
FR		 801 lg_chkerr(ret);
802
803fail:
804 return 0;
805}
806
807static int lgdt3306a_fe_sleep(struct dvb_frontend *fe)
808{
809 struct lgdt3306a_state *state = fe->demodulator_priv;
810
811 return lgdt3306a_sleep(state);
812}
813
814static int lgdt3306a_init(struct dvb_frontend *fe)
815{
816 struct lgdt3306a_state *state = fe->demodulator_priv;
817 u8 val;
818 int ret;
819
097117ca 820 dbg_info("\n");
b63b36fa 821
8e8cd34e
MIK		 822 /* 1. Normal operation mode */
823 ret = lgdt3306a_set_reg_bit(state, 0x0001, 0, 1); /* SIMFASTENB=0x01 */
b63b36fa
FR		 824 if (lg_chkerr(ret))
825 goto fail;
826
8e8cd34e 827 /* 2. Spectrum inversion auto detection (Not valid for VSB) */
b63b36fa
FR		 828 ret = lgdt3306a_set_inversion_auto(state, 0);
829 if (lg_chkerr(ret))
830 goto fail;
831
8e8cd34e 832 /* 3. Spectrum inversion(According to the tuner configuration) */
b63b36fa
FR		 833 ret = lgdt3306a_set_inversion(state, 1);
834 if (lg_chkerr(ret))
835 goto fail;
836
8e8cd34e 837 /* 4. Peak-to-peak voltage of ADC input signal */
534f4364
MCC		 838
839 /* ADCSEL1V=0x80=1Vpp; 0x00=2Vpp */
840 ret = lgdt3306a_set_reg_bit(state, 0x0004, 7, 1);
b63b36fa
FR		 841 if (lg_chkerr(ret))
842 goto fail;
843
8e8cd34e 844 /* 5. ADC output data capture clock phase */
534f4364
MCC		 845
846 /* 0=same phase as ADC clock */
847 ret = lgdt3306a_set_reg_bit(state, 0x0004, 2, 0);
b63b36fa
FR		 848 if (lg_chkerr(ret))
849 goto fail;
850
8e8cd34e 851 /* 5a. ADC sampling clock source */
534f4364
MCC		 852
853 /* ADCCLKPLLSEL=0x08; 0=use ext clock, not PLL */
854 ret = lgdt3306a_set_reg_bit(state, 0x0004, 3, 0);
b63b36fa
FR		 855 if (lg_chkerr(ret))
856 goto fail;
857
8e8cd34e 858 /* 6. Automatic PLL set */
534f4364
MCC		 859
860 /* PLLSETAUTO=0x40; 0=off */
861 ret = lgdt3306a_set_reg_bit(state, 0x0005, 6, 0);
b63b36fa
FR		 862 if (lg_chkerr(ret))
863 goto fail;
864
8e8cd34e
MIK		 865 if (state->cfg->xtalMHz == 24) { /* 24MHz */
866 /* 7. Frequency for PLL output(0x2564 for 192MHz for 24MHz) */
b63b36fa
FR		 867 ret = lgdt3306a_read_reg(state, 0x0005, &val);
868 if (lg_chkerr(ret))
869 goto fail;
4937ba94 870 val &= 0xc0;
b63b36fa
FR		 871 val |= 0x25;
872 ret = lgdt3306a_write_reg(state, 0x0005, val);
873 if (lg_chkerr(ret))
874 goto fail;
875 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
876 if (lg_chkerr(ret))
877 goto fail;
878
8e8cd34e 879 /* 8. ADC sampling frequency(0x180000 for 24MHz sampling) */
4937ba94 880 ret = lgdt3306a_read_reg(state, 0x000d, &val);
b63b36fa
FR		 881 if (lg_chkerr(ret))
882 goto fail;
4937ba94 883 val &= 0xc0;
b63b36fa 884 val |= 0x18;
4937ba94 885 ret = lgdt3306a_write_reg(state, 0x000d, val);
b63b36fa
FR		 886 if (lg_chkerr(ret))
887 goto fail;
888
8e8cd34e
MIK		 889 } else if (state->cfg->xtalMHz == 25) { /* 25MHz */
890 /* 7. Frequency for PLL output */
b63b36fa
FR		 891 ret = lgdt3306a_read_reg(state, 0x0005, &val);
892 if (lg_chkerr(ret))
893 goto fail;
4937ba94 894 val &= 0xc0;
b63b36fa
FR		 895 val |= 0x25;
896 ret = lgdt3306a_write_reg(state, 0x0005, val);
897 if (lg_chkerr(ret))
898 goto fail;
899 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
900 if (lg_chkerr(ret))
901 goto fail;
902
8e8cd34e 903 /* 8. ADC sampling frequency(0x190000 for 25MHz sampling) */
4937ba94 904 ret = lgdt3306a_read_reg(state, 0x000d, &val);
b63b36fa
FR		 905 if (lg_chkerr(ret))
906 goto fail;
4937ba94 907 val &= 0xc0;
b63b36fa 908 val |= 0x19;
4937ba94 909 ret = lgdt3306a_write_reg(state, 0x000d, val);
b63b36fa
FR		 910 if (lg_chkerr(ret))
911 goto fail;
912 } else {
097117ca 913 pr_err("Bad xtalMHz=%d\n", state->cfg->xtalMHz);
b63b36fa 914 }
8e8cd34e 915#if 0
4937ba94
MCC		 916 ret = lgdt3306a_write_reg(state, 0x000e, 0x00);
917 ret = lgdt3306a_write_reg(state, 0x000f, 0x00);
8e8cd34e 918#endif
b63b36fa 919
8e8cd34e
MIK		 920 /* 9. Center frequency of input signal of ADC */
921 ret = lgdt3306a_write_reg(state, 0x0010, 0x34); /* 3.25MHz */
922 ret = lgdt3306a_write_reg(state, 0x0011, 0x00);
b63b36fa 923
8e8cd34e
MIK		 924 /* 10. Fixed gain error value */
925 ret = lgdt3306a_write_reg(state, 0x0014, 0); /* gain error=0 */
b63b36fa 926
8e8cd34e 927 /* 10a. VSB TR BW gear shift initial step */
4937ba94
MCC		 928 ret = lgdt3306a_read_reg(state, 0x103c, &val);
929 val &= 0x0f;
8e8cd34e 930 val |= 0x20; /* SAMGSAUTOSTL_V[3:0] = 2 */
4937ba94 931 ret = lgdt3306a_write_reg(state, 0x103c, val);
b63b36fa 932
8e8cd34e 933 /* 10b. Timing offset calibration in low temperature for VSB */
4937ba94
MCC		 934 ret = lgdt3306a_read_reg(state, 0x103d, &val);
935 val &= 0xfc;
b63b36fa 936 val |= 0x03;
4937ba94 937 ret = lgdt3306a_write_reg(state, 0x103d, val);
b63b36fa 938
8e8cd34e 939 /* 10c. Timing offset calibration in low temperature for QAM */
b63b36fa 940 ret = lgdt3306a_read_reg(state, 0x1036, &val);
4937ba94
MCC		 941 val &= 0xf0;
942 val |= 0x0c;
b63b36fa
FR		 943 ret = lgdt3306a_write_reg(state, 0x1036, val);
944
8e8cd34e 945 /* 11. Using the imaginary part of CIR in CIR loading */
4937ba94
MCC		 946 ret = lgdt3306a_read_reg(state, 0x211f, &val);
947 val &= 0xef; /* do not use imaginary of CIR */
948 ret = lgdt3306a_write_reg(state, 0x211f, val);
b63b36fa 949
8e8cd34e 950 /* 12. Control of no signal detector function */
b63b36fa 951 ret = lgdt3306a_read_reg(state, 0x2849, &val);
4937ba94 952 val &= 0xef; /* NOUSENOSIGDET=0, enable no signal detector */
b63b36fa
FR		 953 ret = lgdt3306a_write_reg(state, 0x2849, val);
954
8e8cd34e 955 /* FGR - put demod in some known mode */
b63b36fa
FR		 956 ret = lgdt3306a_set_vsb(state);
957
8e8cd34e 958 /* 13. TP stream format */
b63b36fa
FR		 959 ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
960
8e8cd34e 961 /* 14. disable output buses */
b63b36fa
FR		 962 ret = lgdt3306a_mpeg_tristate(state, 1);
963
8e8cd34e 964 /* 15. Sleep (in reset) */
b63b36fa
FR		 965 ret = lgdt3306a_sleep(state);
966 lg_chkerr(ret);
967
968fail:
969 return ret;
970}
971
972static int lgdt3306a_set_parameters(struct dvb_frontend *fe)
973{
974 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
975 struct lgdt3306a_state *state = fe->demodulator_priv;
976 int ret;
977
097117ca 978 dbg_info("(%d, %d)\n", p->frequency, p->modulation);
b63b36fa 979
8e8cd34e
MIK		 980 if (state->current_frequency == p->frequency &&
981 state->current_modulation == p->modulation) {
097117ca 982 dbg_info(" (already set, skipping ...)\n");
b63b36fa
FR		 983 return 0;
984 }
985 state->current_frequency = -1;
986 state->current_modulation = -1;
987
8e8cd34e 988 ret = lgdt3306a_power(state, 1); /* power up */
b63b36fa
FR		 989 if (lg_chkerr(ret))
990 goto fail;
991
992 if (fe->ops.tuner_ops.set_params) {
993 ret = fe->ops.tuner_ops.set_params(fe);
994 if (fe->ops.i2c_gate_ctrl)
995 fe->ops.i2c_gate_ctrl(fe, 0);
8e8cd34e
MIK		 996#if 0
997 if (lg_chkerr(ret))
998 goto fail;
999 state->current_frequency = p->frequency;
1000#endif
b63b36fa
FR		 1001 }
1002
1003 ret = lgdt3306a_set_modulation(state, p);
1004 if (lg_chkerr(ret))
1005 goto fail;
1006
1007 ret = lgdt3306a_agc_setup(state, p);
1008 if (lg_chkerr(ret))
1009 goto fail;
1010
1011 ret = lgdt3306a_set_if(state, p);
1012 if (lg_chkerr(ret))
1013 goto fail;
1014
1015 ret = lgdt3306a_spectral_inversion(state, p,
534f4364 1016 state->cfg->spectral_inversion ? 1 : 0);
b63b36fa
FR		 1017 if (lg_chkerr(ret))
1018 goto fail;
1019
1020 ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
1021 if (lg_chkerr(ret))
1022 goto fail;
1023
1024 ret = lgdt3306a_mpeg_mode_polarity(state,
1025 state->cfg->tpclk_edge,
1026 state->cfg->tpvalid_polarity);
1027 if (lg_chkerr(ret))
1028 goto fail;
1029
8e8cd34e 1030 ret = lgdt3306a_mpeg_tristate(state, 0); /* enable data bus */
b63b36fa
FR		 1031 if (lg_chkerr(ret))
1032 goto fail;
1033
1034 ret = lgdt3306a_soft_reset(state);
1035 if (lg_chkerr(ret))
1036 goto fail;
1037
1038#ifdef DBG_DUMP
1039 lgdt3306a_DumpAllRegs(state);
1040#endif
1041 state->current_frequency = p->frequency;
1042fail:
1043 return ret;
1044}
1045
7e3e68bc
MCC		 1046static int lgdt3306a_get_frontend(struct dvb_frontend *fe,
1047 struct dtv_frontend_properties *p)
b63b36fa
FR		 1048{
1049 struct lgdt3306a_state *state = fe->demodulator_priv;
b63b36fa 1050
534f4364
MCC		 1051 dbg_info("(%u, %d)\n",
1052 state->current_frequency, state->current_modulation);
b63b36fa
FR		 1053
1054 p->modulation = state->current_modulation;
1055 p->frequency = state->current_frequency;
1056 return 0;
1057}
1058
1059static enum dvbfe_algo lgdt3306a_get_frontend_algo(struct dvb_frontend *fe)
1060{
1061#if 1
1062 return DVBFE_ALGO_CUSTOM;
1063#else
1064 return DVBFE_ALGO_HW;
1065#endif
1066}
1067
1068/* ------------------------------------------------------------------------ */
ee0133ee 1069static int lgdt3306a_monitor_vsb(struct lgdt3306a_state *state)
b63b36fa
FR		 1070{
1071 u8 val;
1072 int ret;
8e8cd34e
MIK		 1073 u8 snrRef, maxPowerMan, nCombDet;
1074 u16 fbDlyCir;
b63b36fa 1075
4937ba94 1076 ret = lgdt3306a_read_reg(state, 0x21a1, &val);
ee0133ee
MCC		 1077 if (ret)
1078 return ret;
4937ba94 1079 snrRef = val & 0x3f;
b63b36fa
FR		 1080
1081 ret = lgdt3306a_read_reg(state, 0x2185, &maxPowerMan);
ee0133ee
MCC		 1082 if (ret)
1083 return ret;
b63b36fa
FR		 1084
1085 ret = lgdt3306a_read_reg(state, 0x2191, &val);
ee0133ee
MCC		 1086 if (ret)
1087 return ret;
b63b36fa
FR		 1088 nCombDet = (val & 0x80) >> 7;
1089
1090 ret = lgdt3306a_read_reg(state, 0x2180, &val);
ee0133ee
MCC		 1091 if (ret)
1092 return ret;
b63b36fa 1093 fbDlyCir = (val & 0x03) << 8;
ee0133ee 1094
b63b36fa 1095 ret = lgdt3306a_read_reg(state, 0x2181, &val);
ee0133ee
MCC		 1096 if (ret)
1097 return ret;
b63b36fa
FR		 1098 fbDlyCir |= val;
1099
097117ca 1100 dbg_info("snrRef=%d maxPowerMan=0x%x nCombDet=%d fbDlyCir=0x%x\n",
b63b36fa
FR		 1101 snrRef, maxPowerMan, nCombDet, fbDlyCir);
1102
8e8cd34e 1103 /* Carrier offset sub loop bandwidth */
b63b36fa 1104 ret = lgdt3306a_read_reg(state, 0x1061, &val);
ee0133ee
MCC		 1105 if (ret)
1106 return ret;
4937ba94 1107 val &= 0xf8;
534f4364
MCC		 1108 if ((snrRef > 18) && (maxPowerMan > 0x68)
1109 && (nCombDet == 0x01)
1110 && ((fbDlyCir == 0x03FF) || (fbDlyCir < 0x6C))) {
8e8cd34e
MIK		 1111 /* SNR is over 18dB and no ghosting */
1112 val |= 0x00; /* final bandwidth = 0 */
b63b36fa 1113 } else {
8e8cd34e 1114 val |= 0x04; /* final bandwidth = 4 */
b63b36fa
FR		 1115 }
1116 ret = lgdt3306a_write_reg(state, 0x1061, val);
ee0133ee
MCC		 1117 if (ret)
1118 return ret;
b63b36fa 1119
8e8cd34e 1120 /* Adjust Notch Filter */
b63b36fa 1121 ret = lgdt3306a_read_reg(state, 0x0024, &val);
ee0133ee
MCC		 1122 if (ret)
1123 return ret;
4937ba94 1124 val &= 0x0f;
8e8cd34e 1125 if (nCombDet == 0) { /* Turn on the Notch Filter */
b63b36fa
FR		 1126 val |= 0x50;
1127 }
1128 ret = lgdt3306a_write_reg(state, 0x0024, val);
ee0133ee
MCC		 1129 if (ret)
1130 return ret;
b63b36fa 1131
8e8cd34e 1132 /* VSB Timing Recovery output normalization */
4937ba94 1133 ret = lgdt3306a_read_reg(state, 0x103d, &val);
ee0133ee
MCC		 1134 if (ret)
1135 return ret;
4937ba94 1136 val &= 0xcf;
b63b36fa 1137 val |= 0x20;
4937ba94 1138 ret = lgdt3306a_write_reg(state, 0x103d, val);
ee0133ee
MCC		 1139
1140 return ret;
b63b36fa
FR		 1141}
1142
534f4364
MCC		 1143static enum lgdt3306a_modulation
1144lgdt3306a_check_oper_mode(struct lgdt3306a_state *state)
b63b36fa
FR		 1145{
1146 u8 val = 0;
1147 int ret;
1148
1149 ret = lgdt3306a_read_reg(state, 0x0081, &val);
ee0133ee
MCC		 1150 if (ret)
1151 goto err;
b63b36fa
FR		 1152
1153 if (val & 0x80) {
097117ca 1154 dbg_info("VSB\n");
8e8cd34e 1155 return LG3306_VSB;
b63b36fa 1156 }
c714efe4 1157 if (val & 0x08) {
4937ba94 1158 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
ee0133ee
MCC		 1159 if (ret)
1160 goto err;
b63b36fa
FR		 1161 val = val >> 2;
1162 if (val & 0x01) {
097117ca 1163 dbg_info("QAM256\n");
8e8cd34e 1164 return LG3306_QAM256;
b63b36fa 1165 }
b4e43e95
MCC		 1166 dbg_info("QAM64\n");
1167 return LG3306_QAM64;
b63b36fa 1168 }
ee0133ee 1169err:
097117ca 1170 pr_warn("UNKNOWN\n");
8e8cd34e 1171 return LG3306_UNKNOWN_MODE;
b63b36fa
FR		 1172}
1173
534f4364
MCC		 1174static enum lgdt3306a_lock_status
1175lgdt3306a_check_lock_status(struct lgdt3306a_state *state,
1176 enum lgdt3306a_lock_check whatLock)
b63b36fa
FR		 1177{
1178 u8 val = 0;
1179 int ret;
f883d603
MIK		 1180 enum lgdt3306a_modulation modeOper;
1181 enum lgdt3306a_lock_status lockStatus;
b63b36fa
FR		 1182
1183 modeOper = LG3306_UNKNOWN_MODE;
1184
8e8cd34e
MIK		 1185 switch (whatLock) {
1186 case LG3306_SYNC_LOCK:
1187 {
4937ba94 1188 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
ee0133ee
MCC		 1189 if (ret)
1190 return ret;
8e8cd34e
MIK		 1191
1192 if ((val & 0x80) == 0x80)
1193 lockStatus = LG3306_LOCK;
1194 else
1195 lockStatus = LG3306_UNLOCK;
1196
097117ca 1197 dbg_info("SYNC_LOCK=%x\n", lockStatus);
8e8cd34e
MIK		 1198 break;
1199 }
1200 case LG3306_AGC_LOCK:
1201 {
1202 ret = lgdt3306a_read_reg(state, 0x0080, &val);
ee0133ee
MCC		 1203 if (ret)
1204 return ret;
8e8cd34e
MIK		 1205
1206 if ((val & 0x40) == 0x40)
1207 lockStatus = LG3306_LOCK;
1208 else
1209 lockStatus = LG3306_UNLOCK;
1210
097117ca 1211 dbg_info("AGC_LOCK=%x\n", lockStatus);
8e8cd34e
MIK		 1212 break;
1213 }
1214 case LG3306_TR_LOCK:
b63b36fa 1215 {
8e8cd34e
MIK		 1216 modeOper = lgdt3306a_check_oper_mode(state);
1217 if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
1218 ret = lgdt3306a_read_reg(state, 0x1094, &val);
ee0133ee
MCC		 1219 if (ret)
1220 return ret;
b63b36fa
FR		 1221
1222 if ((val & 0x80) == 0x80)
1223 lockStatus = LG3306_LOCK;
1224 else
1225 lockStatus = LG3306_UNLOCK;
8e8cd34e
MIK		 1226 } else
1227 lockStatus = LG3306_UNKNOWN_LOCK;
b63b36fa 1228
097117ca 1229 dbg_info("TR_LOCK=%x\n", lockStatus);
8e8cd34e
MIK		 1230 break;
1231 }
1232 case LG3306_FEC_LOCK:
1233 {
1234 modeOper = lgdt3306a_check_oper_mode(state);
1235 if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
b63b36fa 1236 ret = lgdt3306a_read_reg(state, 0x0080, &val);
ee0133ee
MCC		 1237 if (ret)
1238 return ret;
b63b36fa 1239
8e8cd34e 1240 if ((val & 0x10) == 0x10)
b63b36fa
FR		 1241 lockStatus = LG3306_LOCK;
1242 else
1243 lockStatus = LG3306_UNLOCK;
8e8cd34e
MIK		 1244 } else
1245 lockStatus = LG3306_UNKNOWN_LOCK;
b63b36fa 1246
097117ca 1247 dbg_info("FEC_LOCK=%x\n", lockStatus);
8e8cd34e
MIK		 1248 break;
1249 }
b63b36fa 1250
8e8cd34e
MIK		 1251 default:
1252 lockStatus = LG3306_UNKNOWN_LOCK;
097117ca 1253 pr_warn("UNKNOWN whatLock=%d\n", whatLock);
8e8cd34e 1254 break;
b63b36fa
FR		 1255 }
1256
8e8cd34e 1257 return lockStatus;
b63b36fa
FR		 1258}
1259
534f4364
MCC		 1260static enum lgdt3306a_neverlock_status
1261lgdt3306a_check_neverlock_status(struct lgdt3306a_state *state)
b63b36fa
FR		 1262{
1263 u8 val = 0;
1264 int ret;
f883d603 1265 enum lgdt3306a_neverlock_status lockStatus;
b63b36fa
FR		 1266
1267 ret = lgdt3306a_read_reg(state, 0x0080, &val);
ee0133ee
MCC		 1268 if (ret)
1269 return ret;
f883d603 1270 lockStatus = (enum lgdt3306a_neverlock_status)(val & 0x03);
b63b36fa 1271
097117ca 1272 dbg_info("NeverLock=%d", lockStatus);
b63b36fa 1273
8e8cd34e 1274 return lockStatus;
b63b36fa
FR		 1275}
1276
ee0133ee 1277static int lgdt3306a_pre_monitoring(struct lgdt3306a_state *state)
b63b36fa
FR		 1278{
1279 u8 val = 0;
1280 int ret;
1281 u8 currChDiffACQ, snrRef, mainStrong, aiccrejStatus;
1282
8e8cd34e 1283 /* Channel variation */
4937ba94 1284 ret = lgdt3306a_read_reg(state, 0x21bc, &currChDiffACQ);
ee0133ee
MCC		 1285 if (ret)
1286 return ret;
b63b36fa 1287
8e8cd34e 1288 /* SNR of Frame sync */
4937ba94 1289 ret = lgdt3306a_read_reg(state, 0x21a1, &val);
ee0133ee
MCC		 1290 if (ret)
1291 return ret;
4937ba94 1292 snrRef = val & 0x3f;
b63b36fa 1293
8e8cd34e 1294 /* Strong Main CIR */
b63b36fa 1295 ret = lgdt3306a_read_reg(state, 0x2199, &val);
ee0133ee
MCC		 1296 if (ret)
1297 return ret;
b63b36fa
FR		 1298 mainStrong = (val & 0x40) >> 6;
1299
1300 ret = lgdt3306a_read_reg(state, 0x0090, &val);
ee0133ee
MCC		 1301 if (ret)
1302 return ret;
4937ba94 1303 aiccrejStatus = (val & 0xf0) >> 4;
b63b36fa 1304
097117ca 1305 dbg_info("snrRef=%d mainStrong=%d aiccrejStatus=%d currChDiffACQ=0x%x\n",
b63b36fa
FR		 1306 snrRef, mainStrong, aiccrejStatus, currChDiffACQ);
1307
8e8cd34e 1308#if 0
534f4364
MCC		 1309 /* Dynamic ghost exists */
1310 if ((mainStrong == 0) && (currChDiffACQ > 0x70))
8e8cd34e
MIK		 1311#endif
1312 if (mainStrong == 0) {
b63b36fa 1313 ret = lgdt3306a_read_reg(state, 0x2135, &val);
ee0133ee
MCC		 1314 if (ret)
1315 return ret;
4937ba94
MCC		 1316 val &= 0x0f;
1317 val |= 0xa0;
b63b36fa 1318 ret = lgdt3306a_write_reg(state, 0x2135, val);
ee0133ee
MCC		 1319 if (ret)
1320 return ret;
b63b36fa
FR		 1321
1322 ret = lgdt3306a_read_reg(state, 0x2141, &val);
ee0133ee
MCC		 1323 if (ret)
1324 return ret;
4937ba94 1325 val &= 0x3f;
b63b36fa
FR		 1326 val |= 0x80;
1327 ret = lgdt3306a_write_reg(state, 0x2141, val);
ee0133ee
MCC		 1328 if (ret)
1329 return ret;
b63b36fa
FR		 1330
1331 ret = lgdt3306a_write_reg(state, 0x2122, 0x70);
ee0133ee
MCC		 1332 if (ret)
1333 return ret;
8e8cd34e 1334 } else { /* Weak ghost or static channel */
b63b36fa 1335 ret = lgdt3306a_read_reg(state, 0x2135, &val);
ee0133ee
MCC		 1336 if (ret)
1337 return ret;
4937ba94 1338 val &= 0x0f;
b63b36fa
FR		 1339 val |= 0x70;
1340 ret = lgdt3306a_write_reg(state, 0x2135, val);
ee0133ee
MCC		 1341 if (ret)
1342 return ret;
b63b36fa
FR		 1343
1344 ret = lgdt3306a_read_reg(state, 0x2141, &val);
ee0133ee
MCC		 1345 if (ret)
1346 return ret;
4937ba94 1347 val &= 0x3f;
b63b36fa
FR		 1348 val |= 0x40;
1349 ret = lgdt3306a_write_reg(state, 0x2141, val);
ee0133ee
MCC		 1350 if (ret)
1351 return ret;
b63b36fa
FR		 1352
1353 ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
ee0133ee
MCC		 1354 if (ret)
1355 return ret;
b63b36fa 1356 }
ee0133ee 1357 return 0;
b63b36fa
FR		 1358}
1359
534f4364
MCC		 1360static enum lgdt3306a_lock_status
1361lgdt3306a_sync_lock_poll(struct lgdt3306a_state *state)
b63b36fa 1362{
f883d603 1363 enum lgdt3306a_lock_status syncLockStatus = LG3306_UNLOCK;
b63b36fa
FR		 1364 int i;
1365
1366 for (i = 0; i < 2; i++) {
1367 msleep(30);
1368
534f4364
MCC		 1369 syncLockStatus = lgdt3306a_check_lock_status(state,
1370 LG3306_SYNC_LOCK);
b63b36fa
FR		 1371
1372 if (syncLockStatus == LG3306_LOCK) {
097117ca 1373 dbg_info("locked(%d)\n", i);
8e8cd34e 1374 return LG3306_LOCK;
b63b36fa
FR		 1375 }
1376 }
097117ca 1377 dbg_info("not locked\n");
8e8cd34e 1378 return LG3306_UNLOCK;
b63b36fa
FR		 1379}
1380
534f4364
MCC		 1381static enum lgdt3306a_lock_status
1382lgdt3306a_fec_lock_poll(struct lgdt3306a_state *state)
b63b36fa 1383{
f883d603 1384 enum lgdt3306a_lock_status FECLockStatus = LG3306_UNLOCK;
b63b36fa
FR		 1385 int i;
1386
1387 for (i = 0; i < 2; i++) {
1388 msleep(30);
1389
534f4364
MCC		 1390 FECLockStatus = lgdt3306a_check_lock_status(state,
1391 LG3306_FEC_LOCK);
b63b36fa
FR		 1392
1393 if (FECLockStatus == LG3306_LOCK) {
097117ca 1394 dbg_info("locked(%d)\n", i);
8e8cd34e 1395 return FECLockStatus;
b63b36fa
FR		 1396 }
1397 }
097117ca 1398 dbg_info("not locked\n");
8e8cd34e 1399 return FECLockStatus;
b63b36fa
FR		 1400}
1401
534f4364
MCC		 1402static enum lgdt3306a_neverlock_status
1403lgdt3306a_neverlock_poll(struct lgdt3306a_state *state)
b63b36fa 1404{
f883d603 1405 enum lgdt3306a_neverlock_status NLLockStatus = LG3306_NL_FAIL;
b63b36fa
FR		 1406 int i;
1407
8e8cd34e 1408 for (i = 0; i < 5; i++) {
b63b36fa
FR		 1409 msleep(30);
1410
1411 NLLockStatus = lgdt3306a_check_neverlock_status(state);
1412
1413 if (NLLockStatus == LG3306_NL_LOCK) {
097117ca 1414 dbg_info("NL_LOCK(%d)\n", i);
8e8cd34e 1415 return NLLockStatus;
b63b36fa
FR		 1416 }
1417 }
097117ca 1418 dbg_info("NLLockStatus=%d\n", NLLockStatus);
8e8cd34e 1419 return NLLockStatus;
b63b36fa
FR		 1420}
1421
1422static u8 lgdt3306a_get_packet_error(struct lgdt3306a_state *state)
1423{
1424 u8 val;
1425 int ret;
1426
4937ba94 1427 ret = lgdt3306a_read_reg(state, 0x00fa, &val);
ee0133ee
MCC		 1428 if (ret)
1429 return ret;
b63b36fa 1430
8e8cd34e 1431 return val;
b63b36fa
FR		 1432}
1433
9369fe01
MCC		 1434static const u32 valx_x10[] = {
1435 10, 11, 13, 15, 17, 20, 25, 33, 41, 50, 59, 73, 87, 100
1436};
1437static const u32 log10x_x1000[] = {
95f22c5a 1438 0, 41, 114, 176, 230, 301, 398, 518, 613, 699, 771, 863, 939, 1000
9369fe01
MCC		 1439};
1440
b63b36fa
FR		 1441static u32 log10_x1000(u32 x)
1442{
a132fef8 1443 u32 diff_val, step_val, step_log10;
b63b36fa 1444 u32 log_val = 0;
8e8cd34e 1445 u32 i;
b63b36fa 1446
8e8cd34e
MIK		 1447 if (x <= 0)
1448 return -1000000; /* signal error */
b63b36fa 1449
b4e43e95
MCC		 1450 if (x == 10)
1451 return 0; /* log(1)=0 */
1452
8e8cd34e
MIK		 1453 if (x < 10) {
1454 while (x < 10) {
1455 x = x * 10;
b63b36fa
FR		 1456 log_val--;
1457 }
b4e43e95 1458 } else { /* x > 10 */
8e8cd34e
MIK		 1459 while (x >= 100) {
1460 x = x / 10;
b63b36fa
FR		 1461 log_val++;
1462 }
8e8cd34e 1463 }
b63b36fa
FR		 1464 log_val *= 1000;
1465
8e8cd34e
MIK		 1466 if (x == 10) /* was our input an exact multiple of 10 */
1467 return log_val; /* don't need to interpolate */
b63b36fa 1468
8e8cd34e 1469 /* find our place on the log curve */
9369fe01 1470 for (i = 1; i < ARRAY_SIZE(valx_x10); i++) {
8e8cd34e
MIK		 1471 if (valx_x10[i] >= x)
1472 break;
b63b36fa 1473 }
9369fe01 1474 if (i == ARRAY_SIZE(valx_x10))
a132fef8 1475 return log_val + log10x_x1000[i - 1];
b63b36fa 1476
a132fef8
MCC		 1477 diff_val = x - valx_x10[i-1];
1478 step_val = valx_x10[i] - valx_x10[i - 1];
1479 step_log10 = log10x_x1000[i] - log10x_x1000[i - 1];
1480
1481 /* do a linear interpolation to get in-between values */
1482 return log_val + log10x_x1000[i - 1] +
1483 ((diff_val*step_log10) / step_val);
b63b36fa
FR		 1484}
1485
1486static u32 lgdt3306a_calculate_snr_x100(struct lgdt3306a_state *state)
1487{
34a5a2f8
MIK		 1488 u32 mse; /* Mean-Square Error */
1489 u32 pwr; /* Constelation power */
b63b36fa
FR		 1490 u32 snr_x100;
1491
4937ba94
MCC		 1492 mse = (read_reg(state, 0x00ec) << 8) |
1493 (read_reg(state, 0x00ed));
1494 pwr = (read_reg(state, 0x00e8) << 8) |
1495 (read_reg(state, 0x00e9));
b63b36fa
FR		 1496
1497 if (mse == 0) /* no signal */
1498 return 0;
1499
8e8cd34e 1500 snr_x100 = log10_x1000((pwr * 10000) / mse) - 3000;
097117ca 1501 dbg_info("mse=%u, pwr=%u, snr_x100=%d\n", mse, pwr, snr_x100);
b63b36fa
FR		 1502
1503 return snr_x100;
1504}
1505
534f4364
MCC		 1506static enum lgdt3306a_lock_status
1507lgdt3306a_vsb_lock_poll(struct lgdt3306a_state *state)
b63b36fa 1508{
e2c47fa7 1509 int ret;
8e8cd34e
MIK		 1510 u8 cnt = 0;
1511 u8 packet_error;
1512 u32 snr;
b63b36fa 1513
b1a88c71 1514 for (cnt = 0; cnt < 10; cnt++) {
b63b36fa 1515 if (lgdt3306a_sync_lock_poll(state) == LG3306_UNLOCK) {
097117ca 1516 dbg_info("no sync lock!\n");
8e8cd34e 1517 return LG3306_UNLOCK;
b1a88c71 1518 }
b63b36fa 1519
b1a88c71
MCC		 1520 msleep(20);
1521 ret = lgdt3306a_pre_monitoring(state);
1522 if (ret)
1523 break;
b63b36fa 1524
b1a88c71
MCC		 1525 packet_error = lgdt3306a_get_packet_error(state);
1526 snr = lgdt3306a_calculate_snr_x100(state);
1527 dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr);
b63b36fa 1528
b1a88c71
MCC		 1529 if ((snr >= 1500) && (packet_error < 0xff))
1530 return LG3306_LOCK;
b63b36fa 1531 }
b1a88c71
MCC		 1532
1533 dbg_info("not locked!\n");
8e8cd34e 1534 return LG3306_UNLOCK;
b63b36fa
FR		 1535}
1536
534f4364
MCC		 1537static enum lgdt3306a_lock_status
1538lgdt3306a_qam_lock_poll(struct lgdt3306a_state *state)
b63b36fa 1539{
b1a88c71 1540 u8 cnt;
b63b36fa
FR		 1541 u8 packet_error;
1542 u32 snr;
1543
b1a88c71 1544 for (cnt = 0; cnt < 10; cnt++) {
8e8cd34e 1545 if (lgdt3306a_fec_lock_poll(state) == LG3306_UNLOCK) {
097117ca 1546 dbg_info("no fec lock!\n");
8e8cd34e 1547 return LG3306_UNLOCK;
b1a88c71 1548 }
b63b36fa 1549
b1a88c71 1550 msleep(20);
b63b36fa 1551
b1a88c71
MCC		 1552 packet_error = lgdt3306a_get_packet_error(state);
1553 snr = lgdt3306a_calculate_snr_x100(state);
1554 dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr);
b63b36fa 1555
b1a88c71
MCC		 1556 if ((snr >= 1500) && (packet_error < 0xff))
1557 return LG3306_LOCK;
b63b36fa 1558 }
b1a88c71
MCC		 1559
1560 dbg_info("not locked!\n");
8e8cd34e 1561 return LG3306_UNLOCK;
b63b36fa
FR		 1562}
1563
0df289a2
MCC		 1564static int lgdt3306a_read_status(struct dvb_frontend *fe,
1565 enum fe_status *status)
b63b36fa 1566{
b63b36fa 1567 struct lgdt3306a_state *state = fe->demodulator_priv;
b63b36fa 1568 u16 strength = 0;
8e8cd34e
MIK		 1569 int ret = 0;
1570
b63b36fa
FR		 1571 if (fe->ops.tuner_ops.get_rf_strength) {
1572 ret = fe->ops.tuner_ops.get_rf_strength(fe, &strength);
c9897649 1573 if (ret == 0)
097117ca 1574 dbg_info("strength=%d\n", strength);
c9897649 1575 else
097117ca 1576 dbg_info("fe->ops.tuner_ops.get_rf_strength() failed\n");
b63b36fa
FR		 1577 }
1578
1579 *status = 0;
8e8cd34e 1580 if (lgdt3306a_neverlock_poll(state) == LG3306_NL_LOCK) {
b63b36fa
FR		 1581 *status |= FE_HAS_SIGNAL;
1582 *status |= FE_HAS_CARRIER;
1583
1584 switch (state->current_modulation) {
1585 case QAM_256:
1586 case QAM_64:
8e8cd34e 1587 if (lgdt3306a_qam_lock_poll(state) == LG3306_LOCK) {
b63b36fa
FR		 1588 *status |= FE_HAS_VITERBI;
1589 *status |= FE_HAS_SYNC;
1590
1591 *status |= FE_HAS_LOCK;
1592 }
1593 break;
1594 case VSB_8:
8e8cd34e 1595 if (lgdt3306a_vsb_lock_poll(state) == LG3306_LOCK) {
b63b36fa
FR		 1596 *status |= FE_HAS_VITERBI;
1597 *status |= FE_HAS_SYNC;
1598
1599 *status |= FE_HAS_LOCK;
1600
ee0133ee 1601 ret = lgdt3306a_monitor_vsb(state);
b63b36fa
FR		 1602 }
1603 break;
1604 default:
1605 ret = -EINVAL;
1606 }
1607 }
1608 return ret;
1609}
1610
1611
1612static int lgdt3306a_read_snr(struct dvb_frontend *fe, u16 *snr)
1613{
1614 struct lgdt3306a_state *state = fe->demodulator_priv;
1615
1616 state->snr = lgdt3306a_calculate_snr_x100(state);
1617 /* report SNR in dB * 10 */
1618 *snr = state->snr/10;
1619
1620 return 0;
1621}
1622
1623static int lgdt3306a_read_signal_strength(struct dvb_frontend *fe,
1624 u16 *strength)
1625{
1626 /*
1627 * Calculate some sort of "strength" from SNR
1628 */
1629 struct lgdt3306a_state *state = fe->demodulator_priv;
34a5a2f8 1630 u16 snr; /* snr_x10 */
b63b36fa 1631 int ret;
8e8cd34e 1632 u32 ref_snr; /* snr*100 */
b63b36fa
FR		 1633 u32 str;
1634
1635 *strength = 0;
1636
1637 switch (state->current_modulation) {
1638 case VSB_8:
8e8cd34e 1639 ref_snr = 1600; /* 16dB */
b63b36fa
FR		 1640 break;
1641 case QAM_64:
8e8cd34e 1642 ref_snr = 2200; /* 22dB */
b63b36fa
FR		 1643 break;
1644 case QAM_256:
8e8cd34e 1645 ref_snr = 2800; /* 28dB */
b63b36fa
FR		 1646 break;
1647 default:
1648 return -EINVAL;
1649 }
1650
1651 ret = fe->ops.read_snr(fe, &snr);
1652 if (lg_chkerr(ret))
1653 goto fail;
1654
8e8cd34e 1655 if (state->snr <= (ref_snr - 100))
b63b36fa 1656 str = 0;
8e8cd34e
MIK		 1657 else if (state->snr <= ref_snr)
1658 str = (0xffff * 65) / 100; /* 65% */
b63b36fa
FR		 1659 else {
1660 str = state->snr - ref_snr;
1661 str /= 50;
8e8cd34e
MIK		 1662 str += 78; /* 78%-100% */
1663 if (str > 100)
b63b36fa
FR		 1664 str = 100;
1665 str = (0xffff * str) / 100;
1666 }
1667 *strength = (u16)str;
097117ca 1668 dbg_info("strength=%u\n", *strength);
b63b36fa
FR		 1669
1670fail:
1671 return ret;
1672}
1673
1674/* ------------------------------------------------------------------------ */
1675
1676static int lgdt3306a_read_ber(struct dvb_frontend *fe, u32 *ber)
1677{
1678 struct lgdt3306a_state *state = fe->demodulator_priv;
1679 u32 tmp;
1680
1681 *ber = 0;
1682#if 1
534f4364 1683 /* FGR - FIXME - I don't know what value is expected by dvb_core
8e8cd34e 1684 * what is the scale of the value?? */
4937ba94
MCC		 1685 tmp = read_reg(state, 0x00fc); /* NBERVALUE[24-31] */
1686 tmp = (tmp << 8) | read_reg(state, 0x00fd); /* NBERVALUE[16-23] */
1687 tmp = (tmp << 8) | read_reg(state, 0x00fe); /* NBERVALUE[8-15] */
1688 tmp = (tmp << 8) | read_reg(state, 0x00ff); /* NBERVALUE[0-7] */
b63b36fa 1689 *ber = tmp;
097117ca 1690 dbg_info("ber=%u\n", tmp);
b63b36fa
FR		 1691#endif
1692 return 0;
1693}
1694
1695static int lgdt3306a_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1696{
1697 struct lgdt3306a_state *state = fe->demodulator_priv;
1698
8e8cd34e 1699 *ucblocks = 0;
b63b36fa 1700#if 1
534f4364 1701 /* FGR - FIXME - I don't know what value is expected by dvb_core
8e8cd34e 1702 * what happens when value wraps? */
4937ba94 1703 *ucblocks = read_reg(state, 0x00f4); /* TPIFTPERRCNT[0-7] */
097117ca 1704 dbg_info("ucblocks=%u\n", *ucblocks);
b63b36fa
FR		 1705#endif
1706
1707 return 0;
1708}
1709
534f4364
MCC		 1710static int lgdt3306a_tune(struct dvb_frontend *fe, bool re_tune,
1711 unsigned int mode_flags, unsigned int *delay,
0df289a2 1712 enum fe_status *status)
b63b36fa
FR		 1713{
1714 int ret = 0;
1715 struct lgdt3306a_state *state = fe->demodulator_priv;
1716
097117ca 1717 dbg_info("re_tune=%u\n", re_tune);
b63b36fa
FR		 1718
1719 if (re_tune) {
8e8cd34e 1720 state->current_frequency = -1; /* force re-tune */
ae21e447
MIK		 1721 ret = lgdt3306a_set_parameters(fe);
1722 if (ret != 0)
b63b36fa 1723 return ret;
b63b36fa
FR		 1724 }
1725 *delay = 125;
1726 ret = lgdt3306a_read_status(fe, status);
1727
1728 return ret;
1729}
1730
1731static int lgdt3306a_get_tune_settings(struct dvb_frontend *fe,
8e8cd34e
MIK		 1732 struct dvb_frontend_tune_settings
1733 *fe_tune_settings)
b63b36fa
FR		 1734{
1735 fe_tune_settings->min_delay_ms = 100;
097117ca 1736 dbg_info("\n");
b63b36fa
FR		 1737 return 0;
1738}
1739
1740static int lgdt3306a_search(struct dvb_frontend *fe)
1741{
0df289a2 1742 enum fe_status status = 0;
dd14523a 1743 int ret;
b63b36fa
FR		 1744
1745 /* set frontend */
1746 ret = lgdt3306a_set_parameters(fe);
1747 if (ret)
1748 goto error;
1749
dd14523a
AO		 1750 ret = lgdt3306a_read_status(fe, &status);
1751 if (ret)
1752 goto error;
b63b36fa
FR		 1753
1754 /* check if we have a valid signal */
8e8cd34e 1755 if (status & FE_HAS_LOCK)
b63b36fa 1756 return DVBFE_ALGO_SEARCH_SUCCESS;
8e8cd34e 1757 else
b63b36fa 1758 return DVBFE_ALGO_SEARCH_AGAIN;
b63b36fa
FR		 1759
1760error:
097117ca 1761 dbg_info("failed (%d)\n", ret);
b63b36fa
FR		 1762 return DVBFE_ALGO_SEARCH_ERROR;
1763}
1764
1765static void lgdt3306a_release(struct dvb_frontend *fe)
1766{
1767 struct lgdt3306a_state *state = fe->demodulator_priv;
8e8cd34e 1768
097117ca 1769 dbg_info("\n");
b63b36fa
FR		 1770 kfree(state);
1771}
1772
bd336e63 1773static const struct dvb_frontend_ops lgdt3306a_ops;
b63b36fa
FR		 1774
1775struct dvb_frontend *lgdt3306a_attach(const struct lgdt3306a_config *config,
c43e6512 1776 struct i2c_adapter *i2c_adap)
b63b36fa
FR		 1777{
1778 struct lgdt3306a_state *state = NULL;
1779 int ret;
1780 u8 val;
1781
097117ca 1782 dbg_info("(%d-%04x)\n",
b63b36fa
FR		 1783 i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
1784 config ? config->i2c_addr : 0);
1785
1786 state = kzalloc(sizeof(struct lgdt3306a_state), GFP_KERNEL);
1787 if (state == NULL)
1788 goto fail;
1789
1790 state->cfg = config;
1791 state->i2c_adap = i2c_adap;
1792
1793 memcpy(&state->frontend.ops, &lgdt3306a_ops,
1794 sizeof(struct dvb_frontend_ops));
1795 state->frontend.demodulator_priv = state;
1796
1797 /* verify that we're talking to a lg3306a */
8e8cd34e
MIK		 1798 /* FGR - NOTE - there is no obvious ChipId to check; we check
1799 * some "known" bits after reset, but it's still just a guess */
b63b36fa
FR		 1800 ret = lgdt3306a_read_reg(state, 0x0000, &val);
1801 if (lg_chkerr(ret))
1802 goto fail;
8e8cd34e 1803 if ((val & 0x74) != 0x74) {
097117ca 1804 pr_warn("expected 0x74, got 0x%x\n", (val & 0x74));
8e8cd34e 1805#if 0
534f4364
MCC		 1806 /* FIXME - re-enable when we know this is right */
1807 goto fail;
8e8cd34e 1808#endif
b63b36fa
FR		 1809 }
1810 ret = lgdt3306a_read_reg(state, 0x0001, &val);
1811 if (lg_chkerr(ret))
1812 goto fail;
4937ba94 1813 if ((val & 0xf6) != 0xc6) {
097117ca 1814 pr_warn("expected 0xc6, got 0x%x\n", (val & 0xf6));
8e8cd34e 1815#if 0
534f4364
MCC		 1816 /* FIXME - re-enable when we know this is right */
1817 goto fail;
8e8cd34e 1818#endif
b63b36fa
FR		 1819 }
1820 ret = lgdt3306a_read_reg(state, 0x0002, &val);
1821 if (lg_chkerr(ret))
1822 goto fail;
8e8cd34e 1823 if ((val & 0x73) != 0x03) {
097117ca 1824 pr_warn("expected 0x03, got 0x%x\n", (val & 0x73));
8e8cd34e 1825#if 0
534f4364
MCC		 1826 /* FIXME - re-enable when we know this is right */
1827 goto fail;
8e8cd34e 1828#endif
b63b36fa
FR		 1829 }
1830
1831 state->current_frequency = -1;
1832 state->current_modulation = -1;
1833
1834 lgdt3306a_sleep(state);
1835
1836 return &state->frontend;
1837
1838fail:
097117ca 1839 pr_warn("unable to detect LGDT3306A hardware\n");
b63b36fa
FR		 1840 kfree(state);
1841 return NULL;
1842}
ebd9175e 1843EXPORT_SYMBOL(lgdt3306a_attach);
b63b36fa
FR		 1844
1845#ifdef DBG_DUMP
1846
1847static const short regtab[] = {
cb4671c8
MIK		 1848 0x0000, /* SOFTRSTB 1'b1 1'b1 1'b1 ADCPDB 1'b1 PLLPDB GBBPDB 11111111 */
1849 0x0001, /* 1'b1 1'b1 1'b0 1'b0 AUTORPTRS */
1850 0x0002, /* NI2CRPTEN 1'b0 1'b0 1'b0 SPECINVAUT */
1851 0x0003, /* AGCRFOUT */
1852 0x0004, /* ADCSEL1V ADCCNT ADCCNF ADCCNS ADCCLKPLL */
1853 0x0005, /* PLLINDIVSE */
1854 0x0006, /* PLLCTRL[7:0] 11100001 */
1855 0x0007, /* SYSINITWAITTIME[7:0] (msec) 00001000 */
1856 0x0008, /* STDOPMODE[7:0] 10000000 */
1857 0x0009, /* 1'b0 1'b0 1'b0 STDOPDETTMODE[2:0] STDOPDETCMODE[1:0] 00011110 */
4937ba94
MCC		 1858 0x000a, /* DAFTEN 1'b1 x x SCSYSLOCK */
1859 0x000b, /* SCSYSLOCKCHKTIME[7:0] (10msec) 01100100 */
1860 0x000d, /* x SAMPLING4 */
1861 0x000e, /* SAMFREQ[15:8] 00000000 */
1862 0x000f, /* SAMFREQ[7:0] 00000000 */
cb4671c8
MIK		 1863 0x0010, /* IFFREQ[15:8] 01100000 */
1864 0x0011, /* IFFREQ[7:0] 00000000 */
1865 0x0012, /* AGCEN AGCREFMO */
1866 0x0013, /* AGCRFFIXB AGCIFFIXB AGCLOCKDETRNGSEL[1:0] 1'b1 1'b0 1'b0 1'b0 11101000 */
1867 0x0014, /* AGCFIXVALUE[7:0] 01111111 */
1868 0x0015, /* AGCREF[15:8] 00001010 */
1869 0x0016, /* AGCREF[7:0] 11100100 */
1870 0x0017, /* AGCDELAY[7:0] 00100000 */
1871 0x0018, /* AGCRFBW[3:0] AGCIFBW[3:0] 10001000 */
1872 0x0019, /* AGCUDOUTMODE[1:0] AGCUDCTRLLEN[1:0] AGCUDCTRL */
4937ba94
MCC		 1873 0x001c, /* 1'b1 PFEN MFEN AICCVSYNC */
1874 0x001d, /* 1'b0 1'b1 1'b0 1'b1 AICCVSYNC */
1875 0x001e, /* AICCALPHA[3:0] 1'b1 1'b0 1'b1 1'b0 01111010 */
1876 0x001f, /* AICCDETTH[19:16] AICCOFFTH[19:16] 00000000 */
cb4671c8
MIK		 1877 0x0020, /* AICCDETTH[15:8] 01111100 */
1878 0x0021, /* AICCDETTH[7:0] 00000000 */
1879 0x0022, /* AICCOFFTH[15:8] 00000101 */
1880 0x0023, /* AICCOFFTH[7:0] 11100000 */
1881 0x0024, /* AICCOPMODE3[1:0] AICCOPMODE2[1:0] AICCOPMODE1[1:0] AICCOPMODE0[1:0] 00000000 */
1882 0x0025, /* AICCFIXFREQ3[23:16] 00000000 */
1883 0x0026, /* AICCFIXFREQ3[15:8] 00000000 */
1884 0x0027, /* AICCFIXFREQ3[7:0] 00000000 */
1885 0x0028, /* AICCFIXFREQ2[23:16] 00000000 */
1886 0x0029, /* AICCFIXFREQ2[15:8] 00000000 */
4937ba94
MCC		 1887 0x002a, /* AICCFIXFREQ2[7:0] 00000000 */
1888 0x002b, /* AICCFIXFREQ1[23:16] 00000000 */
1889 0x002c, /* AICCFIXFREQ1[15:8] 00000000 */
1890 0x002d, /* AICCFIXFREQ1[7:0] 00000000 */
1891 0x002e, /* AICCFIXFREQ0[23:16] 00000000 */
1892 0x002f, /* AICCFIXFREQ0[15:8] 00000000 */
cb4671c8
MIK		 1893 0x0030, /* AICCFIXFREQ0[7:0] 00000000 */
1894 0x0031, /* 1'b0 1'b1 1'b0 1'b0 x DAGC1STER */
1895 0x0032, /* DAGC1STEN DAGC1STER */
1896 0x0033, /* DAGC1STREF[15:8] 00001010 */
1897 0x0034, /* DAGC1STREF[7:0] 11100100 */
1898 0x0035, /* DAGC2NDE */
1899 0x0036, /* DAGC2NDREF[15:8] 00001010 */
1900 0x0037, /* DAGC2NDREF[7:0] 10000000 */
1901 0x0038, /* DAGC2NDLOCKDETRNGSEL[1:0] */
4937ba94 1902 0x003d, /* 1'b1 SAMGEARS */
cb4671c8
MIK		 1903 0x0040, /* SAMLFGMA */
1904 0x0041, /* SAMLFBWM */
1905 0x0044, /* 1'b1 CRGEARSHE */
1906 0x0045, /* CRLFGMAN */
1907 0x0046, /* CFLFBWMA */
1908 0x0047, /* CRLFGMAN */
1909 0x0048, /* x x x x CRLFGSTEP_VS[3:0] xxxx1001 */
1910 0x0049, /* CRLFBWMA */
4937ba94 1911 0x004a, /* CRLFBWMA */
cb4671c8
MIK		 1912 0x0050, /* 1'b0 1'b1 1'b1 1'b0 MSECALCDA */
1913 0x0070, /* TPOUTEN TPIFEN TPCLKOUTE */
1914 0x0071, /* TPSENB TPSSOPBITE */
1915 0x0073, /* TP47HINS x x CHBERINT PERMODE[1:0] PERINT[1:0] 1xx11100 */
1916 0x0075, /* x x x x x IQSWAPCTRL[2:0] xxxxx000 */
1917 0x0076, /* NBERCON NBERST NBERPOL NBERWSYN */
1918 0x0077, /* x NBERLOSTTH[2:0] NBERACQTH[3:0] x0000000 */
1919 0x0078, /* NBERPOLY[31:24] 00000000 */
1920 0x0079, /* NBERPOLY[23:16] 00000000 */
4937ba94
MCC		 1921 0x007a, /* NBERPOLY[15:8] 00000000 */
1922 0x007b, /* NBERPOLY[7:0] 00000000 */
1923 0x007c, /* NBERPED[31:24] 00000000 */
1924 0x007d, /* NBERPED[23:16] 00000000 */
1925 0x007e, /* NBERPED[15:8] 00000000 */
1926 0x007f, /* NBERPED[7:0] 00000000 */
cb4671c8
MIK		 1927 0x0080, /* x AGCLOCK DAGCLOCK SYSLOCK x x NEVERLOCK[1:0] */
1928 0x0085, /* SPECINVST */
1929 0x0088, /* SYSLOCKTIME[15:8] */
1930 0x0089, /* SYSLOCKTIME[7:0] */
4937ba94
MCC		 1931 0x008c, /* FECLOCKTIME[15:8] */
1932 0x008d, /* FECLOCKTIME[7:0] */
1933 0x008e, /* AGCACCOUT[15:8] */
1934 0x008f, /* AGCACCOUT[7:0] */
cb4671c8
MIK		 1935 0x0090, /* AICCREJSTATUS[3:0] AICCREJBUSY[3:0] */
1936 0x0091, /* AICCVSYNC */
4937ba94
MCC		 1937 0x009c, /* CARRFREQOFFSET[15:8] */
1938 0x009d, /* CARRFREQOFFSET[7:0] */
1939 0x00a1, /* SAMFREQOFFSET[23:16] */
1940 0x00a2, /* SAMFREQOFFSET[15:8] */
1941 0x00a3, /* SAMFREQOFFSET[7:0] */
1942 0x00a6, /* SYNCLOCK SYNCLOCKH */
6da7ac98 1943#if 0 /* covered elsewhere */
4937ba94
MCC		 1944 0x00e8, /* CONSTPWR[15:8] */
1945 0x00e9, /* CONSTPWR[7:0] */
1946 0x00ea, /* BMSE[15:8] */
1947 0x00eb, /* BMSE[7:0] */
1948 0x00ec, /* MSE[15:8] */
1949 0x00ed, /* MSE[7:0] */
1950 0x00ee, /* CONSTI[7:0] */
1951 0x00ef, /* CONSTQ[7:0] */
b63b36fa 1952#endif
4937ba94
MCC		 1953 0x00f4, /* TPIFTPERRCNT[7:0] */
1954 0x00f5, /* TPCORREC */
1955 0x00f6, /* VBBER[15:8] */
1956 0x00f7, /* VBBER[7:0] */
1957 0x00f8, /* VABER[15:8] */
1958 0x00f9, /* VABER[7:0] */
1959 0x00fa, /* TPERRCNT[7:0] */
1960 0x00fb, /* NBERLOCK x x x x x x x */
1961 0x00fc, /* NBERVALUE[31:24] */
1962 0x00fd, /* NBERVALUE[23:16] */
1963 0x00fe, /* NBERVALUE[15:8] */
1964 0x00ff, /* NBERVALUE[7:0] */
cb4671c8
MIK		 1965 0x1000, /* 1'b0 WODAGCOU */
1966 0x1005, /* x x 1'b1 1'b1 x SRD_Q_QM */
1967 0x1009, /* SRDWAITTIME[7:0] (10msec) 00100011 */
4937ba94
MCC		 1968 0x100a, /* SRDWAITTIME_CQS[7:0] (msec) 01100100 */
1969 0x101a, /* x 1'b1 1'b0 1'b0 x QMDQAMMODE[2:0] x100x010 */
cb4671c8 1970 0x1036, /* 1'b0 1'b1 1'b0 1'b0 SAMGSEND_CQS[3:0] 01001110 */
4937ba94
MCC		 1971 0x103c, /* SAMGSAUTOSTL_V[3:0] SAMGSAUTOEDL_V[3:0] 01000110 */
1972 0x103d, /* 1'b1 1'b1 SAMCNORMBP_V[1:0] 1'b0 1'b0 SAMMODESEL_V[1:0] 11100001 */
1973 0x103f, /* SAMZTEDSE */
1974 0x105d, /* EQSTATUSE */
1975 0x105f, /* x PMAPG2_V[2:0] x DMAPG2_V[2:0] x001x011 */
cb4671c8
MIK		 1976 0x1060, /* 1'b1 EQSTATUSE */
1977 0x1061, /* CRMAPBWSTL_V[3:0] CRMAPBWEDL_V[3:0] 00000100 */
1978 0x1065, /* 1'b0 x CRMODE_V[1:0] 1'b1 x 1'b1 x 0x111x1x */
1979 0x1066, /* 1'b0 1'b0 1'b1 1'b0 1'b1 PNBOOSTSE */
1980 0x1068, /* CREPHNGAIN2_V[3:0] CREPHNPBW_V[3:0] 10010001 */
4937ba94
MCC		 1981 0x106e, /* x x x x x CREPHNEN_ */
1982 0x106f, /* CREPHNTH_V[7:0] 00010101 */
cb4671c8
MIK		 1983 0x1072, /* CRSWEEPN */
1984 0x1073, /* CRPGAIN_V[3:0] x x 1'b1 1'b1 1001xx11 */
1985 0x1074, /* CRPBW_V[3:0] x x 1'b1 1'b1 0001xx11 */
1986 0x1080, /* DAFTSTATUS[1:0] x x x x x x */
1987 0x1081, /* SRDSTATUS[1:0] x x x x x SRDLOCK */
4937ba94
MCC		 1988 0x10a9, /* EQSTATUS_CQS[1:0] x x x x x x */
1989 0x10b7, /* EQSTATUS_V[1:0] x x x x x x */
6da7ac98 1990#if 0 /* SMART_ANT */
4937ba94
MCC		 1991 0x1f00, /* MODEDETE */
1992 0x1f01, /* x x x x x x x SFNRST xxxxxxx0 */
1993 0x1f03, /* NUMOFANT[7:0] 10000000 */
1994 0x1f04, /* x SELMASK[6:0] x0000000 */
1995 0x1f05, /* x SETMASK[6:0] x0000000 */
1996 0x1f06, /* x TXDATA[6:0] x0000000 */
1997 0x1f07, /* x CHNUMBER[6:0] x0000000 */
1998 0x1f09, /* AGCTIME[23:16] 10011000 */
1999 0x1f0a, /* AGCTIME[15:8] 10010110 */
2000 0x1f0b, /* AGCTIME[7:0] 10000000 */
2001 0x1f0c, /* ANTTIME[31:24] 00000000 */
2002 0x1f0d, /* ANTTIME[23:16] 00000011 */
2003 0x1f0e, /* ANTTIME[15:8] 10010000 */
2004 0x1f0f, /* ANTTIME[7:0] 10010000 */
2005 0x1f11, /* SYNCTIME[23:16] 10011000 */
2006 0x1f12, /* SYNCTIME[15:8] 10010110 */
2007 0x1f13, /* SYNCTIME[7:0] 10000000 */
2008 0x1f14, /* SNRTIME[31:24] 00000001 */
2009 0x1f15, /* SNRTIME[23:16] 01111101 */
2010 0x1f16, /* SNRTIME[15:8] 01111000 */
2011 0x1f17, /* SNRTIME[7:0] 01000000 */
2012 0x1f19, /* FECTIME[23:16] 00000000 */
2013 0x1f1a, /* FECTIME[15:8] 01110010 */
2014 0x1f1b, /* FECTIME[7:0] 01110000 */
2015 0x1f1d, /* FECTHD[7:0] 00000011 */
2016 0x1f1f, /* SNRTHD[23:16] 00001000 */
2017 0x1f20, /* SNRTHD[15:8] 01111111 */
2018 0x1f21, /* SNRTHD[7:0] 10000101 */
2019 0x1f80, /* IRQFLG x x SFSDRFLG MODEBFLG SAVEFLG SCANFLG TRACKFLG */
2020 0x1f81, /* x SYNCCON SNRCON FECCON x STDBUSY SYNCRST AGCFZCO */
2021 0x1f82, /* x x x SCANOPCD[4:0] */
2022 0x1f83, /* x x x x MAINOPCD[3:0] */
2023 0x1f84, /* x x RXDATA[13:8] */
2024 0x1f85, /* RXDATA[7:0] */
2025 0x1f86, /* x x SDTDATA[13:8] */
2026 0x1f87, /* SDTDATA[7:0] */
2027 0x1f89, /* ANTSNR[23:16] */
2028 0x1f8a, /* ANTSNR[15:8] */
2029 0x1f8b, /* ANTSNR[7:0] */
2030 0x1f8c, /* x x x x ANTFEC[13:8] */
2031 0x1f8d, /* ANTFEC[7:0] */
2032 0x1f8e, /* MAXCNT[7:0] */
2033 0x1f8f, /* SCANCNT[7:0] */
2034 0x1f91, /* MAXPW[23:16] */
2035 0x1f92, /* MAXPW[15:8] */
2036 0x1f93, /* MAXPW[7:0] */
2037 0x1f95, /* CURPWMSE[23:16] */
2038 0x1f96, /* CURPWMSE[15:8] */
2039 0x1f97, /* CURPWMSE[7:0] */
6da7ac98 2040#endif /* SMART_ANT */
4937ba94
MCC		 2041 0x211f, /* 1'b1 1'b1 1'b1 CIRQEN x x 1'b0 1'b0 1111xx00 */
2042 0x212a, /* EQAUTOST */
cb4671c8 2043 0x2122, /* CHFAST[7:0] 01100000 */
4937ba94
MCC		 2044 0x212b, /* FFFSTEP_V[3:0] x FBFSTEP_V[2:0] 0001x001 */
2045 0x212c, /* PHDEROTBWSEL[3:0] 1'b1 1'b1 1'b1 1'b0 10001110 */
2046 0x212d, /* 1'b1 1'b1 1'b1 1'b1 x x TPIFLOCKS */
cb4671c8
MIK		 2047 0x2135, /* DYNTRACKFDEQ[3:0] x 1'b0 1'b0 1'b0 1010x000 */
2048 0x2141, /* TRMODE[1:0] 1'b1 1'b1 1'b0 1'b1 1'b1 1'b1 01110111 */
2049 0x2162, /* AICCCTRLE */
2050 0x2173, /* PHNCNFCNT[7:0] 00000100 */
2051 0x2179, /* 1'b0 1'b0 1'b0 1'b1 x BADSINGLEDYNTRACKFBF[2:0] 0001x001 */
4937ba94
MCC		 2052 0x217a, /* 1'b0 1'b0 1'b0 1'b1 x BADSLOWSINGLEDYNTRACKFBF[2:0] 0001x001 */
2053 0x217e, /* CNFCNTTPIF[7:0] 00001000 */
2054 0x217f, /* TPERRCNTTPIF[7:0] 00000001 */
cb4671c8
MIK		 2055 0x2180, /* x x x x x x FBDLYCIR[9:8] */
2056 0x2181, /* FBDLYCIR[7:0] */
2057 0x2185, /* MAXPWRMAIN[7:0] */
2058 0x2191, /* NCOMBDET x x x x x x x */
2059 0x2199, /* x MAINSTRON */
4937ba94
MCC		 2060 0x219a, /* FFFEQSTEPOUT_V[3:0] FBFSTEPOUT_V[2:0] */
2061 0x21a1, /* x x SNRREF[5:0] */
cb4671c8
MIK		 2062 0x2845, /* 1'b0 1'b1 x x FFFSTEP_CQS[1:0] FFFCENTERTAP[1:0] 01xx1110 */
2063 0x2846, /* 1'b0 x 1'b0 1'b1 FBFSTEP_CQS[1:0] 1'b1 1'b0 0x011110 */
2064 0x2847, /* ENNOSIGDE */
2065 0x2849, /* 1'b1 1'b1 NOUSENOSI */
4937ba94 2066 0x284a, /* EQINITWAITTIME[7:0] 01100100 */
cb4671c8
MIK		 2067 0x3000, /* 1'b1 1'b1 1'b1 x x x 1'b0 RPTRSTM */
2068 0x3001, /* RPTRSTWAITTIME[7:0] (100msec) 00110010 */
2069 0x3031, /* FRAMELOC */
2070 0x3032, /* 1'b1 1'b0 1'b0 1'b0 x x FRAMELOCKMODE_CQS[1:0] 1000xx11 */
4937ba94
MCC		 2071 0x30a9, /* VDLOCK_Q FRAMELOCK */
2072 0x30aa, /* MPEGLOCK */
b63b36fa
FR		 2073};
2074
34a5a2f8 2075#define numDumpRegs (sizeof(regtab)/sizeof(regtab[0]))
b63b36fa
FR		 2076static u8 regval1[numDumpRegs] = {0, };
2077static u8 regval2[numDumpRegs] = {0, };
2078
2079static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state)
2080{
2081 memset(regval2, 0xff, sizeof(regval2));
2082 lgdt3306a_DumpRegs(state);
2083}
2084
2085static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state)
2086{
2087 int i;
2088 int sav_debug = debug;
8e8cd34e 2089
b63b36fa
FR		 2090 if ((debug & DBG_DUMP) == 0)
2091 return;
831a9112 2092 debug &= ~DBG_REG; /* suppress DBG_REG during reg dump */
b63b36fa 2093
097117ca 2094 lg_debug("\n");
b63b36fa 2095
8e8cd34e 2096 for (i = 0; i < numDumpRegs; i++) {
b63b36fa 2097 lgdt3306a_read_reg(state, regtab[i], &regval1[i]);
8e8cd34e 2098 if (regval1[i] != regval2[i]) {
097117ca 2099 lg_debug(" %04X = %02X\n", regtab[i], regval1[i]);
16afc672 2100 regval2[i] = regval1[i];
b63b36fa
FR		 2101 }
2102 }
2103 debug = sav_debug;
2104}
8e8cd34e 2105#endif /* DBG_DUMP */
b63b36fa
FR		 2106
2107
2108
bd336e63 2109static const struct dvb_frontend_ops lgdt3306a_ops = {
b63b36fa
FR		 2110 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
2111 .info = {
2112 .name = "LG Electronics LGDT3306A VSB/QAM Frontend",
b63b36fa 2113 .frequency_min = 54000000,
8e8cd34e 2114 .frequency_max = 858000000,
b63b36fa
FR		 2115 .frequency_stepsize = 62500,
2116 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
2117 },
2118 .i2c_gate_ctrl = lgdt3306a_i2c_gate_ctrl,
2119 .init = lgdt3306a_init,
2120 .sleep = lgdt3306a_fe_sleep,
2121 /* if this is set, it overrides the default swzigzag */
2122 .tune = lgdt3306a_tune,
2123 .set_frontend = lgdt3306a_set_parameters,
2124 .get_frontend = lgdt3306a_get_frontend,
2125 .get_frontend_algo = lgdt3306a_get_frontend_algo,
2126 .get_tune_settings = lgdt3306a_get_tune_settings,
2127 .read_status = lgdt3306a_read_status,
2128 .read_ber = lgdt3306a_read_ber,
2129 .read_signal_strength = lgdt3306a_read_signal_strength,
2130 .read_snr = lgdt3306a_read_snr,
2131 .read_ucblocks = lgdt3306a_read_ucblocks,
2132 .release = lgdt3306a_release,
2133 .ts_bus_ctrl = lgdt3306a_ts_bus_ctrl,
2134 .search = lgdt3306a_search,
2135};
2136
4f751890
KC		 2137static int lgdt3306a_select(struct i2c_mux_core *muxc, u32 chan)
2138{
2139 struct i2c_client *client = i2c_mux_priv(muxc);
2140 struct lgdt3306a_state *state = i2c_get_clientdata(client);
2141
2142 return lgdt3306a_i2c_gate_ctrl(&state->frontend, 1);
2143}
2144
2145static int lgdt3306a_deselect(struct i2c_mux_core *muxc, u32 chan)
2146{
2147 struct i2c_client *client = i2c_mux_priv(muxc);
2148 struct lgdt3306a_state *state = i2c_get_clientdata(client);
2149
2150 return lgdt3306a_i2c_gate_ctrl(&state->frontend, 0);
2151}
2152
2153static int lgdt3306a_probe(struct i2c_client *client,
2154 const struct i2c_device_id *id)
2155{
2156 struct lgdt3306a_config *config;
2157 struct lgdt3306a_state *state;
2158 struct dvb_frontend *fe;
2159 int ret;
2160
2161 config = kzalloc(sizeof(struct lgdt3306a_config), GFP_KERNEL);
2162 if (config == NULL) {
2163 ret = -ENOMEM;
2164 goto fail;
2165 }
2166
2167 memcpy(config, client->dev.platform_data,
2168 sizeof(struct lgdt3306a_config));
2169
2170 config->i2c_addr = client->addr;
2171 fe = lgdt3306a_attach(config, client->adapter);
2172 if (fe == NULL) {
2173 ret = -ENODEV;
2174 goto err_fe;
2175 }
2176
2177 i2c_set_clientdata(client, fe->demodulator_priv);
2178 state = fe->demodulator_priv;
2179
2180 /* create mux i2c adapter for tuner */
2181 state->muxc = i2c_mux_alloc(client->adapter, &client->dev,
2182 1, 0, I2C_MUX_LOCKED,
2183 lgdt3306a_select, lgdt3306a_deselect);
2184 if (!state->muxc) {
2185 ret = -ENOMEM;
2186 goto err_kfree;
2187 }
2188 state->muxc->priv = client;
2189 ret = i2c_mux_add_adapter(state->muxc, 0, 0, 0);
2190 if (ret)
2191 goto err_kfree;
2192
2193 /* create dvb_frontend */
2194 fe->ops.i2c_gate_ctrl = NULL;
2195 *config->i2c_adapter = state->muxc->adapter[0];
2196 *config->fe = fe;
2197
2198 return 0;
2199
2200err_kfree:
2201 kfree(state);
2202err_fe:
2203 kfree(config);
2204fail:
2205 dev_dbg(&client->dev, "failed=%d\n", ret);
2206 return ret;
2207}
2208
2209static int lgdt3306a_remove(struct i2c_client *client)
2210{
2211 struct lgdt3306a_state *state = i2c_get_clientdata(client);
2212
2213 i2c_mux_del_adapters(state->muxc);
2214
2215 state->frontend.ops.release = NULL;
2216 state->frontend.demodulator_priv = NULL;
2217
2218 kfree(state->cfg);
2219 kfree(state);
2220
2221 return 0;
2222}
2223
2224static const struct i2c_device_id lgdt3306a_id_table[] = {
2225 {"lgdt3306a", 0},
2226 {}
2227};
2228MODULE_DEVICE_TABLE(i2c, lgdt3306a_id_table);
2229
2230static struct i2c_driver lgdt3306a_driver = {
2231 .driver = {
2232 .name = "lgdt3306a",
2233 .suppress_bind_attrs = true,
2234 },
2235 .probe = lgdt3306a_probe,
2236 .remove = lgdt3306a_remove,
2237 .id_table = lgdt3306a_id_table,
2238};
2239
2240module_i2c_driver(lgdt3306a_driver);
2241
b63b36fa
FR		 2242MODULE_DESCRIPTION("LG Electronics LGDT3306A ATSC/QAM-B Demodulator Driver");
2243MODULE_AUTHOR("Fred Richter <frichter@hauppauge.com>");
2244MODULE_LICENSE("GPL");
2245MODULE_VERSION("0.2");
Linux 6.x block layer and io_uring tree(s)