projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[media] lgdt3306a: Don't use else were not needed
[linux-2.6-block.git] / drivers / media / dvb-frontends / lgdt3306a.c
CommitLineData
b63b36fa
FR		 1/*
2 * Support for LGDT3306A - 8VSB/QAM-B
3 *
4 * Copyright (C) 2013 Fred Richter <frichter@hauppauge.com>
5 * - driver structure based on lgdt3305.[ch] by Michael Krufky
6 * - code based on LG3306_V0.35 API by LG Electronics Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
b63b36fa
FR		 17 */
18
097117ca
MCC		 19#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
b63b36fa
FR		 21#include <asm/div64.h>
22#include <linux/dvb/frontend.h>
23#include "dvb_math.h"
24#include "lgdt3306a.h"
25
26
27static int debug;
28module_param(debug, int, 0644);
29MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))");
30
31#define DBG_INFO 1
32#define DBG_REG 2
8e8cd34e 33#define DBG_DUMP 4 /* FGR - comment out to remove dump code */
b63b36fa 34
097117ca
MCC		 35#define lg_debug(fmt, arg...) \
36 printk(KERN_DEBUG pr_fmt(fmt), ## arg)
37
38#define dbg_info(fmt, arg...) \
39 do { \
40 if (debug & DBG_INFO) \
41 lg_debug(fmt, ## arg); \
42 } while (0)
b63b36fa 43
097117ca
MCC		 44#define dbg_reg(fmt, arg...) \
45 do { \
46 if (debug & DBG_REG) \
47 lg_debug(fmt, ## arg); \
48 } while (0)
b63b36fa
FR		 49
50#define lg_chkerr(ret) \
51({ \
52 int __ret; \
53 __ret = (ret < 0); \
54 if (__ret) \
097117ca 55 pr_err("error %d on line %d\n", ret, __LINE__); \
b63b36fa
FR		 56 __ret; \
57})
58
59struct lgdt3306a_state {
60 struct i2c_adapter *i2c_adap;
61 const struct lgdt3306a_config *cfg;
62
63 struct dvb_frontend frontend;
64
65 fe_modulation_t current_modulation;
66 u32 current_frequency;
67 u32 snr;
68};
69
70/* -----------------------------------------------
71 LG3306A Register Usage
72 (LG does not really name the registers, so this code does not either)
73 0000 -> 00FF Common control and status
74 1000 -> 10FF Synchronizer control and status
75 1F00 -> 1FFF Smart Antenna control and status
76 2100 -> 21FF VSB Equalizer control and status
77 2800 -> 28FF QAM Equalizer control and status
78 3000 -> 30FF FEC control and status
79 ---------------------------------------------- */
80
f883d603
MIK		 81enum lgdt3306a_lock_status {
82 LG3306_UNLOCK = 0x00,
83 LG3306_LOCK = 0x01,
4937ba94 84 LG3306_UNKNOWN_LOCK = 0xff
f883d603 85};
b63b36fa 86
f883d603 87enum lgdt3306a_neverlock_status {
b63b36fa
FR		 88 LG3306_NL_INIT = 0x00,
89 LG3306_NL_PROCESS = 0x01,
90 LG3306_NL_LOCK = 0x02,
91 LG3306_NL_FAIL = 0x03,
4937ba94 92 LG3306_NL_UNKNOWN = 0xff
f883d603 93};
b63b36fa 94
f883d603
MIK		 95enum lgdt3306a_modulation {
96 LG3306_VSB = 0x00,
97 LG3306_QAM64 = 0x01,
98 LG3306_QAM256 = 0x02,
4937ba94 99 LG3306_UNKNOWN_MODE = 0xff
f883d603 100};
b63b36fa 101
f883d603 102enum lgdt3306a_lock_check {
b63b36fa
FR		 103 LG3306_SYNC_LOCK,
104 LG3306_FEC_LOCK,
105 LG3306_TR_LOCK,
106 LG3306_AGC_LOCK,
f883d603 107};
b63b36fa
FR		 108
109
110#ifdef DBG_DUMP
111static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state);
112static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state);
113#endif
114
115
116static int lgdt3306a_write_reg(struct lgdt3306a_state *state, u16 reg, u8 val)
117{
118 int ret;
119 u8 buf[] = { reg >> 8, reg & 0xff, val };
120 struct i2c_msg msg = {
121 .addr = state->cfg->i2c_addr, .flags = 0,
122 .buf = buf, .len = 3,
123 };
124
097117ca 125 dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
b63b36fa
FR		 126
127 ret = i2c_transfer(state->i2c_adap, &msg, 1);
128
129 if (ret != 1) {
097117ca 130 pr_err("error (addr %02x %02x <- %02x, err = %i)\n",
b63b36fa
FR		 131 msg.buf[0], msg.buf[1], msg.buf[2], ret);
132 if (ret < 0)
133 return ret;
134 else
135 return -EREMOTEIO;
136 }
137 return 0;
138}
139
140static int lgdt3306a_read_reg(struct lgdt3306a_state *state, u16 reg, u8 *val)
141{
142 int ret;
143 u8 reg_buf[] = { reg >> 8, reg & 0xff };
144 struct i2c_msg msg[] = {
145 { .addr = state->cfg->i2c_addr,
146 .flags = 0, .buf = reg_buf, .len = 2 },
147 { .addr = state->cfg->i2c_addr,
148 .flags = I2C_M_RD, .buf = val, .len = 1 },
149 };
150
151 ret = i2c_transfer(state->i2c_adap, msg, 2);
152
153 if (ret != 2) {
097117ca 154 pr_err("error (addr %02x reg %04x error (ret == %i)\n",
b63b36fa
FR		 155 state->cfg->i2c_addr, reg, ret);
156 if (ret < 0)
157 return ret;
158 else
159 return -EREMOTEIO;
160 }
097117ca 161 dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, *val);
b63b36fa
FR		 162
163 return 0;
164}
165
166#define read_reg(state, reg) \
167({ \
168 u8 __val; \
169 int ret = lgdt3306a_read_reg(state, reg, &__val); \
170 if (lg_chkerr(ret)) \
171 __val = 0; \
172 __val; \
173})
174
175static int lgdt3306a_set_reg_bit(struct lgdt3306a_state *state,
176 u16 reg, int bit, int onoff)
177{
178 u8 val;
179 int ret;
180
097117ca 181 dbg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
b63b36fa
FR		 182
183 ret = lgdt3306a_read_reg(state, reg, &val);
184 if (lg_chkerr(ret))
185 goto fail;
186
187 val &= ~(1 << bit);
188 val |= (onoff & 1) << bit;
189
190 ret = lgdt3306a_write_reg(state, reg, val);
191 lg_chkerr(ret);
192fail:
193 return ret;
194}
195
196/* ------------------------------------------------------------------------ */
197
198static int lgdt3306a_soft_reset(struct lgdt3306a_state *state)
199{
200 int ret;
201
097117ca 202 dbg_info("\n");
b63b36fa
FR		 203
204 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
205 if (lg_chkerr(ret))
206 goto fail;
207
208 msleep(20);
209 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
210 lg_chkerr(ret);
211
212fail:
213 return ret;
214}
215
216static int lgdt3306a_mpeg_mode(struct lgdt3306a_state *state,
217 enum lgdt3306a_mpeg_mode mode)
218{
219 u8 val;
220 int ret;
221
097117ca 222 dbg_info("(%d)\n", mode);
8e8cd34e
MIK		 223 /* transport packet format */
224 ret = lgdt3306a_set_reg_bit(state, 0x0071, 7, mode == LGDT3306A_MPEG_PARALLEL?1:0); /* TPSENB=0x80 */
b63b36fa
FR		 225 if (lg_chkerr(ret))
226 goto fail;
227
8e8cd34e
MIK		 228 /* start of packet signal duration */
229 ret = lgdt3306a_set_reg_bit(state, 0x0071, 6, 0); /* TPSSOPBITEN=0x40; 0=byte duration, 1=bit duration */
b63b36fa
FR		 230 if (lg_chkerr(ret))
231 goto fail;
232
233 ret = lgdt3306a_read_reg(state, 0x0070, &val);
234 if (lg_chkerr(ret))
235 goto fail;
236
8e8cd34e 237 val |= 0x10; /* TPCLKSUPB=0x10 */
b63b36fa 238
8e8cd34e 239 if (mode == LGDT3306A_MPEG_PARALLEL)
b63b36fa
FR		 240 val &= ~0x10;
241
242 ret = lgdt3306a_write_reg(state, 0x0070, val);
243 lg_chkerr(ret);
244
245fail:
246 return ret;
247}
248
249static int lgdt3306a_mpeg_mode_polarity(struct lgdt3306a_state *state,
250 enum lgdt3306a_tp_clock_edge edge,
251 enum lgdt3306a_tp_valid_polarity valid)
252{
253 u8 val;
254 int ret;
255
097117ca 256 dbg_info("edge=%d, valid=%d\n", edge, valid);
b63b36fa
FR		 257
258 ret = lgdt3306a_read_reg(state, 0x0070, &val);
259 if (lg_chkerr(ret))
260 goto fail;
261
8e8cd34e 262 val &= ~0x06; /* TPCLKPOL=0x04, TPVALPOL=0x02 */
b63b36fa 263
8e8cd34e 264 if (edge == LGDT3306A_TPCLK_RISING_EDGE)
b63b36fa 265 val |= 0x04;
8e8cd34e 266 if (valid == LGDT3306A_TP_VALID_HIGH)
b63b36fa
FR		 267 val |= 0x02;
268
269 ret = lgdt3306a_write_reg(state, 0x0070, val);
270 lg_chkerr(ret);
271
272fail:
273 return ret;
274}
275
276static int lgdt3306a_mpeg_tristate(struct lgdt3306a_state *state,
277 int mode)
278{
279 u8 val;
280 int ret;
281
097117ca 282 dbg_info("(%d)\n", mode);
b63b36fa 283
8e8cd34e 284 if (mode) {
b63b36fa
FR		 285 ret = lgdt3306a_read_reg(state, 0x0070, &val);
286 if (lg_chkerr(ret))
287 goto fail;
4937ba94 288 val &= ~0xa8; /* Tristate bus; TPOUTEN=0x80, TPCLKOUTEN=0x20, TPDATAOUTEN=0x08 */
b63b36fa
FR		 289 ret = lgdt3306a_write_reg(state, 0x0070, val);
290 if (lg_chkerr(ret))
291 goto fail;
292
8e8cd34e 293 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 1); /* AGCIFOUTENB=0x40; 1=Disable IFAGC pin */
b63b36fa
FR		 294 if (lg_chkerr(ret))
295 goto fail;
296
297 } else {
8e8cd34e 298 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 0); /* enable IFAGC pin */
b63b36fa
FR		 299 if (lg_chkerr(ret))
300 goto fail;
301
302 ret = lgdt3306a_read_reg(state, 0x0070, &val);
303 if (lg_chkerr(ret))
304 goto fail;
305
4937ba94 306 val |= 0xa8; /* enable bus */
b63b36fa
FR		 307 ret = lgdt3306a_write_reg(state, 0x0070, val);
308 if (lg_chkerr(ret))
309 goto fail;
310 }
311
312fail:
313 return ret;
314}
315
8e8cd34e 316static int lgdt3306a_ts_bus_ctrl(struct dvb_frontend *fe, int acquire)
b63b36fa
FR		 317{
318 struct lgdt3306a_state *state = fe->demodulator_priv;
319
097117ca 320 dbg_info("acquire=%d\n", acquire);
b63b36fa
FR		 321
322 return lgdt3306a_mpeg_tristate(state, acquire ? 0 : 1);
323
324}
325
326static int lgdt3306a_power(struct lgdt3306a_state *state,
327 int mode)
328{
329 int ret;
330
097117ca 331 dbg_info("(%d)\n", mode);
b63b36fa 332
8e8cd34e
MIK		 333 if (mode == 0) {
334 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0); /* into reset */
b63b36fa
FR		 335 if (lg_chkerr(ret))
336 goto fail;
337
8e8cd34e 338 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 0); /* power down */
b63b36fa
FR		 339 if (lg_chkerr(ret))
340 goto fail;
341
342 } else {
8e8cd34e 343 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1); /* out of reset */
b63b36fa
FR		 344 if (lg_chkerr(ret))
345 goto fail;
346
8e8cd34e 347 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 1); /* power up */
b63b36fa
FR		 348 if (lg_chkerr(ret))
349 goto fail;
350 }
351
352#ifdef DBG_DUMP
353 lgdt3306a_DumpAllRegs(state);
354#endif
355fail:
356 return ret;
357}
358
359
360static int lgdt3306a_set_vsb(struct lgdt3306a_state *state)
361{
362 u8 val;
363 int ret;
364
097117ca 365 dbg_info("\n");
b63b36fa 366
8e8cd34e 367 /* 0. Spectrum inversion detection manual; spectrum inverted */
b63b36fa 368 ret = lgdt3306a_read_reg(state, 0x0002, &val);
4937ba94 369 val &= 0xf7; /* SPECINVAUTO Off */
8e8cd34e 370 val |= 0x04; /* SPECINV On */
b63b36fa
FR		 371 ret = lgdt3306a_write_reg(state, 0x0002, val);
372 if (lg_chkerr(ret))
373 goto fail;
374
8e8cd34e 375 /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
b63b36fa
FR		 376 ret = lgdt3306a_write_reg(state, 0x0008, 0x80);
377 if (lg_chkerr(ret))
378 goto fail;
379
8e8cd34e 380 /* 2. Bandwidth mode for VSB(6MHz) */
b63b36fa 381 ret = lgdt3306a_read_reg(state, 0x0009, &val);
4937ba94
MCC		 382 val &= 0xe3;
383 val |= 0x0c; /* STDOPDETTMODE[2:0]=3 */
b63b36fa
FR		 384 ret = lgdt3306a_write_reg(state, 0x0009, val);
385 if (lg_chkerr(ret))
386 goto fail;
387
8e8cd34e 388 /* 3. QAM mode detection mode(None) */
b63b36fa 389 ret = lgdt3306a_read_reg(state, 0x0009, &val);
4937ba94 390 val &= 0xfc; /* STDOPDETCMODE[1:0]=0 */
b63b36fa
FR		 391 ret = lgdt3306a_write_reg(state, 0x0009, val);
392 if (lg_chkerr(ret))
393 goto fail;
394
8e8cd34e 395 /* 4. ADC sampling frequency rate(2x sampling) */
4937ba94
MCC		 396 ret = lgdt3306a_read_reg(state, 0x000d, &val);
397 val &= 0xbf; /* SAMPLING4XFEN=0 */
398 ret = lgdt3306a_write_reg(state, 0x000d, val);
b63b36fa
FR		 399 if (lg_chkerr(ret))
400 goto fail;
401
8e8cd34e
MIK		 402#if 0
403 /* FGR - disable any AICC filtering, testing only */
404
b63b36fa
FR		 405 ret = lgdt3306a_write_reg(state, 0x0024, 0x00);
406 if (lg_chkerr(ret))
407 goto fail;
408
8e8cd34e 409 /* AICCFIXFREQ0 NT N-1(Video rejection) */
4937ba94
MCC		 410 ret = lgdt3306a_write_reg(state, 0x002e, 0x00);
411 ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
b63b36fa
FR		 412 ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
413
8e8cd34e 414 /* AICCFIXFREQ1 NT N-1(Audio rejection) */
4937ba94
MCC		 415 ret = lgdt3306a_write_reg(state, 0x002b, 0x00);
416 ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
417 ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
b63b36fa 418
8e8cd34e 419 /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
b63b36fa
FR		 420 ret = lgdt3306a_write_reg(state, 0x0028, 0x00);
421 ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
4937ba94 422 ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
b63b36fa 423
8e8cd34e 424 /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
b63b36fa
FR		 425 ret = lgdt3306a_write_reg(state, 0x0025, 0x00);
426 ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
427 ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
428
8e8cd34e
MIK		 429#else
430 /* FGR - this works well for HVR-1955,1975 */
431
432 /* 5. AICCOPMODE NT N-1 Adj. */
b63b36fa
FR		 433 ret = lgdt3306a_write_reg(state, 0x0024, 0x5A);
434 if (lg_chkerr(ret))
435 goto fail;
436
8e8cd34e 437 /* AICCFIXFREQ0 NT N-1(Video rejection) */
4937ba94
MCC		 438 ret = lgdt3306a_write_reg(state, 0x002e, 0x5A);
439 ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
b63b36fa
FR		 440 ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
441
8e8cd34e 442 /* AICCFIXFREQ1 NT N-1(Audio rejection) */
4937ba94
MCC		 443 ret = lgdt3306a_write_reg(state, 0x002b, 0x36);
444 ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
445 ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
b63b36fa 446
8e8cd34e 447 /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
b63b36fa
FR		 448 ret = lgdt3306a_write_reg(state, 0x0028, 0x2A);
449 ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
4937ba94 450 ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
b63b36fa 451
8e8cd34e 452 /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
b63b36fa
FR		 453 ret = lgdt3306a_write_reg(state, 0x0025, 0x06);
454 ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
455 ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
456#endif
457
4937ba94
MCC		 458 ret = lgdt3306a_read_reg(state, 0x001e, &val);
459 val &= 0x0f;
460 val |= 0xa0;
461 ret = lgdt3306a_write_reg(state, 0x001e, val);
b63b36fa
FR		 462
463 ret = lgdt3306a_write_reg(state, 0x0022, 0x08);
464
465 ret = lgdt3306a_write_reg(state, 0x0023, 0xFF);
466
4937ba94
MCC		 467 ret = lgdt3306a_read_reg(state, 0x211f, &val);
468 val &= 0xef;
469 ret = lgdt3306a_write_reg(state, 0x211f, val);
b63b36fa
FR		 470
471 ret = lgdt3306a_write_reg(state, 0x2173, 0x01);
472
473 ret = lgdt3306a_read_reg(state, 0x1061, &val);
4937ba94 474 val &= 0xf8;
b63b36fa
FR		 475 val |= 0x04;
476 ret = lgdt3306a_write_reg(state, 0x1061, val);
477
4937ba94
MCC		 478 ret = lgdt3306a_read_reg(state, 0x103d, &val);
479 val &= 0xcf;
480 ret = lgdt3306a_write_reg(state, 0x103d, val);
b63b36fa
FR		 481
482 ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
483
484 ret = lgdt3306a_read_reg(state, 0x2141, &val);
4937ba94 485 val &= 0x3f;
b63b36fa
FR		 486 ret = lgdt3306a_write_reg(state, 0x2141, val);
487
488 ret = lgdt3306a_read_reg(state, 0x2135, &val);
4937ba94 489 val &= 0x0f;
b63b36fa
FR		 490 val |= 0x70;
491 ret = lgdt3306a_write_reg(state, 0x2135, val);
492
493 ret = lgdt3306a_read_reg(state, 0x0003, &val);
4937ba94 494 val &= 0xf7;
b63b36fa
FR		 495 ret = lgdt3306a_write_reg(state, 0x0003, val);
496
4937ba94
MCC		 497 ret = lgdt3306a_read_reg(state, 0x001c, &val);
498 val &= 0x7f;
499 ret = lgdt3306a_write_reg(state, 0x001c, val);
b63b36fa 500
8e8cd34e 501 /* 6. EQ step size */
b63b36fa 502 ret = lgdt3306a_read_reg(state, 0x2179, &val);
4937ba94 503 val &= 0xf8;
b63b36fa
FR		 504 ret = lgdt3306a_write_reg(state, 0x2179, val);
505
4937ba94
MCC		 506 ret = lgdt3306a_read_reg(state, 0x217a, &val);
507 val &= 0xf8;
508 ret = lgdt3306a_write_reg(state, 0x217a, val);
b63b36fa 509
8e8cd34e 510 /* 7. Reset */
b63b36fa
FR		 511 ret = lgdt3306a_soft_reset(state);
512 if (lg_chkerr(ret))
513 goto fail;
514
097117ca 515 dbg_info("complete\n");
b63b36fa
FR		 516fail:
517 return ret;
518}
519
520static int lgdt3306a_set_qam(struct lgdt3306a_state *state, int modulation)
521{
522 u8 val;
523 int ret;
524
097117ca 525 dbg_info("modulation=%d\n", modulation);
b63b36fa 526
8e8cd34e 527 /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
b63b36fa
FR		 528 ret = lgdt3306a_write_reg(state, 0x0008, 0x08);
529 if (lg_chkerr(ret))
530 goto fail;
531
8e8cd34e 532 /* 1a. Spectrum inversion detection to Auto */
b63b36fa 533 ret = lgdt3306a_read_reg(state, 0x0002, &val);
4937ba94 534 val &= 0xfb; /* SPECINV Off */
8e8cd34e 535 val |= 0x08; /* SPECINVAUTO On */
b63b36fa
FR		 536 ret = lgdt3306a_write_reg(state, 0x0002, val);
537 if (lg_chkerr(ret))
538 goto fail;
539
8e8cd34e 540 /* 2. Bandwidth mode for QAM */
b63b36fa 541 ret = lgdt3306a_read_reg(state, 0x0009, &val);
4937ba94 542 val &= 0xe3; /* STDOPDETTMODE[2:0]=0 VSB Off */
b63b36fa
FR		 543 ret = lgdt3306a_write_reg(state, 0x0009, val);
544 if (lg_chkerr(ret))
545 goto fail;
546
8e8cd34e 547 /* 3. : 64QAM/256QAM detection(manual, auto) */
b63b36fa 548 ret = lgdt3306a_read_reg(state, 0x0009, &val);
4937ba94 549 val &= 0xfc;
8e8cd34e 550 val |= 0x02; /* STDOPDETCMODE[1:0]=1=Manual 2=Auto */
b63b36fa
FR		 551 ret = lgdt3306a_write_reg(state, 0x0009, val);
552 if (lg_chkerr(ret))
553 goto fail;
554
8e8cd34e 555 /* 3a. : 64QAM/256QAM selection for manual */
b63b36fa 556 ret = lgdt3306a_read_reg(state, 0x101a, &val);
4937ba94 557 val &= 0xf8;
8e8cd34e
MIK		 558 if (modulation == QAM_64)
559 val |= 0x02; /* QMDQMODE[2:0]=2=QAM64 */
560 else
561 val |= 0x04; /* QMDQMODE[2:0]=4=QAM256 */
562
b63b36fa
FR		 563 ret = lgdt3306a_write_reg(state, 0x101a, val);
564 if (lg_chkerr(ret))
565 goto fail;
566
8e8cd34e 567 /* 4. ADC sampling frequency rate(4x sampling) */
4937ba94
MCC		 568 ret = lgdt3306a_read_reg(state, 0x000d, &val);
569 val &= 0xbf;
8e8cd34e 570 val |= 0x40; /* SAMPLING4XFEN=1 */
4937ba94 571 ret = lgdt3306a_write_reg(state, 0x000d, val);
b63b36fa
FR		 572 if (lg_chkerr(ret))
573 goto fail;
574
8e8cd34e 575 /* 5. No AICC operation in QAM mode */
b63b36fa
FR		 576 ret = lgdt3306a_read_reg(state, 0x0024, &val);
577 val &= 0x00;
578 ret = lgdt3306a_write_reg(state, 0x0024, val);
579 if (lg_chkerr(ret))
580 goto fail;
581
8e8cd34e 582 /* 6. Reset */
b63b36fa
FR		 583 ret = lgdt3306a_soft_reset(state);
584 if (lg_chkerr(ret))
585 goto fail;
586
097117ca 587 dbg_info("complete\n");
b63b36fa
FR		 588fail:
589 return ret;
590}
591
592static int lgdt3306a_set_modulation(struct lgdt3306a_state *state,
593 struct dtv_frontend_properties *p)
594{
595 int ret;
596
097117ca 597 dbg_info("\n");
b63b36fa
FR		 598
599 switch (p->modulation) {
600 case VSB_8:
601 ret = lgdt3306a_set_vsb(state);
602 break;
603 case QAM_64:
604 ret = lgdt3306a_set_qam(state, QAM_64);
605 break;
606 case QAM_256:
607 ret = lgdt3306a_set_qam(state, QAM_256);
608 break;
609 default:
610 return -EINVAL;
611 }
612 if (lg_chkerr(ret))
613 goto fail;
614
615 state->current_modulation = p->modulation;
616
617fail:
618 return ret;
619}
620
621/* ------------------------------------------------------------------------ */
622
623static int lgdt3306a_agc_setup(struct lgdt3306a_state *state,
624 struct dtv_frontend_properties *p)
625{
8e8cd34e 626 /* TODO: anything we want to do here??? */
097117ca 627 dbg_info("\n");
b63b36fa
FR		 628
629 switch (p->modulation) {
630 case VSB_8:
631 break;
632 case QAM_64:
633 case QAM_256:
634 break;
635 default:
636 return -EINVAL;
637 }
638 return 0;
639}
640
641/* ------------------------------------------------------------------------ */
642
643static int lgdt3306a_set_inversion(struct lgdt3306a_state *state,
644 int inversion)
645{
646 int ret;
647
097117ca 648 dbg_info("(%d)\n", inversion);
b63b36fa 649
8e8cd34e 650 ret = lgdt3306a_set_reg_bit(state, 0x0002, 2, inversion ? 1 : 0);
b63b36fa
FR		 651 return ret;
652}
653
654static int lgdt3306a_set_inversion_auto(struct lgdt3306a_state *state,
655 int enabled)
656{
657 int ret;
658
097117ca 659 dbg_info("(%d)\n", enabled);
b63b36fa 660
8e8cd34e
MIK		 661 /* 0=Manual 1=Auto(QAM only) */
662 ret = lgdt3306a_set_reg_bit(state, 0x0002, 3, enabled);/* SPECINVAUTO=0x04 */
b63b36fa
FR		 663 return ret;
664}
665
666static int lgdt3306a_spectral_inversion(struct lgdt3306a_state *state,
667 struct dtv_frontend_properties *p,
668 int inversion)
669{
670 int ret = 0;
671
097117ca 672 dbg_info("(%d)\n", inversion);
8e8cd34e
MIK		 673#if 0
674/* FGR - spectral_inversion defaults already set for VSB and QAM; can enable later if desired */
b63b36fa
FR		 675
676 ret = lgdt3306a_set_inversion(state, inversion);
677
678 switch (p->modulation) {
679 case VSB_8:
8e8cd34e 680 ret = lgdt3306a_set_inversion_auto(state, 0); /* Manual only for VSB */
b63b36fa
FR		 681 break;
682 case QAM_64:
683 case QAM_256:
8e8cd34e 684 ret = lgdt3306a_set_inversion_auto(state, 1); /* Auto ok for QAM */
b63b36fa
FR		 685 break;
686 default:
687 ret = -EINVAL;
688 }
689#endif
690 return ret;
691}
692
693static int lgdt3306a_set_if(struct lgdt3306a_state *state,
694 struct dtv_frontend_properties *p)
695{
696 int ret;
697 u16 if_freq_khz;
698 u8 nco1, nco2;
699
700 switch (p->modulation) {
701 case VSB_8:
702 if_freq_khz = state->cfg->vsb_if_khz;
703 break;
704 case QAM_64:
705 case QAM_256:
706 if_freq_khz = state->cfg->qam_if_khz;
707 break;
708 default:
709 return -EINVAL;
710 }
711
8e8cd34e 712 switch (if_freq_khz) {
b63b36fa 713 default:
097117ca 714 pr_warn("IF=%d KHz is not supportted, 3250 assumed\n", if_freq_khz);
8e8cd34e 715 /* fallthrough */
34a5a2f8 716 case 3250: /* 3.25Mhz */
b63b36fa
FR		 717 nco1 = 0x34;
718 nco2 = 0x00;
719 break;
34a5a2f8 720 case 3500: /* 3.50Mhz */
b63b36fa
FR		 721 nco1 = 0x38;
722 nco2 = 0x00;
723 break;
34a5a2f8 724 case 4000: /* 4.00Mhz */
b63b36fa
FR		 725 nco1 = 0x40;
726 nco2 = 0x00;
727 break;
34a5a2f8 728 case 5000: /* 5.00Mhz */
b63b36fa
FR		 729 nco1 = 0x50;
730 nco2 = 0x00;
731 break;
8e8cd34e 732 case 5380: /* 5.38Mhz */
b63b36fa
FR		 733 nco1 = 0x56;
734 nco2 = 0x14;
735 break;
736 }
737 ret = lgdt3306a_write_reg(state, 0x0010, nco1);
ee0133ee
MCC		 738 if (ret)
739 return ret;
b63b36fa 740 ret = lgdt3306a_write_reg(state, 0x0011, nco2);
ee0133ee
MCC		 741 if (ret)
742 return ret;
b63b36fa 743
097117ca 744 dbg_info("if_freq=%d KHz->[%04x]\n", if_freq_khz, nco1<<8 | nco2);
b63b36fa
FR		 745
746 return 0;
747}
748
749/* ------------------------------------------------------------------------ */
750
751static int lgdt3306a_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
752{
753 struct lgdt3306a_state *state = fe->demodulator_priv;
754
8e8cd34e 755 if (state->cfg->deny_i2c_rptr) {
097117ca 756 dbg_info("deny_i2c_rptr=%d\n", state->cfg->deny_i2c_rptr);
b63b36fa
FR		 757 return 0;
758 }
097117ca 759 dbg_info("(%d)\n", enable);
b63b36fa 760
8e8cd34e 761 return lgdt3306a_set_reg_bit(state, 0x0002, 7, enable ? 0 : 1); /* NI2CRPTEN=0x80 */
b63b36fa
FR		 762}
763
764static int lgdt3306a_sleep(struct lgdt3306a_state *state)
765{
766 int ret;
767
097117ca 768 dbg_info("\n");
8e8cd34e 769 state->current_frequency = -1; /* force re-tune, when we wake */
b63b36fa 770
8e8cd34e 771 ret = lgdt3306a_mpeg_tristate(state, 1); /* disable data bus */
b63b36fa
FR		 772 if (lg_chkerr(ret))
773 goto fail;
774
8e8cd34e 775 ret = lgdt3306a_power(state, 0); /* power down */
b63b36fa
FR		 776 lg_chkerr(ret);
777
778fail:
779 return 0;
780}
781
782static int lgdt3306a_fe_sleep(struct dvb_frontend *fe)
783{
784 struct lgdt3306a_state *state = fe->demodulator_priv;
785
786 return lgdt3306a_sleep(state);
787}
788
789static int lgdt3306a_init(struct dvb_frontend *fe)
790{
791 struct lgdt3306a_state *state = fe->demodulator_priv;
792 u8 val;
793 int ret;
794
097117ca 795 dbg_info("\n");
b63b36fa 796
8e8cd34e
MIK		 797 /* 1. Normal operation mode */
798 ret = lgdt3306a_set_reg_bit(state, 0x0001, 0, 1); /* SIMFASTENB=0x01 */
b63b36fa
FR		 799 if (lg_chkerr(ret))
800 goto fail;
801
8e8cd34e 802 /* 2. Spectrum inversion auto detection (Not valid for VSB) */
b63b36fa
FR		 803 ret = lgdt3306a_set_inversion_auto(state, 0);
804 if (lg_chkerr(ret))
805 goto fail;
806
8e8cd34e 807 /* 3. Spectrum inversion(According to the tuner configuration) */
b63b36fa
FR		 808 ret = lgdt3306a_set_inversion(state, 1);
809 if (lg_chkerr(ret))
810 goto fail;
811
8e8cd34e
MIK		 812 /* 4. Peak-to-peak voltage of ADC input signal */
813 ret = lgdt3306a_set_reg_bit(state, 0x0004, 7, 1); /* ADCSEL1V=0x80=1Vpp; 0x00=2Vpp */
b63b36fa
FR		 814 if (lg_chkerr(ret))
815 goto fail;
816
8e8cd34e
MIK		 817 /* 5. ADC output data capture clock phase */
818 ret = lgdt3306a_set_reg_bit(state, 0x0004, 2, 0); /* 0=same phase as ADC clock */
b63b36fa
FR		 819 if (lg_chkerr(ret))
820 goto fail;
821
8e8cd34e
MIK		 822 /* 5a. ADC sampling clock source */
823 ret = lgdt3306a_set_reg_bit(state, 0x0004, 3, 0); /* ADCCLKPLLSEL=0x08; 0=use ext clock, not PLL */
b63b36fa
FR		 824 if (lg_chkerr(ret))
825 goto fail;
826
8e8cd34e
MIK		 827 /* 6. Automatic PLL set */
828 ret = lgdt3306a_set_reg_bit(state, 0x0005, 6, 0); /* PLLSETAUTO=0x40; 0=off */
b63b36fa
FR		 829 if (lg_chkerr(ret))
830 goto fail;
831
8e8cd34e
MIK		 832 if (state->cfg->xtalMHz == 24) { /* 24MHz */
833 /* 7. Frequency for PLL output(0x2564 for 192MHz for 24MHz) */
b63b36fa
FR		 834 ret = lgdt3306a_read_reg(state, 0x0005, &val);
835 if (lg_chkerr(ret))
836 goto fail;
4937ba94 837 val &= 0xc0;
b63b36fa
FR		 838 val |= 0x25;
839 ret = lgdt3306a_write_reg(state, 0x0005, val);
840 if (lg_chkerr(ret))
841 goto fail;
842 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
843 if (lg_chkerr(ret))
844 goto fail;
845
8e8cd34e 846 /* 8. ADC sampling frequency(0x180000 for 24MHz sampling) */
4937ba94 847 ret = lgdt3306a_read_reg(state, 0x000d, &val);
b63b36fa
FR		 848 if (lg_chkerr(ret))
849 goto fail;
4937ba94 850 val &= 0xc0;
b63b36fa 851 val |= 0x18;
4937ba94 852 ret = lgdt3306a_write_reg(state, 0x000d, val);
b63b36fa
FR		 853 if (lg_chkerr(ret))
854 goto fail;
855
8e8cd34e
MIK		 856 } else if (state->cfg->xtalMHz == 25) { /* 25MHz */
857 /* 7. Frequency for PLL output */
b63b36fa
FR		 858 ret = lgdt3306a_read_reg(state, 0x0005, &val);
859 if (lg_chkerr(ret))
860 goto fail;
4937ba94 861 val &= 0xc0;
b63b36fa
FR		 862 val |= 0x25;
863 ret = lgdt3306a_write_reg(state, 0x0005, val);
864 if (lg_chkerr(ret))
865 goto fail;
866 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
867 if (lg_chkerr(ret))
868 goto fail;
869
8e8cd34e 870 /* 8. ADC sampling frequency(0x190000 for 25MHz sampling) */
4937ba94 871 ret = lgdt3306a_read_reg(state, 0x000d, &val);
b63b36fa
FR		 872 if (lg_chkerr(ret))
873 goto fail;
4937ba94 874 val &= 0xc0;
b63b36fa 875 val |= 0x19;
4937ba94 876 ret = lgdt3306a_write_reg(state, 0x000d, val);
b63b36fa
FR		 877 if (lg_chkerr(ret))
878 goto fail;
879 } else {
097117ca 880 pr_err("Bad xtalMHz=%d\n", state->cfg->xtalMHz);
b63b36fa 881 }
8e8cd34e 882#if 0
4937ba94
MCC		 883 ret = lgdt3306a_write_reg(state, 0x000e, 0x00);
884 ret = lgdt3306a_write_reg(state, 0x000f, 0x00);
8e8cd34e 885#endif
b63b36fa 886
8e8cd34e
MIK		 887 /* 9. Center frequency of input signal of ADC */
888 ret = lgdt3306a_write_reg(state, 0x0010, 0x34); /* 3.25MHz */
889 ret = lgdt3306a_write_reg(state, 0x0011, 0x00);
b63b36fa 890
8e8cd34e
MIK		 891 /* 10. Fixed gain error value */
892 ret = lgdt3306a_write_reg(state, 0x0014, 0); /* gain error=0 */
b63b36fa 893
8e8cd34e 894 /* 10a. VSB TR BW gear shift initial step */
4937ba94
MCC		 895 ret = lgdt3306a_read_reg(state, 0x103c, &val);
896 val &= 0x0f;
8e8cd34e 897 val |= 0x20; /* SAMGSAUTOSTL_V[3:0] = 2 */
4937ba94 898 ret = lgdt3306a_write_reg(state, 0x103c, val);
b63b36fa 899
8e8cd34e 900 /* 10b. Timing offset calibration in low temperature for VSB */
4937ba94
MCC		 901 ret = lgdt3306a_read_reg(state, 0x103d, &val);
902 val &= 0xfc;
b63b36fa 903 val |= 0x03;
4937ba94 904 ret = lgdt3306a_write_reg(state, 0x103d, val);
b63b36fa 905
8e8cd34e 906 /* 10c. Timing offset calibration in low temperature for QAM */
b63b36fa 907 ret = lgdt3306a_read_reg(state, 0x1036, &val);
4937ba94
MCC		 908 val &= 0xf0;
909 val |= 0x0c;
b63b36fa
FR		 910 ret = lgdt3306a_write_reg(state, 0x1036, val);
911
8e8cd34e 912 /* 11. Using the imaginary part of CIR in CIR loading */
4937ba94
MCC		 913 ret = lgdt3306a_read_reg(state, 0x211f, &val);
914 val &= 0xef; /* do not use imaginary of CIR */
915 ret = lgdt3306a_write_reg(state, 0x211f, val);
b63b36fa 916
8e8cd34e 917 /* 12. Control of no signal detector function */
b63b36fa 918 ret = lgdt3306a_read_reg(state, 0x2849, &val);
4937ba94 919 val &= 0xef; /* NOUSENOSIGDET=0, enable no signal detector */
b63b36fa
FR		 920 ret = lgdt3306a_write_reg(state, 0x2849, val);
921
8e8cd34e 922 /* FGR - put demod in some known mode */
b63b36fa
FR		 923 ret = lgdt3306a_set_vsb(state);
924
8e8cd34e 925 /* 13. TP stream format */
b63b36fa
FR		 926 ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
927
8e8cd34e 928 /* 14. disable output buses */
b63b36fa
FR		 929 ret = lgdt3306a_mpeg_tristate(state, 1);
930
8e8cd34e 931 /* 15. Sleep (in reset) */
b63b36fa
FR		 932 ret = lgdt3306a_sleep(state);
933 lg_chkerr(ret);
934
935fail:
936 return ret;
937}
938
939static int lgdt3306a_set_parameters(struct dvb_frontend *fe)
940{
941 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
942 struct lgdt3306a_state *state = fe->demodulator_priv;
943 int ret;
944
097117ca 945 dbg_info("(%d, %d)\n", p->frequency, p->modulation);
b63b36fa 946
8e8cd34e
MIK		 947 if (state->current_frequency == p->frequency &&
948 state->current_modulation == p->modulation) {
097117ca 949 dbg_info(" (already set, skipping ...)\n");
b63b36fa
FR		 950 return 0;
951 }
952 state->current_frequency = -1;
953 state->current_modulation = -1;
954
8e8cd34e 955 ret = lgdt3306a_power(state, 1); /* power up */
b63b36fa
FR		 956 if (lg_chkerr(ret))
957 goto fail;
958
959 if (fe->ops.tuner_ops.set_params) {
960 ret = fe->ops.tuner_ops.set_params(fe);
961 if (fe->ops.i2c_gate_ctrl)
962 fe->ops.i2c_gate_ctrl(fe, 0);
8e8cd34e
MIK		 963#if 0
964 if (lg_chkerr(ret))
965 goto fail;
966 state->current_frequency = p->frequency;
967#endif
b63b36fa
FR		 968 }
969
970 ret = lgdt3306a_set_modulation(state, p);
971 if (lg_chkerr(ret))
972 goto fail;
973
974 ret = lgdt3306a_agc_setup(state, p);
975 if (lg_chkerr(ret))
976 goto fail;
977
978 ret = lgdt3306a_set_if(state, p);
979 if (lg_chkerr(ret))
980 goto fail;
981
982 ret = lgdt3306a_spectral_inversion(state, p,
8e8cd34e 983 state->cfg->spectral_inversion ? 1 : 0);
b63b36fa
FR		 984 if (lg_chkerr(ret))
985 goto fail;
986
987 ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
988 if (lg_chkerr(ret))
989 goto fail;
990
991 ret = lgdt3306a_mpeg_mode_polarity(state,
992 state->cfg->tpclk_edge,
993 state->cfg->tpvalid_polarity);
994 if (lg_chkerr(ret))
995 goto fail;
996
8e8cd34e 997 ret = lgdt3306a_mpeg_tristate(state, 0); /* enable data bus */
b63b36fa
FR		 998 if (lg_chkerr(ret))
999 goto fail;
1000
1001 ret = lgdt3306a_soft_reset(state);
1002 if (lg_chkerr(ret))
1003 goto fail;
1004
1005#ifdef DBG_DUMP
1006 lgdt3306a_DumpAllRegs(state);
1007#endif
1008 state->current_frequency = p->frequency;
1009fail:
1010 return ret;
1011}
1012
1013static int lgdt3306a_get_frontend(struct dvb_frontend *fe)
1014{
1015 struct lgdt3306a_state *state = fe->demodulator_priv;
1016 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1017
097117ca 1018 dbg_info("(%u, %d)\n", state->current_frequency, state->current_modulation);
b63b36fa
FR		 1019
1020 p->modulation = state->current_modulation;
1021 p->frequency = state->current_frequency;
1022 return 0;
1023}
1024
1025static enum dvbfe_algo lgdt3306a_get_frontend_algo(struct dvb_frontend *fe)
1026{
1027#if 1
1028 return DVBFE_ALGO_CUSTOM;
1029#else
1030 return DVBFE_ALGO_HW;
1031#endif
1032}
1033
1034/* ------------------------------------------------------------------------ */
ee0133ee 1035static int lgdt3306a_monitor_vsb(struct lgdt3306a_state *state)
b63b36fa
FR		 1036{
1037 u8 val;
1038 int ret;
8e8cd34e
MIK		 1039 u8 snrRef, maxPowerMan, nCombDet;
1040 u16 fbDlyCir;
b63b36fa 1041
4937ba94 1042 ret = lgdt3306a_read_reg(state, 0x21a1, &val);
ee0133ee
MCC		 1043 if (ret)
1044 return ret;
4937ba94 1045 snrRef = val & 0x3f;
b63b36fa
FR		 1046
1047 ret = lgdt3306a_read_reg(state, 0x2185, &maxPowerMan);
ee0133ee
MCC		 1048 if (ret)
1049 return ret;
b63b36fa
FR		 1050
1051 ret = lgdt3306a_read_reg(state, 0x2191, &val);
ee0133ee
MCC		 1052 if (ret)
1053 return ret;
b63b36fa
FR		 1054 nCombDet = (val & 0x80) >> 7;
1055
1056 ret = lgdt3306a_read_reg(state, 0x2180, &val);
ee0133ee
MCC		 1057 if (ret)
1058 return ret;
b63b36fa 1059 fbDlyCir = (val & 0x03) << 8;
ee0133ee 1060
b63b36fa 1061 ret = lgdt3306a_read_reg(state, 0x2181, &val);
ee0133ee
MCC		 1062 if (ret)
1063 return ret;
b63b36fa
FR		 1064 fbDlyCir |= val;
1065
097117ca 1066 dbg_info("snrRef=%d maxPowerMan=0x%x nCombDet=%d fbDlyCir=0x%x\n",
b63b36fa
FR		 1067 snrRef, maxPowerMan, nCombDet, fbDlyCir);
1068
8e8cd34e 1069 /* Carrier offset sub loop bandwidth */
b63b36fa 1070 ret = lgdt3306a_read_reg(state, 0x1061, &val);
ee0133ee
MCC		 1071 if (ret)
1072 return ret;
4937ba94 1073 val &= 0xf8;
b63b36fa 1074 if ((snrRef > 18) && (maxPowerMan > 0x68) && (nCombDet == 0x01) && ((fbDlyCir == 0x03FF) || (fbDlyCir < 0x6C))) {
8e8cd34e
MIK		 1075 /* SNR is over 18dB and no ghosting */
1076 val |= 0x00; /* final bandwidth = 0 */
b63b36fa 1077 } else {
8e8cd34e 1078 val |= 0x04; /* final bandwidth = 4 */
b63b36fa
FR		 1079 }
1080 ret = lgdt3306a_write_reg(state, 0x1061, val);
ee0133ee
MCC		 1081 if (ret)
1082 return ret;
b63b36fa 1083
8e8cd34e 1084 /* Adjust Notch Filter */
b63b36fa 1085 ret = lgdt3306a_read_reg(state, 0x0024, &val);
ee0133ee
MCC		 1086 if (ret)
1087 return ret;
4937ba94 1088 val &= 0x0f;
8e8cd34e 1089 if (nCombDet == 0) { /* Turn on the Notch Filter */
b63b36fa
FR		 1090 val |= 0x50;
1091 }
1092 ret = lgdt3306a_write_reg(state, 0x0024, val);
ee0133ee
MCC		 1093 if (ret)
1094 return ret;
b63b36fa 1095
8e8cd34e 1096 /* VSB Timing Recovery output normalization */
4937ba94 1097 ret = lgdt3306a_read_reg(state, 0x103d, &val);
ee0133ee
MCC		 1098 if (ret)
1099 return ret;
4937ba94 1100 val &= 0xcf;
b63b36fa 1101 val |= 0x20;
4937ba94 1102 ret = lgdt3306a_write_reg(state, 0x103d, val);
ee0133ee
MCC		 1103
1104 return ret;
b63b36fa
FR		 1105}
1106
f883d603 1107static enum lgdt3306a_modulation lgdt3306a_check_oper_mode(struct lgdt3306a_state *state)
b63b36fa
FR		 1108{
1109 u8 val = 0;
1110 int ret;
1111
1112 ret = lgdt3306a_read_reg(state, 0x0081, &val);
ee0133ee
MCC		 1113 if (ret)
1114 goto err;
b63b36fa
FR		 1115
1116 if (val & 0x80) {
097117ca 1117 dbg_info("VSB\n");
8e8cd34e 1118 return LG3306_VSB;
b63b36fa 1119 }
c714efe4 1120 if (val & 0x08) {
4937ba94 1121 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
ee0133ee
MCC		 1122 if (ret)
1123 goto err;
b63b36fa
FR		 1124 val = val >> 2;
1125 if (val & 0x01) {
097117ca 1126 dbg_info("QAM256\n");
8e8cd34e 1127 return LG3306_QAM256;
b63b36fa 1128 }
b4e43e95
MCC		 1129 dbg_info("QAM64\n");
1130 return LG3306_QAM64;
b63b36fa 1131 }
ee0133ee 1132err:
097117ca 1133 pr_warn("UNKNOWN\n");
8e8cd34e 1134 return LG3306_UNKNOWN_MODE;
b63b36fa
FR		 1135}
1136
f883d603
MIK		 1137static enum lgdt3306a_lock_status lgdt3306a_check_lock_status(struct lgdt3306a_state *state,
1138 enum lgdt3306a_lock_check whatLock)
b63b36fa
FR		 1139{
1140 u8 val = 0;
1141 int ret;
f883d603
MIK		 1142 enum lgdt3306a_modulation modeOper;
1143 enum lgdt3306a_lock_status lockStatus;
b63b36fa
FR		 1144
1145 modeOper = LG3306_UNKNOWN_MODE;
1146
8e8cd34e
MIK		 1147 switch (whatLock) {
1148 case LG3306_SYNC_LOCK:
1149 {
4937ba94 1150 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
ee0133ee
MCC		 1151 if (ret)
1152 return ret;
8e8cd34e
MIK		 1153
1154 if ((val & 0x80) == 0x80)
1155 lockStatus = LG3306_LOCK;
1156 else
1157 lockStatus = LG3306_UNLOCK;
1158
097117ca 1159 dbg_info("SYNC_LOCK=%x\n", lockStatus);
8e8cd34e
MIK		 1160 break;
1161 }
1162 case LG3306_AGC_LOCK:
1163 {
1164 ret = lgdt3306a_read_reg(state, 0x0080, &val);
ee0133ee
MCC		 1165 if (ret)
1166 return ret;
8e8cd34e
MIK		 1167
1168 if ((val & 0x40) == 0x40)
1169 lockStatus = LG3306_LOCK;
1170 else
1171 lockStatus = LG3306_UNLOCK;
1172
097117ca 1173 dbg_info("AGC_LOCK=%x\n", lockStatus);
8e8cd34e
MIK		 1174 break;
1175 }
1176 case LG3306_TR_LOCK:
b63b36fa 1177 {
8e8cd34e
MIK		 1178 modeOper = lgdt3306a_check_oper_mode(state);
1179 if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
1180 ret = lgdt3306a_read_reg(state, 0x1094, &val);
ee0133ee
MCC		 1181 if (ret)
1182 return ret;
b63b36fa
FR		 1183
1184 if ((val & 0x80) == 0x80)
1185 lockStatus = LG3306_LOCK;
1186 else
1187 lockStatus = LG3306_UNLOCK;
8e8cd34e
MIK		 1188 } else
1189 lockStatus = LG3306_UNKNOWN_LOCK;
b63b36fa 1190
097117ca 1191 dbg_info("TR_LOCK=%x\n", lockStatus);
8e8cd34e
MIK		 1192 break;
1193 }
1194 case LG3306_FEC_LOCK:
1195 {
1196 modeOper = lgdt3306a_check_oper_mode(state);
1197 if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
b63b36fa 1198 ret = lgdt3306a_read_reg(state, 0x0080, &val);
ee0133ee
MCC		 1199 if (ret)
1200 return ret;
b63b36fa 1201
8e8cd34e 1202 if ((val & 0x10) == 0x10)
b63b36fa
FR		 1203 lockStatus = LG3306_LOCK;
1204 else
1205 lockStatus = LG3306_UNLOCK;
8e8cd34e
MIK		 1206 } else
1207 lockStatus = LG3306_UNKNOWN_LOCK;
b63b36fa 1208
097117ca 1209 dbg_info("FEC_LOCK=%x\n", lockStatus);
8e8cd34e
MIK		 1210 break;
1211 }
b63b36fa 1212
8e8cd34e
MIK		 1213 default:
1214 lockStatus = LG3306_UNKNOWN_LOCK;
097117ca 1215 pr_warn("UNKNOWN whatLock=%d\n", whatLock);
8e8cd34e 1216 break;
b63b36fa
FR		 1217 }
1218
8e8cd34e 1219 return lockStatus;
b63b36fa
FR		 1220}
1221
f883d603 1222static enum lgdt3306a_neverlock_status lgdt3306a_check_neverlock_status(struct lgdt3306a_state *state)
b63b36fa
FR		 1223{
1224 u8 val = 0;
1225 int ret;
f883d603 1226 enum lgdt3306a_neverlock_status lockStatus;
b63b36fa
FR		 1227
1228 ret = lgdt3306a_read_reg(state, 0x0080, &val);
ee0133ee
MCC		 1229 if (ret)
1230 return ret;
f883d603 1231 lockStatus = (enum lgdt3306a_neverlock_status)(val & 0x03);
b63b36fa 1232
097117ca 1233 dbg_info("NeverLock=%d", lockStatus);
b63b36fa 1234
8e8cd34e 1235 return lockStatus;
b63b36fa
FR		 1236}
1237
ee0133ee 1238static int lgdt3306a_pre_monitoring(struct lgdt3306a_state *state)
b63b36fa
FR		 1239{
1240 u8 val = 0;
1241 int ret;
1242 u8 currChDiffACQ, snrRef, mainStrong, aiccrejStatus;
1243
8e8cd34e 1244 /* Channel variation */
4937ba94 1245 ret = lgdt3306a_read_reg(state, 0x21bc, &currChDiffACQ);
ee0133ee
MCC		 1246 if (ret)
1247 return ret;
b63b36fa 1248
8e8cd34e 1249 /* SNR of Frame sync */
4937ba94 1250 ret = lgdt3306a_read_reg(state, 0x21a1, &val);
ee0133ee
MCC		 1251 if (ret)
1252 return ret;
4937ba94 1253 snrRef = val & 0x3f;
b63b36fa 1254
8e8cd34e 1255 /* Strong Main CIR */
b63b36fa 1256 ret = lgdt3306a_read_reg(state, 0x2199, &val);
ee0133ee
MCC		 1257 if (ret)
1258 return ret;
b63b36fa
FR		 1259 mainStrong = (val & 0x40) >> 6;
1260
1261 ret = lgdt3306a_read_reg(state, 0x0090, &val);
ee0133ee
MCC		 1262 if (ret)
1263 return ret;
4937ba94 1264 aiccrejStatus = (val & 0xf0) >> 4;
b63b36fa 1265
097117ca 1266 dbg_info("snrRef=%d mainStrong=%d aiccrejStatus=%d currChDiffACQ=0x%x\n",
b63b36fa
FR		 1267 snrRef, mainStrong, aiccrejStatus, currChDiffACQ);
1268
8e8cd34e
MIK		 1269#if 0
1270 if ((mainStrong == 0) && (currChDiffACQ > 0x70)) /* Dynamic ghost exists */
1271#endif
1272 if (mainStrong == 0) {
b63b36fa 1273 ret = lgdt3306a_read_reg(state, 0x2135, &val);
ee0133ee
MCC		 1274 if (ret)
1275 return ret;
4937ba94
MCC		 1276 val &= 0x0f;
1277 val |= 0xa0;
b63b36fa 1278 ret = lgdt3306a_write_reg(state, 0x2135, val);
ee0133ee
MCC		 1279 if (ret)
1280 return ret;
b63b36fa
FR		 1281
1282 ret = lgdt3306a_read_reg(state, 0x2141, &val);
ee0133ee
MCC		 1283 if (ret)
1284 return ret;
4937ba94 1285 val &= 0x3f;
b63b36fa
FR		 1286 val |= 0x80;
1287 ret = lgdt3306a_write_reg(state, 0x2141, val);
ee0133ee
MCC		 1288 if (ret)
1289 return ret;
b63b36fa
FR		 1290
1291 ret = lgdt3306a_write_reg(state, 0x2122, 0x70);
ee0133ee
MCC		 1292 if (ret)
1293 return ret;
8e8cd34e 1294 } else { /* Weak ghost or static channel */
b63b36fa 1295 ret = lgdt3306a_read_reg(state, 0x2135, &val);
ee0133ee
MCC		 1296 if (ret)
1297 return ret;
4937ba94 1298 val &= 0x0f;
b63b36fa
FR		 1299 val |= 0x70;
1300 ret = lgdt3306a_write_reg(state, 0x2135, val);
ee0133ee
MCC		 1301 if (ret)
1302 return ret;
b63b36fa
FR		 1303
1304 ret = lgdt3306a_read_reg(state, 0x2141, &val);
ee0133ee
MCC		 1305 if (ret)
1306 return ret;
4937ba94 1307 val &= 0x3f;
b63b36fa
FR		 1308 val |= 0x40;
1309 ret = lgdt3306a_write_reg(state, 0x2141, val);
ee0133ee
MCC		 1310 if (ret)
1311 return ret;
b63b36fa
FR		 1312
1313 ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
ee0133ee
MCC		 1314 if (ret)
1315 return ret;
b63b36fa 1316 }
ee0133ee 1317 return 0;
b63b36fa
FR		 1318}
1319
f883d603 1320static enum lgdt3306a_lock_status lgdt3306a_sync_lock_poll(struct lgdt3306a_state *state)
b63b36fa 1321{
f883d603 1322 enum lgdt3306a_lock_status syncLockStatus = LG3306_UNLOCK;
b63b36fa
FR		 1323 int i;
1324
1325 for (i = 0; i < 2; i++) {
1326 msleep(30);
1327
1328 syncLockStatus = lgdt3306a_check_lock_status(state, LG3306_SYNC_LOCK);
1329
1330 if (syncLockStatus == LG3306_LOCK) {
097117ca 1331 dbg_info("locked(%d)\n", i);
8e8cd34e 1332 return LG3306_LOCK;
b63b36fa
FR		 1333 }
1334 }
097117ca 1335 dbg_info("not locked\n");
8e8cd34e 1336 return LG3306_UNLOCK;
b63b36fa
FR		 1337}
1338
f883d603 1339static enum lgdt3306a_lock_status lgdt3306a_fec_lock_poll(struct lgdt3306a_state *state)
b63b36fa 1340{
f883d603 1341 enum lgdt3306a_lock_status FECLockStatus = LG3306_UNLOCK;
b63b36fa
FR		 1342 int i;
1343
1344 for (i = 0; i < 2; i++) {
1345 msleep(30);
1346
1347 FECLockStatus = lgdt3306a_check_lock_status(state, LG3306_FEC_LOCK);
1348
1349 if (FECLockStatus == LG3306_LOCK) {
097117ca 1350 dbg_info("locked(%d)\n", i);
8e8cd34e 1351 return FECLockStatus;
b63b36fa
FR		 1352 }
1353 }
097117ca 1354 dbg_info("not locked\n");
8e8cd34e 1355 return FECLockStatus;
b63b36fa
FR		 1356}
1357
f883d603 1358static enum lgdt3306a_neverlock_status lgdt3306a_neverlock_poll(struct lgdt3306a_state *state)
b63b36fa 1359{
f883d603 1360 enum lgdt3306a_neverlock_status NLLockStatus = LG3306_NL_FAIL;
b63b36fa
FR		 1361 int i;
1362
8e8cd34e 1363 for (i = 0; i < 5; i++) {
b63b36fa
FR		 1364 msleep(30);
1365
1366 NLLockStatus = lgdt3306a_check_neverlock_status(state);
1367
1368 if (NLLockStatus == LG3306_NL_LOCK) {
097117ca 1369 dbg_info("NL_LOCK(%d)\n", i);
8e8cd34e 1370 return NLLockStatus;
b63b36fa
FR		 1371 }
1372 }
097117ca 1373 dbg_info("NLLockStatus=%d\n", NLLockStatus);
8e8cd34e 1374 return NLLockStatus;
b63b36fa
FR		 1375}
1376
1377static u8 lgdt3306a_get_packet_error(struct lgdt3306a_state *state)
1378{
1379 u8 val;
1380 int ret;
1381
4937ba94 1382 ret = lgdt3306a_read_reg(state, 0x00fa, &val);
ee0133ee
MCC		 1383 if (ret)
1384 return ret;
b63b36fa 1385
8e8cd34e 1386 return val;
b63b36fa
FR		 1387}
1388
1389static u32 log10_x1000(u32 x)
1390{
8e8cd34e
MIK		 1391 static u32 valx_x10[] = { 10, 11, 13, 15, 17, 20, 25, 33, 41, 50, 59, 73, 87, 100 };
1392 static u32 log10x_x1000[] = { 0, 41, 114, 176, 230, 301, 398, 518, 613, 699, 771, 863, 939, 1000 };
1393 static u32 nelems = sizeof(valx_x10)/sizeof(valx_x10[0]);
a132fef8 1394 u32 diff_val, step_val, step_log10;
b63b36fa 1395 u32 log_val = 0;
8e8cd34e 1396 u32 i;
b63b36fa 1397
8e8cd34e
MIK		 1398 if (x <= 0)
1399 return -1000000; /* signal error */
b63b36fa 1400
b4e43e95
MCC		 1401 if (x == 10)
1402 return 0; /* log(1)=0 */
1403
8e8cd34e
MIK		 1404 if (x < 10) {
1405 while (x < 10) {
1406 x = x * 10;
b63b36fa
FR		 1407 log_val--;
1408 }
b4e43e95 1409 } else { /* x > 10 */
8e8cd34e
MIK		 1410 while (x >= 100) {
1411 x = x / 10;
b63b36fa
FR		 1412 log_val++;
1413 }
8e8cd34e 1414 }
b63b36fa
FR		 1415 log_val *= 1000;
1416
8e8cd34e
MIK		 1417 if (x == 10) /* was our input an exact multiple of 10 */
1418 return log_val; /* don't need to interpolate */
b63b36fa 1419
8e8cd34e
MIK		 1420 /* find our place on the log curve */
1421 for (i = 1; i < nelems; i++) {
1422 if (valx_x10[i] >= x)
1423 break;
b63b36fa 1424 }
a132fef8
MCC		 1425 if (i == nelems)
1426 return log_val + log10x_x1000[i - 1];
b63b36fa 1427
a132fef8
MCC		 1428 diff_val = x - valx_x10[i-1];
1429 step_val = valx_x10[i] - valx_x10[i - 1];
1430 step_log10 = log10x_x1000[i] - log10x_x1000[i - 1];
1431
1432 /* do a linear interpolation to get in-between values */
1433 return log_val + log10x_x1000[i - 1] +
1434 ((diff_val*step_log10) / step_val);
b63b36fa
FR		 1435}
1436
1437static u32 lgdt3306a_calculate_snr_x100(struct lgdt3306a_state *state)
1438{
34a5a2f8
MIK		 1439 u32 mse; /* Mean-Square Error */
1440 u32 pwr; /* Constelation power */
b63b36fa
FR		 1441 u32 snr_x100;
1442
4937ba94
MCC		 1443 mse = (read_reg(state, 0x00ec) << 8) |
1444 (read_reg(state, 0x00ed));
1445 pwr = (read_reg(state, 0x00e8) << 8) |
1446 (read_reg(state, 0x00e9));
b63b36fa
FR		 1447
1448 if (mse == 0) /* no signal */
1449 return 0;
1450
8e8cd34e 1451 snr_x100 = log10_x1000((pwr * 10000) / mse) - 3000;
097117ca 1452 dbg_info("mse=%u, pwr=%u, snr_x100=%d\n", mse, pwr, snr_x100);
b63b36fa
FR		 1453
1454 return snr_x100;
1455}
1456
f883d603 1457static enum lgdt3306a_lock_status lgdt3306a_vsb_lock_poll(struct lgdt3306a_state *state)
b63b36fa 1458{
e2c47fa7 1459 int ret;
8e8cd34e
MIK		 1460 u8 cnt = 0;
1461 u8 packet_error;
1462 u32 snr;
b63b36fa 1463
b1a88c71 1464 for (cnt = 0; cnt < 10; cnt++) {
b63b36fa 1465 if (lgdt3306a_sync_lock_poll(state) == LG3306_UNLOCK) {
097117ca 1466 dbg_info("no sync lock!\n");
8e8cd34e 1467 return LG3306_UNLOCK;
b1a88c71 1468 }
b63b36fa 1469
b1a88c71
MCC		 1470 msleep(20);
1471 ret = lgdt3306a_pre_monitoring(state);
1472 if (ret)
1473 break;
b63b36fa 1474
b1a88c71
MCC		 1475 packet_error = lgdt3306a_get_packet_error(state);
1476 snr = lgdt3306a_calculate_snr_x100(state);
1477 dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr);
b63b36fa 1478
b1a88c71
MCC		 1479 if ((snr >= 1500) && (packet_error < 0xff))
1480 return LG3306_LOCK;
b63b36fa 1481 }
b1a88c71
MCC		 1482
1483 dbg_info("not locked!\n");
8e8cd34e 1484 return LG3306_UNLOCK;
b63b36fa
FR		 1485}
1486
f883d603 1487static enum lgdt3306a_lock_status lgdt3306a_qam_lock_poll(struct lgdt3306a_state *state)
b63b36fa 1488{
b1a88c71 1489 u8 cnt;
b63b36fa
FR		 1490 u8 packet_error;
1491 u32 snr;
1492
b1a88c71 1493 for (cnt = 0; cnt < 10; cnt++) {
8e8cd34e 1494 if (lgdt3306a_fec_lock_poll(state) == LG3306_UNLOCK) {
097117ca 1495 dbg_info("no fec lock!\n");
8e8cd34e 1496 return LG3306_UNLOCK;
b1a88c71 1497 }
b63b36fa 1498
b1a88c71 1499 msleep(20);
b63b36fa 1500
b1a88c71
MCC		 1501 packet_error = lgdt3306a_get_packet_error(state);
1502 snr = lgdt3306a_calculate_snr_x100(state);
1503 dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr);
b63b36fa 1504
b1a88c71
MCC		 1505 if ((snr >= 1500) && (packet_error < 0xff))
1506 return LG3306_LOCK;
b63b36fa 1507 }
b1a88c71
MCC		 1508
1509 dbg_info("not locked!\n");
8e8cd34e 1510 return LG3306_UNLOCK;
b63b36fa
FR		 1511}
1512
1513static int lgdt3306a_read_status(struct dvb_frontend *fe, fe_status_t *status)
1514{
b63b36fa 1515 struct lgdt3306a_state *state = fe->demodulator_priv;
b63b36fa 1516 u16 strength = 0;
8e8cd34e
MIK		 1517 int ret = 0;
1518
b63b36fa
FR		 1519 if (fe->ops.tuner_ops.get_rf_strength) {
1520 ret = fe->ops.tuner_ops.get_rf_strength(fe, &strength);
8e8cd34e 1521 if (ret == 0) {
097117ca 1522 dbg_info("strength=%d\n", strength);
b63b36fa 1523 } else {
097117ca 1524 dbg_info("fe->ops.tuner_ops.get_rf_strength() failed\n");
b63b36fa
FR		 1525 }
1526 }
1527
1528 *status = 0;
8e8cd34e 1529 if (lgdt3306a_neverlock_poll(state) == LG3306_NL_LOCK) {
b63b36fa
FR		 1530 *status |= FE_HAS_SIGNAL;
1531 *status |= FE_HAS_CARRIER;
1532
1533 switch (state->current_modulation) {
1534 case QAM_256:
1535 case QAM_64:
8e8cd34e 1536 if (lgdt3306a_qam_lock_poll(state) == LG3306_LOCK) {
b63b36fa
FR		 1537 *status |= FE_HAS_VITERBI;
1538 *status |= FE_HAS_SYNC;
1539
1540 *status |= FE_HAS_LOCK;
1541 }
1542 break;
1543 case VSB_8:
8e8cd34e 1544 if (lgdt3306a_vsb_lock_poll(state) == LG3306_LOCK) {
b63b36fa
FR		 1545 *status |= FE_HAS_VITERBI;
1546 *status |= FE_HAS_SYNC;
1547
1548 *status |= FE_HAS_LOCK;
1549
ee0133ee 1550 ret = lgdt3306a_monitor_vsb(state);
b63b36fa
FR		 1551 }
1552 break;
1553 default:
1554 ret = -EINVAL;
1555 }
1556 }
1557 return ret;
1558}
1559
1560
1561static int lgdt3306a_read_snr(struct dvb_frontend *fe, u16 *snr)
1562{
1563 struct lgdt3306a_state *state = fe->demodulator_priv;
1564
1565 state->snr = lgdt3306a_calculate_snr_x100(state);
1566 /* report SNR in dB * 10 */
1567 *snr = state->snr/10;
1568
1569 return 0;
1570}
1571
1572static int lgdt3306a_read_signal_strength(struct dvb_frontend *fe,
1573 u16 *strength)
1574{
1575 /*
1576 * Calculate some sort of "strength" from SNR
1577 */
1578 struct lgdt3306a_state *state = fe->demodulator_priv;
34a5a2f8 1579 u16 snr; /* snr_x10 */
b63b36fa 1580 int ret;
8e8cd34e 1581 u32 ref_snr; /* snr*100 */
b63b36fa
FR		 1582 u32 str;
1583
1584 *strength = 0;
1585
1586 switch (state->current_modulation) {
1587 case VSB_8:
8e8cd34e 1588 ref_snr = 1600; /* 16dB */
b63b36fa
FR		 1589 break;
1590 case QAM_64:
8e8cd34e 1591 ref_snr = 2200; /* 22dB */
b63b36fa
FR		 1592 break;
1593 case QAM_256:
8e8cd34e 1594 ref_snr = 2800; /* 28dB */
b63b36fa
FR		 1595 break;
1596 default:
1597 return -EINVAL;
1598 }
1599
1600 ret = fe->ops.read_snr(fe, &snr);
1601 if (lg_chkerr(ret))
1602 goto fail;
1603
8e8cd34e 1604 if (state->snr <= (ref_snr - 100))
b63b36fa 1605 str = 0;
8e8cd34e
MIK		 1606 else if (state->snr <= ref_snr)
1607 str = (0xffff * 65) / 100; /* 65% */
b63b36fa
FR		 1608 else {
1609 str = state->snr - ref_snr;
1610 str /= 50;
8e8cd34e
MIK		 1611 str += 78; /* 78%-100% */
1612 if (str > 100)
b63b36fa
FR		 1613 str = 100;
1614 str = (0xffff * str) / 100;
1615 }
1616 *strength = (u16)str;
097117ca 1617 dbg_info("strength=%u\n", *strength);
b63b36fa
FR		 1618
1619fail:
1620 return ret;
1621}
1622
1623/* ------------------------------------------------------------------------ */
1624
1625static int lgdt3306a_read_ber(struct dvb_frontend *fe, u32 *ber)
1626{
1627 struct lgdt3306a_state *state = fe->demodulator_priv;
1628 u32 tmp;
1629
1630 *ber = 0;
1631#if 1
8e8cd34e
MIK		 1632 /* FGR - BUGBUG - I don't know what value is expected by dvb_core
1633 * what is the scale of the value?? */
4937ba94
MCC		 1634 tmp = read_reg(state, 0x00fc); /* NBERVALUE[24-31] */
1635 tmp = (tmp << 8) | read_reg(state, 0x00fd); /* NBERVALUE[16-23] */
1636 tmp = (tmp << 8) | read_reg(state, 0x00fe); /* NBERVALUE[8-15] */
1637 tmp = (tmp << 8) | read_reg(state, 0x00ff); /* NBERVALUE[0-7] */
b63b36fa 1638 *ber = tmp;
097117ca 1639 dbg_info("ber=%u\n", tmp);
b63b36fa
FR		 1640#endif
1641 return 0;
1642}
1643
1644static int lgdt3306a_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1645{
1646 struct lgdt3306a_state *state = fe->demodulator_priv;
1647
8e8cd34e 1648 *ucblocks = 0;
b63b36fa 1649#if 1
8e8cd34e
MIK		 1650 /* FGR - BUGBUG - I don't know what value is expected by dvb_core
1651 * what happens when value wraps? */
4937ba94 1652 *ucblocks = read_reg(state, 0x00f4); /* TPIFTPERRCNT[0-7] */
097117ca 1653 dbg_info("ucblocks=%u\n", *ucblocks);
b63b36fa
FR		 1654#endif
1655
1656 return 0;
1657}
1658
1659static int lgdt3306a_tune(struct dvb_frontend *fe, bool re_tune, unsigned int mode_flags, unsigned int *delay, fe_status_t *status)
1660{
1661 int ret = 0;
1662 struct lgdt3306a_state *state = fe->demodulator_priv;
1663
097117ca 1664 dbg_info("re_tune=%u\n", re_tune);
b63b36fa
FR		 1665
1666 if (re_tune) {
8e8cd34e 1667 state->current_frequency = -1; /* force re-tune */
ae21e447
MIK		 1668 ret = lgdt3306a_set_parameters(fe);
1669 if (ret != 0)
b63b36fa 1670 return ret;
b63b36fa
FR		 1671 }
1672 *delay = 125;
1673 ret = lgdt3306a_read_status(fe, status);
1674
1675 return ret;
1676}
1677
1678static int lgdt3306a_get_tune_settings(struct dvb_frontend *fe,
8e8cd34e
MIK		 1679 struct dvb_frontend_tune_settings
1680 *fe_tune_settings)
b63b36fa
FR		 1681{
1682 fe_tune_settings->min_delay_ms = 100;
097117ca 1683 dbg_info("\n");
b63b36fa
FR		 1684 return 0;
1685}
1686
1687static int lgdt3306a_search(struct dvb_frontend *fe)
1688{
1689 fe_status_t status = 0;
1690 int i, ret;
1691
1692 /* set frontend */
1693 ret = lgdt3306a_set_parameters(fe);
1694 if (ret)
1695 goto error;
1696
1697 /* wait frontend lock */
1698 for (i = 20; i > 0; i--) {
097117ca 1699 dbg_info(": loop=%d\n", i);
b63b36fa
FR		 1700 msleep(50);
1701 ret = lgdt3306a_read_status(fe, &status);
1702 if (ret)
1703 goto error;
1704
1705 if (status & FE_HAS_LOCK)
1706 break;
1707 }
1708
1709 /* check if we have a valid signal */
8e8cd34e 1710 if (status & FE_HAS_LOCK)
b63b36fa 1711 return DVBFE_ALGO_SEARCH_SUCCESS;
8e8cd34e 1712 else
b63b36fa 1713 return DVBFE_ALGO_SEARCH_AGAIN;
b63b36fa
FR		 1714
1715error:
097117ca 1716 dbg_info("failed (%d)\n", ret);
b63b36fa
FR		 1717 return DVBFE_ALGO_SEARCH_ERROR;
1718}
1719
1720static void lgdt3306a_release(struct dvb_frontend *fe)
1721{
1722 struct lgdt3306a_state *state = fe->demodulator_priv;
8e8cd34e 1723
097117ca 1724 dbg_info("\n");
b63b36fa
FR		 1725 kfree(state);
1726}
1727
1728static struct dvb_frontend_ops lgdt3306a_ops;
1729
1730struct dvb_frontend *lgdt3306a_attach(const struct lgdt3306a_config *config,
c43e6512 1731 struct i2c_adapter *i2c_adap)
b63b36fa
FR		 1732{
1733 struct lgdt3306a_state *state = NULL;
1734 int ret;
1735 u8 val;
1736
097117ca 1737 dbg_info("(%d-%04x)\n",
b63b36fa
FR		 1738 i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
1739 config ? config->i2c_addr : 0);
1740
1741 state = kzalloc(sizeof(struct lgdt3306a_state), GFP_KERNEL);
1742 if (state == NULL)
1743 goto fail;
1744
1745 state->cfg = config;
1746 state->i2c_adap = i2c_adap;
1747
1748 memcpy(&state->frontend.ops, &lgdt3306a_ops,
1749 sizeof(struct dvb_frontend_ops));
1750 state->frontend.demodulator_priv = state;
1751
1752 /* verify that we're talking to a lg3306a */
8e8cd34e
MIK		 1753 /* FGR - NOTE - there is no obvious ChipId to check; we check
1754 * some "known" bits after reset, but it's still just a guess */
b63b36fa
FR		 1755 ret = lgdt3306a_read_reg(state, 0x0000, &val);
1756 if (lg_chkerr(ret))
1757 goto fail;
8e8cd34e 1758 if ((val & 0x74) != 0x74) {
097117ca 1759 pr_warn("expected 0x74, got 0x%x\n", (val & 0x74));
8e8cd34e
MIK		 1760#if 0
1761 goto fail; /* BUGBUG - re-enable when we know this is right */
1762#endif
b63b36fa
FR		 1763 }
1764 ret = lgdt3306a_read_reg(state, 0x0001, &val);
1765 if (lg_chkerr(ret))
1766 goto fail;
4937ba94 1767 if ((val & 0xf6) != 0xc6) {
097117ca 1768 pr_warn("expected 0xc6, got 0x%x\n", (val & 0xf6));
8e8cd34e
MIK		 1769#if 0
1770 goto fail; /* BUGBUG - re-enable when we know this is right */
1771#endif
b63b36fa
FR		 1772 }
1773 ret = lgdt3306a_read_reg(state, 0x0002, &val);
1774 if (lg_chkerr(ret))
1775 goto fail;
8e8cd34e 1776 if ((val & 0x73) != 0x03) {
097117ca 1777 pr_warn("expected 0x03, got 0x%x\n", (val & 0x73));
8e8cd34e
MIK		 1778#if 0
1779 goto fail; /* BUGBUG - re-enable when we know this is right */
1780#endif
b63b36fa
FR		 1781 }
1782
1783 state->current_frequency = -1;
1784 state->current_modulation = -1;
1785
1786 lgdt3306a_sleep(state);
1787
1788 return &state->frontend;
1789
1790fail:
097117ca 1791 pr_warn("unable to detect LGDT3306A hardware\n");
b63b36fa
FR		 1792 kfree(state);
1793 return NULL;
1794}
ebd9175e 1795EXPORT_SYMBOL(lgdt3306a_attach);
b63b36fa
FR		 1796
1797#ifdef DBG_DUMP
1798
1799static const short regtab[] = {
cb4671c8
MIK		 1800 0x0000, /* SOFTRSTB 1'b1 1'b1 1'b1 ADCPDB 1'b1 PLLPDB GBBPDB 11111111 */
1801 0x0001, /* 1'b1 1'b1 1'b0 1'b0 AUTORPTRS */
1802 0x0002, /* NI2CRPTEN 1'b0 1'b0 1'b0 SPECINVAUT */
1803 0x0003, /* AGCRFOUT */
1804 0x0004, /* ADCSEL1V ADCCNT ADCCNF ADCCNS ADCCLKPLL */
1805 0x0005, /* PLLINDIVSE */
1806 0x0006, /* PLLCTRL[7:0] 11100001 */
1807 0x0007, /* SYSINITWAITTIME[7:0] (msec) 00001000 */
1808 0x0008, /* STDOPMODE[7:0] 10000000 */
1809 0x0009, /* 1'b0 1'b0 1'b0 STDOPDETTMODE[2:0] STDOPDETCMODE[1:0] 00011110 */
4937ba94
MCC		 1810 0x000a, /* DAFTEN 1'b1 x x SCSYSLOCK */
1811 0x000b, /* SCSYSLOCKCHKTIME[7:0] (10msec) 01100100 */
1812 0x000d, /* x SAMPLING4 */
1813 0x000e, /* SAMFREQ[15:8] 00000000 */
1814 0x000f, /* SAMFREQ[7:0] 00000000 */
cb4671c8
MIK		 1815 0x0010, /* IFFREQ[15:8] 01100000 */
1816 0x0011, /* IFFREQ[7:0] 00000000 */
1817 0x0012, /* AGCEN AGCREFMO */
1818 0x0013, /* AGCRFFIXB AGCIFFIXB AGCLOCKDETRNGSEL[1:0] 1'b1 1'b0 1'b0 1'b0 11101000 */
1819 0x0014, /* AGCFIXVALUE[7:0] 01111111 */
1820 0x0015, /* AGCREF[15:8] 00001010 */
1821 0x0016, /* AGCREF[7:0] 11100100 */
1822 0x0017, /* AGCDELAY[7:0] 00100000 */
1823 0x0018, /* AGCRFBW[3:0] AGCIFBW[3:0] 10001000 */
1824 0x0019, /* AGCUDOUTMODE[1:0] AGCUDCTRLLEN[1:0] AGCUDCTRL */
4937ba94
MCC		 1825 0x001c, /* 1'b1 PFEN MFEN AICCVSYNC */
1826 0x001d, /* 1'b0 1'b1 1'b0 1'b1 AICCVSYNC */
1827 0x001e, /* AICCALPHA[3:0] 1'b1 1'b0 1'b1 1'b0 01111010 */
1828 0x001f, /* AICCDETTH[19:16] AICCOFFTH[19:16] 00000000 */
cb4671c8
MIK		 1829 0x0020, /* AICCDETTH[15:8] 01111100 */
1830 0x0021, /* AICCDETTH[7:0] 00000000 */
1831 0x0022, /* AICCOFFTH[15:8] 00000101 */
1832 0x0023, /* AICCOFFTH[7:0] 11100000 */
1833 0x0024, /* AICCOPMODE3[1:0] AICCOPMODE2[1:0] AICCOPMODE1[1:0] AICCOPMODE0[1:0] 00000000 */
1834 0x0025, /* AICCFIXFREQ3[23:16] 00000000 */
1835 0x0026, /* AICCFIXFREQ3[15:8] 00000000 */
1836 0x0027, /* AICCFIXFREQ3[7:0] 00000000 */
1837 0x0028, /* AICCFIXFREQ2[23:16] 00000000 */
1838 0x0029, /* AICCFIXFREQ2[15:8] 00000000 */
4937ba94
MCC		 1839 0x002a, /* AICCFIXFREQ2[7:0] 00000000 */
1840 0x002b, /* AICCFIXFREQ1[23:16] 00000000 */
1841 0x002c, /* AICCFIXFREQ1[15:8] 00000000 */
1842 0x002d, /* AICCFIXFREQ1[7:0] 00000000 */
1843 0x002e, /* AICCFIXFREQ0[23:16] 00000000 */
1844 0x002f, /* AICCFIXFREQ0[15:8] 00000000 */
cb4671c8
MIK		 1845 0x0030, /* AICCFIXFREQ0[7:0] 00000000 */
1846 0x0031, /* 1'b0 1'b1 1'b0 1'b0 x DAGC1STER */
1847 0x0032, /* DAGC1STEN DAGC1STER */
1848 0x0033, /* DAGC1STREF[15:8] 00001010 */
1849 0x0034, /* DAGC1STREF[7:0] 11100100 */
1850 0x0035, /* DAGC2NDE */
1851 0x0036, /* DAGC2NDREF[15:8] 00001010 */
1852 0x0037, /* DAGC2NDREF[7:0] 10000000 */
1853 0x0038, /* DAGC2NDLOCKDETRNGSEL[1:0] */
4937ba94 1854 0x003d, /* 1'b1 SAMGEARS */
cb4671c8
MIK		 1855 0x0040, /* SAMLFGMA */
1856 0x0041, /* SAMLFBWM */
1857 0x0044, /* 1'b1 CRGEARSHE */
1858 0x0045, /* CRLFGMAN */
1859 0x0046, /* CFLFBWMA */
1860 0x0047, /* CRLFGMAN */
1861 0x0048, /* x x x x CRLFGSTEP_VS[3:0] xxxx1001 */
1862 0x0049, /* CRLFBWMA */
4937ba94 1863 0x004a, /* CRLFBWMA */
cb4671c8
MIK		 1864 0x0050, /* 1'b0 1'b1 1'b1 1'b0 MSECALCDA */
1865 0x0070, /* TPOUTEN TPIFEN TPCLKOUTE */
1866 0x0071, /* TPSENB TPSSOPBITE */
1867 0x0073, /* TP47HINS x x CHBERINT PERMODE[1:0] PERINT[1:0] 1xx11100 */
1868 0x0075, /* x x x x x IQSWAPCTRL[2:0] xxxxx000 */
1869 0x0076, /* NBERCON NBERST NBERPOL NBERWSYN */
1870 0x0077, /* x NBERLOSTTH[2:0] NBERACQTH[3:0] x0000000 */
1871 0x0078, /* NBERPOLY[31:24] 00000000 */
1872 0x0079, /* NBERPOLY[23:16] 00000000 */
4937ba94
MCC		 1873 0x007a, /* NBERPOLY[15:8] 00000000 */
1874 0x007b, /* NBERPOLY[7:0] 00000000 */
1875 0x007c, /* NBERPED[31:24] 00000000 */
1876 0x007d, /* NBERPED[23:16] 00000000 */
1877 0x007e, /* NBERPED[15:8] 00000000 */
1878 0x007f, /* NBERPED[7:0] 00000000 */
cb4671c8
MIK		 1879 0x0080, /* x AGCLOCK DAGCLOCK SYSLOCK x x NEVERLOCK[1:0] */
1880 0x0085, /* SPECINVST */
1881 0x0088, /* SYSLOCKTIME[15:8] */
1882 0x0089, /* SYSLOCKTIME[7:0] */
4937ba94
MCC		 1883 0x008c, /* FECLOCKTIME[15:8] */
1884 0x008d, /* FECLOCKTIME[7:0] */
1885 0x008e, /* AGCACCOUT[15:8] */
1886 0x008f, /* AGCACCOUT[7:0] */
cb4671c8
MIK		 1887 0x0090, /* AICCREJSTATUS[3:0] AICCREJBUSY[3:0] */
1888 0x0091, /* AICCVSYNC */
4937ba94
MCC		 1889 0x009c, /* CARRFREQOFFSET[15:8] */
1890 0x009d, /* CARRFREQOFFSET[7:0] */
1891 0x00a1, /* SAMFREQOFFSET[23:16] */
1892 0x00a2, /* SAMFREQOFFSET[15:8] */
1893 0x00a3, /* SAMFREQOFFSET[7:0] */
1894 0x00a6, /* SYNCLOCK SYNCLOCKH */
6da7ac98 1895#if 0 /* covered elsewhere */
4937ba94
MCC		 1896 0x00e8, /* CONSTPWR[15:8] */
1897 0x00e9, /* CONSTPWR[7:0] */
1898 0x00ea, /* BMSE[15:8] */
1899 0x00eb, /* BMSE[7:0] */
1900 0x00ec, /* MSE[15:8] */
1901 0x00ed, /* MSE[7:0] */
1902 0x00ee, /* CONSTI[7:0] */
1903 0x00ef, /* CONSTQ[7:0] */
b63b36fa 1904#endif
4937ba94
MCC		 1905 0x00f4, /* TPIFTPERRCNT[7:0] */
1906 0x00f5, /* TPCORREC */
1907 0x00f6, /* VBBER[15:8] */
1908 0x00f7, /* VBBER[7:0] */
1909 0x00f8, /* VABER[15:8] */
1910 0x00f9, /* VABER[7:0] */
1911 0x00fa, /* TPERRCNT[7:0] */
1912 0x00fb, /* NBERLOCK x x x x x x x */
1913 0x00fc, /* NBERVALUE[31:24] */
1914 0x00fd, /* NBERVALUE[23:16] */
1915 0x00fe, /* NBERVALUE[15:8] */
1916 0x00ff, /* NBERVALUE[7:0] */
cb4671c8
MIK		 1917 0x1000, /* 1'b0 WODAGCOU */
1918 0x1005, /* x x 1'b1 1'b1 x SRD_Q_QM */
1919 0x1009, /* SRDWAITTIME[7:0] (10msec) 00100011 */
4937ba94
MCC		 1920 0x100a, /* SRDWAITTIME_CQS[7:0] (msec) 01100100 */
1921 0x101a, /* x 1'b1 1'b0 1'b0 x QMDQAMMODE[2:0] x100x010 */
cb4671c8 1922 0x1036, /* 1'b0 1'b1 1'b0 1'b0 SAMGSEND_CQS[3:0] 01001110 */
4937ba94
MCC		 1923 0x103c, /* SAMGSAUTOSTL_V[3:0] SAMGSAUTOEDL_V[3:0] 01000110 */
1924 0x103d, /* 1'b1 1'b1 SAMCNORMBP_V[1:0] 1'b0 1'b0 SAMMODESEL_V[1:0] 11100001 */
1925 0x103f, /* SAMZTEDSE */
1926 0x105d, /* EQSTATUSE */
1927 0x105f, /* x PMAPG2_V[2:0] x DMAPG2_V[2:0] x001x011 */
cb4671c8
MIK		 1928 0x1060, /* 1'b1 EQSTATUSE */
1929 0x1061, /* CRMAPBWSTL_V[3:0] CRMAPBWEDL_V[3:0] 00000100 */
1930 0x1065, /* 1'b0 x CRMODE_V[1:0] 1'b1 x 1'b1 x 0x111x1x */
1931 0x1066, /* 1'b0 1'b0 1'b1 1'b0 1'b1 PNBOOSTSE */
1932 0x1068, /* CREPHNGAIN2_V[3:0] CREPHNPBW_V[3:0] 10010001 */
4937ba94
MCC		 1933 0x106e, /* x x x x x CREPHNEN_ */
1934 0x106f, /* CREPHNTH_V[7:0] 00010101 */
cb4671c8
MIK		 1935 0x1072, /* CRSWEEPN */
1936 0x1073, /* CRPGAIN_V[3:0] x x 1'b1 1'b1 1001xx11 */
1937 0x1074, /* CRPBW_V[3:0] x x 1'b1 1'b1 0001xx11 */
1938 0x1080, /* DAFTSTATUS[1:0] x x x x x x */
1939 0x1081, /* SRDSTATUS[1:0] x x x x x SRDLOCK */
4937ba94
MCC		 1940 0x10a9, /* EQSTATUS_CQS[1:0] x x x x x x */
1941 0x10b7, /* EQSTATUS_V[1:0] x x x x x x */
6da7ac98 1942#if 0 /* SMART_ANT */
4937ba94
MCC		 1943 0x1f00, /* MODEDETE */
1944 0x1f01, /* x x x x x x x SFNRST xxxxxxx0 */
1945 0x1f03, /* NUMOFANT[7:0] 10000000 */
1946 0x1f04, /* x SELMASK[6:0] x0000000 */
1947 0x1f05, /* x SETMASK[6:0] x0000000 */
1948 0x1f06, /* x TXDATA[6:0] x0000000 */
1949 0x1f07, /* x CHNUMBER[6:0] x0000000 */
1950 0x1f09, /* AGCTIME[23:16] 10011000 */
1951 0x1f0a, /* AGCTIME[15:8] 10010110 */
1952 0x1f0b, /* AGCTIME[7:0] 10000000 */
1953 0x1f0c, /* ANTTIME[31:24] 00000000 */
1954 0x1f0d, /* ANTTIME[23:16] 00000011 */
1955 0x1f0e, /* ANTTIME[15:8] 10010000 */
1956 0x1f0f, /* ANTTIME[7:0] 10010000 */
1957 0x1f11, /* SYNCTIME[23:16] 10011000 */
1958 0x1f12, /* SYNCTIME[15:8] 10010110 */
1959 0x1f13, /* SYNCTIME[7:0] 10000000 */
1960 0x1f14, /* SNRTIME[31:24] 00000001 */
1961 0x1f15, /* SNRTIME[23:16] 01111101 */
1962 0x1f16, /* SNRTIME[15:8] 01111000 */
1963 0x1f17, /* SNRTIME[7:0] 01000000 */
1964 0x1f19, /* FECTIME[23:16] 00000000 */
1965 0x1f1a, /* FECTIME[15:8] 01110010 */
1966 0x1f1b, /* FECTIME[7:0] 01110000 */
1967 0x1f1d, /* FECTHD[7:0] 00000011 */
1968 0x1f1f, /* SNRTHD[23:16] 00001000 */
1969 0x1f20, /* SNRTHD[15:8] 01111111 */
1970 0x1f21, /* SNRTHD[7:0] 10000101 */
1971 0x1f80, /* IRQFLG x x SFSDRFLG MODEBFLG SAVEFLG SCANFLG TRACKFLG */
1972 0x1f81, /* x SYNCCON SNRCON FECCON x STDBUSY SYNCRST AGCFZCO */
1973 0x1f82, /* x x x SCANOPCD[4:0] */
1974 0x1f83, /* x x x x MAINOPCD[3:0] */
1975 0x1f84, /* x x RXDATA[13:8] */
1976 0x1f85, /* RXDATA[7:0] */
1977 0x1f86, /* x x SDTDATA[13:8] */
1978 0x1f87, /* SDTDATA[7:0] */
1979 0x1f89, /* ANTSNR[23:16] */
1980 0x1f8a, /* ANTSNR[15:8] */
1981 0x1f8b, /* ANTSNR[7:0] */
1982 0x1f8c, /* x x x x ANTFEC[13:8] */
1983 0x1f8d, /* ANTFEC[7:0] */
1984 0x1f8e, /* MAXCNT[7:0] */
1985 0x1f8f, /* SCANCNT[7:0] */
1986 0x1f91, /* MAXPW[23:16] */
1987 0x1f92, /* MAXPW[15:8] */
1988 0x1f93, /* MAXPW[7:0] */
1989 0x1f95, /* CURPWMSE[23:16] */
1990 0x1f96, /* CURPWMSE[15:8] */
1991 0x1f97, /* CURPWMSE[7:0] */
6da7ac98 1992#endif /* SMART_ANT */
4937ba94
MCC		 1993 0x211f, /* 1'b1 1'b1 1'b1 CIRQEN x x 1'b0 1'b0 1111xx00 */
1994 0x212a, /* EQAUTOST */
cb4671c8 1995 0x2122, /* CHFAST[7:0] 01100000 */
4937ba94
MCC		 1996 0x212b, /* FFFSTEP_V[3:0] x FBFSTEP_V[2:0] 0001x001 */
1997 0x212c, /* PHDEROTBWSEL[3:0] 1'b1 1'b1 1'b1 1'b0 10001110 */
1998 0x212d, /* 1'b1 1'b1 1'b1 1'b1 x x TPIFLOCKS */
cb4671c8
MIK		 1999 0x2135, /* DYNTRACKFDEQ[3:0] x 1'b0 1'b0 1'b0 1010x000 */
2000 0x2141, /* TRMODE[1:0] 1'b1 1'b1 1'b0 1'b1 1'b1 1'b1 01110111 */
2001 0x2162, /* AICCCTRLE */
2002 0x2173, /* PHNCNFCNT[7:0] 00000100 */
2003 0x2179, /* 1'b0 1'b0 1'b0 1'b1 x BADSINGLEDYNTRACKFBF[2:0] 0001x001 */
4937ba94
MCC		 2004 0x217a, /* 1'b0 1'b0 1'b0 1'b1 x BADSLOWSINGLEDYNTRACKFBF[2:0] 0001x001 */
2005 0x217e, /* CNFCNTTPIF[7:0] 00001000 */
2006 0x217f, /* TPERRCNTTPIF[7:0] 00000001 */
cb4671c8
MIK		 2007 0x2180, /* x x x x x x FBDLYCIR[9:8] */
2008 0x2181, /* FBDLYCIR[7:0] */
2009 0x2185, /* MAXPWRMAIN[7:0] */
2010 0x2191, /* NCOMBDET x x x x x x x */
2011 0x2199, /* x MAINSTRON */
4937ba94
MCC		 2012 0x219a, /* FFFEQSTEPOUT_V[3:0] FBFSTEPOUT_V[2:0] */
2013 0x21a1, /* x x SNRREF[5:0] */
cb4671c8
MIK		 2014 0x2845, /* 1'b0 1'b1 x x FFFSTEP_CQS[1:0] FFFCENTERTAP[1:0] 01xx1110 */
2015 0x2846, /* 1'b0 x 1'b0 1'b1 FBFSTEP_CQS[1:0] 1'b1 1'b0 0x011110 */
2016 0x2847, /* ENNOSIGDE */
2017 0x2849, /* 1'b1 1'b1 NOUSENOSI */
4937ba94 2018 0x284a, /* EQINITWAITTIME[7:0] 01100100 */
cb4671c8
MIK		 2019 0x3000, /* 1'b1 1'b1 1'b1 x x x 1'b0 RPTRSTM */
2020 0x3001, /* RPTRSTWAITTIME[7:0] (100msec) 00110010 */
2021 0x3031, /* FRAMELOC */
2022 0x3032, /* 1'b1 1'b0 1'b0 1'b0 x x FRAMELOCKMODE_CQS[1:0] 1000xx11 */
4937ba94
MCC		 2023 0x30a9, /* VDLOCK_Q FRAMELOCK */
2024 0x30aa, /* MPEGLOCK */
b63b36fa
FR		 2025};
2026
34a5a2f8 2027#define numDumpRegs (sizeof(regtab)/sizeof(regtab[0]))
b63b36fa
FR		 2028static u8 regval1[numDumpRegs] = {0, };
2029static u8 regval2[numDumpRegs] = {0, };
2030
2031static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state)
2032{
2033 memset(regval2, 0xff, sizeof(regval2));
2034 lgdt3306a_DumpRegs(state);
2035}
2036
2037static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state)
2038{
2039 int i;
2040 int sav_debug = debug;
8e8cd34e 2041
b63b36fa
FR		 2042 if ((debug & DBG_DUMP) == 0)
2043 return;
831a9112 2044 debug &= ~DBG_REG; /* suppress DBG_REG during reg dump */
b63b36fa 2045
097117ca 2046 lg_debug("\n");
b63b36fa 2047
8e8cd34e 2048 for (i = 0; i < numDumpRegs; i++) {
b63b36fa 2049 lgdt3306a_read_reg(state, regtab[i], &regval1[i]);
8e8cd34e 2050 if (regval1[i] != regval2[i]) {
097117ca
MCC		 2051 lg_debug(" %04X = %02X\n", regtab[i], regval1[i]);
2052 regval2[i] = regval1[i];
b63b36fa
FR		 2053 }
2054 }
2055 debug = sav_debug;
2056}
8e8cd34e 2057#endif /* DBG_DUMP */
b63b36fa
FR		 2058
2059
2060
b63b36fa
FR		 2061static struct dvb_frontend_ops lgdt3306a_ops = {
2062 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
2063 .info = {
2064 .name = "LG Electronics LGDT3306A VSB/QAM Frontend",
8e8cd34e
MIK		 2065#if 0
2066 .type = FE_ATSC,
2067#endif
b63b36fa 2068 .frequency_min = 54000000,
8e8cd34e 2069 .frequency_max = 858000000,
b63b36fa
FR		 2070 .frequency_stepsize = 62500,
2071 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
2072 },
2073 .i2c_gate_ctrl = lgdt3306a_i2c_gate_ctrl,
2074 .init = lgdt3306a_init,
2075 .sleep = lgdt3306a_fe_sleep,
2076 /* if this is set, it overrides the default swzigzag */
2077 .tune = lgdt3306a_tune,
2078 .set_frontend = lgdt3306a_set_parameters,
2079 .get_frontend = lgdt3306a_get_frontend,
2080 .get_frontend_algo = lgdt3306a_get_frontend_algo,
2081 .get_tune_settings = lgdt3306a_get_tune_settings,
2082 .read_status = lgdt3306a_read_status,
2083 .read_ber = lgdt3306a_read_ber,
2084 .read_signal_strength = lgdt3306a_read_signal_strength,
2085 .read_snr = lgdt3306a_read_snr,
2086 .read_ucblocks = lgdt3306a_read_ucblocks,
2087 .release = lgdt3306a_release,
2088 .ts_bus_ctrl = lgdt3306a_ts_bus_ctrl,
2089 .search = lgdt3306a_search,
2090};
2091
2092MODULE_DESCRIPTION("LG Electronics LGDT3306A ATSC/QAM-B Demodulator Driver");
2093MODULE_AUTHOR("Fred Richter <frichter@hauppauge.com>");
2094MODULE_LICENSE("GPL");
2095MODULE_VERSION("0.2");
2096
2097/*
2098 * Local variables:
2099 * c-basic-offset: 8
2100 * End:
2101 */
Linux 6.x block layer and io_uring tree(s)