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media: replace strncpy() by strscpy()
[linux-block.git] / drivers / media / dvb-frontends / lgdt3306a.c
CommitLineData
b63b36fa
FR		 1/*
2 * Support for LGDT3306A - 8VSB/QAM-B
3 *
4 * Copyright (C) 2013 Fred Richter <frichter@hauppauge.com>
5 * - driver structure based on lgdt3305.[ch] by Michael Krufky
6 * - code based on LG3306_V0.35 API by LG Electronics Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
b63b36fa
FR		 17 */
18
097117ca
MCC		 19#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
b63b36fa 21#include <asm/div64.h>
1f679ff6 22#include <linux/kernel.h>
b63b36fa 23#include <linux/dvb/frontend.h>
fada1935 24#include <media/dvb_math.h>
b63b36fa 25#include "lgdt3306a.h"
4f751890 26#include <linux/i2c-mux.h>
b63b36fa
FR		 27
28
29static int debug;
30module_param(debug, int, 0644);
31MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))");
32
4966c0c5
BL		 33/*
34 * Older drivers treated QAM64 and QAM256 the same; that is the HW always
35 * used "Auto" mode during detection. Setting "forced_manual"=1 allows
36 * the user to treat these modes as separate. For backwards compatibility,
37 * it's off by default. QAM_AUTO can now be specified to achive that
38 * effect even if "forced_manual"=1
39 */
40static int forced_manual;
41module_param(forced_manual, int, 0644);
42MODULE_PARM_DESC(forced_manual, "if set, QAM64 and QAM256 will only lock to modulation specified");
43
b63b36fa
FR		 44#define DBG_INFO 1
45#define DBG_REG 2
8e8cd34e 46#define DBG_DUMP 4 /* FGR - comment out to remove dump code */
b63b36fa 47
097117ca
MCC		 48#define lg_debug(fmt, arg...) \
49 printk(KERN_DEBUG pr_fmt(fmt), ## arg)
50
51#define dbg_info(fmt, arg...) \
52 do { \
53 if (debug & DBG_INFO) \
54 lg_debug(fmt, ## arg); \
55 } while (0)
b63b36fa 56
097117ca
MCC		 57#define dbg_reg(fmt, arg...) \
58 do { \
59 if (debug & DBG_REG) \
60 lg_debug(fmt, ## arg); \
61 } while (0)
b63b36fa
FR		 62
63#define lg_chkerr(ret) \
64({ \
65 int __ret; \
66 __ret = (ret < 0); \
67 if (__ret) \
097117ca 68 pr_err("error %d on line %d\n", ret, __LINE__); \
b63b36fa
FR		 69 __ret; \
70})
71
72struct lgdt3306a_state {
73 struct i2c_adapter *i2c_adap;
74 const struct lgdt3306a_config *cfg;
75
76 struct dvb_frontend frontend;
77
0df289a2 78 enum fe_modulation current_modulation;
b63b36fa
FR		 79 u32 current_frequency;
80 u32 snr;
4f751890
KC		 81
82 struct i2c_mux_core *muxc;
b63b36fa
FR		 83};
84
95f22c5a
MCC		 85/*
86 * LG3306A Register Usage
87 * (LG does not really name the registers, so this code does not either)
88 *
89 * 0000 -> 00FF Common control and status
90 * 1000 -> 10FF Synchronizer control and status
91 * 1F00 -> 1FFF Smart Antenna control and status
92 * 2100 -> 21FF VSB Equalizer control and status
93 * 2800 -> 28FF QAM Equalizer control and status
94 * 3000 -> 30FF FEC control and status
95 */
b63b36fa 96
f883d603
MIK		 97enum lgdt3306a_lock_status {
98 LG3306_UNLOCK = 0x00,
99 LG3306_LOCK = 0x01,
4937ba94 100 LG3306_UNKNOWN_LOCK = 0xff
f883d603 101};
b63b36fa 102
f883d603 103enum lgdt3306a_neverlock_status {
b63b36fa
FR		 104 LG3306_NL_INIT = 0x00,
105 LG3306_NL_PROCESS = 0x01,
106 LG3306_NL_LOCK = 0x02,
107 LG3306_NL_FAIL = 0x03,
4937ba94 108 LG3306_NL_UNKNOWN = 0xff
f883d603 109};
b63b36fa 110
f883d603
MIK		 111enum lgdt3306a_modulation {
112 LG3306_VSB = 0x00,
113 LG3306_QAM64 = 0x01,
114 LG3306_QAM256 = 0x02,
4937ba94 115 LG3306_UNKNOWN_MODE = 0xff
f883d603 116};
b63b36fa 117
f883d603 118enum lgdt3306a_lock_check {
b63b36fa
FR		 119 LG3306_SYNC_LOCK,
120 LG3306_FEC_LOCK,
121 LG3306_TR_LOCK,
122 LG3306_AGC_LOCK,
f883d603 123};
b63b36fa
FR		 124
125
126#ifdef DBG_DUMP
127static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state);
128static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state);
129#endif
130
131
132static int lgdt3306a_write_reg(struct lgdt3306a_state *state, u16 reg, u8 val)
133{
134 int ret;
135 u8 buf[] = { reg >> 8, reg & 0xff, val };
136 struct i2c_msg msg = {
137 .addr = state->cfg->i2c_addr, .flags = 0,
138 .buf = buf, .len = 3,
139 };
140
097117ca 141 dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
b63b36fa
FR		 142
143 ret = i2c_transfer(state->i2c_adap, &msg, 1);
144
145 if (ret != 1) {
097117ca 146 pr_err("error (addr %02x %02x <- %02x, err = %i)\n",
b63b36fa
FR		 147 msg.buf[0], msg.buf[1], msg.buf[2], ret);
148 if (ret < 0)
149 return ret;
150 else
151 return -EREMOTEIO;
152 }
153 return 0;
154}
155
156static int lgdt3306a_read_reg(struct lgdt3306a_state *state, u16 reg, u8 *val)
157{
158 int ret;
159 u8 reg_buf[] = { reg >> 8, reg & 0xff };
160 struct i2c_msg msg[] = {
161 { .addr = state->cfg->i2c_addr,
162 .flags = 0, .buf = reg_buf, .len = 2 },
163 { .addr = state->cfg->i2c_addr,
164 .flags = I2C_M_RD, .buf = val, .len = 1 },
165 };
166
167 ret = i2c_transfer(state->i2c_adap, msg, 2);
168
169 if (ret != 2) {
097117ca 170 pr_err("error (addr %02x reg %04x error (ret == %i)\n",
b63b36fa
FR		 171 state->cfg->i2c_addr, reg, ret);
172 if (ret < 0)
173 return ret;
174 else
175 return -EREMOTEIO;
176 }
097117ca 177 dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, *val);
b63b36fa
FR		 178
179 return 0;
180}
181
182#define read_reg(state, reg) \
183({ \
184 u8 __val; \
185 int ret = lgdt3306a_read_reg(state, reg, &__val); \
186 if (lg_chkerr(ret)) \
187 __val = 0; \
188 __val; \
189})
190
191static int lgdt3306a_set_reg_bit(struct lgdt3306a_state *state,
192 u16 reg, int bit, int onoff)
193{
194 u8 val;
195 int ret;
196
097117ca 197 dbg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
b63b36fa
FR		 198
199 ret = lgdt3306a_read_reg(state, reg, &val);
200 if (lg_chkerr(ret))
201 goto fail;
202
203 val &= ~(1 << bit);
204 val |= (onoff & 1) << bit;
205
206 ret = lgdt3306a_write_reg(state, reg, val);
207 lg_chkerr(ret);
208fail:
209 return ret;
210}
211
212/* ------------------------------------------------------------------------ */
213
214static int lgdt3306a_soft_reset(struct lgdt3306a_state *state)
215{
216 int ret;
217
097117ca 218 dbg_info("\n");
b63b36fa
FR		 219
220 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
221 if (lg_chkerr(ret))
222 goto fail;
223
224 msleep(20);
225 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
226 lg_chkerr(ret);
227
228fail:
229 return ret;
230}
231
232static int lgdt3306a_mpeg_mode(struct lgdt3306a_state *state,
233 enum lgdt3306a_mpeg_mode mode)
234{
235 u8 val;
236 int ret;
237
097117ca 238 dbg_info("(%d)\n", mode);
534f4364
MCC		 239 /* transport packet format - TPSENB=0x80 */
240 ret = lgdt3306a_set_reg_bit(state, 0x0071, 7,
241 mode == LGDT3306A_MPEG_PARALLEL ? 1 : 0);
b63b36fa
FR		 242 if (lg_chkerr(ret))
243 goto fail;
244
534f4364
MCC		 245 /*
246 * start of packet signal duration
247 * TPSSOPBITEN=0x40; 0=byte duration, 1=bit duration
248 */
249 ret = lgdt3306a_set_reg_bit(state, 0x0071, 6, 0);
b63b36fa
FR		 250 if (lg_chkerr(ret))
251 goto fail;
252
253 ret = lgdt3306a_read_reg(state, 0x0070, &val);
254 if (lg_chkerr(ret))
255 goto fail;
256
8e8cd34e 257 val |= 0x10; /* TPCLKSUPB=0x10 */
b63b36fa 258
8e8cd34e 259 if (mode == LGDT3306A_MPEG_PARALLEL)
b63b36fa
FR		 260 val &= ~0x10;
261
262 ret = lgdt3306a_write_reg(state, 0x0070, val);
263 lg_chkerr(ret);
264
265fail:
266 return ret;
267}
268
269static int lgdt3306a_mpeg_mode_polarity(struct lgdt3306a_state *state,
270 enum lgdt3306a_tp_clock_edge edge,
271 enum lgdt3306a_tp_valid_polarity valid)
272{
273 u8 val;
274 int ret;
275
097117ca 276 dbg_info("edge=%d, valid=%d\n", edge, valid);
b63b36fa
FR		 277
278 ret = lgdt3306a_read_reg(state, 0x0070, &val);
279 if (lg_chkerr(ret))
280 goto fail;
281
8e8cd34e 282 val &= ~0x06; /* TPCLKPOL=0x04, TPVALPOL=0x02 */
b63b36fa 283
8e8cd34e 284 if (edge == LGDT3306A_TPCLK_RISING_EDGE)
b63b36fa 285 val |= 0x04;
8e8cd34e 286 if (valid == LGDT3306A_TP_VALID_HIGH)
b63b36fa
FR		 287 val |= 0x02;
288
289 ret = lgdt3306a_write_reg(state, 0x0070, val);
290 lg_chkerr(ret);
291
292fail:
293 return ret;
294}
295
296static int lgdt3306a_mpeg_tristate(struct lgdt3306a_state *state,
297 int mode)
298{
299 u8 val;
300 int ret;
301
097117ca 302 dbg_info("(%d)\n", mode);
b63b36fa 303
8e8cd34e 304 if (mode) {
b63b36fa
FR		 305 ret = lgdt3306a_read_reg(state, 0x0070, &val);
306 if (lg_chkerr(ret))
307 goto fail;
534f4364
MCC		 308 /*
309 * Tristate bus; TPOUTEN=0x80, TPCLKOUTEN=0x20,
310 * TPDATAOUTEN=0x08
311 */
312 val &= ~0xa8;
b63b36fa
FR		 313 ret = lgdt3306a_write_reg(state, 0x0070, val);
314 if (lg_chkerr(ret))
315 goto fail;
316
534f4364
MCC		 317 /* AGCIFOUTENB=0x40; 1=Disable IFAGC pin */
318 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 1);
b63b36fa
FR		 319 if (lg_chkerr(ret))
320 goto fail;
321
322 } else {
534f4364
MCC		 323 /* enable IFAGC pin */
324 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 0);
b63b36fa
FR		 325 if (lg_chkerr(ret))
326 goto fail;
327
328 ret = lgdt3306a_read_reg(state, 0x0070, &val);
329 if (lg_chkerr(ret))
330 goto fail;
331
4937ba94 332 val |= 0xa8; /* enable bus */
b63b36fa
FR		 333 ret = lgdt3306a_write_reg(state, 0x0070, val);
334 if (lg_chkerr(ret))
335 goto fail;
336 }
337
338fail:
339 return ret;
340}
341
8e8cd34e 342static int lgdt3306a_ts_bus_ctrl(struct dvb_frontend *fe, int acquire)
b63b36fa
FR		 343{
344 struct lgdt3306a_state *state = fe->demodulator_priv;
345
097117ca 346 dbg_info("acquire=%d\n", acquire);
b63b36fa
FR		 347
348 return lgdt3306a_mpeg_tristate(state, acquire ? 0 : 1);
349
350}
351
352static int lgdt3306a_power(struct lgdt3306a_state *state,
353 int mode)
354{
355 int ret;
356
097117ca 357 dbg_info("(%d)\n", mode);
b63b36fa 358
8e8cd34e 359 if (mode == 0) {
534f4364
MCC		 360 /* into reset */
361 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
b63b36fa
FR		 362 if (lg_chkerr(ret))
363 goto fail;
364
534f4364
MCC		 365 /* power down */
366 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 0);
b63b36fa
FR		 367 if (lg_chkerr(ret))
368 goto fail;
369
370 } else {
534f4364
MCC		 371 /* out of reset */
372 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
b63b36fa
FR		 373 if (lg_chkerr(ret))
374 goto fail;
375
534f4364
MCC		 376 /* power up */
377 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 1);
b63b36fa
FR		 378 if (lg_chkerr(ret))
379 goto fail;
380 }
381
382#ifdef DBG_DUMP
383 lgdt3306a_DumpAllRegs(state);
384#endif
385fail:
386 return ret;
387}
388
389
390static int lgdt3306a_set_vsb(struct lgdt3306a_state *state)
391{
392 u8 val;
393 int ret;
394
097117ca 395 dbg_info("\n");
b63b36fa 396
8e8cd34e 397 /* 0. Spectrum inversion detection manual; spectrum inverted */
b63b36fa 398 ret = lgdt3306a_read_reg(state, 0x0002, &val);
4937ba94 399 val &= 0xf7; /* SPECINVAUTO Off */
8e8cd34e 400 val |= 0x04; /* SPECINV On */
b63b36fa
FR		 401 ret = lgdt3306a_write_reg(state, 0x0002, val);
402 if (lg_chkerr(ret))
403 goto fail;
404
8e8cd34e 405 /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
b63b36fa
FR		 406 ret = lgdt3306a_write_reg(state, 0x0008, 0x80);
407 if (lg_chkerr(ret))
408 goto fail;
409
8e8cd34e 410 /* 2. Bandwidth mode for VSB(6MHz) */
b63b36fa 411 ret = lgdt3306a_read_reg(state, 0x0009, &val);
4937ba94
MCC		 412 val &= 0xe3;
413 val |= 0x0c; /* STDOPDETTMODE[2:0]=3 */
b63b36fa
FR		 414 ret = lgdt3306a_write_reg(state, 0x0009, val);
415 if (lg_chkerr(ret))
416 goto fail;
417
8e8cd34e 418 /* 3. QAM mode detection mode(None) */
b63b36fa 419 ret = lgdt3306a_read_reg(state, 0x0009, &val);
4937ba94 420 val &= 0xfc; /* STDOPDETCMODE[1:0]=0 */
b63b36fa
FR		 421 ret = lgdt3306a_write_reg(state, 0x0009, val);
422 if (lg_chkerr(ret))
423 goto fail;
424
8e8cd34e 425 /* 4. ADC sampling frequency rate(2x sampling) */
4937ba94
MCC		 426 ret = lgdt3306a_read_reg(state, 0x000d, &val);
427 val &= 0xbf; /* SAMPLING4XFEN=0 */
428 ret = lgdt3306a_write_reg(state, 0x000d, val);
b63b36fa
FR		 429 if (lg_chkerr(ret))
430 goto fail;
431
8e8cd34e
MIK		 432#if 0
433 /* FGR - disable any AICC filtering, testing only */
434
b63b36fa
FR		 435 ret = lgdt3306a_write_reg(state, 0x0024, 0x00);
436 if (lg_chkerr(ret))
437 goto fail;
438
8e8cd34e 439 /* AICCFIXFREQ0 NT N-1(Video rejection) */
4937ba94
MCC		 440 ret = lgdt3306a_write_reg(state, 0x002e, 0x00);
441 ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
b63b36fa
FR		 442 ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
443
8e8cd34e 444 /* AICCFIXFREQ1 NT N-1(Audio rejection) */
4937ba94
MCC		 445 ret = lgdt3306a_write_reg(state, 0x002b, 0x00);
446 ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
447 ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
b63b36fa 448
8e8cd34e 449 /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
b63b36fa
FR		 450 ret = lgdt3306a_write_reg(state, 0x0028, 0x00);
451 ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
4937ba94 452 ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
b63b36fa 453
8e8cd34e 454 /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
b63b36fa
FR		 455 ret = lgdt3306a_write_reg(state, 0x0025, 0x00);
456 ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
457 ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
458
8e8cd34e
MIK		 459#else
460 /* FGR - this works well for HVR-1955,1975 */
461
462 /* 5. AICCOPMODE NT N-1 Adj. */
b63b36fa
FR		 463 ret = lgdt3306a_write_reg(state, 0x0024, 0x5A);
464 if (lg_chkerr(ret))
465 goto fail;
466
8e8cd34e 467 /* AICCFIXFREQ0 NT N-1(Video rejection) */
4937ba94
MCC		 468 ret = lgdt3306a_write_reg(state, 0x002e, 0x5A);
469 ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
b63b36fa
FR		 470 ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
471
8e8cd34e 472 /* AICCFIXFREQ1 NT N-1(Audio rejection) */
4937ba94
MCC		 473 ret = lgdt3306a_write_reg(state, 0x002b, 0x36);
474 ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
475 ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
b63b36fa 476
8e8cd34e 477 /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
b63b36fa
FR		 478 ret = lgdt3306a_write_reg(state, 0x0028, 0x2A);
479 ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
4937ba94 480 ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
b63b36fa 481
8e8cd34e 482 /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
b63b36fa
FR		 483 ret = lgdt3306a_write_reg(state, 0x0025, 0x06);
484 ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
485 ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
486#endif
487
4937ba94
MCC		 488 ret = lgdt3306a_read_reg(state, 0x001e, &val);
489 val &= 0x0f;
490 val |= 0xa0;
491 ret = lgdt3306a_write_reg(state, 0x001e, val);
b63b36fa
FR		 492
493 ret = lgdt3306a_write_reg(state, 0x0022, 0x08);
494
495 ret = lgdt3306a_write_reg(state, 0x0023, 0xFF);
496
4937ba94
MCC		 497 ret = lgdt3306a_read_reg(state, 0x211f, &val);
498 val &= 0xef;
499 ret = lgdt3306a_write_reg(state, 0x211f, val);
b63b36fa
FR		 500
501 ret = lgdt3306a_write_reg(state, 0x2173, 0x01);
502
503 ret = lgdt3306a_read_reg(state, 0x1061, &val);
4937ba94 504 val &= 0xf8;
b63b36fa
FR		 505 val |= 0x04;
506 ret = lgdt3306a_write_reg(state, 0x1061, val);
507
4937ba94
MCC		 508 ret = lgdt3306a_read_reg(state, 0x103d, &val);
509 val &= 0xcf;
510 ret = lgdt3306a_write_reg(state, 0x103d, val);
b63b36fa
FR		 511
512 ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
513
514 ret = lgdt3306a_read_reg(state, 0x2141, &val);
4937ba94 515 val &= 0x3f;
b63b36fa
FR		 516 ret = lgdt3306a_write_reg(state, 0x2141, val);
517
518 ret = lgdt3306a_read_reg(state, 0x2135, &val);
4937ba94 519 val &= 0x0f;
b63b36fa
FR		 520 val |= 0x70;
521 ret = lgdt3306a_write_reg(state, 0x2135, val);
522
523 ret = lgdt3306a_read_reg(state, 0x0003, &val);
4937ba94 524 val &= 0xf7;
b63b36fa
FR		 525 ret = lgdt3306a_write_reg(state, 0x0003, val);
526
4937ba94
MCC		 527 ret = lgdt3306a_read_reg(state, 0x001c, &val);
528 val &= 0x7f;
529 ret = lgdt3306a_write_reg(state, 0x001c, val);
b63b36fa 530
8e8cd34e 531 /* 6. EQ step size */
b63b36fa 532 ret = lgdt3306a_read_reg(state, 0x2179, &val);
4937ba94 533 val &= 0xf8;
b63b36fa
FR		 534 ret = lgdt3306a_write_reg(state, 0x2179, val);
535
4937ba94
MCC		 536 ret = lgdt3306a_read_reg(state, 0x217a, &val);
537 val &= 0xf8;
538 ret = lgdt3306a_write_reg(state, 0x217a, val);
b63b36fa 539
8e8cd34e 540 /* 7. Reset */
b63b36fa
FR		 541 ret = lgdt3306a_soft_reset(state);
542 if (lg_chkerr(ret))
543 goto fail;
544
097117ca 545 dbg_info("complete\n");
b63b36fa
FR		 546fail:
547 return ret;
548}
549
550static int lgdt3306a_set_qam(struct lgdt3306a_state *state, int modulation)
551{
552 u8 val;
553 int ret;
554
097117ca 555 dbg_info("modulation=%d\n", modulation);
b63b36fa 556
8e8cd34e 557 /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
b63b36fa
FR		 558 ret = lgdt3306a_write_reg(state, 0x0008, 0x08);
559 if (lg_chkerr(ret))
560 goto fail;
561
8e8cd34e 562 /* 1a. Spectrum inversion detection to Auto */
b63b36fa 563 ret = lgdt3306a_read_reg(state, 0x0002, &val);
4937ba94 564 val &= 0xfb; /* SPECINV Off */
8e8cd34e 565 val |= 0x08; /* SPECINVAUTO On */
b63b36fa
FR		 566 ret = lgdt3306a_write_reg(state, 0x0002, val);
567 if (lg_chkerr(ret))
568 goto fail;
569
8e8cd34e 570 /* 2. Bandwidth mode for QAM */
b63b36fa 571 ret = lgdt3306a_read_reg(state, 0x0009, &val);
4937ba94 572 val &= 0xe3; /* STDOPDETTMODE[2:0]=0 VSB Off */
b63b36fa
FR		 573 ret = lgdt3306a_write_reg(state, 0x0009, val);
574 if (lg_chkerr(ret))
575 goto fail;
576
8e8cd34e 577 /* 3. : 64QAM/256QAM detection(manual, auto) */
b63b36fa 578 ret = lgdt3306a_read_reg(state, 0x0009, &val);
4937ba94 579 val &= 0xfc;
4966c0c5
BL		 580 /* Check for forced Manual modulation modes; otherwise always "auto" */
581 if(forced_manual && (modulation != QAM_AUTO)){
582 val |= 0x01; /* STDOPDETCMODE[1:0]= 1=Manual */
583 } else {
584 val |= 0x02; /* STDOPDETCMODE[1:0]= 2=Auto */
585 }
b63b36fa
FR		 586 ret = lgdt3306a_write_reg(state, 0x0009, val);
587 if (lg_chkerr(ret))
588 goto fail;
589
8e8cd34e 590 /* 3a. : 64QAM/256QAM selection for manual */
b63b36fa 591 ret = lgdt3306a_read_reg(state, 0x101a, &val);
4937ba94 592 val &= 0xf8;
8e8cd34e
MIK		 593 if (modulation == QAM_64)
594 val |= 0x02; /* QMDQMODE[2:0]=2=QAM64 */
595 else
596 val |= 0x04; /* QMDQMODE[2:0]=4=QAM256 */
597
b63b36fa
FR		 598 ret = lgdt3306a_write_reg(state, 0x101a, val);
599 if (lg_chkerr(ret))
600 goto fail;
601
8e8cd34e 602 /* 4. ADC sampling frequency rate(4x sampling) */
4937ba94
MCC		 603 ret = lgdt3306a_read_reg(state, 0x000d, &val);
604 val &= 0xbf;
8e8cd34e 605 val |= 0x40; /* SAMPLING4XFEN=1 */
4937ba94 606 ret = lgdt3306a_write_reg(state, 0x000d, val);
b63b36fa
FR		 607 if (lg_chkerr(ret))
608 goto fail;
609
8e8cd34e 610 /* 5. No AICC operation in QAM mode */
b63b36fa
FR		 611 ret = lgdt3306a_read_reg(state, 0x0024, &val);
612 val &= 0x00;
613 ret = lgdt3306a_write_reg(state, 0x0024, val);
614 if (lg_chkerr(ret))
615 goto fail;
616
4c7c3f9b
BL		 617 /* 5.1 V0.36 SRDCHKALWAYS : For better QAM detection */
618 ret = lgdt3306a_read_reg(state, 0x000a, &val);
619 val &= 0xfd;
620 val |= 0x02;
621 ret = lgdt3306a_write_reg(state, 0x000a, val);
622 if (lg_chkerr(ret))
623 goto fail;
624
625 /* 5.2 V0.36 Control of "no signal" detector function */
626 ret = lgdt3306a_read_reg(state, 0x2849, &val);
627 val &= 0xdf;
628 ret = lgdt3306a_write_reg(state, 0x2849, val);
629 if (lg_chkerr(ret))
630 goto fail;
631
632 /* 5.3 Fix for Blonder Tongue HDE-2H-QAM and AQM modulators */
633 ret = lgdt3306a_read_reg(state, 0x302b, &val);
634 val &= 0x7f; /* SELFSYNCFINDEN_CQS=0; disable auto reset */
635 ret = lgdt3306a_write_reg(state, 0x302b, val);
636 if (lg_chkerr(ret))
637 goto fail;
638
8e8cd34e 639 /* 6. Reset */
b63b36fa
FR		 640 ret = lgdt3306a_soft_reset(state);
641 if (lg_chkerr(ret))
642 goto fail;
643
097117ca 644 dbg_info("complete\n");
b63b36fa
FR		 645fail:
646 return ret;
647}
648
649static int lgdt3306a_set_modulation(struct lgdt3306a_state *state,
650 struct dtv_frontend_properties *p)
651{
652 int ret;
653
097117ca 654 dbg_info("\n");
b63b36fa
FR		 655
656 switch (p->modulation) {
657 case VSB_8:
658 ret = lgdt3306a_set_vsb(state);
659 break;
660 case QAM_64:
b63b36fa 661 case QAM_256:
4966c0c5
BL		 662 case QAM_AUTO:
663 ret = lgdt3306a_set_qam(state, p->modulation);
b63b36fa
FR		 664 break;
665 default:
666 return -EINVAL;
667 }
668 if (lg_chkerr(ret))
669 goto fail;
670
671 state->current_modulation = p->modulation;
672
673fail:
674 return ret;
675}
676
677/* ------------------------------------------------------------------------ */
678
679static int lgdt3306a_agc_setup(struct lgdt3306a_state *state,
680 struct dtv_frontend_properties *p)
681{
8e8cd34e 682 /* TODO: anything we want to do here??? */
097117ca 683 dbg_info("\n");
b63b36fa
FR		 684
685 switch (p->modulation) {
686 case VSB_8:
687 break;
688 case QAM_64:
689 case QAM_256:
4966c0c5 690 case QAM_AUTO:
b63b36fa
FR		 691 break;
692 default:
693 return -EINVAL;
694 }
695 return 0;
696}
697
698/* ------------------------------------------------------------------------ */
699
700static int lgdt3306a_set_inversion(struct lgdt3306a_state *state,
701 int inversion)
702{
703 int ret;
704
097117ca 705 dbg_info("(%d)\n", inversion);
b63b36fa 706
8e8cd34e 707 ret = lgdt3306a_set_reg_bit(state, 0x0002, 2, inversion ? 1 : 0);
b63b36fa
FR		 708 return ret;
709}
710
711static int lgdt3306a_set_inversion_auto(struct lgdt3306a_state *state,
712 int enabled)
713{
714 int ret;
715
097117ca 716 dbg_info("(%d)\n", enabled);
b63b36fa 717
534f4364
MCC		 718 /* 0=Manual 1=Auto(QAM only) - SPECINVAUTO=0x04 */
719 ret = lgdt3306a_set_reg_bit(state, 0x0002, 3, enabled);
b63b36fa
FR		 720 return ret;
721}
722
723static int lgdt3306a_spectral_inversion(struct lgdt3306a_state *state,
724 struct dtv_frontend_properties *p,
725 int inversion)
726{
727 int ret = 0;
728
097117ca 729 dbg_info("(%d)\n", inversion);
8e8cd34e 730#if 0
534f4364
MCC		 731 /*
732 * FGR - spectral_inversion defaults already set for VSB and QAM;
733 * can enable later if desired
734 */
b63b36fa
FR		 735
736 ret = lgdt3306a_set_inversion(state, inversion);
737
738 switch (p->modulation) {
739 case VSB_8:
534f4364
MCC		 740 /* Manual only for VSB */
741 ret = lgdt3306a_set_inversion_auto(state, 0);
b63b36fa
FR		 742 break;
743 case QAM_64:
744 case QAM_256:
4966c0c5 745 case QAM_AUTO:
534f4364
MCC		 746 /* Auto ok for QAM */
747 ret = lgdt3306a_set_inversion_auto(state, 1);
b63b36fa
FR		 748 break;
749 default:
750 ret = -EINVAL;
751 }
752#endif
753 return ret;
754}
755
756static int lgdt3306a_set_if(struct lgdt3306a_state *state,
757 struct dtv_frontend_properties *p)
758{
759 int ret;
760 u16 if_freq_khz;
761 u8 nco1, nco2;
762
763 switch (p->modulation) {
764 case VSB_8:
765 if_freq_khz = state->cfg->vsb_if_khz;
766 break;
767 case QAM_64:
768 case QAM_256:
4966c0c5 769 case QAM_AUTO:
b63b36fa
FR		 770 if_freq_khz = state->cfg->qam_if_khz;
771 break;
772 default:
773 return -EINVAL;
774 }
775
8e8cd34e 776 switch (if_freq_khz) {
b63b36fa 777 default:
f86548cf 778 pr_warn("IF=%d KHz is not supported, 3250 assumed\n",
534f4364 779 if_freq_khz);
8e8cd34e 780 /* fallthrough */
34a5a2f8 781 case 3250: /* 3.25Mhz */
b63b36fa
FR		 782 nco1 = 0x34;
783 nco2 = 0x00;
784 break;
34a5a2f8 785 case 3500: /* 3.50Mhz */
b63b36fa
FR		 786 nco1 = 0x38;
787 nco2 = 0x00;
788 break;
34a5a2f8 789 case 4000: /* 4.00Mhz */
b63b36fa
FR		 790 nco1 = 0x40;
791 nco2 = 0x00;
792 break;
34a5a2f8 793 case 5000: /* 5.00Mhz */
b63b36fa
FR		 794 nco1 = 0x50;
795 nco2 = 0x00;
796 break;
8e8cd34e 797 case 5380: /* 5.38Mhz */
b63b36fa
FR		 798 nco1 = 0x56;
799 nco2 = 0x14;
800 break;
801 }
802 ret = lgdt3306a_write_reg(state, 0x0010, nco1);
ee0133ee
MCC		 803 if (ret)
804 return ret;
b63b36fa 805 ret = lgdt3306a_write_reg(state, 0x0011, nco2);
ee0133ee
MCC		 806 if (ret)
807 return ret;
b63b36fa 808
097117ca 809 dbg_info("if_freq=%d KHz->[%04x]\n", if_freq_khz, nco1<<8 | nco2);
b63b36fa
FR		 810
811 return 0;
812}
813
814/* ------------------------------------------------------------------------ */
815
816static int lgdt3306a_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
817{
818 struct lgdt3306a_state *state = fe->demodulator_priv;
819
8e8cd34e 820 if (state->cfg->deny_i2c_rptr) {
097117ca 821 dbg_info("deny_i2c_rptr=%d\n", state->cfg->deny_i2c_rptr);
b63b36fa
FR		 822 return 0;
823 }
097117ca 824 dbg_info("(%d)\n", enable);
b63b36fa 825
534f4364
MCC		 826 /* NI2CRPTEN=0x80 */
827 return lgdt3306a_set_reg_bit(state, 0x0002, 7, enable ? 0 : 1);
b63b36fa
FR		 828}
829
830static int lgdt3306a_sleep(struct lgdt3306a_state *state)
831{
832 int ret;
833
097117ca 834 dbg_info("\n");
8e8cd34e 835 state->current_frequency = -1; /* force re-tune, when we wake */
b63b36fa 836
8e8cd34e 837 ret = lgdt3306a_mpeg_tristate(state, 1); /* disable data bus */
b63b36fa
FR		 838 if (lg_chkerr(ret))
839 goto fail;
840
8e8cd34e 841 ret = lgdt3306a_power(state, 0); /* power down */
b63b36fa
FR		 842 lg_chkerr(ret);
843
844fail:
845 return 0;
846}
847
848static int lgdt3306a_fe_sleep(struct dvb_frontend *fe)
849{
850 struct lgdt3306a_state *state = fe->demodulator_priv;
851
852 return lgdt3306a_sleep(state);
853}
854
855static int lgdt3306a_init(struct dvb_frontend *fe)
856{
857 struct lgdt3306a_state *state = fe->demodulator_priv;
858 u8 val;
859 int ret;
860
097117ca 861 dbg_info("\n");
b63b36fa 862
8e8cd34e
MIK		 863 /* 1. Normal operation mode */
864 ret = lgdt3306a_set_reg_bit(state, 0x0001, 0, 1); /* SIMFASTENB=0x01 */
b63b36fa
FR		 865 if (lg_chkerr(ret))
866 goto fail;
867
8e8cd34e 868 /* 2. Spectrum inversion auto detection (Not valid for VSB) */
b63b36fa
FR		 869 ret = lgdt3306a_set_inversion_auto(state, 0);
870 if (lg_chkerr(ret))
871 goto fail;
872
8e8cd34e 873 /* 3. Spectrum inversion(According to the tuner configuration) */
b63b36fa
FR		 874 ret = lgdt3306a_set_inversion(state, 1);
875 if (lg_chkerr(ret))
876 goto fail;
877
8e8cd34e 878 /* 4. Peak-to-peak voltage of ADC input signal */
534f4364
MCC		 879
880 /* ADCSEL1V=0x80=1Vpp; 0x00=2Vpp */
881 ret = lgdt3306a_set_reg_bit(state, 0x0004, 7, 1);
b63b36fa
FR		 882 if (lg_chkerr(ret))
883 goto fail;
884
8e8cd34e 885 /* 5. ADC output data capture clock phase */
534f4364
MCC		 886
887 /* 0=same phase as ADC clock */
888 ret = lgdt3306a_set_reg_bit(state, 0x0004, 2, 0);
b63b36fa
FR		 889 if (lg_chkerr(ret))
890 goto fail;
891
8e8cd34e 892 /* 5a. ADC sampling clock source */
534f4364
MCC		 893
894 /* ADCCLKPLLSEL=0x08; 0=use ext clock, not PLL */
895 ret = lgdt3306a_set_reg_bit(state, 0x0004, 3, 0);
b63b36fa
FR		 896 if (lg_chkerr(ret))
897 goto fail;
898
8e8cd34e 899 /* 6. Automatic PLL set */
534f4364
MCC		 900
901 /* PLLSETAUTO=0x40; 0=off */
902 ret = lgdt3306a_set_reg_bit(state, 0x0005, 6, 0);
b63b36fa
FR		 903 if (lg_chkerr(ret))
904 goto fail;
905
8e8cd34e
MIK		 906 if (state->cfg->xtalMHz == 24) { /* 24MHz */
907 /* 7. Frequency for PLL output(0x2564 for 192MHz for 24MHz) */
b63b36fa
FR		 908 ret = lgdt3306a_read_reg(state, 0x0005, &val);
909 if (lg_chkerr(ret))
910 goto fail;
4937ba94 911 val &= 0xc0;
b63b36fa
FR		 912 val |= 0x25;
913 ret = lgdt3306a_write_reg(state, 0x0005, val);
914 if (lg_chkerr(ret))
915 goto fail;
916 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
917 if (lg_chkerr(ret))
918 goto fail;
919
8e8cd34e 920 /* 8. ADC sampling frequency(0x180000 for 24MHz sampling) */
4937ba94 921 ret = lgdt3306a_read_reg(state, 0x000d, &val);
b63b36fa
FR		 922 if (lg_chkerr(ret))
923 goto fail;
4937ba94 924 val &= 0xc0;
b63b36fa 925 val |= 0x18;
4937ba94 926 ret = lgdt3306a_write_reg(state, 0x000d, val);
b63b36fa
FR		 927 if (lg_chkerr(ret))
928 goto fail;
929
8e8cd34e
MIK		 930 } else if (state->cfg->xtalMHz == 25) { /* 25MHz */
931 /* 7. Frequency for PLL output */
b63b36fa
FR		 932 ret = lgdt3306a_read_reg(state, 0x0005, &val);
933 if (lg_chkerr(ret))
934 goto fail;
4937ba94 935 val &= 0xc0;
b63b36fa
FR		 936 val |= 0x25;
937 ret = lgdt3306a_write_reg(state, 0x0005, val);
938 if (lg_chkerr(ret))
939 goto fail;
940 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
941 if (lg_chkerr(ret))
942 goto fail;
943
8e8cd34e 944 /* 8. ADC sampling frequency(0x190000 for 25MHz sampling) */
4937ba94 945 ret = lgdt3306a_read_reg(state, 0x000d, &val);
b63b36fa
FR		 946 if (lg_chkerr(ret))
947 goto fail;
4937ba94 948 val &= 0xc0;
b63b36fa 949 val |= 0x19;
4937ba94 950 ret = lgdt3306a_write_reg(state, 0x000d, val);
b63b36fa
FR		 951 if (lg_chkerr(ret))
952 goto fail;
953 } else {
097117ca 954 pr_err("Bad xtalMHz=%d\n", state->cfg->xtalMHz);
b63b36fa 955 }
8e8cd34e 956#if 0
4937ba94
MCC		 957 ret = lgdt3306a_write_reg(state, 0x000e, 0x00);
958 ret = lgdt3306a_write_reg(state, 0x000f, 0x00);
8e8cd34e 959#endif
b63b36fa 960
8e8cd34e
MIK		 961 /* 9. Center frequency of input signal of ADC */
962 ret = lgdt3306a_write_reg(state, 0x0010, 0x34); /* 3.25MHz */
963 ret = lgdt3306a_write_reg(state, 0x0011, 0x00);
b63b36fa 964
8e8cd34e
MIK		 965 /* 10. Fixed gain error value */
966 ret = lgdt3306a_write_reg(state, 0x0014, 0); /* gain error=0 */
b63b36fa 967
8e8cd34e 968 /* 10a. VSB TR BW gear shift initial step */
4937ba94
MCC		 969 ret = lgdt3306a_read_reg(state, 0x103c, &val);
970 val &= 0x0f;
8e8cd34e 971 val |= 0x20; /* SAMGSAUTOSTL_V[3:0] = 2 */
4937ba94 972 ret = lgdt3306a_write_reg(state, 0x103c, val);
b63b36fa 973
8e8cd34e 974 /* 10b. Timing offset calibration in low temperature for VSB */
4937ba94
MCC		 975 ret = lgdt3306a_read_reg(state, 0x103d, &val);
976 val &= 0xfc;
b63b36fa 977 val |= 0x03;
4937ba94 978 ret = lgdt3306a_write_reg(state, 0x103d, val);
b63b36fa 979
8e8cd34e 980 /* 10c. Timing offset calibration in low temperature for QAM */
b63b36fa 981 ret = lgdt3306a_read_reg(state, 0x1036, &val);
4937ba94
MCC		 982 val &= 0xf0;
983 val |= 0x0c;
b63b36fa
FR		 984 ret = lgdt3306a_write_reg(state, 0x1036, val);
985
8e8cd34e 986 /* 11. Using the imaginary part of CIR in CIR loading */
4937ba94
MCC		 987 ret = lgdt3306a_read_reg(state, 0x211f, &val);
988 val &= 0xef; /* do not use imaginary of CIR */
989 ret = lgdt3306a_write_reg(state, 0x211f, val);
b63b36fa 990
8e8cd34e 991 /* 12. Control of no signal detector function */
b63b36fa 992 ret = lgdt3306a_read_reg(state, 0x2849, &val);
4937ba94 993 val &= 0xef; /* NOUSENOSIGDET=0, enable no signal detector */
b63b36fa
FR		 994 ret = lgdt3306a_write_reg(state, 0x2849, val);
995
8e8cd34e 996 /* FGR - put demod in some known mode */
b63b36fa
FR		 997 ret = lgdt3306a_set_vsb(state);
998
8e8cd34e 999 /* 13. TP stream format */
b63b36fa
FR		 1000 ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
1001
8e8cd34e 1002 /* 14. disable output buses */
b63b36fa
FR		 1003 ret = lgdt3306a_mpeg_tristate(state, 1);
1004
8e8cd34e 1005 /* 15. Sleep (in reset) */
b63b36fa
FR		 1006 ret = lgdt3306a_sleep(state);
1007 lg_chkerr(ret);
1008
1009fail:
1010 return ret;
1011}
1012
1013static int lgdt3306a_set_parameters(struct dvb_frontend *fe)
1014{
1015 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1016 struct lgdt3306a_state *state = fe->demodulator_priv;
1017 int ret;
1018
097117ca 1019 dbg_info("(%d, %d)\n", p->frequency, p->modulation);
b63b36fa 1020
8e8cd34e
MIK		 1021 if (state->current_frequency == p->frequency &&
1022 state->current_modulation == p->modulation) {
097117ca 1023 dbg_info(" (already set, skipping ...)\n");
b63b36fa
FR		 1024 return 0;
1025 }
1026 state->current_frequency = -1;
1027 state->current_modulation = -1;
1028
8e8cd34e 1029 ret = lgdt3306a_power(state, 1); /* power up */
b63b36fa
FR		 1030 if (lg_chkerr(ret))
1031 goto fail;
1032
1033 if (fe->ops.tuner_ops.set_params) {
1034 ret = fe->ops.tuner_ops.set_params(fe);
1035 if (fe->ops.i2c_gate_ctrl)
1036 fe->ops.i2c_gate_ctrl(fe, 0);
8e8cd34e
MIK		 1037#if 0
1038 if (lg_chkerr(ret))
1039 goto fail;
1040 state->current_frequency = p->frequency;
1041#endif
b63b36fa
FR		 1042 }
1043
1044 ret = lgdt3306a_set_modulation(state, p);
1045 if (lg_chkerr(ret))
1046 goto fail;
1047
1048 ret = lgdt3306a_agc_setup(state, p);
1049 if (lg_chkerr(ret))
1050 goto fail;
1051
1052 ret = lgdt3306a_set_if(state, p);
1053 if (lg_chkerr(ret))
1054 goto fail;
1055
1056 ret = lgdt3306a_spectral_inversion(state, p,
534f4364 1057 state->cfg->spectral_inversion ? 1 : 0);
b63b36fa
FR		 1058 if (lg_chkerr(ret))
1059 goto fail;
1060
1061 ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
1062 if (lg_chkerr(ret))
1063 goto fail;
1064
1065 ret = lgdt3306a_mpeg_mode_polarity(state,
1066 state->cfg->tpclk_edge,
1067 state->cfg->tpvalid_polarity);
1068 if (lg_chkerr(ret))
1069 goto fail;
1070
8e8cd34e 1071 ret = lgdt3306a_mpeg_tristate(state, 0); /* enable data bus */
b63b36fa
FR		 1072 if (lg_chkerr(ret))
1073 goto fail;
1074
1075 ret = lgdt3306a_soft_reset(state);
1076 if (lg_chkerr(ret))
1077 goto fail;
1078
1079#ifdef DBG_DUMP
1080 lgdt3306a_DumpAllRegs(state);
1081#endif
1082 state->current_frequency = p->frequency;
1083fail:
1084 return ret;
1085}
1086
7e3e68bc
MCC		 1087static int lgdt3306a_get_frontend(struct dvb_frontend *fe,
1088 struct dtv_frontend_properties *p)
b63b36fa
FR		 1089{
1090 struct lgdt3306a_state *state = fe->demodulator_priv;
b63b36fa 1091
534f4364
MCC		 1092 dbg_info("(%u, %d)\n",
1093 state->current_frequency, state->current_modulation);
b63b36fa
FR		 1094
1095 p->modulation = state->current_modulation;
1096 p->frequency = state->current_frequency;
1097 return 0;
1098}
1099
1100static enum dvbfe_algo lgdt3306a_get_frontend_algo(struct dvb_frontend *fe)
1101{
1102#if 1
1103 return DVBFE_ALGO_CUSTOM;
1104#else
1105 return DVBFE_ALGO_HW;
1106#endif
1107}
1108
1109/* ------------------------------------------------------------------------ */
ee0133ee 1110static int lgdt3306a_monitor_vsb(struct lgdt3306a_state *state)
b63b36fa
FR		 1111{
1112 u8 val;
1113 int ret;
8e8cd34e
MIK		 1114 u8 snrRef, maxPowerMan, nCombDet;
1115 u16 fbDlyCir;
b63b36fa 1116
4937ba94 1117 ret = lgdt3306a_read_reg(state, 0x21a1, &val);
ee0133ee
MCC		 1118 if (ret)
1119 return ret;
4937ba94 1120 snrRef = val & 0x3f;
b63b36fa
FR		 1121
1122 ret = lgdt3306a_read_reg(state, 0x2185, &maxPowerMan);
ee0133ee
MCC		 1123 if (ret)
1124 return ret;
b63b36fa
FR		 1125
1126 ret = lgdt3306a_read_reg(state, 0x2191, &val);
ee0133ee
MCC		 1127 if (ret)
1128 return ret;
b63b36fa
FR		 1129 nCombDet = (val & 0x80) >> 7;
1130
1131 ret = lgdt3306a_read_reg(state, 0x2180, &val);
ee0133ee
MCC		 1132 if (ret)
1133 return ret;
b63b36fa 1134 fbDlyCir = (val & 0x03) << 8;
ee0133ee 1135
b63b36fa 1136 ret = lgdt3306a_read_reg(state, 0x2181, &val);
ee0133ee
MCC		 1137 if (ret)
1138 return ret;
b63b36fa
FR		 1139 fbDlyCir |= val;
1140
097117ca 1141 dbg_info("snrRef=%d maxPowerMan=0x%x nCombDet=%d fbDlyCir=0x%x\n",
b63b36fa
FR		 1142 snrRef, maxPowerMan, nCombDet, fbDlyCir);
1143
8e8cd34e 1144 /* Carrier offset sub loop bandwidth */
b63b36fa 1145 ret = lgdt3306a_read_reg(state, 0x1061, &val);
ee0133ee
MCC		 1146 if (ret)
1147 return ret;
4937ba94 1148 val &= 0xf8;
534f4364
MCC		 1149 if ((snrRef > 18) && (maxPowerMan > 0x68)
1150 && (nCombDet == 0x01)
1151 && ((fbDlyCir == 0x03FF) || (fbDlyCir < 0x6C))) {
8e8cd34e
MIK		 1152 /* SNR is over 18dB and no ghosting */
1153 val |= 0x00; /* final bandwidth = 0 */
b63b36fa 1154 } else {
8e8cd34e 1155 val |= 0x04; /* final bandwidth = 4 */
b63b36fa
FR		 1156 }
1157 ret = lgdt3306a_write_reg(state, 0x1061, val);
ee0133ee
MCC		 1158 if (ret)
1159 return ret;
b63b36fa 1160
8e8cd34e 1161 /* Adjust Notch Filter */
b63b36fa 1162 ret = lgdt3306a_read_reg(state, 0x0024, &val);
ee0133ee
MCC		 1163 if (ret)
1164 return ret;
4937ba94 1165 val &= 0x0f;
8e8cd34e 1166 if (nCombDet == 0) { /* Turn on the Notch Filter */
b63b36fa
FR		 1167 val |= 0x50;
1168 }
1169 ret = lgdt3306a_write_reg(state, 0x0024, val);
ee0133ee
MCC		 1170 if (ret)
1171 return ret;
b63b36fa 1172
8e8cd34e 1173 /* VSB Timing Recovery output normalization */
4937ba94 1174 ret = lgdt3306a_read_reg(state, 0x103d, &val);
ee0133ee
MCC		 1175 if (ret)
1176 return ret;
4937ba94 1177 val &= 0xcf;
b63b36fa 1178 val |= 0x20;
4937ba94 1179 ret = lgdt3306a_write_reg(state, 0x103d, val);
ee0133ee
MCC		 1180
1181 return ret;
b63b36fa
FR		 1182}
1183
534f4364
MCC		 1184static enum lgdt3306a_modulation
1185lgdt3306a_check_oper_mode(struct lgdt3306a_state *state)
b63b36fa
FR		 1186{
1187 u8 val = 0;
1188 int ret;
1189
1190 ret = lgdt3306a_read_reg(state, 0x0081, &val);
ee0133ee
MCC		 1191 if (ret)
1192 goto err;
b63b36fa
FR		 1193
1194 if (val & 0x80) {
097117ca 1195 dbg_info("VSB\n");
8e8cd34e 1196 return LG3306_VSB;
b63b36fa 1197 }
c714efe4 1198 if (val & 0x08) {
4937ba94 1199 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
ee0133ee
MCC		 1200 if (ret)
1201 goto err;
b63b36fa
FR		 1202 val = val >> 2;
1203 if (val & 0x01) {
097117ca 1204 dbg_info("QAM256\n");
8e8cd34e 1205 return LG3306_QAM256;
b63b36fa 1206 }
b4e43e95
MCC		 1207 dbg_info("QAM64\n");
1208 return LG3306_QAM64;
b63b36fa 1209 }
ee0133ee 1210err:
097117ca 1211 pr_warn("UNKNOWN\n");
8e8cd34e 1212 return LG3306_UNKNOWN_MODE;
b63b36fa
FR		 1213}
1214
534f4364
MCC		 1215static enum lgdt3306a_lock_status
1216lgdt3306a_check_lock_status(struct lgdt3306a_state *state,
1217 enum lgdt3306a_lock_check whatLock)
b63b36fa
FR		 1218{
1219 u8 val = 0;
1220 int ret;
f883d603
MIK		 1221 enum lgdt3306a_modulation modeOper;
1222 enum lgdt3306a_lock_status lockStatus;
b63b36fa
FR		 1223
1224 modeOper = LG3306_UNKNOWN_MODE;
1225
8e8cd34e
MIK		 1226 switch (whatLock) {
1227 case LG3306_SYNC_LOCK:
1228 {
4937ba94 1229 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
ee0133ee
MCC		 1230 if (ret)
1231 return ret;
8e8cd34e
MIK		 1232
1233 if ((val & 0x80) == 0x80)
1234 lockStatus = LG3306_LOCK;
1235 else
1236 lockStatus = LG3306_UNLOCK;
1237
097117ca 1238 dbg_info("SYNC_LOCK=%x\n", lockStatus);
8e8cd34e
MIK		 1239 break;
1240 }
1241 case LG3306_AGC_LOCK:
1242 {
1243 ret = lgdt3306a_read_reg(state, 0x0080, &val);
ee0133ee
MCC		 1244 if (ret)
1245 return ret;
8e8cd34e
MIK		 1246
1247 if ((val & 0x40) == 0x40)
1248 lockStatus = LG3306_LOCK;
1249 else
1250 lockStatus = LG3306_UNLOCK;
1251
097117ca 1252 dbg_info("AGC_LOCK=%x\n", lockStatus);
8e8cd34e
MIK		 1253 break;
1254 }
1255 case LG3306_TR_LOCK:
b63b36fa 1256 {
8e8cd34e
MIK		 1257 modeOper = lgdt3306a_check_oper_mode(state);
1258 if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
1259 ret = lgdt3306a_read_reg(state, 0x1094, &val);
ee0133ee
MCC		 1260 if (ret)
1261 return ret;
b63b36fa
FR		 1262
1263 if ((val & 0x80) == 0x80)
1264 lockStatus = LG3306_LOCK;
1265 else
1266 lockStatus = LG3306_UNLOCK;
8e8cd34e
MIK		 1267 } else
1268 lockStatus = LG3306_UNKNOWN_LOCK;
b63b36fa 1269
097117ca 1270 dbg_info("TR_LOCK=%x\n", lockStatus);
8e8cd34e
MIK		 1271 break;
1272 }
1273 case LG3306_FEC_LOCK:
1274 {
1275 modeOper = lgdt3306a_check_oper_mode(state);
1276 if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
b63b36fa 1277 ret = lgdt3306a_read_reg(state, 0x0080, &val);
ee0133ee
MCC		 1278 if (ret)
1279 return ret;
b63b36fa 1280
8e8cd34e 1281 if ((val & 0x10) == 0x10)
b63b36fa
FR		 1282 lockStatus = LG3306_LOCK;
1283 else
1284 lockStatus = LG3306_UNLOCK;
8e8cd34e
MIK		 1285 } else
1286 lockStatus = LG3306_UNKNOWN_LOCK;
b63b36fa 1287
097117ca 1288 dbg_info("FEC_LOCK=%x\n", lockStatus);
8e8cd34e
MIK		 1289 break;
1290 }
b63b36fa 1291
8e8cd34e
MIK		 1292 default:
1293 lockStatus = LG3306_UNKNOWN_LOCK;
097117ca 1294 pr_warn("UNKNOWN whatLock=%d\n", whatLock);
8e8cd34e 1295 break;
b63b36fa
FR		 1296 }
1297
8e8cd34e 1298 return lockStatus;
b63b36fa
FR		 1299}
1300
534f4364
MCC		 1301static enum lgdt3306a_neverlock_status
1302lgdt3306a_check_neverlock_status(struct lgdt3306a_state *state)
b63b36fa
FR		 1303{
1304 u8 val = 0;
1305 int ret;
f883d603 1306 enum lgdt3306a_neverlock_status lockStatus;
b63b36fa
FR		 1307
1308 ret = lgdt3306a_read_reg(state, 0x0080, &val);
ee0133ee
MCC		 1309 if (ret)
1310 return ret;
f883d603 1311 lockStatus = (enum lgdt3306a_neverlock_status)(val & 0x03);
b63b36fa 1312
097117ca 1313 dbg_info("NeverLock=%d", lockStatus);
b63b36fa 1314
8e8cd34e 1315 return lockStatus;
b63b36fa
FR		 1316}
1317
ee0133ee 1318static int lgdt3306a_pre_monitoring(struct lgdt3306a_state *state)
b63b36fa
FR		 1319{
1320 u8 val = 0;
1321 int ret;
1322 u8 currChDiffACQ, snrRef, mainStrong, aiccrejStatus;
1323
8e8cd34e 1324 /* Channel variation */
4937ba94 1325 ret = lgdt3306a_read_reg(state, 0x21bc, &currChDiffACQ);
ee0133ee
MCC		 1326 if (ret)
1327 return ret;
b63b36fa 1328
8e8cd34e 1329 /* SNR of Frame sync */
4937ba94 1330 ret = lgdt3306a_read_reg(state, 0x21a1, &val);
ee0133ee
MCC		 1331 if (ret)
1332 return ret;
4937ba94 1333 snrRef = val & 0x3f;
b63b36fa 1334
8e8cd34e 1335 /* Strong Main CIR */
b63b36fa 1336 ret = lgdt3306a_read_reg(state, 0x2199, &val);
ee0133ee
MCC		 1337 if (ret)
1338 return ret;
b63b36fa
FR		 1339 mainStrong = (val & 0x40) >> 6;
1340
1341 ret = lgdt3306a_read_reg(state, 0x0090, &val);
ee0133ee
MCC		 1342 if (ret)
1343 return ret;
4937ba94 1344 aiccrejStatus = (val & 0xf0) >> 4;
b63b36fa 1345
097117ca 1346 dbg_info("snrRef=%d mainStrong=%d aiccrejStatus=%d currChDiffACQ=0x%x\n",
b63b36fa
FR		 1347 snrRef, mainStrong, aiccrejStatus, currChDiffACQ);
1348
8e8cd34e 1349#if 0
534f4364
MCC		 1350 /* Dynamic ghost exists */
1351 if ((mainStrong == 0) && (currChDiffACQ > 0x70))
8e8cd34e
MIK		 1352#endif
1353 if (mainStrong == 0) {
b63b36fa 1354 ret = lgdt3306a_read_reg(state, 0x2135, &val);
ee0133ee
MCC		 1355 if (ret)
1356 return ret;
4937ba94
MCC		 1357 val &= 0x0f;
1358 val |= 0xa0;
b63b36fa 1359 ret = lgdt3306a_write_reg(state, 0x2135, val);
ee0133ee
MCC		 1360 if (ret)
1361 return ret;
b63b36fa
FR		 1362
1363 ret = lgdt3306a_read_reg(state, 0x2141, &val);
ee0133ee
MCC		 1364 if (ret)
1365 return ret;
4937ba94 1366 val &= 0x3f;
b63b36fa
FR		 1367 val |= 0x80;
1368 ret = lgdt3306a_write_reg(state, 0x2141, val);
ee0133ee
MCC		 1369 if (ret)
1370 return ret;
b63b36fa
FR		 1371
1372 ret = lgdt3306a_write_reg(state, 0x2122, 0x70);
ee0133ee
MCC		 1373 if (ret)
1374 return ret;
8e8cd34e 1375 } else { /* Weak ghost or static channel */
b63b36fa 1376 ret = lgdt3306a_read_reg(state, 0x2135, &val);
ee0133ee
MCC		 1377 if (ret)
1378 return ret;
4937ba94 1379 val &= 0x0f;
b63b36fa
FR		 1380 val |= 0x70;
1381 ret = lgdt3306a_write_reg(state, 0x2135, val);
ee0133ee
MCC		 1382 if (ret)
1383 return ret;
b63b36fa
FR		 1384
1385 ret = lgdt3306a_read_reg(state, 0x2141, &val);
ee0133ee
MCC		 1386 if (ret)
1387 return ret;
4937ba94 1388 val &= 0x3f;
b63b36fa
FR		 1389 val |= 0x40;
1390 ret = lgdt3306a_write_reg(state, 0x2141, val);
ee0133ee
MCC		 1391 if (ret)
1392 return ret;
b63b36fa
FR		 1393
1394 ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
ee0133ee
MCC		 1395 if (ret)
1396 return ret;
b63b36fa 1397 }
ee0133ee 1398 return 0;
b63b36fa
FR		 1399}
1400
534f4364
MCC		 1401static enum lgdt3306a_lock_status
1402lgdt3306a_sync_lock_poll(struct lgdt3306a_state *state)
b63b36fa 1403{
f883d603 1404 enum lgdt3306a_lock_status syncLockStatus = LG3306_UNLOCK;
b63b36fa
FR		 1405 int i;
1406
1407 for (i = 0; i < 2; i++) {
1408 msleep(30);
1409
534f4364
MCC		 1410 syncLockStatus = lgdt3306a_check_lock_status(state,
1411 LG3306_SYNC_LOCK);
b63b36fa
FR		 1412
1413 if (syncLockStatus == LG3306_LOCK) {
097117ca 1414 dbg_info("locked(%d)\n", i);
8e8cd34e 1415 return LG3306_LOCK;
b63b36fa
FR		 1416 }
1417 }
097117ca 1418 dbg_info("not locked\n");
8e8cd34e 1419 return LG3306_UNLOCK;
b63b36fa
FR		 1420}
1421
534f4364
MCC		 1422static enum lgdt3306a_lock_status
1423lgdt3306a_fec_lock_poll(struct lgdt3306a_state *state)
b63b36fa 1424{
f883d603 1425 enum lgdt3306a_lock_status FECLockStatus = LG3306_UNLOCK;
b63b36fa
FR		 1426 int i;
1427
1428 for (i = 0; i < 2; i++) {
1429 msleep(30);
1430
534f4364
MCC		 1431 FECLockStatus = lgdt3306a_check_lock_status(state,
1432 LG3306_FEC_LOCK);
b63b36fa
FR		 1433
1434 if (FECLockStatus == LG3306_LOCK) {
097117ca 1435 dbg_info("locked(%d)\n", i);
8e8cd34e 1436 return FECLockStatus;
b63b36fa
FR		 1437 }
1438 }
097117ca 1439 dbg_info("not locked\n");
8e8cd34e 1440 return FECLockStatus;
b63b36fa
FR		 1441}
1442
534f4364
MCC		 1443static enum lgdt3306a_neverlock_status
1444lgdt3306a_neverlock_poll(struct lgdt3306a_state *state)
b63b36fa 1445{
f883d603 1446 enum lgdt3306a_neverlock_status NLLockStatus = LG3306_NL_FAIL;
b63b36fa
FR		 1447 int i;
1448
8e8cd34e 1449 for (i = 0; i < 5; i++) {
b63b36fa
FR		 1450 msleep(30);
1451
1452 NLLockStatus = lgdt3306a_check_neverlock_status(state);
1453
1454 if (NLLockStatus == LG3306_NL_LOCK) {
097117ca 1455 dbg_info("NL_LOCK(%d)\n", i);
8e8cd34e 1456 return NLLockStatus;
b63b36fa
FR		 1457 }
1458 }
097117ca 1459 dbg_info("NLLockStatus=%d\n", NLLockStatus);
8e8cd34e 1460 return NLLockStatus;
b63b36fa
FR		 1461}
1462
1463static u8 lgdt3306a_get_packet_error(struct lgdt3306a_state *state)
1464{
1465 u8 val;
1466 int ret;
1467
4937ba94 1468 ret = lgdt3306a_read_reg(state, 0x00fa, &val);
ee0133ee
MCC		 1469 if (ret)
1470 return ret;
b63b36fa 1471
8e8cd34e 1472 return val;
b63b36fa
FR		 1473}
1474
9369fe01
MCC		 1475static const u32 valx_x10[] = {
1476 10, 11, 13, 15, 17, 20, 25, 33, 41, 50, 59, 73, 87, 100
1477};
1478static const u32 log10x_x1000[] = {
95f22c5a 1479 0, 41, 114, 176, 230, 301, 398, 518, 613, 699, 771, 863, 939, 1000
9369fe01
MCC		 1480};
1481
b63b36fa
FR		 1482static u32 log10_x1000(u32 x)
1483{
a132fef8 1484 u32 diff_val, step_val, step_log10;
b63b36fa 1485 u32 log_val = 0;
8e8cd34e 1486 u32 i;
b63b36fa 1487
8e8cd34e
MIK		 1488 if (x <= 0)
1489 return -1000000; /* signal error */
b63b36fa 1490
b4e43e95
MCC		 1491 if (x == 10)
1492 return 0; /* log(1)=0 */
1493
8e8cd34e
MIK		 1494 if (x < 10) {
1495 while (x < 10) {
1496 x = x * 10;
b63b36fa
FR		 1497 log_val--;
1498 }
b4e43e95 1499 } else { /* x > 10 */
8e8cd34e
MIK		 1500 while (x >= 100) {
1501 x = x / 10;
b63b36fa
FR		 1502 log_val++;
1503 }
8e8cd34e 1504 }
b63b36fa
FR		 1505 log_val *= 1000;
1506
8e8cd34e
MIK		 1507 if (x == 10) /* was our input an exact multiple of 10 */
1508 return log_val; /* don't need to interpolate */
b63b36fa 1509
8e8cd34e 1510 /* find our place on the log curve */
9369fe01 1511 for (i = 1; i < ARRAY_SIZE(valx_x10); i++) {
8e8cd34e
MIK		 1512 if (valx_x10[i] >= x)
1513 break;
b63b36fa 1514 }
9369fe01 1515 if (i == ARRAY_SIZE(valx_x10))
a132fef8 1516 return log_val + log10x_x1000[i - 1];
b63b36fa 1517
a132fef8
MCC		 1518 diff_val = x - valx_x10[i-1];
1519 step_val = valx_x10[i] - valx_x10[i - 1];
1520 step_log10 = log10x_x1000[i] - log10x_x1000[i - 1];
1521
1522 /* do a linear interpolation to get in-between values */
1523 return log_val + log10x_x1000[i - 1] +
1524 ((diff_val*step_log10) / step_val);
b63b36fa
FR		 1525}
1526
1527static u32 lgdt3306a_calculate_snr_x100(struct lgdt3306a_state *state)
1528{
34a5a2f8
MIK		 1529 u32 mse; /* Mean-Square Error */
1530 u32 pwr; /* Constelation power */
b63b36fa
FR		 1531 u32 snr_x100;
1532
4937ba94
MCC		 1533 mse = (read_reg(state, 0x00ec) << 8) |
1534 (read_reg(state, 0x00ed));
1535 pwr = (read_reg(state, 0x00e8) << 8) |
1536 (read_reg(state, 0x00e9));
b63b36fa
FR		 1537
1538 if (mse == 0) /* no signal */
1539 return 0;
1540
8e8cd34e 1541 snr_x100 = log10_x1000((pwr * 10000) / mse) - 3000;
097117ca 1542 dbg_info("mse=%u, pwr=%u, snr_x100=%d\n", mse, pwr, snr_x100);
b63b36fa
FR		 1543
1544 return snr_x100;
1545}
1546
534f4364
MCC		 1547static enum lgdt3306a_lock_status
1548lgdt3306a_vsb_lock_poll(struct lgdt3306a_state *state)
b63b36fa 1549{
e2c47fa7 1550 int ret;
8e8cd34e
MIK		 1551 u8 cnt = 0;
1552 u8 packet_error;
1553 u32 snr;
b63b36fa 1554
b1a88c71 1555 for (cnt = 0; cnt < 10; cnt++) {
b63b36fa 1556 if (lgdt3306a_sync_lock_poll(state) == LG3306_UNLOCK) {
097117ca 1557 dbg_info("no sync lock!\n");
8e8cd34e 1558 return LG3306_UNLOCK;
b1a88c71 1559 }
b63b36fa 1560
b1a88c71
MCC		 1561 msleep(20);
1562 ret = lgdt3306a_pre_monitoring(state);
1563 if (ret)
1564 break;
b63b36fa 1565
b1a88c71
MCC		 1566 packet_error = lgdt3306a_get_packet_error(state);
1567 snr = lgdt3306a_calculate_snr_x100(state);
1568 dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr);
b63b36fa 1569
b1a88c71
MCC		 1570 if ((snr >= 1500) && (packet_error < 0xff))
1571 return LG3306_LOCK;
b63b36fa 1572 }
b1a88c71
MCC		 1573
1574 dbg_info("not locked!\n");
8e8cd34e 1575 return LG3306_UNLOCK;
b63b36fa
FR		 1576}
1577
534f4364
MCC		 1578static enum lgdt3306a_lock_status
1579lgdt3306a_qam_lock_poll(struct lgdt3306a_state *state)
b63b36fa 1580{
b1a88c71 1581 u8 cnt;
b63b36fa
FR		 1582 u8 packet_error;
1583 u32 snr;
1584
b1a88c71 1585 for (cnt = 0; cnt < 10; cnt++) {
8e8cd34e 1586 if (lgdt3306a_fec_lock_poll(state) == LG3306_UNLOCK) {
097117ca 1587 dbg_info("no fec lock!\n");
8e8cd34e 1588 return LG3306_UNLOCK;
b1a88c71 1589 }
b63b36fa 1590
b1a88c71 1591 msleep(20);
b63b36fa 1592
b1a88c71
MCC		 1593 packet_error = lgdt3306a_get_packet_error(state);
1594 snr = lgdt3306a_calculate_snr_x100(state);
1595 dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr);
b63b36fa 1596
b1a88c71
MCC		 1597 if ((snr >= 1500) && (packet_error < 0xff))
1598 return LG3306_LOCK;
b63b36fa 1599 }
b1a88c71
MCC		 1600
1601 dbg_info("not locked!\n");
8e8cd34e 1602 return LG3306_UNLOCK;
b63b36fa
FR		 1603}
1604
0df289a2
MCC		 1605static int lgdt3306a_read_status(struct dvb_frontend *fe,
1606 enum fe_status *status)
b63b36fa 1607{
b63b36fa 1608 struct lgdt3306a_state *state = fe->demodulator_priv;
b63b36fa 1609 u16 strength = 0;
8e8cd34e
MIK		 1610 int ret = 0;
1611
b63b36fa
FR		 1612 if (fe->ops.tuner_ops.get_rf_strength) {
1613 ret = fe->ops.tuner_ops.get_rf_strength(fe, &strength);
c9897649 1614 if (ret == 0)
097117ca 1615 dbg_info("strength=%d\n", strength);
c9897649 1616 else
097117ca 1617 dbg_info("fe->ops.tuner_ops.get_rf_strength() failed\n");
b63b36fa
FR		 1618 }
1619
1620 *status = 0;
8e8cd34e 1621 if (lgdt3306a_neverlock_poll(state) == LG3306_NL_LOCK) {
b63b36fa
FR		 1622 *status |= FE_HAS_SIGNAL;
1623 *status |= FE_HAS_CARRIER;
1624
1625 switch (state->current_modulation) {
1626 case QAM_256:
1627 case QAM_64:
4966c0c5 1628 case QAM_AUTO:
8e8cd34e 1629 if (lgdt3306a_qam_lock_poll(state) == LG3306_LOCK) {
b63b36fa
FR		 1630 *status |= FE_HAS_VITERBI;
1631 *status |= FE_HAS_SYNC;
1632
1633 *status |= FE_HAS_LOCK;
1634 }
1635 break;
1636 case VSB_8:
8e8cd34e 1637 if (lgdt3306a_vsb_lock_poll(state) == LG3306_LOCK) {
b63b36fa
FR		 1638 *status |= FE_HAS_VITERBI;
1639 *status |= FE_HAS_SYNC;
1640
1641 *status |= FE_HAS_LOCK;
1642
ee0133ee 1643 ret = lgdt3306a_monitor_vsb(state);
b63b36fa
FR		 1644 }
1645 break;
1646 default:
1647 ret = -EINVAL;
1648 }
1649 }
1650 return ret;
1651}
1652
1653
1654static int lgdt3306a_read_snr(struct dvb_frontend *fe, u16 *snr)
1655{
1656 struct lgdt3306a_state *state = fe->demodulator_priv;
1657
1658 state->snr = lgdt3306a_calculate_snr_x100(state);
1659 /* report SNR in dB * 10 */
1660 *snr = state->snr/10;
1661
1662 return 0;
1663}
1664
1665static int lgdt3306a_read_signal_strength(struct dvb_frontend *fe,
1666 u16 *strength)
1667{
1668 /*
1669 * Calculate some sort of "strength" from SNR
1670 */
1671 struct lgdt3306a_state *state = fe->demodulator_priv;
4966c0c5 1672 u8 val;
34a5a2f8 1673 u16 snr; /* snr_x10 */
b63b36fa 1674 int ret;
8e8cd34e 1675 u32 ref_snr; /* snr*100 */
b63b36fa
FR		 1676 u32 str;
1677
1678 *strength = 0;
1679
1680 switch (state->current_modulation) {
1681 case VSB_8:
8e8cd34e 1682 ref_snr = 1600; /* 16dB */
b63b36fa
FR		 1683 break;
1684 case QAM_64:
b63b36fa 1685 case QAM_256:
4966c0c5
BL		 1686 case QAM_AUTO:
1687 /* need to know actual modulation to set proper SNR baseline */
c9b7d8f2
KL		 1688 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1689 if (lg_chkerr(ret))
1690 goto fail;
1691
4966c0c5
BL		 1692 if(val & 0x04)
1693 ref_snr = 2800; /* QAM-256 28dB */
1694 else
1695 ref_snr = 2200; /* QAM-64 22dB */
1696 break;
b63b36fa
FR		 1697 default:
1698 return -EINVAL;
1699 }
1700
1701 ret = fe->ops.read_snr(fe, &snr);
1702 if (lg_chkerr(ret))
1703 goto fail;
1704
8e8cd34e 1705 if (state->snr <= (ref_snr - 100))
b63b36fa 1706 str = 0;
8e8cd34e
MIK		 1707 else if (state->snr <= ref_snr)
1708 str = (0xffff * 65) / 100; /* 65% */
b63b36fa
FR		 1709 else {
1710 str = state->snr - ref_snr;
1711 str /= 50;
8e8cd34e
MIK		 1712 str += 78; /* 78%-100% */
1713 if (str > 100)
b63b36fa
FR		 1714 str = 100;
1715 str = (0xffff * str) / 100;
1716 }
1717 *strength = (u16)str;
097117ca 1718 dbg_info("strength=%u\n", *strength);
b63b36fa
FR		 1719
1720fail:
1721 return ret;
1722}
1723
1724/* ------------------------------------------------------------------------ */
1725
1726static int lgdt3306a_read_ber(struct dvb_frontend *fe, u32 *ber)
1727{
1728 struct lgdt3306a_state *state = fe->demodulator_priv;
1729 u32 tmp;
1730
1731 *ber = 0;
1732#if 1
534f4364 1733 /* FGR - FIXME - I don't know what value is expected by dvb_core
8e8cd34e 1734 * what is the scale of the value?? */
4937ba94
MCC		 1735 tmp = read_reg(state, 0x00fc); /* NBERVALUE[24-31] */
1736 tmp = (tmp << 8) | read_reg(state, 0x00fd); /* NBERVALUE[16-23] */
1737 tmp = (tmp << 8) | read_reg(state, 0x00fe); /* NBERVALUE[8-15] */
1738 tmp = (tmp << 8) | read_reg(state, 0x00ff); /* NBERVALUE[0-7] */
b63b36fa 1739 *ber = tmp;
097117ca 1740 dbg_info("ber=%u\n", tmp);
b63b36fa
FR		 1741#endif
1742 return 0;
1743}
1744
1745static int lgdt3306a_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1746{
1747 struct lgdt3306a_state *state = fe->demodulator_priv;
1748
8e8cd34e 1749 *ucblocks = 0;
b63b36fa 1750#if 1
534f4364 1751 /* FGR - FIXME - I don't know what value is expected by dvb_core
8e8cd34e 1752 * what happens when value wraps? */
4937ba94 1753 *ucblocks = read_reg(state, 0x00f4); /* TPIFTPERRCNT[0-7] */
097117ca 1754 dbg_info("ucblocks=%u\n", *ucblocks);
b63b36fa
FR		 1755#endif
1756
1757 return 0;
1758}
1759
534f4364
MCC		 1760static int lgdt3306a_tune(struct dvb_frontend *fe, bool re_tune,
1761 unsigned int mode_flags, unsigned int *delay,
0df289a2 1762 enum fe_status *status)
b63b36fa
FR		 1763{
1764 int ret = 0;
1765 struct lgdt3306a_state *state = fe->demodulator_priv;
1766
097117ca 1767 dbg_info("re_tune=%u\n", re_tune);
b63b36fa
FR		 1768
1769 if (re_tune) {
8e8cd34e 1770 state->current_frequency = -1; /* force re-tune */
ae21e447
MIK		 1771 ret = lgdt3306a_set_parameters(fe);
1772 if (ret != 0)
b63b36fa 1773 return ret;
b63b36fa
FR		 1774 }
1775 *delay = 125;
1776 ret = lgdt3306a_read_status(fe, status);
1777
1778 return ret;
1779}
1780
1781static int lgdt3306a_get_tune_settings(struct dvb_frontend *fe,
8e8cd34e
MIK		 1782 struct dvb_frontend_tune_settings
1783 *fe_tune_settings)
b63b36fa
FR		 1784{
1785 fe_tune_settings->min_delay_ms = 100;
097117ca 1786 dbg_info("\n");
b63b36fa
FR		 1787 return 0;
1788}
1789
f172fe9f 1790static enum dvbfe_search lgdt3306a_search(struct dvb_frontend *fe)
b63b36fa 1791{
0df289a2 1792 enum fe_status status = 0;
dd14523a 1793 int ret;
b63b36fa
FR		 1794
1795 /* set frontend */
1796 ret = lgdt3306a_set_parameters(fe);
1797 if (ret)
1798 goto error;
1799
dd14523a
AO		 1800 ret = lgdt3306a_read_status(fe, &status);
1801 if (ret)
1802 goto error;
b63b36fa
FR		 1803
1804 /* check if we have a valid signal */
8e8cd34e 1805 if (status & FE_HAS_LOCK)
b63b36fa 1806 return DVBFE_ALGO_SEARCH_SUCCESS;
8e8cd34e 1807 else
b63b36fa 1808 return DVBFE_ALGO_SEARCH_AGAIN;
b63b36fa
FR		 1809
1810error:
097117ca 1811 dbg_info("failed (%d)\n", ret);
b63b36fa
FR		 1812 return DVBFE_ALGO_SEARCH_ERROR;
1813}
1814
1815static void lgdt3306a_release(struct dvb_frontend *fe)
1816{
1817 struct lgdt3306a_state *state = fe->demodulator_priv;
8e8cd34e 1818
097117ca 1819 dbg_info("\n");
f6618cc8 1820 kfree(state);
b63b36fa
FR		 1821}
1822
bd336e63 1823static const struct dvb_frontend_ops lgdt3306a_ops;
b63b36fa
FR		 1824
1825struct dvb_frontend *lgdt3306a_attach(const struct lgdt3306a_config *config,
c43e6512 1826 struct i2c_adapter *i2c_adap)
b63b36fa
FR		 1827{
1828 struct lgdt3306a_state *state = NULL;
1829 int ret;
1830 u8 val;
1831
097117ca 1832 dbg_info("(%d-%04x)\n",
b63b36fa
FR		 1833 i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
1834 config ? config->i2c_addr : 0);
1835
1836 state = kzalloc(sizeof(struct lgdt3306a_state), GFP_KERNEL);
1837 if (state == NULL)
1838 goto fail;
1839
1840 state->cfg = config;
1841 state->i2c_adap = i2c_adap;
1842
1843 memcpy(&state->frontend.ops, &lgdt3306a_ops,
1844 sizeof(struct dvb_frontend_ops));
1845 state->frontend.demodulator_priv = state;
1846
1847 /* verify that we're talking to a lg3306a */
8e8cd34e
MIK		 1848 /* FGR - NOTE - there is no obvious ChipId to check; we check
1849 * some "known" bits after reset, but it's still just a guess */
b63b36fa
FR		 1850 ret = lgdt3306a_read_reg(state, 0x0000, &val);
1851 if (lg_chkerr(ret))
1852 goto fail;
8e8cd34e 1853 if ((val & 0x74) != 0x74) {
097117ca 1854 pr_warn("expected 0x74, got 0x%x\n", (val & 0x74));
8e8cd34e 1855#if 0
534f4364
MCC		 1856 /* FIXME - re-enable when we know this is right */
1857 goto fail;
8e8cd34e 1858#endif
b63b36fa
FR		 1859 }
1860 ret = lgdt3306a_read_reg(state, 0x0001, &val);
1861 if (lg_chkerr(ret))
1862 goto fail;
4937ba94 1863 if ((val & 0xf6) != 0xc6) {
097117ca 1864 pr_warn("expected 0xc6, got 0x%x\n", (val & 0xf6));
8e8cd34e 1865#if 0
534f4364
MCC		 1866 /* FIXME - re-enable when we know this is right */
1867 goto fail;
8e8cd34e 1868#endif
b63b36fa
FR		 1869 }
1870 ret = lgdt3306a_read_reg(state, 0x0002, &val);
1871 if (lg_chkerr(ret))
1872 goto fail;
8e8cd34e 1873 if ((val & 0x73) != 0x03) {
097117ca 1874 pr_warn("expected 0x03, got 0x%x\n", (val & 0x73));
8e8cd34e 1875#if 0
534f4364
MCC		 1876 /* FIXME - re-enable when we know this is right */
1877 goto fail;
8e8cd34e 1878#endif
b63b36fa
FR		 1879 }
1880
1881 state->current_frequency = -1;
1882 state->current_modulation = -1;
1883
1884 lgdt3306a_sleep(state);
1885
1886 return &state->frontend;
1887
1888fail:
097117ca 1889 pr_warn("unable to detect LGDT3306A hardware\n");
b63b36fa
FR		 1890 kfree(state);
1891 return NULL;
1892}
ebd9175e 1893EXPORT_SYMBOL(lgdt3306a_attach);
b63b36fa
FR		 1894
1895#ifdef DBG_DUMP
1896
1897static const short regtab[] = {
cb4671c8
MIK		 1898 0x0000, /* SOFTRSTB 1'b1 1'b1 1'b1 ADCPDB 1'b1 PLLPDB GBBPDB 11111111 */
1899 0x0001, /* 1'b1 1'b1 1'b0 1'b0 AUTORPTRS */
1900 0x0002, /* NI2CRPTEN 1'b0 1'b0 1'b0 SPECINVAUT */
1901 0x0003, /* AGCRFOUT */
1902 0x0004, /* ADCSEL1V ADCCNT ADCCNF ADCCNS ADCCLKPLL */
1903 0x0005, /* PLLINDIVSE */
1904 0x0006, /* PLLCTRL[7:0] 11100001 */
1905 0x0007, /* SYSINITWAITTIME[7:0] (msec) 00001000 */
1906 0x0008, /* STDOPMODE[7:0] 10000000 */
1907 0x0009, /* 1'b0 1'b0 1'b0 STDOPDETTMODE[2:0] STDOPDETCMODE[1:0] 00011110 */
4937ba94
MCC		 1908 0x000a, /* DAFTEN 1'b1 x x SCSYSLOCK */
1909 0x000b, /* SCSYSLOCKCHKTIME[7:0] (10msec) 01100100 */
1910 0x000d, /* x SAMPLING4 */
1911 0x000e, /* SAMFREQ[15:8] 00000000 */
1912 0x000f, /* SAMFREQ[7:0] 00000000 */
cb4671c8
MIK		 1913 0x0010, /* IFFREQ[15:8] 01100000 */
1914 0x0011, /* IFFREQ[7:0] 00000000 */
1915 0x0012, /* AGCEN AGCREFMO */
1916 0x0013, /* AGCRFFIXB AGCIFFIXB AGCLOCKDETRNGSEL[1:0] 1'b1 1'b0 1'b0 1'b0 11101000 */
1917 0x0014, /* AGCFIXVALUE[7:0] 01111111 */
1918 0x0015, /* AGCREF[15:8] 00001010 */
1919 0x0016, /* AGCREF[7:0] 11100100 */
1920 0x0017, /* AGCDELAY[7:0] 00100000 */
1921 0x0018, /* AGCRFBW[3:0] AGCIFBW[3:0] 10001000 */
1922 0x0019, /* AGCUDOUTMODE[1:0] AGCUDCTRLLEN[1:0] AGCUDCTRL */
4937ba94
MCC		 1923 0x001c, /* 1'b1 PFEN MFEN AICCVSYNC */
1924 0x001d, /* 1'b0 1'b1 1'b0 1'b1 AICCVSYNC */
1925 0x001e, /* AICCALPHA[3:0] 1'b1 1'b0 1'b1 1'b0 01111010 */
1926 0x001f, /* AICCDETTH[19:16] AICCOFFTH[19:16] 00000000 */
cb4671c8
MIK		 1927 0x0020, /* AICCDETTH[15:8] 01111100 */
1928 0x0021, /* AICCDETTH[7:0] 00000000 */
1929 0x0022, /* AICCOFFTH[15:8] 00000101 */
1930 0x0023, /* AICCOFFTH[7:0] 11100000 */
1931 0x0024, /* AICCOPMODE3[1:0] AICCOPMODE2[1:0] AICCOPMODE1[1:0] AICCOPMODE0[1:0] 00000000 */
1932 0x0025, /* AICCFIXFREQ3[23:16] 00000000 */
1933 0x0026, /* AICCFIXFREQ3[15:8] 00000000 */
1934 0x0027, /* AICCFIXFREQ3[7:0] 00000000 */
1935 0x0028, /* AICCFIXFREQ2[23:16] 00000000 */
1936 0x0029, /* AICCFIXFREQ2[15:8] 00000000 */
4937ba94
MCC		 1937 0x002a, /* AICCFIXFREQ2[7:0] 00000000 */
1938 0x002b, /* AICCFIXFREQ1[23:16] 00000000 */
1939 0x002c, /* AICCFIXFREQ1[15:8] 00000000 */
1940 0x002d, /* AICCFIXFREQ1[7:0] 00000000 */
1941 0x002e, /* AICCFIXFREQ0[23:16] 00000000 */
1942 0x002f, /* AICCFIXFREQ0[15:8] 00000000 */
cb4671c8
MIK		 1943 0x0030, /* AICCFIXFREQ0[7:0] 00000000 */
1944 0x0031, /* 1'b0 1'b1 1'b0 1'b0 x DAGC1STER */
1945 0x0032, /* DAGC1STEN DAGC1STER */
1946 0x0033, /* DAGC1STREF[15:8] 00001010 */
1947 0x0034, /* DAGC1STREF[7:0] 11100100 */
1948 0x0035, /* DAGC2NDE */
1949 0x0036, /* DAGC2NDREF[15:8] 00001010 */
1950 0x0037, /* DAGC2NDREF[7:0] 10000000 */
1951 0x0038, /* DAGC2NDLOCKDETRNGSEL[1:0] */
4937ba94 1952 0x003d, /* 1'b1 SAMGEARS */
cb4671c8
MIK		 1953 0x0040, /* SAMLFGMA */
1954 0x0041, /* SAMLFBWM */
1955 0x0044, /* 1'b1 CRGEARSHE */
1956 0x0045, /* CRLFGMAN */
1957 0x0046, /* CFLFBWMA */
1958 0x0047, /* CRLFGMAN */
1959 0x0048, /* x x x x CRLFGSTEP_VS[3:0] xxxx1001 */
1960 0x0049, /* CRLFBWMA */
4937ba94 1961 0x004a, /* CRLFBWMA */
cb4671c8
MIK		 1962 0x0050, /* 1'b0 1'b1 1'b1 1'b0 MSECALCDA */
1963 0x0070, /* TPOUTEN TPIFEN TPCLKOUTE */
1964 0x0071, /* TPSENB TPSSOPBITE */
1965 0x0073, /* TP47HINS x x CHBERINT PERMODE[1:0] PERINT[1:0] 1xx11100 */
1966 0x0075, /* x x x x x IQSWAPCTRL[2:0] xxxxx000 */
1967 0x0076, /* NBERCON NBERST NBERPOL NBERWSYN */
1968 0x0077, /* x NBERLOSTTH[2:0] NBERACQTH[3:0] x0000000 */
1969 0x0078, /* NBERPOLY[31:24] 00000000 */
1970 0x0079, /* NBERPOLY[23:16] 00000000 */
4937ba94
MCC		 1971 0x007a, /* NBERPOLY[15:8] 00000000 */
1972 0x007b, /* NBERPOLY[7:0] 00000000 */
1973 0x007c, /* NBERPED[31:24] 00000000 */
1974 0x007d, /* NBERPED[23:16] 00000000 */
1975 0x007e, /* NBERPED[15:8] 00000000 */
1976 0x007f, /* NBERPED[7:0] 00000000 */
cb4671c8
MIK		 1977 0x0080, /* x AGCLOCK DAGCLOCK SYSLOCK x x NEVERLOCK[1:0] */
1978 0x0085, /* SPECINVST */
1979 0x0088, /* SYSLOCKTIME[15:8] */
1980 0x0089, /* SYSLOCKTIME[7:0] */
4937ba94
MCC		 1981 0x008c, /* FECLOCKTIME[15:8] */
1982 0x008d, /* FECLOCKTIME[7:0] */
1983 0x008e, /* AGCACCOUT[15:8] */
1984 0x008f, /* AGCACCOUT[7:0] */
cb4671c8
MIK		 1985 0x0090, /* AICCREJSTATUS[3:0] AICCREJBUSY[3:0] */
1986 0x0091, /* AICCVSYNC */
4937ba94
MCC		 1987 0x009c, /* CARRFREQOFFSET[15:8] */
1988 0x009d, /* CARRFREQOFFSET[7:0] */
1989 0x00a1, /* SAMFREQOFFSET[23:16] */
1990 0x00a2, /* SAMFREQOFFSET[15:8] */
1991 0x00a3, /* SAMFREQOFFSET[7:0] */
1992 0x00a6, /* SYNCLOCK SYNCLOCKH */
6da7ac98 1993#if 0 /* covered elsewhere */
4937ba94
MCC		 1994 0x00e8, /* CONSTPWR[15:8] */
1995 0x00e9, /* CONSTPWR[7:0] */
1996 0x00ea, /* BMSE[15:8] */
1997 0x00eb, /* BMSE[7:0] */
1998 0x00ec, /* MSE[15:8] */
1999 0x00ed, /* MSE[7:0] */
2000 0x00ee, /* CONSTI[7:0] */
2001 0x00ef, /* CONSTQ[7:0] */
b63b36fa 2002#endif
4937ba94
MCC		 2003 0x00f4, /* TPIFTPERRCNT[7:0] */
2004 0x00f5, /* TPCORREC */
2005 0x00f6, /* VBBER[15:8] */
2006 0x00f7, /* VBBER[7:0] */
2007 0x00f8, /* VABER[15:8] */
2008 0x00f9, /* VABER[7:0] */
2009 0x00fa, /* TPERRCNT[7:0] */
2010 0x00fb, /* NBERLOCK x x x x x x x */
2011 0x00fc, /* NBERVALUE[31:24] */
2012 0x00fd, /* NBERVALUE[23:16] */
2013 0x00fe, /* NBERVALUE[15:8] */
2014 0x00ff, /* NBERVALUE[7:0] */
cb4671c8
MIK		 2015 0x1000, /* 1'b0 WODAGCOU */
2016 0x1005, /* x x 1'b1 1'b1 x SRD_Q_QM */
2017 0x1009, /* SRDWAITTIME[7:0] (10msec) 00100011 */
4937ba94
MCC		 2018 0x100a, /* SRDWAITTIME_CQS[7:0] (msec) 01100100 */
2019 0x101a, /* x 1'b1 1'b0 1'b0 x QMDQAMMODE[2:0] x100x010 */
cb4671c8 2020 0x1036, /* 1'b0 1'b1 1'b0 1'b0 SAMGSEND_CQS[3:0] 01001110 */
4937ba94
MCC		 2021 0x103c, /* SAMGSAUTOSTL_V[3:0] SAMGSAUTOEDL_V[3:0] 01000110 */
2022 0x103d, /* 1'b1 1'b1 SAMCNORMBP_V[1:0] 1'b0 1'b0 SAMMODESEL_V[1:0] 11100001 */
2023 0x103f, /* SAMZTEDSE */
2024 0x105d, /* EQSTATUSE */
2025 0x105f, /* x PMAPG2_V[2:0] x DMAPG2_V[2:0] x001x011 */
cb4671c8
MIK		 2026 0x1060, /* 1'b1 EQSTATUSE */
2027 0x1061, /* CRMAPBWSTL_V[3:0] CRMAPBWEDL_V[3:0] 00000100 */
2028 0x1065, /* 1'b0 x CRMODE_V[1:0] 1'b1 x 1'b1 x 0x111x1x */
2029 0x1066, /* 1'b0 1'b0 1'b1 1'b0 1'b1 PNBOOSTSE */
2030 0x1068, /* CREPHNGAIN2_V[3:0] CREPHNPBW_V[3:0] 10010001 */
4937ba94
MCC		 2031 0x106e, /* x x x x x CREPHNEN_ */
2032 0x106f, /* CREPHNTH_V[7:0] 00010101 */
cb4671c8
MIK		 2033 0x1072, /* CRSWEEPN */
2034 0x1073, /* CRPGAIN_V[3:0] x x 1'b1 1'b1 1001xx11 */
2035 0x1074, /* CRPBW_V[3:0] x x 1'b1 1'b1 0001xx11 */
2036 0x1080, /* DAFTSTATUS[1:0] x x x x x x */
2037 0x1081, /* SRDSTATUS[1:0] x x x x x SRDLOCK */
4937ba94
MCC		 2038 0x10a9, /* EQSTATUS_CQS[1:0] x x x x x x */
2039 0x10b7, /* EQSTATUS_V[1:0] x x x x x x */
6da7ac98 2040#if 0 /* SMART_ANT */
4937ba94
MCC		 2041 0x1f00, /* MODEDETE */
2042 0x1f01, /* x x x x x x x SFNRST xxxxxxx0 */
2043 0x1f03, /* NUMOFANT[7:0] 10000000 */
2044 0x1f04, /* x SELMASK[6:0] x0000000 */
2045 0x1f05, /* x SETMASK[6:0] x0000000 */
2046 0x1f06, /* x TXDATA[6:0] x0000000 */
2047 0x1f07, /* x CHNUMBER[6:0] x0000000 */
2048 0x1f09, /* AGCTIME[23:16] 10011000 */
2049 0x1f0a, /* AGCTIME[15:8] 10010110 */
2050 0x1f0b, /* AGCTIME[7:0] 10000000 */
2051 0x1f0c, /* ANTTIME[31:24] 00000000 */
2052 0x1f0d, /* ANTTIME[23:16] 00000011 */
2053 0x1f0e, /* ANTTIME[15:8] 10010000 */
2054 0x1f0f, /* ANTTIME[7:0] 10010000 */
2055 0x1f11, /* SYNCTIME[23:16] 10011000 */
2056 0x1f12, /* SYNCTIME[15:8] 10010110 */
2057 0x1f13, /* SYNCTIME[7:0] 10000000 */
2058 0x1f14, /* SNRTIME[31:24] 00000001 */
2059 0x1f15, /* SNRTIME[23:16] 01111101 */
2060 0x1f16, /* SNRTIME[15:8] 01111000 */
2061 0x1f17, /* SNRTIME[7:0] 01000000 */
2062 0x1f19, /* FECTIME[23:16] 00000000 */
2063 0x1f1a, /* FECTIME[15:8] 01110010 */
2064 0x1f1b, /* FECTIME[7:0] 01110000 */
2065 0x1f1d, /* FECTHD[7:0] 00000011 */
2066 0x1f1f, /* SNRTHD[23:16] 00001000 */
2067 0x1f20, /* SNRTHD[15:8] 01111111 */
2068 0x1f21, /* SNRTHD[7:0] 10000101 */
2069 0x1f80, /* IRQFLG x x SFSDRFLG MODEBFLG SAVEFLG SCANFLG TRACKFLG */
2070 0x1f81, /* x SYNCCON SNRCON FECCON x STDBUSY SYNCRST AGCFZCO */
2071 0x1f82, /* x x x SCANOPCD[4:0] */
2072 0x1f83, /* x x x x MAINOPCD[3:0] */
2073 0x1f84, /* x x RXDATA[13:8] */
2074 0x1f85, /* RXDATA[7:0] */
2075 0x1f86, /* x x SDTDATA[13:8] */
2076 0x1f87, /* SDTDATA[7:0] */
2077 0x1f89, /* ANTSNR[23:16] */
2078 0x1f8a, /* ANTSNR[15:8] */
2079 0x1f8b, /* ANTSNR[7:0] */
2080 0x1f8c, /* x x x x ANTFEC[13:8] */
2081 0x1f8d, /* ANTFEC[7:0] */
2082 0x1f8e, /* MAXCNT[7:0] */
2083 0x1f8f, /* SCANCNT[7:0] */
2084 0x1f91, /* MAXPW[23:16] */
2085 0x1f92, /* MAXPW[15:8] */
2086 0x1f93, /* MAXPW[7:0] */
2087 0x1f95, /* CURPWMSE[23:16] */
2088 0x1f96, /* CURPWMSE[15:8] */
2089 0x1f97, /* CURPWMSE[7:0] */
6da7ac98 2090#endif /* SMART_ANT */
4937ba94
MCC		 2091 0x211f, /* 1'b1 1'b1 1'b1 CIRQEN x x 1'b0 1'b0 1111xx00 */
2092 0x212a, /* EQAUTOST */
cb4671c8 2093 0x2122, /* CHFAST[7:0] 01100000 */
4937ba94
MCC		 2094 0x212b, /* FFFSTEP_V[3:0] x FBFSTEP_V[2:0] 0001x001 */
2095 0x212c, /* PHDEROTBWSEL[3:0] 1'b1 1'b1 1'b1 1'b0 10001110 */
2096 0x212d, /* 1'b1 1'b1 1'b1 1'b1 x x TPIFLOCKS */
cb4671c8
MIK		 2097 0x2135, /* DYNTRACKFDEQ[3:0] x 1'b0 1'b0 1'b0 1010x000 */
2098 0x2141, /* TRMODE[1:0] 1'b1 1'b1 1'b0 1'b1 1'b1 1'b1 01110111 */
2099 0x2162, /* AICCCTRLE */
2100 0x2173, /* PHNCNFCNT[7:0] 00000100 */
2101 0x2179, /* 1'b0 1'b0 1'b0 1'b1 x BADSINGLEDYNTRACKFBF[2:0] 0001x001 */
4937ba94
MCC		 2102 0x217a, /* 1'b0 1'b0 1'b0 1'b1 x BADSLOWSINGLEDYNTRACKFBF[2:0] 0001x001 */
2103 0x217e, /* CNFCNTTPIF[7:0] 00001000 */
2104 0x217f, /* TPERRCNTTPIF[7:0] 00000001 */
cb4671c8
MIK		 2105 0x2180, /* x x x x x x FBDLYCIR[9:8] */
2106 0x2181, /* FBDLYCIR[7:0] */
2107 0x2185, /* MAXPWRMAIN[7:0] */
2108 0x2191, /* NCOMBDET x x x x x x x */
2109 0x2199, /* x MAINSTRON */
4937ba94
MCC		 2110 0x219a, /* FFFEQSTEPOUT_V[3:0] FBFSTEPOUT_V[2:0] */
2111 0x21a1, /* x x SNRREF[5:0] */
cb4671c8
MIK		 2112 0x2845, /* 1'b0 1'b1 x x FFFSTEP_CQS[1:0] FFFCENTERTAP[1:0] 01xx1110 */
2113 0x2846, /* 1'b0 x 1'b0 1'b1 FBFSTEP_CQS[1:0] 1'b1 1'b0 0x011110 */
2114 0x2847, /* ENNOSIGDE */
2115 0x2849, /* 1'b1 1'b1 NOUSENOSI */
4937ba94 2116 0x284a, /* EQINITWAITTIME[7:0] 01100100 */
cb4671c8
MIK		 2117 0x3000, /* 1'b1 1'b1 1'b1 x x x 1'b0 RPTRSTM */
2118 0x3001, /* RPTRSTWAITTIME[7:0] (100msec) 00110010 */
2119 0x3031, /* FRAMELOC */
2120 0x3032, /* 1'b1 1'b0 1'b0 1'b0 x x FRAMELOCKMODE_CQS[1:0] 1000xx11 */
4937ba94
MCC		 2121 0x30a9, /* VDLOCK_Q FRAMELOCK */
2122 0x30aa, /* MPEGLOCK */
b63b36fa
FR		 2123};
2124
1f679ff6 2125#define numDumpRegs (ARRAY_SIZE(regtab))
b63b36fa
FR		 2126static u8 regval1[numDumpRegs] = {0, };
2127static u8 regval2[numDumpRegs] = {0, };
2128
2129static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state)
2130{
2131 memset(regval2, 0xff, sizeof(regval2));
2132 lgdt3306a_DumpRegs(state);
2133}
2134
2135static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state)
2136{
2137 int i;
2138 int sav_debug = debug;
8e8cd34e 2139
b63b36fa
FR		 2140 if ((debug & DBG_DUMP) == 0)
2141 return;
831a9112 2142 debug &= ~DBG_REG; /* suppress DBG_REG during reg dump */
b63b36fa 2143
097117ca 2144 lg_debug("\n");
b63b36fa 2145
8e8cd34e 2146 for (i = 0; i < numDumpRegs; i++) {
b63b36fa 2147 lgdt3306a_read_reg(state, regtab[i], &regval1[i]);
8e8cd34e 2148 if (regval1[i] != regval2[i]) {
097117ca 2149 lg_debug(" %04X = %02X\n", regtab[i], regval1[i]);
16afc672 2150 regval2[i] = regval1[i];
b63b36fa
FR		 2151 }
2152 }
2153 debug = sav_debug;
2154}
8e8cd34e 2155#endif /* DBG_DUMP */
b63b36fa
FR		 2156
2157
2158
bd336e63 2159static const struct dvb_frontend_ops lgdt3306a_ops = {
b63b36fa
FR		 2160 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
2161 .info = {
2162 .name = "LG Electronics LGDT3306A VSB/QAM Frontend",
f1b1eabf
MCC		 2163 .frequency_min_hz = 54 * MHz,
2164 .frequency_max_hz = 858 * MHz,
2165 .frequency_stepsize_hz = 62500,
4966c0c5 2166 .caps = FE_CAN_QAM_AUTO | FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
b63b36fa
FR		 2167 },
2168 .i2c_gate_ctrl = lgdt3306a_i2c_gate_ctrl,
2169 .init = lgdt3306a_init,
2170 .sleep = lgdt3306a_fe_sleep,
2171 /* if this is set, it overrides the default swzigzag */
2172 .tune = lgdt3306a_tune,
2173 .set_frontend = lgdt3306a_set_parameters,
2174 .get_frontend = lgdt3306a_get_frontend,
2175 .get_frontend_algo = lgdt3306a_get_frontend_algo,
2176 .get_tune_settings = lgdt3306a_get_tune_settings,
2177 .read_status = lgdt3306a_read_status,
2178 .read_ber = lgdt3306a_read_ber,
2179 .read_signal_strength = lgdt3306a_read_signal_strength,
2180 .read_snr = lgdt3306a_read_snr,
2181 .read_ucblocks = lgdt3306a_read_ucblocks,
2182 .release = lgdt3306a_release,
2183 .ts_bus_ctrl = lgdt3306a_ts_bus_ctrl,
2184 .search = lgdt3306a_search,
2185};
2186
4f751890
KC		 2187static int lgdt3306a_select(struct i2c_mux_core *muxc, u32 chan)
2188{
2189 struct i2c_client *client = i2c_mux_priv(muxc);
2190 struct lgdt3306a_state *state = i2c_get_clientdata(client);
2191
2192 return lgdt3306a_i2c_gate_ctrl(&state->frontend, 1);
2193}
2194
2195static int lgdt3306a_deselect(struct i2c_mux_core *muxc, u32 chan)
2196{
2197 struct i2c_client *client = i2c_mux_priv(muxc);
2198 struct lgdt3306a_state *state = i2c_get_clientdata(client);
2199
2200 return lgdt3306a_i2c_gate_ctrl(&state->frontend, 0);
2201}
2202
2203static int lgdt3306a_probe(struct i2c_client *client,
2204 const struct i2c_device_id *id)
2205{
2206 struct lgdt3306a_config *config;
2207 struct lgdt3306a_state *state;
2208 struct dvb_frontend *fe;
2209 int ret;
2210
2c4746cf 2211 config = kmemdup(client->dev.platform_data,
2212 sizeof(struct lgdt3306a_config), GFP_KERNEL);
4f751890
KC		 2213 if (config == NULL) {
2214 ret = -ENOMEM;
2215 goto fail;
2216 }
2217
4f751890 2218 config->i2c_addr = client->addr;
f6618cc8 2219 fe = lgdt3306a_attach(config, client->adapter);
4f751890
KC		 2220 if (fe == NULL) {
2221 ret = -ENODEV;
2222 goto err_fe;
2223 }
2224
2225 i2c_set_clientdata(client, fe->demodulator_priv);
2226 state = fe->demodulator_priv;
5b3a8e90 2227 state->frontend.ops.release = NULL;
4f751890
KC		 2228
2229 /* create mux i2c adapter for tuner */
2230 state->muxc = i2c_mux_alloc(client->adapter, &client->dev,
2231 1, 0, I2C_MUX_LOCKED,
2232 lgdt3306a_select, lgdt3306a_deselect);
2233 if (!state->muxc) {
2234 ret = -ENOMEM;
2235 goto err_kfree;
2236 }
2237 state->muxc->priv = client;
2238 ret = i2c_mux_add_adapter(state->muxc, 0, 0, 0);
2239 if (ret)
2240 goto err_kfree;
2241
2242 /* create dvb_frontend */
2243 fe->ops.i2c_gate_ctrl = NULL;
2244 *config->i2c_adapter = state->muxc->adapter[0];
2245 *config->fe = fe;
2246
e7f4d751
BL		 2247 dev_info(&client->dev, "LG Electronics LGDT3306A successfully identified\n");
2248
4f751890
KC		 2249 return 0;
2250
2251err_kfree:
2252 kfree(state);
2253err_fe:
2254 kfree(config);
2255fail:
e7f4d751 2256 dev_warn(&client->dev, "probe failed = %d\n", ret);
4f751890
KC		 2257 return ret;
2258}
2259
2260static int lgdt3306a_remove(struct i2c_client *client)
2261{
2262 struct lgdt3306a_state *state = i2c_get_clientdata(client);
2263
2264 i2c_mux_del_adapters(state->muxc);
2265
2266 state->frontend.ops.release = NULL;
2267 state->frontend.demodulator_priv = NULL;
2268
2269 kfree(state->cfg);
2270 kfree(state);
2271
2272 return 0;
2273}
2274
2275static const struct i2c_device_id lgdt3306a_id_table[] = {
2276 {"lgdt3306a", 0},
2277 {}
2278};
2279MODULE_DEVICE_TABLE(i2c, lgdt3306a_id_table);
2280
2281static struct i2c_driver lgdt3306a_driver = {
2282 .driver = {
2283 .name = "lgdt3306a",
2284 .suppress_bind_attrs = true,
2285 },
2286 .probe = lgdt3306a_probe,
2287 .remove = lgdt3306a_remove,
2288 .id_table = lgdt3306a_id_table,
2289};
2290
2291module_i2c_driver(lgdt3306a_driver);
2292
b63b36fa
FR		 2293MODULE_DESCRIPTION("LG Electronics LGDT3306A ATSC/QAM-B Demodulator Driver");
2294MODULE_AUTHOR("Fred Richter <frichter@hauppauge.com>");
2295MODULE_LICENSE("GPL");
2296MODULE_VERSION("0.2");
Linux 6.x block layer and io_uring tree(s)