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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/livepatchin...
[linux-2.6-block.git] / drivers / media / dvb-frontends / lgdt3306a.c
CommitLineData
c942fddf 1// SPDX-License-Identifier: GPL-2.0-or-later
b63b36fa
FR		 2/*
3 * Support for LGDT3306A - 8VSB/QAM-B
4 *
5 * Copyright (C) 2013 Fred Richter <frichter@hauppauge.com>
6 * - driver structure based on lgdt3305.[ch] by Michael Krufky
7 * - code based on LG3306_V0.35 API by LG Electronics Inc.
b63b36fa
FR		 8 */
9
097117ca
MCC		 10#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11
b63b36fa 12#include <asm/div64.h>
1f679ff6 13#include <linux/kernel.h>
b63b36fa 14#include <linux/dvb/frontend.h>
fada1935 15#include <media/dvb_math.h>
b63b36fa 16#include "lgdt3306a.h"
4f751890 17#include <linux/i2c-mux.h>
b63b36fa
FR		 18
19
20static int debug;
21module_param(debug, int, 0644);
22MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))");
23
4966c0c5
BL		 24/*
25 * Older drivers treated QAM64 and QAM256 the same; that is the HW always
26 * used "Auto" mode during detection. Setting "forced_manual"=1 allows
27 * the user to treat these modes as separate. For backwards compatibility,
28 * it's off by default. QAM_AUTO can now be specified to achive that
29 * effect even if "forced_manual"=1
30 */
31static int forced_manual;
32module_param(forced_manual, int, 0644);
33MODULE_PARM_DESC(forced_manual, "if set, QAM64 and QAM256 will only lock to modulation specified");
34
b63b36fa
FR		 35#define DBG_INFO 1
36#define DBG_REG 2
8e8cd34e 37#define DBG_DUMP 4 /* FGR - comment out to remove dump code */
b63b36fa 38
097117ca
MCC		 39#define lg_debug(fmt, arg...) \
40 printk(KERN_DEBUG pr_fmt(fmt), ## arg)
41
42#define dbg_info(fmt, arg...) \
43 do { \
44 if (debug & DBG_INFO) \
45 lg_debug(fmt, ## arg); \
46 } while (0)
b63b36fa 47
097117ca
MCC		 48#define dbg_reg(fmt, arg...) \
49 do { \
50 if (debug & DBG_REG) \
51 lg_debug(fmt, ## arg); \
52 } while (0)
b63b36fa
FR		 53
54#define lg_chkerr(ret) \
55({ \
56 int __ret; \
57 __ret = (ret < 0); \
58 if (__ret) \
097117ca 59 pr_err("error %d on line %d\n", ret, __LINE__); \
b63b36fa
FR		 60 __ret; \
61})
62
63struct lgdt3306a_state {
64 struct i2c_adapter *i2c_adap;
65 const struct lgdt3306a_config *cfg;
66
67 struct dvb_frontend frontend;
68
0df289a2 69 enum fe_modulation current_modulation;
b63b36fa
FR		 70 u32 current_frequency;
71 u32 snr;
4f751890
KC		 72
73 struct i2c_mux_core *muxc;
b63b36fa
FR		 74};
75
95f22c5a
MCC		 76/*
77 * LG3306A Register Usage
78 * (LG does not really name the registers, so this code does not either)
79 *
80 * 0000 -> 00FF Common control and status
81 * 1000 -> 10FF Synchronizer control and status
82 * 1F00 -> 1FFF Smart Antenna control and status
83 * 2100 -> 21FF VSB Equalizer control and status
84 * 2800 -> 28FF QAM Equalizer control and status
85 * 3000 -> 30FF FEC control and status
86 */
b63b36fa 87
f883d603
MIK		 88enum lgdt3306a_lock_status {
89 LG3306_UNLOCK = 0x00,
90 LG3306_LOCK = 0x01,
4937ba94 91 LG3306_UNKNOWN_LOCK = 0xff
f883d603 92};
b63b36fa 93
f883d603 94enum lgdt3306a_neverlock_status {
b63b36fa
FR		 95 LG3306_NL_INIT = 0x00,
96 LG3306_NL_PROCESS = 0x01,
97 LG3306_NL_LOCK = 0x02,
98 LG3306_NL_FAIL = 0x03,
4937ba94 99 LG3306_NL_UNKNOWN = 0xff
f883d603 100};
b63b36fa 101
f883d603
MIK		 102enum lgdt3306a_modulation {
103 LG3306_VSB = 0x00,
104 LG3306_QAM64 = 0x01,
105 LG3306_QAM256 = 0x02,
4937ba94 106 LG3306_UNKNOWN_MODE = 0xff
f883d603 107};
b63b36fa 108
f883d603 109enum lgdt3306a_lock_check {
b63b36fa
FR		 110 LG3306_SYNC_LOCK,
111 LG3306_FEC_LOCK,
112 LG3306_TR_LOCK,
113 LG3306_AGC_LOCK,
f883d603 114};
b63b36fa
FR		 115
116
117#ifdef DBG_DUMP
118static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state);
119static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state);
120#endif
121
122
123static int lgdt3306a_write_reg(struct lgdt3306a_state *state, u16 reg, u8 val)
124{
125 int ret;
126 u8 buf[] = { reg >> 8, reg & 0xff, val };
127 struct i2c_msg msg = {
128 .addr = state->cfg->i2c_addr, .flags = 0,
129 .buf = buf, .len = 3,
130 };
131
097117ca 132 dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
b63b36fa
FR		 133
134 ret = i2c_transfer(state->i2c_adap, &msg, 1);
135
136 if (ret != 1) {
097117ca 137 pr_err("error (addr %02x %02x <- %02x, err = %i)\n",
b63b36fa
FR		 138 msg.buf[0], msg.buf[1], msg.buf[2], ret);
139 if (ret < 0)
140 return ret;
141 else
142 return -EREMOTEIO;
143 }
144 return 0;
145}
146
147static int lgdt3306a_read_reg(struct lgdt3306a_state *state, u16 reg, u8 *val)
148{
149 int ret;
150 u8 reg_buf[] = { reg >> 8, reg & 0xff };
151 struct i2c_msg msg[] = {
152 { .addr = state->cfg->i2c_addr,
153 .flags = 0, .buf = reg_buf, .len = 2 },
154 { .addr = state->cfg->i2c_addr,
155 .flags = I2C_M_RD, .buf = val, .len = 1 },
156 };
157
158 ret = i2c_transfer(state->i2c_adap, msg, 2);
159
160 if (ret != 2) {
097117ca 161 pr_err("error (addr %02x reg %04x error (ret == %i)\n",
b63b36fa
FR		 162 state->cfg->i2c_addr, reg, ret);
163 if (ret < 0)
164 return ret;
165 else
166 return -EREMOTEIO;
167 }
097117ca 168 dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, *val);
b63b36fa
FR		 169
170 return 0;
171}
172
173#define read_reg(state, reg) \
174({ \
175 u8 __val; \
176 int ret = lgdt3306a_read_reg(state, reg, &__val); \
177 if (lg_chkerr(ret)) \
178 __val = 0; \
179 __val; \
180})
181
182static int lgdt3306a_set_reg_bit(struct lgdt3306a_state *state,
183 u16 reg, int bit, int onoff)
184{
185 u8 val;
186 int ret;
187
097117ca 188 dbg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
b63b36fa
FR		 189
190 ret = lgdt3306a_read_reg(state, reg, &val);
191 if (lg_chkerr(ret))
192 goto fail;
193
194 val &= ~(1 << bit);
195 val |= (onoff & 1) << bit;
196
197 ret = lgdt3306a_write_reg(state, reg, val);
198 lg_chkerr(ret);
199fail:
200 return ret;
201}
202
203/* ------------------------------------------------------------------------ */
204
205static int lgdt3306a_soft_reset(struct lgdt3306a_state *state)
206{
207 int ret;
208
097117ca 209 dbg_info("\n");
b63b36fa
FR		 210
211 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
212 if (lg_chkerr(ret))
213 goto fail;
214
215 msleep(20);
216 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
217 lg_chkerr(ret);
218
219fail:
220 return ret;
221}
222
223static int lgdt3306a_mpeg_mode(struct lgdt3306a_state *state,
224 enum lgdt3306a_mpeg_mode mode)
225{
226 u8 val;
227 int ret;
228
097117ca 229 dbg_info("(%d)\n", mode);
534f4364
MCC		 230 /* transport packet format - TPSENB=0x80 */
231 ret = lgdt3306a_set_reg_bit(state, 0x0071, 7,
232 mode == LGDT3306A_MPEG_PARALLEL ? 1 : 0);
b63b36fa
FR		 233 if (lg_chkerr(ret))
234 goto fail;
235
534f4364
MCC		 236 /*
237 * start of packet signal duration
238 * TPSSOPBITEN=0x40; 0=byte duration, 1=bit duration
239 */
240 ret = lgdt3306a_set_reg_bit(state, 0x0071, 6, 0);
b63b36fa
FR		 241 if (lg_chkerr(ret))
242 goto fail;
243
244 ret = lgdt3306a_read_reg(state, 0x0070, &val);
245 if (lg_chkerr(ret))
246 goto fail;
247
8e8cd34e 248 val |= 0x10; /* TPCLKSUPB=0x10 */
b63b36fa 249
8e8cd34e 250 if (mode == LGDT3306A_MPEG_PARALLEL)
b63b36fa
FR		 251 val &= ~0x10;
252
253 ret = lgdt3306a_write_reg(state, 0x0070, val);
254 lg_chkerr(ret);
255
256fail:
257 return ret;
258}
259
260static int lgdt3306a_mpeg_mode_polarity(struct lgdt3306a_state *state,
261 enum lgdt3306a_tp_clock_edge edge,
262 enum lgdt3306a_tp_valid_polarity valid)
263{
264 u8 val;
265 int ret;
266
097117ca 267 dbg_info("edge=%d, valid=%d\n", edge, valid);
b63b36fa
FR		 268
269 ret = lgdt3306a_read_reg(state, 0x0070, &val);
270 if (lg_chkerr(ret))
271 goto fail;
272
8e8cd34e 273 val &= ~0x06; /* TPCLKPOL=0x04, TPVALPOL=0x02 */
b63b36fa 274
8e8cd34e 275 if (edge == LGDT3306A_TPCLK_RISING_EDGE)
b63b36fa 276 val |= 0x04;
8e8cd34e 277 if (valid == LGDT3306A_TP_VALID_HIGH)
b63b36fa
FR		 278 val |= 0x02;
279
280 ret = lgdt3306a_write_reg(state, 0x0070, val);
281 lg_chkerr(ret);
282
283fail:
284 return ret;
285}
286
287static int lgdt3306a_mpeg_tristate(struct lgdt3306a_state *state,
288 int mode)
289{
290 u8 val;
291 int ret;
292
097117ca 293 dbg_info("(%d)\n", mode);
b63b36fa 294
8e8cd34e 295 if (mode) {
b63b36fa
FR		 296 ret = lgdt3306a_read_reg(state, 0x0070, &val);
297 if (lg_chkerr(ret))
298 goto fail;
534f4364
MCC		 299 /*
300 * Tristate bus; TPOUTEN=0x80, TPCLKOUTEN=0x20,
301 * TPDATAOUTEN=0x08
302 */
303 val &= ~0xa8;
b63b36fa
FR		 304 ret = lgdt3306a_write_reg(state, 0x0070, val);
305 if (lg_chkerr(ret))
306 goto fail;
307
534f4364
MCC		 308 /* AGCIFOUTENB=0x40; 1=Disable IFAGC pin */
309 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 1);
b63b36fa
FR		 310 if (lg_chkerr(ret))
311 goto fail;
312
313 } else {
534f4364
MCC		 314 /* enable IFAGC pin */
315 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 0);
b63b36fa
FR		 316 if (lg_chkerr(ret))
317 goto fail;
318
319 ret = lgdt3306a_read_reg(state, 0x0070, &val);
320 if (lg_chkerr(ret))
321 goto fail;
322
4937ba94 323 val |= 0xa8; /* enable bus */
b63b36fa
FR		 324 ret = lgdt3306a_write_reg(state, 0x0070, val);
325 if (lg_chkerr(ret))
326 goto fail;
327 }
328
329fail:
330 return ret;
331}
332
8e8cd34e 333static int lgdt3306a_ts_bus_ctrl(struct dvb_frontend *fe, int acquire)
b63b36fa
FR		 334{
335 struct lgdt3306a_state *state = fe->demodulator_priv;
336
097117ca 337 dbg_info("acquire=%d\n", acquire);
b63b36fa
FR		 338
339 return lgdt3306a_mpeg_tristate(state, acquire ? 0 : 1);
340
341}
342
343static int lgdt3306a_power(struct lgdt3306a_state *state,
344 int mode)
345{
346 int ret;
347
097117ca 348 dbg_info("(%d)\n", mode);
b63b36fa 349
8e8cd34e 350 if (mode == 0) {
534f4364
MCC		 351 /* into reset */
352 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
b63b36fa
FR		 353 if (lg_chkerr(ret))
354 goto fail;
355
534f4364
MCC		 356 /* power down */
357 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 0);
b63b36fa
FR		 358 if (lg_chkerr(ret))
359 goto fail;
360
361 } else {
534f4364
MCC		 362 /* out of reset */
363 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
b63b36fa
FR		 364 if (lg_chkerr(ret))
365 goto fail;
366
534f4364
MCC		 367 /* power up */
368 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 1);
b63b36fa
FR		 369 if (lg_chkerr(ret))
370 goto fail;
371 }
372
373#ifdef DBG_DUMP
374 lgdt3306a_DumpAllRegs(state);
375#endif
376fail:
377 return ret;
378}
379
380
381static int lgdt3306a_set_vsb(struct lgdt3306a_state *state)
382{
383 u8 val;
384 int ret;
385
097117ca 386 dbg_info("\n");
b63b36fa 387
8e8cd34e 388 /* 0. Spectrum inversion detection manual; spectrum inverted */
b63b36fa 389 ret = lgdt3306a_read_reg(state, 0x0002, &val);
4937ba94 390 val &= 0xf7; /* SPECINVAUTO Off */
8e8cd34e 391 val |= 0x04; /* SPECINV On */
b63b36fa
FR		 392 ret = lgdt3306a_write_reg(state, 0x0002, val);
393 if (lg_chkerr(ret))
394 goto fail;
395
8e8cd34e 396 /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
b63b36fa
FR		 397 ret = lgdt3306a_write_reg(state, 0x0008, 0x80);
398 if (lg_chkerr(ret))
399 goto fail;
400
8e8cd34e 401 /* 2. Bandwidth mode for VSB(6MHz) */
b63b36fa 402 ret = lgdt3306a_read_reg(state, 0x0009, &val);
4937ba94
MCC		 403 val &= 0xe3;
404 val |= 0x0c; /* STDOPDETTMODE[2:0]=3 */
b63b36fa
FR		 405 ret = lgdt3306a_write_reg(state, 0x0009, val);
406 if (lg_chkerr(ret))
407 goto fail;
408
8e8cd34e 409 /* 3. QAM mode detection mode(None) */
b63b36fa 410 ret = lgdt3306a_read_reg(state, 0x0009, &val);
4937ba94 411 val &= 0xfc; /* STDOPDETCMODE[1:0]=0 */
b63b36fa
FR		 412 ret = lgdt3306a_write_reg(state, 0x0009, val);
413 if (lg_chkerr(ret))
414 goto fail;
415
8e8cd34e 416 /* 4. ADC sampling frequency rate(2x sampling) */
4937ba94
MCC		 417 ret = lgdt3306a_read_reg(state, 0x000d, &val);
418 val &= 0xbf; /* SAMPLING4XFEN=0 */
419 ret = lgdt3306a_write_reg(state, 0x000d, val);
b63b36fa
FR		 420 if (lg_chkerr(ret))
421 goto fail;
422
8e8cd34e
MIK		 423#if 0
424 /* FGR - disable any AICC filtering, testing only */
425
b63b36fa
FR		 426 ret = lgdt3306a_write_reg(state, 0x0024, 0x00);
427 if (lg_chkerr(ret))
428 goto fail;
429
8e8cd34e 430 /* AICCFIXFREQ0 NT N-1(Video rejection) */
4937ba94
MCC		 431 ret = lgdt3306a_write_reg(state, 0x002e, 0x00);
432 ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
b63b36fa
FR		 433 ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
434
8e8cd34e 435 /* AICCFIXFREQ1 NT N-1(Audio rejection) */
4937ba94
MCC		 436 ret = lgdt3306a_write_reg(state, 0x002b, 0x00);
437 ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
438 ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
b63b36fa 439
8e8cd34e 440 /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
b63b36fa
FR		 441 ret = lgdt3306a_write_reg(state, 0x0028, 0x00);
442 ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
4937ba94 443 ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
b63b36fa 444
8e8cd34e 445 /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
b63b36fa
FR		 446 ret = lgdt3306a_write_reg(state, 0x0025, 0x00);
447 ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
448 ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
449
8e8cd34e
MIK		 450#else
451 /* FGR - this works well for HVR-1955,1975 */
452
453 /* 5. AICCOPMODE NT N-1 Adj. */
b63b36fa
FR		 454 ret = lgdt3306a_write_reg(state, 0x0024, 0x5A);
455 if (lg_chkerr(ret))
456 goto fail;
457
8e8cd34e 458 /* AICCFIXFREQ0 NT N-1(Video rejection) */
4937ba94
MCC		 459 ret = lgdt3306a_write_reg(state, 0x002e, 0x5A);
460 ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
b63b36fa
FR		 461 ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
462
8e8cd34e 463 /* AICCFIXFREQ1 NT N-1(Audio rejection) */
4937ba94
MCC		 464 ret = lgdt3306a_write_reg(state, 0x002b, 0x36);
465 ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
466 ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
b63b36fa 467
8e8cd34e 468 /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
b63b36fa
FR		 469 ret = lgdt3306a_write_reg(state, 0x0028, 0x2A);
470 ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
4937ba94 471 ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
b63b36fa 472
8e8cd34e 473 /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
b63b36fa
FR		 474 ret = lgdt3306a_write_reg(state, 0x0025, 0x06);
475 ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
476 ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
477#endif
478
4937ba94
MCC		 479 ret = lgdt3306a_read_reg(state, 0x001e, &val);
480 val &= 0x0f;
481 val |= 0xa0;
482 ret = lgdt3306a_write_reg(state, 0x001e, val);
b63b36fa
FR		 483
484 ret = lgdt3306a_write_reg(state, 0x0022, 0x08);
485
486 ret = lgdt3306a_write_reg(state, 0x0023, 0xFF);
487
4937ba94
MCC		 488 ret = lgdt3306a_read_reg(state, 0x211f, &val);
489 val &= 0xef;
490 ret = lgdt3306a_write_reg(state, 0x211f, val);
b63b36fa
FR		 491
492 ret = lgdt3306a_write_reg(state, 0x2173, 0x01);
493
494 ret = lgdt3306a_read_reg(state, 0x1061, &val);
4937ba94 495 val &= 0xf8;
b63b36fa
FR		 496 val |= 0x04;
497 ret = lgdt3306a_write_reg(state, 0x1061, val);
498
4937ba94
MCC		 499 ret = lgdt3306a_read_reg(state, 0x103d, &val);
500 val &= 0xcf;
501 ret = lgdt3306a_write_reg(state, 0x103d, val);
b63b36fa
FR		 502
503 ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
504
505 ret = lgdt3306a_read_reg(state, 0x2141, &val);
4937ba94 506 val &= 0x3f;
b63b36fa
FR		 507 ret = lgdt3306a_write_reg(state, 0x2141, val);
508
509 ret = lgdt3306a_read_reg(state, 0x2135, &val);
4937ba94 510 val &= 0x0f;
b63b36fa
FR		 511 val |= 0x70;
512 ret = lgdt3306a_write_reg(state, 0x2135, val);
513
514 ret = lgdt3306a_read_reg(state, 0x0003, &val);
4937ba94 515 val &= 0xf7;
b63b36fa
FR		 516 ret = lgdt3306a_write_reg(state, 0x0003, val);
517
4937ba94
MCC		 518 ret = lgdt3306a_read_reg(state, 0x001c, &val);
519 val &= 0x7f;
520 ret = lgdt3306a_write_reg(state, 0x001c, val);
b63b36fa 521
8e8cd34e 522 /* 6. EQ step size */
b63b36fa 523 ret = lgdt3306a_read_reg(state, 0x2179, &val);
4937ba94 524 val &= 0xf8;
b63b36fa
FR		 525 ret = lgdt3306a_write_reg(state, 0x2179, val);
526
4937ba94
MCC		 527 ret = lgdt3306a_read_reg(state, 0x217a, &val);
528 val &= 0xf8;
529 ret = lgdt3306a_write_reg(state, 0x217a, val);
b63b36fa 530
8e8cd34e 531 /* 7. Reset */
b63b36fa
FR		 532 ret = lgdt3306a_soft_reset(state);
533 if (lg_chkerr(ret))
534 goto fail;
535
097117ca 536 dbg_info("complete\n");
b63b36fa
FR		 537fail:
538 return ret;
539}
540
541static int lgdt3306a_set_qam(struct lgdt3306a_state *state, int modulation)
542{
543 u8 val;
544 int ret;
545
097117ca 546 dbg_info("modulation=%d\n", modulation);
b63b36fa 547
8e8cd34e 548 /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
b63b36fa
FR		 549 ret = lgdt3306a_write_reg(state, 0x0008, 0x08);
550 if (lg_chkerr(ret))
551 goto fail;
552
8e8cd34e 553 /* 1a. Spectrum inversion detection to Auto */
b63b36fa 554 ret = lgdt3306a_read_reg(state, 0x0002, &val);
4937ba94 555 val &= 0xfb; /* SPECINV Off */
8e8cd34e 556 val |= 0x08; /* SPECINVAUTO On */
b63b36fa
FR		 557 ret = lgdt3306a_write_reg(state, 0x0002, val);
558 if (lg_chkerr(ret))
559 goto fail;
560
8e8cd34e 561 /* 2. Bandwidth mode for QAM */
b63b36fa 562 ret = lgdt3306a_read_reg(state, 0x0009, &val);
4937ba94 563 val &= 0xe3; /* STDOPDETTMODE[2:0]=0 VSB Off */
b63b36fa
FR		 564 ret = lgdt3306a_write_reg(state, 0x0009, val);
565 if (lg_chkerr(ret))
566 goto fail;
567
8e8cd34e 568 /* 3. : 64QAM/256QAM detection(manual, auto) */
b63b36fa 569 ret = lgdt3306a_read_reg(state, 0x0009, &val);
4937ba94 570 val &= 0xfc;
4966c0c5
BL		 571 /* Check for forced Manual modulation modes; otherwise always "auto" */
572 if(forced_manual && (modulation != QAM_AUTO)){
573 val |= 0x01; /* STDOPDETCMODE[1:0]= 1=Manual */
574 } else {
575 val |= 0x02; /* STDOPDETCMODE[1:0]= 2=Auto */
576 }
b63b36fa
FR		 577 ret = lgdt3306a_write_reg(state, 0x0009, val);
578 if (lg_chkerr(ret))
579 goto fail;
580
8e8cd34e 581 /* 3a. : 64QAM/256QAM selection for manual */
b63b36fa 582 ret = lgdt3306a_read_reg(state, 0x101a, &val);
4937ba94 583 val &= 0xf8;
8e8cd34e
MIK		 584 if (modulation == QAM_64)
585 val |= 0x02; /* QMDQMODE[2:0]=2=QAM64 */
586 else
587 val |= 0x04; /* QMDQMODE[2:0]=4=QAM256 */
588
b63b36fa
FR		 589 ret = lgdt3306a_write_reg(state, 0x101a, val);
590 if (lg_chkerr(ret))
591 goto fail;
592
8e8cd34e 593 /* 4. ADC sampling frequency rate(4x sampling) */
4937ba94
MCC		 594 ret = lgdt3306a_read_reg(state, 0x000d, &val);
595 val &= 0xbf;
8e8cd34e 596 val |= 0x40; /* SAMPLING4XFEN=1 */
4937ba94 597 ret = lgdt3306a_write_reg(state, 0x000d, val);
b63b36fa
FR		 598 if (lg_chkerr(ret))
599 goto fail;
600
8e8cd34e 601 /* 5. No AICC operation in QAM mode */
b63b36fa
FR		 602 ret = lgdt3306a_read_reg(state, 0x0024, &val);
603 val &= 0x00;
604 ret = lgdt3306a_write_reg(state, 0x0024, val);
605 if (lg_chkerr(ret))
606 goto fail;
607
4c7c3f9b
BL		 608 /* 5.1 V0.36 SRDCHKALWAYS : For better QAM detection */
609 ret = lgdt3306a_read_reg(state, 0x000a, &val);
610 val &= 0xfd;
611 val |= 0x02;
612 ret = lgdt3306a_write_reg(state, 0x000a, val);
613 if (lg_chkerr(ret))
614 goto fail;
615
616 /* 5.2 V0.36 Control of "no signal" detector function */
617 ret = lgdt3306a_read_reg(state, 0x2849, &val);
618 val &= 0xdf;
619 ret = lgdt3306a_write_reg(state, 0x2849, val);
620 if (lg_chkerr(ret))
621 goto fail;
622
623 /* 5.3 Fix for Blonder Tongue HDE-2H-QAM and AQM modulators */
624 ret = lgdt3306a_read_reg(state, 0x302b, &val);
625 val &= 0x7f; /* SELFSYNCFINDEN_CQS=0; disable auto reset */
626 ret = lgdt3306a_write_reg(state, 0x302b, val);
627 if (lg_chkerr(ret))
628 goto fail;
629
8e8cd34e 630 /* 6. Reset */
b63b36fa
FR		 631 ret = lgdt3306a_soft_reset(state);
632 if (lg_chkerr(ret))
633 goto fail;
634
097117ca 635 dbg_info("complete\n");
b63b36fa
FR		 636fail:
637 return ret;
638}
639
640static int lgdt3306a_set_modulation(struct lgdt3306a_state *state,
641 struct dtv_frontend_properties *p)
642{
643 int ret;
644
097117ca 645 dbg_info("\n");
b63b36fa
FR		 646
647 switch (p->modulation) {
648 case VSB_8:
649 ret = lgdt3306a_set_vsb(state);
650 break;
651 case QAM_64:
b63b36fa 652 case QAM_256:
4966c0c5
BL		 653 case QAM_AUTO:
654 ret = lgdt3306a_set_qam(state, p->modulation);
b63b36fa
FR		 655 break;
656 default:
657 return -EINVAL;
658 }
659 if (lg_chkerr(ret))
660 goto fail;
661
662 state->current_modulation = p->modulation;
663
664fail:
665 return ret;
666}
667
668/* ------------------------------------------------------------------------ */
669
670static int lgdt3306a_agc_setup(struct lgdt3306a_state *state,
671 struct dtv_frontend_properties *p)
672{
8e8cd34e 673 /* TODO: anything we want to do here??? */
097117ca 674 dbg_info("\n");
b63b36fa
FR		 675
676 switch (p->modulation) {
677 case VSB_8:
678 break;
679 case QAM_64:
680 case QAM_256:
4966c0c5 681 case QAM_AUTO:
b63b36fa
FR		 682 break;
683 default:
684 return -EINVAL;
685 }
686 return 0;
687}
688
689/* ------------------------------------------------------------------------ */
690
691static int lgdt3306a_set_inversion(struct lgdt3306a_state *state,
692 int inversion)
693{
694 int ret;
695
097117ca 696 dbg_info("(%d)\n", inversion);
b63b36fa 697
8e8cd34e 698 ret = lgdt3306a_set_reg_bit(state, 0x0002, 2, inversion ? 1 : 0);
b63b36fa
FR		 699 return ret;
700}
701
702static int lgdt3306a_set_inversion_auto(struct lgdt3306a_state *state,
703 int enabled)
704{
705 int ret;
706
097117ca 707 dbg_info("(%d)\n", enabled);
b63b36fa 708
534f4364
MCC		 709 /* 0=Manual 1=Auto(QAM only) - SPECINVAUTO=0x04 */
710 ret = lgdt3306a_set_reg_bit(state, 0x0002, 3, enabled);
b63b36fa
FR		 711 return ret;
712}
713
714static int lgdt3306a_spectral_inversion(struct lgdt3306a_state *state,
715 struct dtv_frontend_properties *p,
716 int inversion)
717{
718 int ret = 0;
719
097117ca 720 dbg_info("(%d)\n", inversion);
8e8cd34e 721#if 0
534f4364
MCC		 722 /*
723 * FGR - spectral_inversion defaults already set for VSB and QAM;
724 * can enable later if desired
725 */
b63b36fa
FR		 726
727 ret = lgdt3306a_set_inversion(state, inversion);
728
729 switch (p->modulation) {
730 case VSB_8:
534f4364
MCC		 731 /* Manual only for VSB */
732 ret = lgdt3306a_set_inversion_auto(state, 0);
b63b36fa
FR		 733 break;
734 case QAM_64:
735 case QAM_256:
4966c0c5 736 case QAM_AUTO:
534f4364
MCC		 737 /* Auto ok for QAM */
738 ret = lgdt3306a_set_inversion_auto(state, 1);
b63b36fa
FR		 739 break;
740 default:
741 ret = -EINVAL;
742 }
743#endif
744 return ret;
745}
746
747static int lgdt3306a_set_if(struct lgdt3306a_state *state,
748 struct dtv_frontend_properties *p)
749{
750 int ret;
751 u16 if_freq_khz;
752 u8 nco1, nco2;
753
754 switch (p->modulation) {
755 case VSB_8:
756 if_freq_khz = state->cfg->vsb_if_khz;
757 break;
758 case QAM_64:
759 case QAM_256:
4966c0c5 760 case QAM_AUTO:
b63b36fa
FR		 761 if_freq_khz = state->cfg->qam_if_khz;
762 break;
763 default:
764 return -EINVAL;
765 }
766
8e8cd34e 767 switch (if_freq_khz) {
b63b36fa 768 default:
f86548cf 769 pr_warn("IF=%d KHz is not supported, 3250 assumed\n",
534f4364 770 if_freq_khz);
8e8cd34e 771 /* fallthrough */
34a5a2f8 772 case 3250: /* 3.25Mhz */
b63b36fa
FR		 773 nco1 = 0x34;
774 nco2 = 0x00;
775 break;
34a5a2f8 776 case 3500: /* 3.50Mhz */
b63b36fa
FR		 777 nco1 = 0x38;
778 nco2 = 0x00;
779 break;
34a5a2f8 780 case 4000: /* 4.00Mhz */
b63b36fa
FR		 781 nco1 = 0x40;
782 nco2 = 0x00;
783 break;
34a5a2f8 784 case 5000: /* 5.00Mhz */
b63b36fa
FR		 785 nco1 = 0x50;
786 nco2 = 0x00;
787 break;
8e8cd34e 788 case 5380: /* 5.38Mhz */
b63b36fa
FR		 789 nco1 = 0x56;
790 nco2 = 0x14;
791 break;
792 }
793 ret = lgdt3306a_write_reg(state, 0x0010, nco1);
ee0133ee
MCC		 794 if (ret)
795 return ret;
b63b36fa 796 ret = lgdt3306a_write_reg(state, 0x0011, nco2);
ee0133ee
MCC		 797 if (ret)
798 return ret;
b63b36fa 799
097117ca 800 dbg_info("if_freq=%d KHz->[%04x]\n", if_freq_khz, nco1<<8 | nco2);
b63b36fa
FR		 801
802 return 0;
803}
804
805/* ------------------------------------------------------------------------ */
806
807static int lgdt3306a_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
808{
809 struct lgdt3306a_state *state = fe->demodulator_priv;
810
8e8cd34e 811 if (state->cfg->deny_i2c_rptr) {
097117ca 812 dbg_info("deny_i2c_rptr=%d\n", state->cfg->deny_i2c_rptr);
b63b36fa
FR		 813 return 0;
814 }
097117ca 815 dbg_info("(%d)\n", enable);
b63b36fa 816
534f4364
MCC		 817 /* NI2CRPTEN=0x80 */
818 return lgdt3306a_set_reg_bit(state, 0x0002, 7, enable ? 0 : 1);
b63b36fa
FR		 819}
820
821static int lgdt3306a_sleep(struct lgdt3306a_state *state)
822{
823 int ret;
824
097117ca 825 dbg_info("\n");
8e8cd34e 826 state->current_frequency = -1; /* force re-tune, when we wake */
b63b36fa 827
8e8cd34e 828 ret = lgdt3306a_mpeg_tristate(state, 1); /* disable data bus */
b63b36fa
FR		 829 if (lg_chkerr(ret))
830 goto fail;
831
8e8cd34e 832 ret = lgdt3306a_power(state, 0); /* power down */
b63b36fa
FR		 833 lg_chkerr(ret);
834
835fail:
836 return 0;
837}
838
839static int lgdt3306a_fe_sleep(struct dvb_frontend *fe)
840{
841 struct lgdt3306a_state *state = fe->demodulator_priv;
842
843 return lgdt3306a_sleep(state);
844}
845
846static int lgdt3306a_init(struct dvb_frontend *fe)
847{
848 struct lgdt3306a_state *state = fe->demodulator_priv;
849 u8 val;
850 int ret;
851
097117ca 852 dbg_info("\n");
b63b36fa 853
8e8cd34e
MIK		 854 /* 1. Normal operation mode */
855 ret = lgdt3306a_set_reg_bit(state, 0x0001, 0, 1); /* SIMFASTENB=0x01 */
b63b36fa
FR		 856 if (lg_chkerr(ret))
857 goto fail;
858
8e8cd34e 859 /* 2. Spectrum inversion auto detection (Not valid for VSB) */
b63b36fa
FR		 860 ret = lgdt3306a_set_inversion_auto(state, 0);
861 if (lg_chkerr(ret))
862 goto fail;
863
8e8cd34e 864 /* 3. Spectrum inversion(According to the tuner configuration) */
b63b36fa
FR		 865 ret = lgdt3306a_set_inversion(state, 1);
866 if (lg_chkerr(ret))
867 goto fail;
868
8e8cd34e 869 /* 4. Peak-to-peak voltage of ADC input signal */
534f4364
MCC		 870
871 /* ADCSEL1V=0x80=1Vpp; 0x00=2Vpp */
872 ret = lgdt3306a_set_reg_bit(state, 0x0004, 7, 1);
b63b36fa
FR		 873 if (lg_chkerr(ret))
874 goto fail;
875
8e8cd34e 876 /* 5. ADC output data capture clock phase */
534f4364
MCC		 877
878 /* 0=same phase as ADC clock */
879 ret = lgdt3306a_set_reg_bit(state, 0x0004, 2, 0);
b63b36fa
FR		 880 if (lg_chkerr(ret))
881 goto fail;
882
8e8cd34e 883 /* 5a. ADC sampling clock source */
534f4364
MCC		 884
885 /* ADCCLKPLLSEL=0x08; 0=use ext clock, not PLL */
886 ret = lgdt3306a_set_reg_bit(state, 0x0004, 3, 0);
b63b36fa
FR		 887 if (lg_chkerr(ret))
888 goto fail;
889
8e8cd34e 890 /* 6. Automatic PLL set */
534f4364
MCC		 891
892 /* PLLSETAUTO=0x40; 0=off */
893 ret = lgdt3306a_set_reg_bit(state, 0x0005, 6, 0);
b63b36fa
FR		 894 if (lg_chkerr(ret))
895 goto fail;
896
8e8cd34e
MIK		 897 if (state->cfg->xtalMHz == 24) { /* 24MHz */
898 /* 7. Frequency for PLL output(0x2564 for 192MHz for 24MHz) */
b63b36fa
FR		 899 ret = lgdt3306a_read_reg(state, 0x0005, &val);
900 if (lg_chkerr(ret))
901 goto fail;
4937ba94 902 val &= 0xc0;
b63b36fa
FR		 903 val |= 0x25;
904 ret = lgdt3306a_write_reg(state, 0x0005, val);
905 if (lg_chkerr(ret))
906 goto fail;
907 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
908 if (lg_chkerr(ret))
909 goto fail;
910
8e8cd34e 911 /* 8. ADC sampling frequency(0x180000 for 24MHz sampling) */
4937ba94 912 ret = lgdt3306a_read_reg(state, 0x000d, &val);
b63b36fa
FR		 913 if (lg_chkerr(ret))
914 goto fail;
4937ba94 915 val &= 0xc0;
b63b36fa 916 val |= 0x18;
4937ba94 917 ret = lgdt3306a_write_reg(state, 0x000d, val);
b63b36fa
FR		 918 if (lg_chkerr(ret))
919 goto fail;
920
8e8cd34e
MIK		 921 } else if (state->cfg->xtalMHz == 25) { /* 25MHz */
922 /* 7. Frequency for PLL output */
b63b36fa
FR		 923 ret = lgdt3306a_read_reg(state, 0x0005, &val);
924 if (lg_chkerr(ret))
925 goto fail;
4937ba94 926 val &= 0xc0;
b63b36fa
FR		 927 val |= 0x25;
928 ret = lgdt3306a_write_reg(state, 0x0005, val);
929 if (lg_chkerr(ret))
930 goto fail;
931 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
932 if (lg_chkerr(ret))
933 goto fail;
934
8e8cd34e 935 /* 8. ADC sampling frequency(0x190000 for 25MHz sampling) */
4937ba94 936 ret = lgdt3306a_read_reg(state, 0x000d, &val);
b63b36fa
FR		 937 if (lg_chkerr(ret))
938 goto fail;
4937ba94 939 val &= 0xc0;
b63b36fa 940 val |= 0x19;
4937ba94 941 ret = lgdt3306a_write_reg(state, 0x000d, val);
b63b36fa
FR		 942 if (lg_chkerr(ret))
943 goto fail;
944 } else {
097117ca 945 pr_err("Bad xtalMHz=%d\n", state->cfg->xtalMHz);
b63b36fa 946 }
8e8cd34e 947#if 0
4937ba94
MCC		 948 ret = lgdt3306a_write_reg(state, 0x000e, 0x00);
949 ret = lgdt3306a_write_reg(state, 0x000f, 0x00);
8e8cd34e 950#endif
b63b36fa 951
8e8cd34e
MIK		 952 /* 9. Center frequency of input signal of ADC */
953 ret = lgdt3306a_write_reg(state, 0x0010, 0x34); /* 3.25MHz */
954 ret = lgdt3306a_write_reg(state, 0x0011, 0x00);
b63b36fa 955
8e8cd34e
MIK		 956 /* 10. Fixed gain error value */
957 ret = lgdt3306a_write_reg(state, 0x0014, 0); /* gain error=0 */
b63b36fa 958
8e8cd34e 959 /* 10a. VSB TR BW gear shift initial step */
4937ba94
MCC		 960 ret = lgdt3306a_read_reg(state, 0x103c, &val);
961 val &= 0x0f;
8e8cd34e 962 val |= 0x20; /* SAMGSAUTOSTL_V[3:0] = 2 */
4937ba94 963 ret = lgdt3306a_write_reg(state, 0x103c, val);
b63b36fa 964
8e8cd34e 965 /* 10b. Timing offset calibration in low temperature for VSB */
4937ba94
MCC		 966 ret = lgdt3306a_read_reg(state, 0x103d, &val);
967 val &= 0xfc;
b63b36fa 968 val |= 0x03;
4937ba94 969 ret = lgdt3306a_write_reg(state, 0x103d, val);
b63b36fa 970
8e8cd34e 971 /* 10c. Timing offset calibration in low temperature for QAM */
b63b36fa 972 ret = lgdt3306a_read_reg(state, 0x1036, &val);
4937ba94
MCC		 973 val &= 0xf0;
974 val |= 0x0c;
b63b36fa
FR		 975 ret = lgdt3306a_write_reg(state, 0x1036, val);
976
8e8cd34e 977 /* 11. Using the imaginary part of CIR in CIR loading */
4937ba94
MCC		 978 ret = lgdt3306a_read_reg(state, 0x211f, &val);
979 val &= 0xef; /* do not use imaginary of CIR */
980 ret = lgdt3306a_write_reg(state, 0x211f, val);
b63b36fa 981
8e8cd34e 982 /* 12. Control of no signal detector function */
b63b36fa 983 ret = lgdt3306a_read_reg(state, 0x2849, &val);
4937ba94 984 val &= 0xef; /* NOUSENOSIGDET=0, enable no signal detector */
b63b36fa
FR		 985 ret = lgdt3306a_write_reg(state, 0x2849, val);
986
8e8cd34e 987 /* FGR - put demod in some known mode */
b63b36fa
FR		 988 ret = lgdt3306a_set_vsb(state);
989
8e8cd34e 990 /* 13. TP stream format */
b63b36fa
FR		 991 ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
992
8e8cd34e 993 /* 14. disable output buses */
b63b36fa
FR		 994 ret = lgdt3306a_mpeg_tristate(state, 1);
995
8e8cd34e 996 /* 15. Sleep (in reset) */
b63b36fa
FR		 997 ret = lgdt3306a_sleep(state);
998 lg_chkerr(ret);
999
1000fail:
1001 return ret;
1002}
1003
1004static int lgdt3306a_set_parameters(struct dvb_frontend *fe)
1005{
1006 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1007 struct lgdt3306a_state *state = fe->demodulator_priv;
1008 int ret;
1009
097117ca 1010 dbg_info("(%d, %d)\n", p->frequency, p->modulation);
b63b36fa 1011
8e8cd34e
MIK		 1012 if (state->current_frequency == p->frequency &&
1013 state->current_modulation == p->modulation) {
097117ca 1014 dbg_info(" (already set, skipping ...)\n");
b63b36fa
FR		 1015 return 0;
1016 }
1017 state->current_frequency = -1;
1018 state->current_modulation = -1;
1019
8e8cd34e 1020 ret = lgdt3306a_power(state, 1); /* power up */
b63b36fa
FR		 1021 if (lg_chkerr(ret))
1022 goto fail;
1023
1024 if (fe->ops.tuner_ops.set_params) {
1025 ret = fe->ops.tuner_ops.set_params(fe);
1026 if (fe->ops.i2c_gate_ctrl)
1027 fe->ops.i2c_gate_ctrl(fe, 0);
8e8cd34e
MIK		 1028#if 0
1029 if (lg_chkerr(ret))
1030 goto fail;
1031 state->current_frequency = p->frequency;
1032#endif
b63b36fa
FR		 1033 }
1034
1035 ret = lgdt3306a_set_modulation(state, p);
1036 if (lg_chkerr(ret))
1037 goto fail;
1038
1039 ret = lgdt3306a_agc_setup(state, p);
1040 if (lg_chkerr(ret))
1041 goto fail;
1042
1043 ret = lgdt3306a_set_if(state, p);
1044 if (lg_chkerr(ret))
1045 goto fail;
1046
1047 ret = lgdt3306a_spectral_inversion(state, p,
534f4364 1048 state->cfg->spectral_inversion ? 1 : 0);
b63b36fa
FR		 1049 if (lg_chkerr(ret))
1050 goto fail;
1051
1052 ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
1053 if (lg_chkerr(ret))
1054 goto fail;
1055
1056 ret = lgdt3306a_mpeg_mode_polarity(state,
1057 state->cfg->tpclk_edge,
1058 state->cfg->tpvalid_polarity);
1059 if (lg_chkerr(ret))
1060 goto fail;
1061
8e8cd34e 1062 ret = lgdt3306a_mpeg_tristate(state, 0); /* enable data bus */
b63b36fa
FR		 1063 if (lg_chkerr(ret))
1064 goto fail;
1065
1066 ret = lgdt3306a_soft_reset(state);
1067 if (lg_chkerr(ret))
1068 goto fail;
1069
1070#ifdef DBG_DUMP
1071 lgdt3306a_DumpAllRegs(state);
1072#endif
1073 state->current_frequency = p->frequency;
1074fail:
1075 return ret;
1076}
1077
7e3e68bc
MCC		 1078static int lgdt3306a_get_frontend(struct dvb_frontend *fe,
1079 struct dtv_frontend_properties *p)
b63b36fa
FR		 1080{
1081 struct lgdt3306a_state *state = fe->demodulator_priv;
b63b36fa 1082
534f4364
MCC		 1083 dbg_info("(%u, %d)\n",
1084 state->current_frequency, state->current_modulation);
b63b36fa
FR		 1085
1086 p->modulation = state->current_modulation;
1087 p->frequency = state->current_frequency;
1088 return 0;
1089}
1090
1091static enum dvbfe_algo lgdt3306a_get_frontend_algo(struct dvb_frontend *fe)
1092{
1093#if 1
1094 return DVBFE_ALGO_CUSTOM;
1095#else
1096 return DVBFE_ALGO_HW;
1097#endif
1098}
1099
1100/* ------------------------------------------------------------------------ */
ee0133ee 1101static int lgdt3306a_monitor_vsb(struct lgdt3306a_state *state)
b63b36fa
FR		 1102{
1103 u8 val;
1104 int ret;
8e8cd34e
MIK		 1105 u8 snrRef, maxPowerMan, nCombDet;
1106 u16 fbDlyCir;
b63b36fa 1107
4937ba94 1108 ret = lgdt3306a_read_reg(state, 0x21a1, &val);
ee0133ee
MCC		 1109 if (ret)
1110 return ret;
4937ba94 1111 snrRef = val & 0x3f;
b63b36fa
FR		 1112
1113 ret = lgdt3306a_read_reg(state, 0x2185, &maxPowerMan);
ee0133ee
MCC		 1114 if (ret)
1115 return ret;
b63b36fa
FR		 1116
1117 ret = lgdt3306a_read_reg(state, 0x2191, &val);
ee0133ee
MCC		 1118 if (ret)
1119 return ret;
b63b36fa
FR		 1120 nCombDet = (val & 0x80) >> 7;
1121
1122 ret = lgdt3306a_read_reg(state, 0x2180, &val);
ee0133ee
MCC		 1123 if (ret)
1124 return ret;
b63b36fa 1125 fbDlyCir = (val & 0x03) << 8;
ee0133ee 1126
b63b36fa 1127 ret = lgdt3306a_read_reg(state, 0x2181, &val);
ee0133ee
MCC		 1128 if (ret)
1129 return ret;
b63b36fa
FR		 1130 fbDlyCir |= val;
1131
097117ca 1132 dbg_info("snrRef=%d maxPowerMan=0x%x nCombDet=%d fbDlyCir=0x%x\n",
b63b36fa
FR		 1133 snrRef, maxPowerMan, nCombDet, fbDlyCir);
1134
8e8cd34e 1135 /* Carrier offset sub loop bandwidth */
b63b36fa 1136 ret = lgdt3306a_read_reg(state, 0x1061, &val);
ee0133ee
MCC		 1137 if (ret)
1138 return ret;
4937ba94 1139 val &= 0xf8;
534f4364
MCC		 1140 if ((snrRef > 18) && (maxPowerMan > 0x68)
1141 && (nCombDet == 0x01)
1142 && ((fbDlyCir == 0x03FF) || (fbDlyCir < 0x6C))) {
8e8cd34e
MIK		 1143 /* SNR is over 18dB and no ghosting */
1144 val |= 0x00; /* final bandwidth = 0 */
b63b36fa 1145 } else {
8e8cd34e 1146 val |= 0x04; /* final bandwidth = 4 */
b63b36fa
FR		 1147 }
1148 ret = lgdt3306a_write_reg(state, 0x1061, val);
ee0133ee
MCC		 1149 if (ret)
1150 return ret;
b63b36fa 1151
8e8cd34e 1152 /* Adjust Notch Filter */
b63b36fa 1153 ret = lgdt3306a_read_reg(state, 0x0024, &val);
ee0133ee
MCC		 1154 if (ret)
1155 return ret;
4937ba94 1156 val &= 0x0f;
8e8cd34e 1157 if (nCombDet == 0) { /* Turn on the Notch Filter */
b63b36fa
FR		 1158 val |= 0x50;
1159 }
1160 ret = lgdt3306a_write_reg(state, 0x0024, val);
ee0133ee
MCC		 1161 if (ret)
1162 return ret;
b63b36fa 1163
8e8cd34e 1164 /* VSB Timing Recovery output normalization */
4937ba94 1165 ret = lgdt3306a_read_reg(state, 0x103d, &val);
ee0133ee
MCC		 1166 if (ret)
1167 return ret;
4937ba94 1168 val &= 0xcf;
b63b36fa 1169 val |= 0x20;
4937ba94 1170 ret = lgdt3306a_write_reg(state, 0x103d, val);
ee0133ee
MCC		 1171
1172 return ret;
b63b36fa
FR		 1173}
1174
534f4364
MCC		 1175static enum lgdt3306a_modulation
1176lgdt3306a_check_oper_mode(struct lgdt3306a_state *state)
b63b36fa
FR		 1177{
1178 u8 val = 0;
1179 int ret;
1180
1181 ret = lgdt3306a_read_reg(state, 0x0081, &val);
ee0133ee
MCC		 1182 if (ret)
1183 goto err;
b63b36fa
FR		 1184
1185 if (val & 0x80) {
097117ca 1186 dbg_info("VSB\n");
8e8cd34e 1187 return LG3306_VSB;
b63b36fa 1188 }
c714efe4 1189 if (val & 0x08) {
4937ba94 1190 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
ee0133ee
MCC		 1191 if (ret)
1192 goto err;
b63b36fa
FR		 1193 val = val >> 2;
1194 if (val & 0x01) {
097117ca 1195 dbg_info("QAM256\n");
8e8cd34e 1196 return LG3306_QAM256;
b63b36fa 1197 }
b4e43e95
MCC		 1198 dbg_info("QAM64\n");
1199 return LG3306_QAM64;
b63b36fa 1200 }
ee0133ee 1201err:
097117ca 1202 pr_warn("UNKNOWN\n");
8e8cd34e 1203 return LG3306_UNKNOWN_MODE;
b63b36fa
FR		 1204}
1205
534f4364
MCC		 1206static enum lgdt3306a_lock_status
1207lgdt3306a_check_lock_status(struct lgdt3306a_state *state,
1208 enum lgdt3306a_lock_check whatLock)
b63b36fa
FR		 1209{
1210 u8 val = 0;
1211 int ret;
f883d603
MIK		 1212 enum lgdt3306a_modulation modeOper;
1213 enum lgdt3306a_lock_status lockStatus;
b63b36fa
FR		 1214
1215 modeOper = LG3306_UNKNOWN_MODE;
1216
8e8cd34e
MIK		 1217 switch (whatLock) {
1218 case LG3306_SYNC_LOCK:
1219 {
4937ba94 1220 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
ee0133ee
MCC		 1221 if (ret)
1222 return ret;
8e8cd34e
MIK		 1223
1224 if ((val & 0x80) == 0x80)
1225 lockStatus = LG3306_LOCK;
1226 else
1227 lockStatus = LG3306_UNLOCK;
1228
097117ca 1229 dbg_info("SYNC_LOCK=%x\n", lockStatus);
8e8cd34e
MIK		 1230 break;
1231 }
1232 case LG3306_AGC_LOCK:
1233 {
1234 ret = lgdt3306a_read_reg(state, 0x0080, &val);
ee0133ee
MCC		 1235 if (ret)
1236 return ret;
8e8cd34e
MIK		 1237
1238 if ((val & 0x40) == 0x40)
1239 lockStatus = LG3306_LOCK;
1240 else
1241 lockStatus = LG3306_UNLOCK;
1242
097117ca 1243 dbg_info("AGC_LOCK=%x\n", lockStatus);
8e8cd34e
MIK		 1244 break;
1245 }
1246 case LG3306_TR_LOCK:
b63b36fa 1247 {
8e8cd34e
MIK		 1248 modeOper = lgdt3306a_check_oper_mode(state);
1249 if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
1250 ret = lgdt3306a_read_reg(state, 0x1094, &val);
ee0133ee
MCC		 1251 if (ret)
1252 return ret;
b63b36fa
FR		 1253
1254 if ((val & 0x80) == 0x80)
1255 lockStatus = LG3306_LOCK;
1256 else
1257 lockStatus = LG3306_UNLOCK;
8e8cd34e
MIK		 1258 } else
1259 lockStatus = LG3306_UNKNOWN_LOCK;
b63b36fa 1260
097117ca 1261 dbg_info("TR_LOCK=%x\n", lockStatus);
8e8cd34e
MIK		 1262 break;
1263 }
1264 case LG3306_FEC_LOCK:
1265 {
1266 modeOper = lgdt3306a_check_oper_mode(state);
1267 if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
b63b36fa 1268 ret = lgdt3306a_read_reg(state, 0x0080, &val);
ee0133ee
MCC		 1269 if (ret)
1270 return ret;
b63b36fa 1271
8e8cd34e 1272 if ((val & 0x10) == 0x10)
b63b36fa
FR		 1273 lockStatus = LG3306_LOCK;
1274 else
1275 lockStatus = LG3306_UNLOCK;
8e8cd34e
MIK		 1276 } else
1277 lockStatus = LG3306_UNKNOWN_LOCK;
b63b36fa 1278
097117ca 1279 dbg_info("FEC_LOCK=%x\n", lockStatus);
8e8cd34e
MIK		 1280 break;
1281 }
b63b36fa 1282
8e8cd34e
MIK		 1283 default:
1284 lockStatus = LG3306_UNKNOWN_LOCK;
097117ca 1285 pr_warn("UNKNOWN whatLock=%d\n", whatLock);
8e8cd34e 1286 break;
b63b36fa
FR		 1287 }
1288
8e8cd34e 1289 return lockStatus;
b63b36fa
FR		 1290}
1291
534f4364
MCC		 1292static enum lgdt3306a_neverlock_status
1293lgdt3306a_check_neverlock_status(struct lgdt3306a_state *state)
b63b36fa
FR		 1294{
1295 u8 val = 0;
1296 int ret;
f883d603 1297 enum lgdt3306a_neverlock_status lockStatus;
b63b36fa
FR		 1298
1299 ret = lgdt3306a_read_reg(state, 0x0080, &val);
ee0133ee
MCC		 1300 if (ret)
1301 return ret;
f883d603 1302 lockStatus = (enum lgdt3306a_neverlock_status)(val & 0x03);
b63b36fa 1303
097117ca 1304 dbg_info("NeverLock=%d", lockStatus);
b63b36fa 1305
8e8cd34e 1306 return lockStatus;
b63b36fa
FR		 1307}
1308
ee0133ee 1309static int lgdt3306a_pre_monitoring(struct lgdt3306a_state *state)
b63b36fa
FR		 1310{
1311 u8 val = 0;
1312 int ret;
1313 u8 currChDiffACQ, snrRef, mainStrong, aiccrejStatus;
1314
8e8cd34e 1315 /* Channel variation */
4937ba94 1316 ret = lgdt3306a_read_reg(state, 0x21bc, &currChDiffACQ);
ee0133ee
MCC		 1317 if (ret)
1318 return ret;
b63b36fa 1319
8e8cd34e 1320 /* SNR of Frame sync */
4937ba94 1321 ret = lgdt3306a_read_reg(state, 0x21a1, &val);
ee0133ee
MCC		 1322 if (ret)
1323 return ret;
4937ba94 1324 snrRef = val & 0x3f;
b63b36fa 1325
8e8cd34e 1326 /* Strong Main CIR */
b63b36fa 1327 ret = lgdt3306a_read_reg(state, 0x2199, &val);
ee0133ee
MCC		 1328 if (ret)
1329 return ret;
b63b36fa
FR		 1330 mainStrong = (val & 0x40) >> 6;
1331
1332 ret = lgdt3306a_read_reg(state, 0x0090, &val);
ee0133ee
MCC		 1333 if (ret)
1334 return ret;
4937ba94 1335 aiccrejStatus = (val & 0xf0) >> 4;
b63b36fa 1336
097117ca 1337 dbg_info("snrRef=%d mainStrong=%d aiccrejStatus=%d currChDiffACQ=0x%x\n",
b63b36fa
FR		 1338 snrRef, mainStrong, aiccrejStatus, currChDiffACQ);
1339
8e8cd34e 1340#if 0
534f4364
MCC		 1341 /* Dynamic ghost exists */
1342 if ((mainStrong == 0) && (currChDiffACQ > 0x70))
8e8cd34e
MIK		 1343#endif
1344 if (mainStrong == 0) {
b63b36fa 1345 ret = lgdt3306a_read_reg(state, 0x2135, &val);
ee0133ee
MCC		 1346 if (ret)
1347 return ret;
4937ba94
MCC		 1348 val &= 0x0f;
1349 val |= 0xa0;
b63b36fa 1350 ret = lgdt3306a_write_reg(state, 0x2135, val);
ee0133ee
MCC		 1351 if (ret)
1352 return ret;
b63b36fa
FR		 1353
1354 ret = lgdt3306a_read_reg(state, 0x2141, &val);
ee0133ee
MCC		 1355 if (ret)
1356 return ret;
4937ba94 1357 val &= 0x3f;
b63b36fa
FR		 1358 val |= 0x80;
1359 ret = lgdt3306a_write_reg(state, 0x2141, val);
ee0133ee
MCC		 1360 if (ret)
1361 return ret;
b63b36fa
FR		 1362
1363 ret = lgdt3306a_write_reg(state, 0x2122, 0x70);
ee0133ee
MCC		 1364 if (ret)
1365 return ret;
8e8cd34e 1366 } else { /* Weak ghost or static channel */
b63b36fa 1367 ret = lgdt3306a_read_reg(state, 0x2135, &val);
ee0133ee
MCC		 1368 if (ret)
1369 return ret;
4937ba94 1370 val &= 0x0f;
b63b36fa
FR		 1371 val |= 0x70;
1372 ret = lgdt3306a_write_reg(state, 0x2135, val);
ee0133ee
MCC		 1373 if (ret)
1374 return ret;
b63b36fa
FR		 1375
1376 ret = lgdt3306a_read_reg(state, 0x2141, &val);
ee0133ee
MCC		 1377 if (ret)
1378 return ret;
4937ba94 1379 val &= 0x3f;
b63b36fa
FR		 1380 val |= 0x40;
1381 ret = lgdt3306a_write_reg(state, 0x2141, val);
ee0133ee
MCC		 1382 if (ret)
1383 return ret;
b63b36fa
FR		 1384
1385 ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
ee0133ee
MCC		 1386 if (ret)
1387 return ret;
b63b36fa 1388 }
ee0133ee 1389 return 0;
b63b36fa
FR		 1390}
1391
534f4364
MCC		 1392static enum lgdt3306a_lock_status
1393lgdt3306a_sync_lock_poll(struct lgdt3306a_state *state)
b63b36fa 1394{
f883d603 1395 enum lgdt3306a_lock_status syncLockStatus = LG3306_UNLOCK;
b63b36fa
FR		 1396 int i;
1397
1398 for (i = 0; i < 2; i++) {
1399 msleep(30);
1400
534f4364
MCC		 1401 syncLockStatus = lgdt3306a_check_lock_status(state,
1402 LG3306_SYNC_LOCK);
b63b36fa
FR		 1403
1404 if (syncLockStatus == LG3306_LOCK) {
097117ca 1405 dbg_info("locked(%d)\n", i);
8e8cd34e 1406 return LG3306_LOCK;
b63b36fa
FR		 1407 }
1408 }
097117ca 1409 dbg_info("not locked\n");
8e8cd34e 1410 return LG3306_UNLOCK;
b63b36fa
FR		 1411}
1412
534f4364
MCC		 1413static enum lgdt3306a_lock_status
1414lgdt3306a_fec_lock_poll(struct lgdt3306a_state *state)
b63b36fa 1415{
f883d603 1416 enum lgdt3306a_lock_status FECLockStatus = LG3306_UNLOCK;
b63b36fa
FR		 1417 int i;
1418
1419 for (i = 0; i < 2; i++) {
1420 msleep(30);
1421
534f4364
MCC		 1422 FECLockStatus = lgdt3306a_check_lock_status(state,
1423 LG3306_FEC_LOCK);
b63b36fa
FR		 1424
1425 if (FECLockStatus == LG3306_LOCK) {
097117ca 1426 dbg_info("locked(%d)\n", i);
8e8cd34e 1427 return FECLockStatus;
b63b36fa
FR		 1428 }
1429 }
097117ca 1430 dbg_info("not locked\n");
8e8cd34e 1431 return FECLockStatus;
b63b36fa
FR		 1432}
1433
534f4364
MCC		 1434static enum lgdt3306a_neverlock_status
1435lgdt3306a_neverlock_poll(struct lgdt3306a_state *state)
b63b36fa 1436{
f883d603 1437 enum lgdt3306a_neverlock_status NLLockStatus = LG3306_NL_FAIL;
b63b36fa
FR		 1438 int i;
1439
8e8cd34e 1440 for (i = 0; i < 5; i++) {
b63b36fa
FR		 1441 msleep(30);
1442
1443 NLLockStatus = lgdt3306a_check_neverlock_status(state);
1444
1445 if (NLLockStatus == LG3306_NL_LOCK) {
097117ca 1446 dbg_info("NL_LOCK(%d)\n", i);
8e8cd34e 1447 return NLLockStatus;
b63b36fa
FR		 1448 }
1449 }
097117ca 1450 dbg_info("NLLockStatus=%d\n", NLLockStatus);
8e8cd34e 1451 return NLLockStatus;
b63b36fa
FR		 1452}
1453
1454static u8 lgdt3306a_get_packet_error(struct lgdt3306a_state *state)
1455{
1456 u8 val;
1457 int ret;
1458
4937ba94 1459 ret = lgdt3306a_read_reg(state, 0x00fa, &val);
ee0133ee
MCC		 1460 if (ret)
1461 return ret;
b63b36fa 1462
8e8cd34e 1463 return val;
b63b36fa
FR		 1464}
1465
9369fe01
MCC		 1466static const u32 valx_x10[] = {
1467 10, 11, 13, 15, 17, 20, 25, 33, 41, 50, 59, 73, 87, 100
1468};
1469static const u32 log10x_x1000[] = {
95f22c5a 1470 0, 41, 114, 176, 230, 301, 398, 518, 613, 699, 771, 863, 939, 1000
9369fe01
MCC		 1471};
1472
b63b36fa
FR		 1473static u32 log10_x1000(u32 x)
1474{
a132fef8 1475 u32 diff_val, step_val, step_log10;
b63b36fa 1476 u32 log_val = 0;
8e8cd34e 1477 u32 i;
b63b36fa 1478
8e8cd34e
MIK		 1479 if (x <= 0)
1480 return -1000000; /* signal error */
b63b36fa 1481
b4e43e95
MCC		 1482 if (x == 10)
1483 return 0; /* log(1)=0 */
1484
8e8cd34e
MIK		 1485 if (x < 10) {
1486 while (x < 10) {
1487 x = x * 10;
b63b36fa
FR		 1488 log_val--;
1489 }
b4e43e95 1490 } else { /* x > 10 */
8e8cd34e
MIK		 1491 while (x >= 100) {
1492 x = x / 10;
b63b36fa
FR		 1493 log_val++;
1494 }
8e8cd34e 1495 }
b63b36fa
FR		 1496 log_val *= 1000;
1497
8e8cd34e
MIK		 1498 if (x == 10) /* was our input an exact multiple of 10 */
1499 return log_val; /* don't need to interpolate */
b63b36fa 1500
8e8cd34e 1501 /* find our place on the log curve */
9369fe01 1502 for (i = 1; i < ARRAY_SIZE(valx_x10); i++) {
8e8cd34e
MIK		 1503 if (valx_x10[i] >= x)
1504 break;
b63b36fa 1505 }
9369fe01 1506 if (i == ARRAY_SIZE(valx_x10))
a132fef8 1507 return log_val + log10x_x1000[i - 1];
b63b36fa 1508
a132fef8
MCC		 1509 diff_val = x - valx_x10[i-1];
1510 step_val = valx_x10[i] - valx_x10[i - 1];
1511 step_log10 = log10x_x1000[i] - log10x_x1000[i - 1];
1512
1513 /* do a linear interpolation to get in-between values */
1514 return log_val + log10x_x1000[i - 1] +
1515 ((diff_val*step_log10) / step_val);
b63b36fa
FR		 1516}
1517
1518static u32 lgdt3306a_calculate_snr_x100(struct lgdt3306a_state *state)
1519{
34a5a2f8
MIK		 1520 u32 mse; /* Mean-Square Error */
1521 u32 pwr; /* Constelation power */
b63b36fa
FR		 1522 u32 snr_x100;
1523
4937ba94
MCC		 1524 mse = (read_reg(state, 0x00ec) << 8) |
1525 (read_reg(state, 0x00ed));
1526 pwr = (read_reg(state, 0x00e8) << 8) |
1527 (read_reg(state, 0x00e9));
b63b36fa
FR		 1528
1529 if (mse == 0) /* no signal */
1530 return 0;
1531
8e8cd34e 1532 snr_x100 = log10_x1000((pwr * 10000) / mse) - 3000;
097117ca 1533 dbg_info("mse=%u, pwr=%u, snr_x100=%d\n", mse, pwr, snr_x100);
b63b36fa
FR		 1534
1535 return snr_x100;
1536}
1537
534f4364
MCC		 1538static enum lgdt3306a_lock_status
1539lgdt3306a_vsb_lock_poll(struct lgdt3306a_state *state)
b63b36fa 1540{
e2c47fa7 1541 int ret;
8e8cd34e
MIK		 1542 u8 cnt = 0;
1543 u8 packet_error;
1544 u32 snr;
b63b36fa 1545
b1a88c71 1546 for (cnt = 0; cnt < 10; cnt++) {
b63b36fa 1547 if (lgdt3306a_sync_lock_poll(state) == LG3306_UNLOCK) {
097117ca 1548 dbg_info("no sync lock!\n");
8e8cd34e 1549 return LG3306_UNLOCK;
b1a88c71 1550 }
b63b36fa 1551
b1a88c71
MCC		 1552 msleep(20);
1553 ret = lgdt3306a_pre_monitoring(state);
1554 if (ret)
1555 break;
b63b36fa 1556
b1a88c71
MCC		 1557 packet_error = lgdt3306a_get_packet_error(state);
1558 snr = lgdt3306a_calculate_snr_x100(state);
1559 dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr);
b63b36fa 1560
b1a88c71
MCC		 1561 if ((snr >= 1500) && (packet_error < 0xff))
1562 return LG3306_LOCK;
b63b36fa 1563 }
b1a88c71
MCC		 1564
1565 dbg_info("not locked!\n");
8e8cd34e 1566 return LG3306_UNLOCK;
b63b36fa
FR		 1567}
1568
534f4364
MCC		 1569static enum lgdt3306a_lock_status
1570lgdt3306a_qam_lock_poll(struct lgdt3306a_state *state)
b63b36fa 1571{
b1a88c71 1572 u8 cnt;
b63b36fa
FR		 1573 u8 packet_error;
1574 u32 snr;
1575
b1a88c71 1576 for (cnt = 0; cnt < 10; cnt++) {
8e8cd34e 1577 if (lgdt3306a_fec_lock_poll(state) == LG3306_UNLOCK) {
097117ca 1578 dbg_info("no fec lock!\n");
8e8cd34e 1579 return LG3306_UNLOCK;
b1a88c71 1580 }
b63b36fa 1581
b1a88c71 1582 msleep(20);
b63b36fa 1583
b1a88c71
MCC		 1584 packet_error = lgdt3306a_get_packet_error(state);
1585 snr = lgdt3306a_calculate_snr_x100(state);
1586 dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr);
b63b36fa 1587
b1a88c71
MCC		 1588 if ((snr >= 1500) && (packet_error < 0xff))
1589 return LG3306_LOCK;
b63b36fa 1590 }
b1a88c71
MCC		 1591
1592 dbg_info("not locked!\n");
8e8cd34e 1593 return LG3306_UNLOCK;
b63b36fa
FR		 1594}
1595
0df289a2
MCC		 1596static int lgdt3306a_read_status(struct dvb_frontend *fe,
1597 enum fe_status *status)
b63b36fa 1598{
b63b36fa 1599 struct lgdt3306a_state *state = fe->demodulator_priv;
b63b36fa 1600 u16 strength = 0;
8e8cd34e
MIK		 1601 int ret = 0;
1602
b63b36fa
FR		 1603 if (fe->ops.tuner_ops.get_rf_strength) {
1604 ret = fe->ops.tuner_ops.get_rf_strength(fe, &strength);
c9897649 1605 if (ret == 0)
097117ca 1606 dbg_info("strength=%d\n", strength);
c9897649 1607 else
097117ca 1608 dbg_info("fe->ops.tuner_ops.get_rf_strength() failed\n");
b63b36fa
FR		 1609 }
1610
1611 *status = 0;
8e8cd34e 1612 if (lgdt3306a_neverlock_poll(state) == LG3306_NL_LOCK) {
b63b36fa
FR		 1613 *status |= FE_HAS_SIGNAL;
1614 *status |= FE_HAS_CARRIER;
1615
1616 switch (state->current_modulation) {
1617 case QAM_256:
1618 case QAM_64:
4966c0c5 1619 case QAM_AUTO:
8e8cd34e 1620 if (lgdt3306a_qam_lock_poll(state) == LG3306_LOCK) {
b63b36fa
FR		 1621 *status |= FE_HAS_VITERBI;
1622 *status |= FE_HAS_SYNC;
1623
1624 *status |= FE_HAS_LOCK;
1625 }
1626 break;
1627 case VSB_8:
8e8cd34e 1628 if (lgdt3306a_vsb_lock_poll(state) == LG3306_LOCK) {
b63b36fa
FR		 1629 *status |= FE_HAS_VITERBI;
1630 *status |= FE_HAS_SYNC;
1631
1632 *status |= FE_HAS_LOCK;
1633
ee0133ee 1634 ret = lgdt3306a_monitor_vsb(state);
b63b36fa
FR		 1635 }
1636 break;
1637 default:
1638 ret = -EINVAL;
1639 }
1640 }
1641 return ret;
1642}
1643
1644
1645static int lgdt3306a_read_snr(struct dvb_frontend *fe, u16 *snr)
1646{
1647 struct lgdt3306a_state *state = fe->demodulator_priv;
1648
1649 state->snr = lgdt3306a_calculate_snr_x100(state);
1650 /* report SNR in dB * 10 */
1651 *snr = state->snr/10;
1652
1653 return 0;
1654}
1655
1656static int lgdt3306a_read_signal_strength(struct dvb_frontend *fe,
1657 u16 *strength)
1658{
1659 /*
1660 * Calculate some sort of "strength" from SNR
1661 */
1662 struct lgdt3306a_state *state = fe->demodulator_priv;
4966c0c5 1663 u8 val;
34a5a2f8 1664 u16 snr; /* snr_x10 */
b63b36fa 1665 int ret;
8e8cd34e 1666 u32 ref_snr; /* snr*100 */
b63b36fa
FR		 1667 u32 str;
1668
1669 *strength = 0;
1670
1671 switch (state->current_modulation) {
1672 case VSB_8:
8e8cd34e 1673 ref_snr = 1600; /* 16dB */
b63b36fa
FR		 1674 break;
1675 case QAM_64:
b63b36fa 1676 case QAM_256:
4966c0c5
BL		 1677 case QAM_AUTO:
1678 /* need to know actual modulation to set proper SNR baseline */
c9b7d8f2
KL		 1679 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1680 if (lg_chkerr(ret))
1681 goto fail;
1682
4966c0c5
BL		 1683 if(val & 0x04)
1684 ref_snr = 2800; /* QAM-256 28dB */
1685 else
1686 ref_snr = 2200; /* QAM-64 22dB */
1687 break;
b63b36fa
FR		 1688 default:
1689 return -EINVAL;
1690 }
1691
1692 ret = fe->ops.read_snr(fe, &snr);
1693 if (lg_chkerr(ret))
1694 goto fail;
1695
8e8cd34e 1696 if (state->snr <= (ref_snr - 100))
b63b36fa 1697 str = 0;
8e8cd34e
MIK		 1698 else if (state->snr <= ref_snr)
1699 str = (0xffff * 65) / 100; /* 65% */
b63b36fa
FR		 1700 else {
1701 str = state->snr - ref_snr;
1702 str /= 50;
8e8cd34e
MIK		 1703 str += 78; /* 78%-100% */
1704 if (str > 100)
b63b36fa
FR		 1705 str = 100;
1706 str = (0xffff * str) / 100;
1707 }
1708 *strength = (u16)str;
097117ca 1709 dbg_info("strength=%u\n", *strength);
b63b36fa
FR		 1710
1711fail:
1712 return ret;
1713}
1714
1715/* ------------------------------------------------------------------------ */
1716
1717static int lgdt3306a_read_ber(struct dvb_frontend *fe, u32 *ber)
1718{
1719 struct lgdt3306a_state *state = fe->demodulator_priv;
1720 u32 tmp;
1721
1722 *ber = 0;
1723#if 1
534f4364 1724 /* FGR - FIXME - I don't know what value is expected by dvb_core
8e8cd34e 1725 * what is the scale of the value?? */
4937ba94
MCC		 1726 tmp = read_reg(state, 0x00fc); /* NBERVALUE[24-31] */
1727 tmp = (tmp << 8) | read_reg(state, 0x00fd); /* NBERVALUE[16-23] */
1728 tmp = (tmp << 8) | read_reg(state, 0x00fe); /* NBERVALUE[8-15] */
1729 tmp = (tmp << 8) | read_reg(state, 0x00ff); /* NBERVALUE[0-7] */
b63b36fa 1730 *ber = tmp;
097117ca 1731 dbg_info("ber=%u\n", tmp);
b63b36fa
FR		 1732#endif
1733 return 0;
1734}
1735
1736static int lgdt3306a_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1737{
1738 struct lgdt3306a_state *state = fe->demodulator_priv;
1739
8e8cd34e 1740 *ucblocks = 0;
b63b36fa 1741#if 1
534f4364 1742 /* FGR - FIXME - I don't know what value is expected by dvb_core
8e8cd34e 1743 * what happens when value wraps? */
4937ba94 1744 *ucblocks = read_reg(state, 0x00f4); /* TPIFTPERRCNT[0-7] */
097117ca 1745 dbg_info("ucblocks=%u\n", *ucblocks);
b63b36fa
FR		 1746#endif
1747
1748 return 0;
1749}
1750
534f4364
MCC		 1751static int lgdt3306a_tune(struct dvb_frontend *fe, bool re_tune,
1752 unsigned int mode_flags, unsigned int *delay,
0df289a2 1753 enum fe_status *status)
b63b36fa
FR		 1754{
1755 int ret = 0;
1756 struct lgdt3306a_state *state = fe->demodulator_priv;
1757
097117ca 1758 dbg_info("re_tune=%u\n", re_tune);
b63b36fa
FR		 1759
1760 if (re_tune) {
8e8cd34e 1761 state->current_frequency = -1; /* force re-tune */
ae21e447
MIK		 1762 ret = lgdt3306a_set_parameters(fe);
1763 if (ret != 0)
b63b36fa 1764 return ret;
b63b36fa
FR		 1765 }
1766 *delay = 125;
1767 ret = lgdt3306a_read_status(fe, status);
1768
1769 return ret;
1770}
1771
1772static int lgdt3306a_get_tune_settings(struct dvb_frontend *fe,
8e8cd34e
MIK		 1773 struct dvb_frontend_tune_settings
1774 *fe_tune_settings)
b63b36fa
FR		 1775{
1776 fe_tune_settings->min_delay_ms = 100;
097117ca 1777 dbg_info("\n");
b63b36fa
FR		 1778 return 0;
1779}
1780
f172fe9f 1781static enum dvbfe_search lgdt3306a_search(struct dvb_frontend *fe)
b63b36fa 1782{
0df289a2 1783 enum fe_status status = 0;
dd14523a 1784 int ret;
b63b36fa
FR		 1785
1786 /* set frontend */
1787 ret = lgdt3306a_set_parameters(fe);
1788 if (ret)
1789 goto error;
1790
dd14523a
AO		 1791 ret = lgdt3306a_read_status(fe, &status);
1792 if (ret)
1793 goto error;
b63b36fa
FR		 1794
1795 /* check if we have a valid signal */
8e8cd34e 1796 if (status & FE_HAS_LOCK)
b63b36fa 1797 return DVBFE_ALGO_SEARCH_SUCCESS;
8e8cd34e 1798 else
b63b36fa 1799 return DVBFE_ALGO_SEARCH_AGAIN;
b63b36fa
FR		 1800
1801error:
097117ca 1802 dbg_info("failed (%d)\n", ret);
b63b36fa
FR		 1803 return DVBFE_ALGO_SEARCH_ERROR;
1804}
1805
1806static void lgdt3306a_release(struct dvb_frontend *fe)
1807{
1808 struct lgdt3306a_state *state = fe->demodulator_priv;
8e8cd34e 1809
097117ca 1810 dbg_info("\n");
f6618cc8 1811 kfree(state);
b63b36fa
FR		 1812}
1813
bd336e63 1814static const struct dvb_frontend_ops lgdt3306a_ops;
b63b36fa
FR		 1815
1816struct dvb_frontend *lgdt3306a_attach(const struct lgdt3306a_config *config,
c43e6512 1817 struct i2c_adapter *i2c_adap)
b63b36fa
FR		 1818{
1819 struct lgdt3306a_state *state = NULL;
1820 int ret;
1821 u8 val;
1822
097117ca 1823 dbg_info("(%d-%04x)\n",
b63b36fa
FR		 1824 i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
1825 config ? config->i2c_addr : 0);
1826
1827 state = kzalloc(sizeof(struct lgdt3306a_state), GFP_KERNEL);
1828 if (state == NULL)
1829 goto fail;
1830
1831 state->cfg = config;
1832 state->i2c_adap = i2c_adap;
1833
1834 memcpy(&state->frontend.ops, &lgdt3306a_ops,
1835 sizeof(struct dvb_frontend_ops));
1836 state->frontend.demodulator_priv = state;
1837
1838 /* verify that we're talking to a lg3306a */
8e8cd34e
MIK		 1839 /* FGR - NOTE - there is no obvious ChipId to check; we check
1840 * some "known" bits after reset, but it's still just a guess */
b63b36fa
FR		 1841 ret = lgdt3306a_read_reg(state, 0x0000, &val);
1842 if (lg_chkerr(ret))
1843 goto fail;
8e8cd34e 1844 if ((val & 0x74) != 0x74) {
097117ca 1845 pr_warn("expected 0x74, got 0x%x\n", (val & 0x74));
8e8cd34e 1846#if 0
534f4364
MCC		 1847 /* FIXME - re-enable when we know this is right */
1848 goto fail;
8e8cd34e 1849#endif
b63b36fa
FR		 1850 }
1851 ret = lgdt3306a_read_reg(state, 0x0001, &val);
1852 if (lg_chkerr(ret))
1853 goto fail;
4937ba94 1854 if ((val & 0xf6) != 0xc6) {
097117ca 1855 pr_warn("expected 0xc6, got 0x%x\n", (val & 0xf6));
8e8cd34e 1856#if 0
534f4364
MCC		 1857 /* FIXME - re-enable when we know this is right */
1858 goto fail;
8e8cd34e 1859#endif
b63b36fa
FR		 1860 }
1861 ret = lgdt3306a_read_reg(state, 0x0002, &val);
1862 if (lg_chkerr(ret))
1863 goto fail;
8e8cd34e 1864 if ((val & 0x73) != 0x03) {
097117ca 1865 pr_warn("expected 0x03, got 0x%x\n", (val & 0x73));
8e8cd34e 1866#if 0
534f4364
MCC		 1867 /* FIXME - re-enable when we know this is right */
1868 goto fail;
8e8cd34e 1869#endif
b63b36fa
FR		 1870 }
1871
1872 state->current_frequency = -1;
1873 state->current_modulation = -1;
1874
1875 lgdt3306a_sleep(state);
1876
1877 return &state->frontend;
1878
1879fail:
097117ca 1880 pr_warn("unable to detect LGDT3306A hardware\n");
b63b36fa
FR		 1881 kfree(state);
1882 return NULL;
1883}
ebd9175e 1884EXPORT_SYMBOL(lgdt3306a_attach);
b63b36fa
FR		 1885
1886#ifdef DBG_DUMP
1887
1888static const short regtab[] = {
cb4671c8
MIK		 1889 0x0000, /* SOFTRSTB 1'b1 1'b1 1'b1 ADCPDB 1'b1 PLLPDB GBBPDB 11111111 */
1890 0x0001, /* 1'b1 1'b1 1'b0 1'b0 AUTORPTRS */
1891 0x0002, /* NI2CRPTEN 1'b0 1'b0 1'b0 SPECINVAUT */
1892 0x0003, /* AGCRFOUT */
1893 0x0004, /* ADCSEL1V ADCCNT ADCCNF ADCCNS ADCCLKPLL */
1894 0x0005, /* PLLINDIVSE */
1895 0x0006, /* PLLCTRL[7:0] 11100001 */
1896 0x0007, /* SYSINITWAITTIME[7:0] (msec) 00001000 */
1897 0x0008, /* STDOPMODE[7:0] 10000000 */
1898 0x0009, /* 1'b0 1'b0 1'b0 STDOPDETTMODE[2:0] STDOPDETCMODE[1:0] 00011110 */
4937ba94
MCC		 1899 0x000a, /* DAFTEN 1'b1 x x SCSYSLOCK */
1900 0x000b, /* SCSYSLOCKCHKTIME[7:0] (10msec) 01100100 */
1901 0x000d, /* x SAMPLING4 */
1902 0x000e, /* SAMFREQ[15:8] 00000000 */
1903 0x000f, /* SAMFREQ[7:0] 00000000 */
cb4671c8
MIK		 1904 0x0010, /* IFFREQ[15:8] 01100000 */
1905 0x0011, /* IFFREQ[7:0] 00000000 */
1906 0x0012, /* AGCEN AGCREFMO */
1907 0x0013, /* AGCRFFIXB AGCIFFIXB AGCLOCKDETRNGSEL[1:0] 1'b1 1'b0 1'b0 1'b0 11101000 */
1908 0x0014, /* AGCFIXVALUE[7:0] 01111111 */
1909 0x0015, /* AGCREF[15:8] 00001010 */
1910 0x0016, /* AGCREF[7:0] 11100100 */
1911 0x0017, /* AGCDELAY[7:0] 00100000 */
1912 0x0018, /* AGCRFBW[3:0] AGCIFBW[3:0] 10001000 */
1913 0x0019, /* AGCUDOUTMODE[1:0] AGCUDCTRLLEN[1:0] AGCUDCTRL */
4937ba94
MCC		 1914 0x001c, /* 1'b1 PFEN MFEN AICCVSYNC */
1915 0x001d, /* 1'b0 1'b1 1'b0 1'b1 AICCVSYNC */
1916 0x001e, /* AICCALPHA[3:0] 1'b1 1'b0 1'b1 1'b0 01111010 */
1917 0x001f, /* AICCDETTH[19:16] AICCOFFTH[19:16] 00000000 */
cb4671c8
MIK		 1918 0x0020, /* AICCDETTH[15:8] 01111100 */
1919 0x0021, /* AICCDETTH[7:0] 00000000 */
1920 0x0022, /* AICCOFFTH[15:8] 00000101 */
1921 0x0023, /* AICCOFFTH[7:0] 11100000 */
1922 0x0024, /* AICCOPMODE3[1:0] AICCOPMODE2[1:0] AICCOPMODE1[1:0] AICCOPMODE0[1:0] 00000000 */
1923 0x0025, /* AICCFIXFREQ3[23:16] 00000000 */
1924 0x0026, /* AICCFIXFREQ3[15:8] 00000000 */
1925 0x0027, /* AICCFIXFREQ3[7:0] 00000000 */
1926 0x0028, /* AICCFIXFREQ2[23:16] 00000000 */
1927 0x0029, /* AICCFIXFREQ2[15:8] 00000000 */
4937ba94
MCC		 1928 0x002a, /* AICCFIXFREQ2[7:0] 00000000 */
1929 0x002b, /* AICCFIXFREQ1[23:16] 00000000 */
1930 0x002c, /* AICCFIXFREQ1[15:8] 00000000 */
1931 0x002d, /* AICCFIXFREQ1[7:0] 00000000 */
1932 0x002e, /* AICCFIXFREQ0[23:16] 00000000 */
1933 0x002f, /* AICCFIXFREQ0[15:8] 00000000 */
cb4671c8
MIK		 1934 0x0030, /* AICCFIXFREQ0[7:0] 00000000 */
1935 0x0031, /* 1'b0 1'b1 1'b0 1'b0 x DAGC1STER */
1936 0x0032, /* DAGC1STEN DAGC1STER */
1937 0x0033, /* DAGC1STREF[15:8] 00001010 */
1938 0x0034, /* DAGC1STREF[7:0] 11100100 */
1939 0x0035, /* DAGC2NDE */
1940 0x0036, /* DAGC2NDREF[15:8] 00001010 */
1941 0x0037, /* DAGC2NDREF[7:0] 10000000 */
1942 0x0038, /* DAGC2NDLOCKDETRNGSEL[1:0] */
4937ba94 1943 0x003d, /* 1'b1 SAMGEARS */
cb4671c8
MIK		 1944 0x0040, /* SAMLFGMA */
1945 0x0041, /* SAMLFBWM */
1946 0x0044, /* 1'b1 CRGEARSHE */
1947 0x0045, /* CRLFGMAN */
1948 0x0046, /* CFLFBWMA */
1949 0x0047, /* CRLFGMAN */
1950 0x0048, /* x x x x CRLFGSTEP_VS[3:0] xxxx1001 */
1951 0x0049, /* CRLFBWMA */
4937ba94 1952 0x004a, /* CRLFBWMA */
cb4671c8
MIK		 1953 0x0050, /* 1'b0 1'b1 1'b1 1'b0 MSECALCDA */
1954 0x0070, /* TPOUTEN TPIFEN TPCLKOUTE */
1955 0x0071, /* TPSENB TPSSOPBITE */
1956 0x0073, /* TP47HINS x x CHBERINT PERMODE[1:0] PERINT[1:0] 1xx11100 */
1957 0x0075, /* x x x x x IQSWAPCTRL[2:0] xxxxx000 */
1958 0x0076, /* NBERCON NBERST NBERPOL NBERWSYN */
1959 0x0077, /* x NBERLOSTTH[2:0] NBERACQTH[3:0] x0000000 */
1960 0x0078, /* NBERPOLY[31:24] 00000000 */
1961 0x0079, /* NBERPOLY[23:16] 00000000 */
4937ba94
MCC		 1962 0x007a, /* NBERPOLY[15:8] 00000000 */
1963 0x007b, /* NBERPOLY[7:0] 00000000 */
1964 0x007c, /* NBERPED[31:24] 00000000 */
1965 0x007d, /* NBERPED[23:16] 00000000 */
1966 0x007e, /* NBERPED[15:8] 00000000 */
1967 0x007f, /* NBERPED[7:0] 00000000 */
cb4671c8
MIK		 1968 0x0080, /* x AGCLOCK DAGCLOCK SYSLOCK x x NEVERLOCK[1:0] */
1969 0x0085, /* SPECINVST */
1970 0x0088, /* SYSLOCKTIME[15:8] */
1971 0x0089, /* SYSLOCKTIME[7:0] */
4937ba94
MCC		 1972 0x008c, /* FECLOCKTIME[15:8] */
1973 0x008d, /* FECLOCKTIME[7:0] */
1974 0x008e, /* AGCACCOUT[15:8] */
1975 0x008f, /* AGCACCOUT[7:0] */
cb4671c8
MIK		 1976 0x0090, /* AICCREJSTATUS[3:0] AICCREJBUSY[3:0] */
1977 0x0091, /* AICCVSYNC */
4937ba94
MCC		 1978 0x009c, /* CARRFREQOFFSET[15:8] */
1979 0x009d, /* CARRFREQOFFSET[7:0] */
1980 0x00a1, /* SAMFREQOFFSET[23:16] */
1981 0x00a2, /* SAMFREQOFFSET[15:8] */
1982 0x00a3, /* SAMFREQOFFSET[7:0] */
1983 0x00a6, /* SYNCLOCK SYNCLOCKH */
6da7ac98 1984#if 0 /* covered elsewhere */
4937ba94
MCC		 1985 0x00e8, /* CONSTPWR[15:8] */
1986 0x00e9, /* CONSTPWR[7:0] */
1987 0x00ea, /* BMSE[15:8] */
1988 0x00eb, /* BMSE[7:0] */
1989 0x00ec, /* MSE[15:8] */
1990 0x00ed, /* MSE[7:0] */
1991 0x00ee, /* CONSTI[7:0] */
1992 0x00ef, /* CONSTQ[7:0] */
b63b36fa 1993#endif
4937ba94
MCC		 1994 0x00f4, /* TPIFTPERRCNT[7:0] */
1995 0x00f5, /* TPCORREC */
1996 0x00f6, /* VBBER[15:8] */
1997 0x00f7, /* VBBER[7:0] */
1998 0x00f8, /* VABER[15:8] */
1999 0x00f9, /* VABER[7:0] */
2000 0x00fa, /* TPERRCNT[7:0] */
2001 0x00fb, /* NBERLOCK x x x x x x x */
2002 0x00fc, /* NBERVALUE[31:24] */
2003 0x00fd, /* NBERVALUE[23:16] */
2004 0x00fe, /* NBERVALUE[15:8] */
2005 0x00ff, /* NBERVALUE[7:0] */
cb4671c8
MIK		 2006 0x1000, /* 1'b0 WODAGCOU */
2007 0x1005, /* x x 1'b1 1'b1 x SRD_Q_QM */
2008 0x1009, /* SRDWAITTIME[7:0] (10msec) 00100011 */
4937ba94
MCC		 2009 0x100a, /* SRDWAITTIME_CQS[7:0] (msec) 01100100 */
2010 0x101a, /* x 1'b1 1'b0 1'b0 x QMDQAMMODE[2:0] x100x010 */
cb4671c8 2011 0x1036, /* 1'b0 1'b1 1'b0 1'b0 SAMGSEND_CQS[3:0] 01001110 */
4937ba94
MCC		 2012 0x103c, /* SAMGSAUTOSTL_V[3:0] SAMGSAUTOEDL_V[3:0] 01000110 */
2013 0x103d, /* 1'b1 1'b1 SAMCNORMBP_V[1:0] 1'b0 1'b0 SAMMODESEL_V[1:0] 11100001 */
2014 0x103f, /* SAMZTEDSE */
2015 0x105d, /* EQSTATUSE */
2016 0x105f, /* x PMAPG2_V[2:0] x DMAPG2_V[2:0] x001x011 */
cb4671c8
MIK		 2017 0x1060, /* 1'b1 EQSTATUSE */
2018 0x1061, /* CRMAPBWSTL_V[3:0] CRMAPBWEDL_V[3:0] 00000100 */
2019 0x1065, /* 1'b0 x CRMODE_V[1:0] 1'b1 x 1'b1 x 0x111x1x */
2020 0x1066, /* 1'b0 1'b0 1'b1 1'b0 1'b1 PNBOOSTSE */
2021 0x1068, /* CREPHNGAIN2_V[3:0] CREPHNPBW_V[3:0] 10010001 */
4937ba94
MCC		 2022 0x106e, /* x x x x x CREPHNEN_ */
2023 0x106f, /* CREPHNTH_V[7:0] 00010101 */
cb4671c8
MIK		 2024 0x1072, /* CRSWEEPN */
2025 0x1073, /* CRPGAIN_V[3:0] x x 1'b1 1'b1 1001xx11 */
2026 0x1074, /* CRPBW_V[3:0] x x 1'b1 1'b1 0001xx11 */
2027 0x1080, /* DAFTSTATUS[1:0] x x x x x x */
2028 0x1081, /* SRDSTATUS[1:0] x x x x x SRDLOCK */
4937ba94
MCC		 2029 0x10a9, /* EQSTATUS_CQS[1:0] x x x x x x */
2030 0x10b7, /* EQSTATUS_V[1:0] x x x x x x */
6da7ac98 2031#if 0 /* SMART_ANT */
4937ba94
MCC		 2032 0x1f00, /* MODEDETE */
2033 0x1f01, /* x x x x x x x SFNRST xxxxxxx0 */
2034 0x1f03, /* NUMOFANT[7:0] 10000000 */
2035 0x1f04, /* x SELMASK[6:0] x0000000 */
2036 0x1f05, /* x SETMASK[6:0] x0000000 */
2037 0x1f06, /* x TXDATA[6:0] x0000000 */
2038 0x1f07, /* x CHNUMBER[6:0] x0000000 */
2039 0x1f09, /* AGCTIME[23:16] 10011000 */
2040 0x1f0a, /* AGCTIME[15:8] 10010110 */
2041 0x1f0b, /* AGCTIME[7:0] 10000000 */
2042 0x1f0c, /* ANTTIME[31:24] 00000000 */
2043 0x1f0d, /* ANTTIME[23:16] 00000011 */
2044 0x1f0e, /* ANTTIME[15:8] 10010000 */
2045 0x1f0f, /* ANTTIME[7:0] 10010000 */
2046 0x1f11, /* SYNCTIME[23:16] 10011000 */
2047 0x1f12, /* SYNCTIME[15:8] 10010110 */
2048 0x1f13, /* SYNCTIME[7:0] 10000000 */
2049 0x1f14, /* SNRTIME[31:24] 00000001 */
2050 0x1f15, /* SNRTIME[23:16] 01111101 */
2051 0x1f16, /* SNRTIME[15:8] 01111000 */
2052 0x1f17, /* SNRTIME[7:0] 01000000 */
2053 0x1f19, /* FECTIME[23:16] 00000000 */
2054 0x1f1a, /* FECTIME[15:8] 01110010 */
2055 0x1f1b, /* FECTIME[7:0] 01110000 */
2056 0x1f1d, /* FECTHD[7:0] 00000011 */
2057 0x1f1f, /* SNRTHD[23:16] 00001000 */
2058 0x1f20, /* SNRTHD[15:8] 01111111 */
2059 0x1f21, /* SNRTHD[7:0] 10000101 */
2060 0x1f80, /* IRQFLG x x SFSDRFLG MODEBFLG SAVEFLG SCANFLG TRACKFLG */
2061 0x1f81, /* x SYNCCON SNRCON FECCON x STDBUSY SYNCRST AGCFZCO */
2062 0x1f82, /* x x x SCANOPCD[4:0] */
2063 0x1f83, /* x x x x MAINOPCD[3:0] */
2064 0x1f84, /* x x RXDATA[13:8] */
2065 0x1f85, /* RXDATA[7:0] */
2066 0x1f86, /* x x SDTDATA[13:8] */
2067 0x1f87, /* SDTDATA[7:0] */
2068 0x1f89, /* ANTSNR[23:16] */
2069 0x1f8a, /* ANTSNR[15:8] */
2070 0x1f8b, /* ANTSNR[7:0] */
2071 0x1f8c, /* x x x x ANTFEC[13:8] */
2072 0x1f8d, /* ANTFEC[7:0] */
2073 0x1f8e, /* MAXCNT[7:0] */
2074 0x1f8f, /* SCANCNT[7:0] */
2075 0x1f91, /* MAXPW[23:16] */
2076 0x1f92, /* MAXPW[15:8] */
2077 0x1f93, /* MAXPW[7:0] */
2078 0x1f95, /* CURPWMSE[23:16] */
2079 0x1f96, /* CURPWMSE[15:8] */
2080 0x1f97, /* CURPWMSE[7:0] */
6da7ac98 2081#endif /* SMART_ANT */
4937ba94
MCC		 2082 0x211f, /* 1'b1 1'b1 1'b1 CIRQEN x x 1'b0 1'b0 1111xx00 */
2083 0x212a, /* EQAUTOST */
cb4671c8 2084 0x2122, /* CHFAST[7:0] 01100000 */
4937ba94
MCC		 2085 0x212b, /* FFFSTEP_V[3:0] x FBFSTEP_V[2:0] 0001x001 */
2086 0x212c, /* PHDEROTBWSEL[3:0] 1'b1 1'b1 1'b1 1'b0 10001110 */
2087 0x212d, /* 1'b1 1'b1 1'b1 1'b1 x x TPIFLOCKS */
cb4671c8
MIK		 2088 0x2135, /* DYNTRACKFDEQ[3:0] x 1'b0 1'b0 1'b0 1010x000 */
2089 0x2141, /* TRMODE[1:0] 1'b1 1'b1 1'b0 1'b1 1'b1 1'b1 01110111 */
2090 0x2162, /* AICCCTRLE */
2091 0x2173, /* PHNCNFCNT[7:0] 00000100 */
2092 0x2179, /* 1'b0 1'b0 1'b0 1'b1 x BADSINGLEDYNTRACKFBF[2:0] 0001x001 */
4937ba94
MCC		 2093 0x217a, /* 1'b0 1'b0 1'b0 1'b1 x BADSLOWSINGLEDYNTRACKFBF[2:0] 0001x001 */
2094 0x217e, /* CNFCNTTPIF[7:0] 00001000 */
2095 0x217f, /* TPERRCNTTPIF[7:0] 00000001 */
cb4671c8
MIK		 2096 0x2180, /* x x x x x x FBDLYCIR[9:8] */
2097 0x2181, /* FBDLYCIR[7:0] */
2098 0x2185, /* MAXPWRMAIN[7:0] */
2099 0x2191, /* NCOMBDET x x x x x x x */
2100 0x2199, /* x MAINSTRON */
4937ba94
MCC		 2101 0x219a, /* FFFEQSTEPOUT_V[3:0] FBFSTEPOUT_V[2:0] */
2102 0x21a1, /* x x SNRREF[5:0] */
cb4671c8
MIK		 2103 0x2845, /* 1'b0 1'b1 x x FFFSTEP_CQS[1:0] FFFCENTERTAP[1:0] 01xx1110 */
2104 0x2846, /* 1'b0 x 1'b0 1'b1 FBFSTEP_CQS[1:0] 1'b1 1'b0 0x011110 */
2105 0x2847, /* ENNOSIGDE */
2106 0x2849, /* 1'b1 1'b1 NOUSENOSI */
4937ba94 2107 0x284a, /* EQINITWAITTIME[7:0] 01100100 */
cb4671c8
MIK		 2108 0x3000, /* 1'b1 1'b1 1'b1 x x x 1'b0 RPTRSTM */
2109 0x3001, /* RPTRSTWAITTIME[7:0] (100msec) 00110010 */
2110 0x3031, /* FRAMELOC */
2111 0x3032, /* 1'b1 1'b0 1'b0 1'b0 x x FRAMELOCKMODE_CQS[1:0] 1000xx11 */
4937ba94
MCC		 2112 0x30a9, /* VDLOCK_Q FRAMELOCK */
2113 0x30aa, /* MPEGLOCK */
b63b36fa
FR		 2114};
2115
1f679ff6 2116#define numDumpRegs (ARRAY_SIZE(regtab))
b63b36fa
FR		 2117static u8 regval1[numDumpRegs] = {0, };
2118static u8 regval2[numDumpRegs] = {0, };
2119
2120static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state)
2121{
2122 memset(regval2, 0xff, sizeof(regval2));
2123 lgdt3306a_DumpRegs(state);
2124}
2125
2126static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state)
2127{
2128 int i;
2129 int sav_debug = debug;
8e8cd34e 2130
b63b36fa
FR		 2131 if ((debug & DBG_DUMP) == 0)
2132 return;
831a9112 2133 debug &= ~DBG_REG; /* suppress DBG_REG during reg dump */
b63b36fa 2134
097117ca 2135 lg_debug("\n");
b63b36fa 2136
8e8cd34e 2137 for (i = 0; i < numDumpRegs; i++) {
b63b36fa 2138 lgdt3306a_read_reg(state, regtab[i], &regval1[i]);
8e8cd34e 2139 if (regval1[i] != regval2[i]) {
097117ca 2140 lg_debug(" %04X = %02X\n", regtab[i], regval1[i]);
16afc672 2141 regval2[i] = regval1[i];
b63b36fa
FR		 2142 }
2143 }
2144 debug = sav_debug;
2145}
8e8cd34e 2146#endif /* DBG_DUMP */
b63b36fa
FR		 2147
2148
2149
bd336e63 2150static const struct dvb_frontend_ops lgdt3306a_ops = {
b63b36fa
FR		 2151 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
2152 .info = {
2153 .name = "LG Electronics LGDT3306A VSB/QAM Frontend",
f1b1eabf
MCC		 2154 .frequency_min_hz = 54 * MHz,
2155 .frequency_max_hz = 858 * MHz,
2156 .frequency_stepsize_hz = 62500,
4966c0c5 2157 .caps = FE_CAN_QAM_AUTO | FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
b63b36fa
FR		 2158 },
2159 .i2c_gate_ctrl = lgdt3306a_i2c_gate_ctrl,
2160 .init = lgdt3306a_init,
2161 .sleep = lgdt3306a_fe_sleep,
2162 /* if this is set, it overrides the default swzigzag */
2163 .tune = lgdt3306a_tune,
2164 .set_frontend = lgdt3306a_set_parameters,
2165 .get_frontend = lgdt3306a_get_frontend,
2166 .get_frontend_algo = lgdt3306a_get_frontend_algo,
2167 .get_tune_settings = lgdt3306a_get_tune_settings,
2168 .read_status = lgdt3306a_read_status,
2169 .read_ber = lgdt3306a_read_ber,
2170 .read_signal_strength = lgdt3306a_read_signal_strength,
2171 .read_snr = lgdt3306a_read_snr,
2172 .read_ucblocks = lgdt3306a_read_ucblocks,
2173 .release = lgdt3306a_release,
2174 .ts_bus_ctrl = lgdt3306a_ts_bus_ctrl,
2175 .search = lgdt3306a_search,
2176};
2177
4f751890
KC		 2178static int lgdt3306a_select(struct i2c_mux_core *muxc, u32 chan)
2179{
2180 struct i2c_client *client = i2c_mux_priv(muxc);
2181 struct lgdt3306a_state *state = i2c_get_clientdata(client);
2182
2183 return lgdt3306a_i2c_gate_ctrl(&state->frontend, 1);
2184}
2185
2186static int lgdt3306a_deselect(struct i2c_mux_core *muxc, u32 chan)
2187{
2188 struct i2c_client *client = i2c_mux_priv(muxc);
2189 struct lgdt3306a_state *state = i2c_get_clientdata(client);
2190
2191 return lgdt3306a_i2c_gate_ctrl(&state->frontend, 0);
2192}
2193
2194static int lgdt3306a_probe(struct i2c_client *client,
2195 const struct i2c_device_id *id)
2196{
2197 struct lgdt3306a_config *config;
2198 struct lgdt3306a_state *state;
2199 struct dvb_frontend *fe;
2200 int ret;
2201
2c4746cf 2202 config = kmemdup(client->dev.platform_data,
2203 sizeof(struct lgdt3306a_config), GFP_KERNEL);
4f751890
KC		 2204 if (config == NULL) {
2205 ret = -ENOMEM;
2206 goto fail;
2207 }
2208
4f751890 2209 config->i2c_addr = client->addr;
f6618cc8 2210 fe = lgdt3306a_attach(config, client->adapter);
4f751890
KC		 2211 if (fe == NULL) {
2212 ret = -ENODEV;
2213 goto err_fe;
2214 }
2215
2216 i2c_set_clientdata(client, fe->demodulator_priv);
2217 state = fe->demodulator_priv;
5b3a8e90 2218 state->frontend.ops.release = NULL;
4f751890
KC		 2219
2220 /* create mux i2c adapter for tuner */
2221 state->muxc = i2c_mux_alloc(client->adapter, &client->dev,
2222 1, 0, I2C_MUX_LOCKED,
2223 lgdt3306a_select, lgdt3306a_deselect);
2224 if (!state->muxc) {
2225 ret = -ENOMEM;
2226 goto err_kfree;
2227 }
2228 state->muxc->priv = client;
2229 ret = i2c_mux_add_adapter(state->muxc, 0, 0, 0);
2230 if (ret)
2231 goto err_kfree;
2232
2233 /* create dvb_frontend */
2234 fe->ops.i2c_gate_ctrl = NULL;
2235 *config->i2c_adapter = state->muxc->adapter[0];
2236 *config->fe = fe;
2237
e7f4d751
BL		 2238 dev_info(&client->dev, "LG Electronics LGDT3306A successfully identified\n");
2239
4f751890
KC		 2240 return 0;
2241
2242err_kfree:
2243 kfree(state);
2244err_fe:
2245 kfree(config);
2246fail:
e7f4d751 2247 dev_warn(&client->dev, "probe failed = %d\n", ret);
4f751890
KC		 2248 return ret;
2249}
2250
2251static int lgdt3306a_remove(struct i2c_client *client)
2252{
2253 struct lgdt3306a_state *state = i2c_get_clientdata(client);
2254
2255 i2c_mux_del_adapters(state->muxc);
2256
2257 state->frontend.ops.release = NULL;
2258 state->frontend.demodulator_priv = NULL;
2259
2260 kfree(state->cfg);
2261 kfree(state);
2262
2263 return 0;
2264}
2265
2266static const struct i2c_device_id lgdt3306a_id_table[] = {
2267 {"lgdt3306a", 0},
2268 {}
2269};
2270MODULE_DEVICE_TABLE(i2c, lgdt3306a_id_table);
2271
2272static struct i2c_driver lgdt3306a_driver = {
2273 .driver = {
2274 .name = "lgdt3306a",
2275 .suppress_bind_attrs = true,
2276 },
2277 .probe = lgdt3306a_probe,
2278 .remove = lgdt3306a_remove,
2279 .id_table = lgdt3306a_id_table,
2280};
2281
2282module_i2c_driver(lgdt3306a_driver);
2283
b63b36fa
FR		 2284MODULE_DESCRIPTION("LG Electronics LGDT3306A ATSC/QAM-B Demodulator Driver");
2285MODULE_AUTHOR("Fred Richter <frichter@hauppauge.com>");
2286MODULE_LICENSE("GPL");
2287MODULE_VERSION("0.2");
Linux 6.x block layer and io_uring tree(s)