Commit | Line | Data |
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43dd07f7 | 1 | #define AUD_COMM_EXEC__A 0x1000000 |
43dd07f7 | 2 | #define AUD_COMM_EXEC_STOP 0x0 |
43dd07f7 | 3 | #define FEC_COMM_EXEC__A 0x1C00000 |
43dd07f7 RM |
4 | #define FEC_COMM_EXEC_STOP 0x0 |
5 | #define FEC_COMM_EXEC_ACTIVE 0x1 | |
43dd07f7 | 6 | #define FEC_DI_COMM_EXEC__A 0x1C20000 |
43dd07f7 | 7 | #define FEC_DI_COMM_EXEC_STOP 0x0 |
43dd07f7 | 8 | #define FEC_DI_INPUT_CTL__A 0x1C20016 |
43dd07f7 | 9 | #define FEC_RS_COMM_EXEC__A 0x1C30000 |
43dd07f7 | 10 | #define FEC_RS_COMM_EXEC_STOP 0x0 |
43dd07f7 | 11 | #define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012 |
43dd07f7 | 12 | #define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013 |
8f3741e0 | 13 | #define FEC_RS_NR_BIT_ERRORS__A 0x1C30014 |
43dd07f7 | 14 | #define FEC_OC_MODE__A 0x1C40011 |
43dd07f7 | 15 | #define FEC_OC_MODE_PARITY__M 0x1 |
43dd07f7 | 16 | #define FEC_OC_DTO_MODE__A 0x1C40014 |
43dd07f7 | 17 | #define FEC_OC_DTO_MODE_DYNAMIC__M 0x1 |
43dd07f7 | 18 | #define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4 |
43dd07f7 | 19 | #define FEC_OC_DTO_PERIOD__A 0x1C40015 |
43dd07f7 | 20 | #define FEC_OC_DTO_BURST_LEN__A 0x1C40018 |
43dd07f7 | 21 | #define FEC_OC_FCT_MODE__A 0x1C4001A |
43dd07f7 | 22 | #define FEC_OC_FCT_MODE__PRE 0x0 |
43dd07f7 | 23 | #define FEC_OC_FCT_MODE_RAT_ENA__M 0x1 |
43dd07f7 | 24 | #define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2 |
43dd07f7 | 25 | #define FEC_OC_TMD_MODE__A 0x1C4001E |
43dd07f7 | 26 | #define FEC_OC_TMD_COUNT__A 0x1C4001F |
43dd07f7 | 27 | #define FEC_OC_TMD_HI_MARGIN__A 0x1C40020 |
43dd07f7 | 28 | #define FEC_OC_TMD_LO_MARGIN__A 0x1C40021 |
43dd07f7 | 29 | #define FEC_OC_TMD_INT_UPD_RATE__A 0x1C40023 |
43dd07f7 | 30 | #define FEC_OC_AVR_PARM_A__A 0x1C40026 |
43dd07f7 | 31 | #define FEC_OC_AVR_PARM_B__A 0x1C40027 |
43dd07f7 | 32 | #define FEC_OC_RCN_GAIN__A 0x1C4002E |
43dd07f7 | 33 | #define FEC_OC_RCN_CTL_RATE_LO__A 0x1C40030 |
43dd07f7 | 34 | #define FEC_OC_RCN_CTL_STEP_LO__A 0x1C40032 |
43dd07f7 | 35 | #define FEC_OC_RCN_CTL_STEP_HI__A 0x1C40033 |
43dd07f7 | 36 | #define FEC_OC_SNC_MODE__A 0x1C40040 |
43dd07f7 | 37 | #define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10 |
43dd07f7 | 38 | #define FEC_OC_SNC_LWM__A 0x1C40041 |
43dd07f7 | 39 | #define FEC_OC_SNC_HWM__A 0x1C40042 |
43dd07f7 | 40 | #define FEC_OC_SNC_UNLOCK__A 0x1C40043 |
43dd07f7 | 41 | #define FEC_OC_SNC_FAIL_PERIOD__A 0x1C40046 |
43dd07f7 | 42 | #define FEC_OC_IPR_MODE__A 0x1C40048 |
43dd07f7 | 43 | #define FEC_OC_IPR_MODE_SERIAL__M 0x1 |
43dd07f7 | 44 | #define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4 |
43dd07f7 | 45 | #define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10 |
43dd07f7 | 46 | #define FEC_OC_IPR_INVERT__A 0x1C40049 |
43dd07f7 | 47 | #define FEC_OC_IPR_INVERT_MD0__M 0x1 |
43dd07f7 | 48 | #define FEC_OC_IPR_INVERT_MD1__M 0x2 |
43dd07f7 | 49 | #define FEC_OC_IPR_INVERT_MD2__M 0x4 |
43dd07f7 | 50 | #define FEC_OC_IPR_INVERT_MD3__M 0x8 |
43dd07f7 | 51 | #define FEC_OC_IPR_INVERT_MD4__M 0x10 |
43dd07f7 | 52 | #define FEC_OC_IPR_INVERT_MD5__M 0x20 |
43dd07f7 | 53 | #define FEC_OC_IPR_INVERT_MD6__M 0x40 |
43dd07f7 | 54 | #define FEC_OC_IPR_INVERT_MD7__M 0x80 |
43dd07f7 | 55 | #define FEC_OC_IPR_INVERT_MERR__M 0x100 |
43dd07f7 | 56 | #define FEC_OC_IPR_INVERT_MSTRT__M 0x200 |
43dd07f7 | 57 | #define FEC_OC_IPR_INVERT_MVAL__M 0x400 |
43dd07f7 | 58 | #define FEC_OC_IPR_INVERT_MCLK__M 0x800 |
43dd07f7 | 59 | #define FEC_OC_OCR_INVERT__A 0x1C40052 |
43dd07f7 | 60 | #define IQM_COMM_EXEC__A 0x1800000 |
43dd07f7 RM |
61 | #define IQM_COMM_EXEC_B_STOP 0x0 |
62 | #define IQM_COMM_EXEC_B_ACTIVE 0x1 | |
43dd07f7 | 63 | #define IQM_FS_RATE_OFS_LO__A 0x1820010 |
43dd07f7 | 64 | #define IQM_FS_ADJ_SEL__A 0x1820014 |
43dd07f7 RM |
65 | #define IQM_FS_ADJ_SEL_B_OFF 0x0 |
66 | #define IQM_FS_ADJ_SEL_B_QAM 0x1 | |
67 | #define IQM_FS_ADJ_SEL_B_VSB 0x2 | |
43dd07f7 | 68 | #define IQM_FD_RATESEL__A 0x1830010 |
43dd07f7 RM |
69 | #define IQM_RC_RATE_OFS_LO__A 0x1840010 |
70 | #define IQM_RC_RATE_OFS_LO__W 16 | |
71 | #define IQM_RC_RATE_OFS_LO__M 0xFFFF | |
43dd07f7 | 72 | #define IQM_RC_RATE_OFS_HI__M 0xFF |
43dd07f7 | 73 | #define IQM_RC_ADJ_SEL__A 0x1840014 |
43dd07f7 RM |
74 | #define IQM_RC_ADJ_SEL_B_OFF 0x0 |
75 | #define IQM_RC_ADJ_SEL_B_QAM 0x1 | |
76 | #define IQM_RC_ADJ_SEL_B_VSB 0x2 | |
43dd07f7 | 77 | #define IQM_RC_STRETCH__A 0x1840016 |
43dd07f7 | 78 | #define IQM_CF_COMM_INT_MSK__A 0x1860006 |
43dd07f7 | 79 | #define IQM_CF_SYMMETRIC__A 0x1860010 |
43dd07f7 | 80 | #define IQM_CF_MIDTAP__A 0x1860011 |
43dd07f7 | 81 | #define IQM_CF_MIDTAP_RE__B 0 |
43dd07f7 | 82 | #define IQM_CF_MIDTAP_IM__B 1 |
43dd07f7 | 83 | #define IQM_CF_OUT_ENA__A 0x1860012 |
43dd07f7 | 84 | #define IQM_CF_OUT_ENA_QAM__B 1 |
43dd07f7 | 85 | #define IQM_CF_OUT_ENA_OFDM__M 0x4 |
43dd07f7 | 86 | #define IQM_CF_ADJ_SEL__A 0x1860013 |
43dd07f7 | 87 | #define IQM_CF_SCALE__A 0x1860014 |
43dd07f7 | 88 | #define IQM_CF_SCALE_SH__A 0x1860015 |
43dd07f7 | 89 | #define IQM_CF_SCALE_SH__PRE 0x0 |
43dd07f7 | 90 | #define IQM_CF_POW_MEAS_LEN__A 0x1860017 |
43dd07f7 | 91 | #define IQM_CF_DS_ENA__A 0x1860019 |
43dd07f7 | 92 | #define IQM_CF_TAP_RE0__A 0x1860020 |
43dd07f7 | 93 | #define IQM_CF_TAP_IM0__A 0x1860040 |
43dd07f7 | 94 | #define IQM_CF_CLP_VAL__A 0x1860060 |
43dd07f7 | 95 | #define IQM_CF_DATATH__A 0x1860061 |
43dd07f7 | 96 | #define IQM_CF_PKDTH__A 0x1860062 |
43dd07f7 | 97 | #define IQM_CF_WND_LEN__A 0x1860063 |
43dd07f7 | 98 | #define IQM_CF_DET_LCT__A 0x1860064 |
43dd07f7 | 99 | #define IQM_CF_BYPASSDET__A 0x1860067 |
43dd07f7 | 100 | #define IQM_AF_COMM_EXEC__A 0x1870000 |
43dd07f7 | 101 | #define IQM_AF_COMM_EXEC_ACTIVE 0x1 |
43dd07f7 | 102 | #define IQM_AF_CLKNEG__A 0x1870012 |
43dd07f7 | 103 | #define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2 |
43dd07f7 RM |
104 | #define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0 |
105 | #define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2 | |
43dd07f7 | 106 | #define IQM_AF_START_LOCK__A 0x187001B |
43dd07f7 | 107 | #define IQM_AF_PHASE0__A 0x187001C |
43dd07f7 | 108 | #define IQM_AF_PHASE1__A 0x187001D |
43dd07f7 | 109 | #define IQM_AF_PHASE2__A 0x187001E |
43dd07f7 | 110 | #define IQM_AF_CLP_LEN__A 0x1870023 |
43dd07f7 | 111 | #define IQM_AF_CLP_TH__A 0x1870024 |
43dd07f7 | 112 | #define IQM_AF_SNS_LEN__A 0x1870026 |
43dd07f7 | 113 | #define IQM_AF_AGC_IF__A 0x1870028 |
43dd07f7 | 114 | #define IQM_AF_AGC_RF__A 0x1870029 |
43dd07f7 | 115 | #define IQM_AF_PDREF__A 0x187002B |
43dd07f7 | 116 | #define IQM_AF_PDREF__M 0x1F |
43dd07f7 | 117 | #define IQM_AF_STDBY__A 0x187002C |
43dd07f7 | 118 | #define IQM_AF_STDBY_STDBY_ADC_STANDBY 0x2 |
43dd07f7 | 119 | #define IQM_AF_STDBY_STDBY_AMP_STANDBY 0x4 |
43dd07f7 | 120 | #define IQM_AF_STDBY_STDBY_PD_STANDBY 0x8 |
43dd07f7 | 121 | #define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10 |
43dd07f7 | 122 | #define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20 |
43dd07f7 | 123 | #define IQM_AF_AMUX__A 0x187002D |
43dd07f7 | 124 | #define IQM_AF_AMUX_SIGNAL2ADC 0x1 |
43dd07f7 | 125 | #define IQM_AF_UPD_SEL__A 0x187002F |
43dd07f7 | 126 | #define IQM_AF_INC_LCT__A 0x1870034 |
43dd07f7 | 127 | #define IQM_AF_INC_BYPASS__A 0x1870036 |
43dd07f7 | 128 | #define OFDM_CP_COMM_EXEC__A 0x2800000 |
43dd07f7 | 129 | #define OFDM_CP_COMM_EXEC_STOP 0x0 |
43dd07f7 | 130 | #define OFDM_EC_SB_PRIOR__A 0x3410013 |
43dd07f7 RM |
131 | #define OFDM_EC_SB_PRIOR_HI 0x0 |
132 | #define OFDM_EC_SB_PRIOR_LO 0x1 | |
8f3741e0 MCC |
133 | #define OFDM_EC_VD_ERR_BIT_CNT__A 0x3420017 |
134 | #define OFDM_EC_VD_IN_BIT_CNT__A 0x3420018 | |
43dd07f7 | 135 | #define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054 |
43dd07f7 | 136 | #define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3 |
43dd07f7 | 137 | #define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2 |
43dd07f7 | 138 | #define OFDM_EQ_TOP_TD_TPS_CODE_HP__A 0x3010056 |
43dd07f7 | 139 | #define OFDM_EQ_TOP_TD_TPS_CODE_HP__M 0x7 |
43dd07f7 | 140 | #define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8 0x4 |
43dd07f7 | 141 | #define OFDM_EQ_TOP_TD_SQR_ERR_I__A 0x301005E |
43dd07f7 | 142 | #define OFDM_EQ_TOP_TD_SQR_ERR_Q__A 0x301005F |
43dd07f7 | 143 | #define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A 0x3010060 |
43dd07f7 | 144 | #define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A 0x3010061 |
43dd07f7 | 145 | #define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A 0x3010062 |
43dd07f7 | 146 | #define OFDM_LC_COMM_EXEC__A 0x3800000 |
43dd07f7 | 147 | #define OFDM_LC_COMM_EXEC_STOP 0x0 |
43dd07f7 | 148 | #define OFDM_SC_COMM_EXEC__A 0x3C00000 |
43dd07f7 | 149 | #define OFDM_SC_COMM_EXEC_STOP 0x0 |
43dd07f7 | 150 | #define OFDM_SC_COMM_STATE__A 0x3C00001 |
43dd07f7 | 151 | #define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040 |
43dd07f7 | 152 | #define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041 |
43dd07f7 | 153 | #define OFDM_SC_RA_RAM_CMD_ADDR__A 0x3C20042 |
43dd07f7 | 154 | #define OFDM_SC_RA_RAM_CMD__A 0x3C20043 |
43dd07f7 RM |
155 | #define OFDM_SC_RA_RAM_CMD_NULL 0x0 |
156 | #define OFDM_SC_RA_RAM_CMD_PROC_START 0x1 | |
43dd07f7 RM |
157 | #define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 |
158 | #define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 | |
159 | #define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 | |
160 | #define OFDM_SC_RA_RAM_CMD_USER_IO 0x6 | |
161 | #define OFDM_SC_RA_RAM_CMD_SET_TIMER 0x7 | |
162 | #define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 | |
43dd07f7 | 163 | #define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 |
43dd07f7 | 164 | #define OFDM_SC_RA_RAM_LOCKTRACK_MIN 0x1 |
43dd07f7 | 165 | #define OFDM_SC_RA_RAM_OP_PARAM__A 0x3C20048 |
43dd07f7 | 166 | #define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3 |
43dd07f7 RM |
167 | #define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 |
168 | #define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 | |
43dd07f7 RM |
169 | #define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 |
170 | #define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 | |
171 | #define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 | |
172 | #define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4 0xC | |
43dd07f7 RM |
173 | #define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 |
174 | #define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 | |
175 | #define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 | |
43dd07f7 RM |
176 | #define OFDM_SC_RA_RAM_OP_PARAM_HIER_NO 0x0 |
177 | #define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 | |
178 | #define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 | |
179 | #define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 | |
43dd07f7 RM |
180 | #define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 |
181 | #define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 | |
182 | #define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 | |
183 | #define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 | |
184 | #define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 | |
43dd07f7 RM |
185 | #define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 |
186 | #define OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 | |
43dd07f7 | 187 | #define OFDM_SC_RA_RAM_OP_AUTO_MODE__M 0x1 |
43dd07f7 | 188 | #define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 |
43dd07f7 | 189 | #define OFDM_SC_RA_RAM_OP_AUTO_CONST__M 0x4 |
43dd07f7 | 190 | #define OFDM_SC_RA_RAM_OP_AUTO_HIER__M 0x8 |
43dd07f7 | 191 | #define OFDM_SC_RA_RAM_OP_AUTO_RATE__M 0x10 |
43dd07f7 | 192 | #define OFDM_SC_RA_RAM_LOCK__A 0x3C2004B |
43dd07f7 | 193 | #define OFDM_SC_RA_RAM_LOCK_DEMOD__M 0x1 |
43dd07f7 | 194 | #define OFDM_SC_RA_RAM_LOCK_FEC__M 0x2 |
43dd07f7 | 195 | #define OFDM_SC_RA_RAM_LOCK_MPEG__M 0x4 |
43dd07f7 | 196 | #define OFDM_SC_RA_RAM_LOCK_NODVBT__M 0x8 |
43dd07f7 | 197 | #define OFDM_SC_RA_RAM_BE_OPT_DELAY__A 0x3C2004D |
43dd07f7 | 198 | #define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x3C2004E |
43dd07f7 | 199 | #define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F |
43dd07f7 | 200 | #define OFDM_SC_RA_RAM_ECHO_THRES_8K__B 0 |
43dd07f7 | 201 | #define OFDM_SC_RA_RAM_ECHO_THRES_8K__M 0xFF |
43dd07f7 | 202 | #define OFDM_SC_RA_RAM_ECHO_THRES_2K__B 8 |
43dd07f7 | 203 | #define OFDM_SC_RA_RAM_ECHO_THRES_2K__M 0xFF00 |
43dd07f7 | 204 | #define OFDM_SC_RA_RAM_CONFIG__A 0x3C20050 |
43dd07f7 | 205 | #define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M 0x800 |
43dd07f7 | 206 | #define OFDM_SC_RA_RAM_FR_THRES_8K__A 0x3C2007D |
43dd07f7 | 207 | #define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x3C200E0 |
43dd07f7 | 208 | #define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x3C200E1 |
43dd07f7 | 209 | #define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x3C200E3 |
43dd07f7 | 210 | #define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x3C200E4 |
43dd07f7 | 211 | #define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A 0x3C200F8 |
43dd07f7 | 212 | #define QAM_COMM_EXEC__A 0x1400000 |
43dd07f7 RM |
213 | #define QAM_COMM_EXEC_STOP 0x0 |
214 | #define QAM_COMM_EXEC_ACTIVE 0x1 | |
43dd07f7 | 215 | #define QAM_TOP_ANNEX_A 0x0 |
43dd07f7 | 216 | #define QAM_TOP_ANNEX_C 0x2 |
43dd07f7 | 217 | #define QAM_SL_ERR_POWER__A 0x1430017 |
43dd07f7 | 218 | #define QAM_DQ_QUAL_FUN0__A 0x1440018 |
43dd07f7 | 219 | #define QAM_DQ_QUAL_FUN1__A 0x1440019 |
43dd07f7 | 220 | #define QAM_DQ_QUAL_FUN2__A 0x144001A |
43dd07f7 | 221 | #define QAM_DQ_QUAL_FUN3__A 0x144001B |
43dd07f7 | 222 | #define QAM_DQ_QUAL_FUN4__A 0x144001C |
43dd07f7 | 223 | #define QAM_DQ_QUAL_FUN5__A 0x144001D |
43dd07f7 | 224 | #define QAM_LC_MODE__A 0x1450010 |
43dd07f7 | 225 | #define QAM_LC_QUAL_TAB0__A 0x1450018 |
43dd07f7 | 226 | #define QAM_LC_QUAL_TAB1__A 0x1450019 |
43dd07f7 | 227 | #define QAM_LC_QUAL_TAB2__A 0x145001A |
43dd07f7 | 228 | #define QAM_LC_QUAL_TAB3__A 0x145001B |
43dd07f7 | 229 | #define QAM_LC_QUAL_TAB4__A 0x145001C |
43dd07f7 | 230 | #define QAM_LC_QUAL_TAB5__A 0x145001D |
43dd07f7 | 231 | #define QAM_LC_QUAL_TAB6__A 0x145001E |
43dd07f7 | 232 | #define QAM_LC_QUAL_TAB8__A 0x145001F |
43dd07f7 | 233 | #define QAM_LC_QUAL_TAB9__A 0x1450020 |
43dd07f7 | 234 | #define QAM_LC_QUAL_TAB10__A 0x1450021 |
43dd07f7 | 235 | #define QAM_LC_QUAL_TAB12__A 0x1450022 |
43dd07f7 | 236 | #define QAM_LC_QUAL_TAB15__A 0x1450023 |
43dd07f7 | 237 | #define QAM_LC_QUAL_TAB16__A 0x1450024 |
43dd07f7 | 238 | #define QAM_LC_QUAL_TAB20__A 0x1450025 |
43dd07f7 | 239 | #define QAM_LC_QUAL_TAB25__A 0x1450026 |
43dd07f7 | 240 | #define QAM_LC_LPF_FACTORP__A 0x1450028 |
43dd07f7 | 241 | #define QAM_LC_LPF_FACTORI__A 0x1450029 |
43dd07f7 | 242 | #define QAM_LC_RATE_LIMIT__A 0x145002A |
43dd07f7 | 243 | #define QAM_LC_SYMBOL_FREQ__A 0x145002B |
43dd07f7 | 244 | #define QAM_SY_TIMEOUT__A 0x1470011 |
43dd07f7 | 245 | #define QAM_SY_TIMEOUT__PRE 0x3A98 |
43dd07f7 | 246 | #define QAM_SY_SYNC_LWM__A 0x1470012 |
43dd07f7 | 247 | #define QAM_SY_SYNC_AWM__A 0x1470013 |
43dd07f7 | 248 | #define QAM_SY_SYNC_HWM__A 0x1470014 |
43dd07f7 | 249 | #define QAM_SY_SP_INV__A 0x1470017 |
43dd07f7 | 250 | #define QAM_SY_SP_INV_SPECTRUM_INV_DIS 0x0 |
43dd07f7 | 251 | #define SCU_COMM_EXEC__A 0x800000 |
43dd07f7 RM |
252 | #define SCU_COMM_EXEC_STOP 0x0 |
253 | #define SCU_COMM_EXEC_ACTIVE 0x1 | |
254 | #define SCU_COMM_EXEC_HOLD 0x2 | |
43dd07f7 | 255 | #define SCU_RAM_DRIVER_DEBUG__A 0x831EBF |
43dd07f7 | 256 | #define SCU_RAM_QAM_FSM_STEP_PERIOD__A 0x831EC4 |
43dd07f7 | 257 | #define SCU_RAM_GPIO__A 0x831EC7 |
43dd07f7 | 258 | #define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 |
43dd07f7 | 259 | #define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8 |
43dd07f7 | 260 | #define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB |
43dd07f7 | 261 | #define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A 0x831F05 |
43dd07f7 | 262 | #define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831F15 |
43dd07f7 | 263 | #define SCU_RAM_AGC_KI_CYCLEN__A 0x831F17 |
43dd07f7 | 264 | #define SCU_RAM_AGC_SNS_CYCLEN__A 0x831F18 |
43dd07f7 | 265 | #define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831F19 |
43dd07f7 | 266 | #define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831F1A |
43dd07f7 | 267 | #define SCU_RAM_AGC_RF_MAX__A 0x831F1B |
43dd07f7 | 268 | #define SCU_RAM_AGC_CONFIG__A 0x831F24 |
43dd07f7 | 269 | #define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M 0x1 |
43dd07f7 | 270 | #define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M 0x2 |
43dd07f7 | 271 | #define SCU_RAM_AGC_CONFIG_INV_IF_POL__M 0x100 |
43dd07f7 | 272 | #define SCU_RAM_AGC_CONFIG_INV_RF_POL__M 0x200 |
43dd07f7 | 273 | #define SCU_RAM_AGC_KI__A 0x831F25 |
43dd07f7 | 274 | #define SCU_RAM_AGC_KI_RF__B 4 |
43dd07f7 | 275 | #define SCU_RAM_AGC_KI_RF__M 0xF0 |
43dd07f7 | 276 | #define SCU_RAM_AGC_KI_IF__B 8 |
43dd07f7 | 277 | #define SCU_RAM_AGC_KI_IF__M 0xF00 |
43dd07f7 | 278 | #define SCU_RAM_AGC_KI_RED__A 0x831F26 |
43dd07f7 | 279 | #define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2 |
43dd07f7 | 280 | #define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC |
43dd07f7 | 281 | #define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4 |
43dd07f7 | 282 | #define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30 |
43dd07f7 | 283 | #define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831F27 |
43dd07f7 | 284 | #define SCU_RAM_AGC_KI_MINGAIN__A 0x831F28 |
43dd07f7 | 285 | #define SCU_RAM_AGC_KI_MAXGAIN__A 0x831F29 |
43dd07f7 | 286 | #define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831F2A |
43dd07f7 | 287 | #define SCU_RAM_AGC_KI_MIN__A 0x831F2B |
43dd07f7 | 288 | #define SCU_RAM_AGC_KI_MAX__A 0x831F2C |
43dd07f7 | 289 | #define SCU_RAM_AGC_CLP_SUM__A 0x831F2D |
43dd07f7 | 290 | #define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831F2E |
43dd07f7 | 291 | #define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831F2F |
43dd07f7 | 292 | #define SCU_RAM_AGC_CLP_CYCLEN__A 0x831F30 |
43dd07f7 | 293 | #define SCU_RAM_AGC_CLP_CYCCNT__A 0x831F31 |
43dd07f7 | 294 | #define SCU_RAM_AGC_CLP_DIR_TO__A 0x831F32 |
43dd07f7 | 295 | #define SCU_RAM_AGC_CLP_DIR_WD__A 0x831F33 |
43dd07f7 | 296 | #define SCU_RAM_AGC_CLP_DIR_STP__A 0x831F34 |
43dd07f7 | 297 | #define SCU_RAM_AGC_SNS_SUM__A 0x831F35 |
43dd07f7 | 298 | #define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831F36 |
43dd07f7 | 299 | #define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831F37 |
43dd07f7 | 300 | #define SCU_RAM_AGC_SNS_CYCCNT__A 0x831F38 |
43dd07f7 | 301 | #define SCU_RAM_AGC_SNS_DIR_TO__A 0x831F39 |
43dd07f7 | 302 | #define SCU_RAM_AGC_SNS_DIR_WD__A 0x831F3A |
43dd07f7 | 303 | #define SCU_RAM_AGC_SNS_DIR_STP__A 0x831F3B |
43dd07f7 | 304 | #define SCU_RAM_AGC_INGAIN_TGT__A 0x831F3D |
43dd07f7 | 305 | #define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E |
43dd07f7 | 306 | #define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F |
43dd07f7 | 307 | #define SCU_RAM_AGC_IF_IACCU_HI__A 0x831F40 |
43dd07f7 | 308 | #define SCU_RAM_AGC_IF_IACCU_LO__A 0x831F41 |
43dd07f7 | 309 | #define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831F42 |
43dd07f7 | 310 | #define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831F43 |
43dd07f7 | 311 | #define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44 |
43dd07f7 | 312 | #define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45 |
43dd07f7 | 313 | #define SCU_RAM_AGC_RF_IACCU_LO__A 0x831F46 |
43dd07f7 | 314 | #define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831F47 |
43dd07f7 | 315 | #define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 |
43dd07f7 | 316 | #define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 |
43dd07f7 | 317 | #define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 |
43dd07f7 | 318 | #define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 |
43dd07f7 | 319 | #define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 |
43dd07f7 | 320 | #define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 |
43dd07f7 | 321 | #define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A |
43dd07f7 | 322 | #define SCU_RAM_QAM_FSM_RTH__A 0x831F8E |
43dd07f7 | 323 | #define SCU_RAM_QAM_FSM_FTH__A 0x831F8F |
43dd07f7 | 324 | #define SCU_RAM_QAM_FSM_PTH__A 0x831F90 |
43dd07f7 | 325 | #define SCU_RAM_QAM_FSM_MTH__A 0x831F91 |
43dd07f7 | 326 | #define SCU_RAM_QAM_FSM_CTH__A 0x831F92 |
43dd07f7 | 327 | #define SCU_RAM_QAM_FSM_QTH__A 0x831F93 |
43dd07f7 | 328 | #define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 |
43dd07f7 | 329 | #define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 |
43dd07f7 | 330 | #define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 |
43dd07f7 | 331 | #define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 |
43dd07f7 | 332 | #define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 |
43dd07f7 | 333 | #define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A |
43dd07f7 | 334 | #define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B |
43dd07f7 | 335 | #define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C |
43dd07f7 | 336 | #define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D |
43dd07f7 | 337 | #define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E |
43dd07f7 | 338 | #define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F |
43dd07f7 | 339 | #define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 |
43dd07f7 | 340 | #define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 |
43dd07f7 | 341 | #define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 |
43dd07f7 | 342 | #define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 |
43dd07f7 | 343 | #define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 |
43dd07f7 | 344 | #define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 |
43dd07f7 | 345 | #define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 |
43dd07f7 | 346 | #define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 |
43dd07f7 | 347 | #define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 |
43dd07f7 | 348 | #define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 |
43dd07f7 | 349 | #define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA |
43dd07f7 | 350 | #define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB |
43dd07f7 | 351 | #define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC |
43dd07f7 | 352 | #define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD |
43dd07f7 | 353 | #define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE |
43dd07f7 | 354 | #define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF |
43dd07f7 | 355 | #define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 |
43dd07f7 | 356 | #define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 |
43dd07f7 | 357 | #define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 |
43dd07f7 RM |
358 | #define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000 |
359 | #define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000 | |
360 | #define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000 | |
43dd07f7 | 361 | #define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA |
43dd07f7 | 362 | #define SCU_RAM_DRIVER_VER_HI__A 0x831FEB |
43dd07f7 | 363 | #define SCU_RAM_DRIVER_VER_LO__A 0x831FEC |
43dd07f7 | 364 | #define SCU_RAM_PARAM_15__A 0x831FED |
43dd07f7 | 365 | #define SCU_RAM_PARAM_0__A 0x831FFC |
43dd07f7 | 366 | #define SCU_RAM_COMMAND__A 0x831FFD |
43dd07f7 RM |
367 | #define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 |
368 | #define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2 | |
369 | #define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3 | |
370 | #define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4 | |
371 | #define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5 | |
43dd07f7 | 372 | #define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 |
43dd07f7 | 373 | #define SCU_RAM_COMMAND_STANDARD_QAM 0x200 |
43dd07f7 | 374 | #define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 |
43dd07f7 | 375 | #define SIO_TOP_COMM_KEY__A 0x41000F |
43dd07f7 | 376 | #define SIO_TOP_COMM_KEY_KEY 0xFABA |
43dd07f7 | 377 | #define SIO_TOP_JTAGID_LO__A 0x410012 |
43dd07f7 | 378 | #define SIO_HI_RA_RAM_RES__A 0x420031 |
43dd07f7 | 379 | #define SIO_HI_RA_RAM_CMD__A 0x420032 |
43dd07f7 RM |
380 | #define SIO_HI_RA_RAM_CMD_RESET 0x2 |
381 | #define SIO_HI_RA_RAM_CMD_CONFIG 0x3 | |
43dd07f7 | 382 | #define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7 |
43dd07f7 | 383 | #define SIO_HI_RA_RAM_PAR_1__A 0x420033 |
43dd07f7 | 384 | #define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 |
43dd07f7 | 385 | #define SIO_HI_RA_RAM_PAR_2__A 0x420034 |
43dd07f7 | 386 | #define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F |
43dd07f7 RM |
387 | #define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 |
388 | #define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 | |
43dd07f7 | 389 | #define SIO_HI_RA_RAM_PAR_3__A 0x420035 |
43dd07f7 | 390 | #define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F |
43dd07f7 | 391 | #define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 |
43dd07f7 RM |
392 | #define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 |
393 | #define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 | |
43dd07f7 | 394 | #define SIO_HI_RA_RAM_PAR_4__A 0x420036 |
43dd07f7 | 395 | #define SIO_HI_RA_RAM_PAR_5__A 0x420037 |
43dd07f7 | 396 | #define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 |
43dd07f7 | 397 | #define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 |
43dd07f7 | 398 | #define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 |
43dd07f7 | 399 | #define SIO_HI_RA_RAM_PAR_6__A 0x420038 |
43dd07f7 | 400 | #define SIO_CC_PLL_LOCK__A 0x450012 |
43dd07f7 | 401 | #define SIO_CC_PWD_MODE__A 0x450015 |
43dd07f7 RM |
402 | #define SIO_CC_PWD_MODE_LEVEL_NONE 0x0 |
403 | #define SIO_CC_PWD_MODE_LEVEL_OFDM 0x1 | |
404 | #define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2 | |
405 | #define SIO_CC_PWD_MODE_LEVEL_PLL 0x3 | |
406 | #define SIO_CC_PWD_MODE_LEVEL_OSC 0x4 | |
43dd07f7 | 407 | #define SIO_CC_SOFT_RST__A 0x450016 |
43dd07f7 | 408 | #define SIO_CC_SOFT_RST_OFDM__M 0x1 |
43dd07f7 | 409 | #define SIO_CC_SOFT_RST_SYS__M 0x2 |
43dd07f7 | 410 | #define SIO_CC_SOFT_RST_OSC__M 0x4 |
43dd07f7 | 411 | #define SIO_CC_UPDATE__A 0x450017 |
43dd07f7 | 412 | #define SIO_CC_UPDATE_KEY 0xFABA |
43dd07f7 | 413 | #define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010 |
43dd07f7 RM |
414 | #define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0 |
415 | #define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1 | |
43dd07f7 | 416 | #define SIO_OFDM_SH_OFDM_RING_STATUS__A 0x470012 |
43dd07f7 RM |
417 | #define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN 0x0 |
418 | #define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED 0x1 | |
43dd07f7 | 419 | #define SIO_BL_COMM_EXEC__A 0x480000 |
43dd07f7 | 420 | #define SIO_BL_COMM_EXEC_ACTIVE 0x1 |
43dd07f7 | 421 | #define SIO_BL_STATUS__A 0x480010 |
43dd07f7 | 422 | #define SIO_BL_MODE__A 0x480011 |
43dd07f7 RM |
423 | #define SIO_BL_MODE_DIRECT 0x0 |
424 | #define SIO_BL_MODE_CHAIN 0x1 | |
43dd07f7 | 425 | #define SIO_BL_ENABLE__A 0x480012 |
43dd07f7 | 426 | #define SIO_BL_ENABLE_ON 0x1 |
43dd07f7 | 427 | #define SIO_BL_TGT_HDR__A 0x480014 |
43dd07f7 | 428 | #define SIO_BL_TGT_ADDR__A 0x480015 |
43dd07f7 | 429 | #define SIO_BL_SRC_ADDR__A 0x480016 |
43dd07f7 | 430 | #define SIO_BL_SRC_LEN__A 0x480017 |
43dd07f7 | 431 | #define SIO_BL_CHAIN_ADDR__A 0x480018 |
43dd07f7 | 432 | #define SIO_BL_CHAIN_LEN__A 0x480019 |
43dd07f7 | 433 | #define SIO_PDR_MON_CFG__A 0x7F0010 |
43dd07f7 | 434 | #define SIO_PDR_UIO_IN_HI__A 0x7F0015 |
43dd07f7 | 435 | #define SIO_PDR_UIO_OUT_LO__A 0x7F0016 |
43dd07f7 | 436 | #define SIO_PDR_OHW_CFG__A 0x7F001F |
43dd07f7 | 437 | #define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3 |
14053443 | 438 | #define SIO_PDR_GPIO_CFG__A 0x7F0021 |
43dd07f7 | 439 | #define SIO_PDR_MSTRT_CFG__A 0x7F0025 |
43dd07f7 | 440 | #define SIO_PDR_MERR_CFG__A 0x7F0026 |
43dd07f7 | 441 | #define SIO_PDR_MCLK_CFG__A 0x7F0028 |
43dd07f7 | 442 | #define SIO_PDR_MCLK_CFG_DRIVE__B 3 |
43dd07f7 | 443 | #define SIO_PDR_MVAL_CFG__A 0x7F0029 |
43dd07f7 | 444 | #define SIO_PDR_MD0_CFG__A 0x7F002A |
43dd07f7 | 445 | #define SIO_PDR_MD0_CFG_DRIVE__B 3 |
43dd07f7 | 446 | #define SIO_PDR_MD1_CFG__A 0x7F002B |
43dd07f7 | 447 | #define SIO_PDR_MD2_CFG__A 0x7F002C |
43dd07f7 | 448 | #define SIO_PDR_MD3_CFG__A 0x7F002D |
43dd07f7 | 449 | #define SIO_PDR_MD4_CFG__A 0x7F002F |
43dd07f7 | 450 | #define SIO_PDR_MD5_CFG__A 0x7F0030 |
43dd07f7 | 451 | #define SIO_PDR_MD6_CFG__A 0x7F0031 |
43dd07f7 | 452 | #define SIO_PDR_MD7_CFG__A 0x7F0032 |
14053443 | 453 | #define SIO_PDR_SMA_RX_CFG__A 0x7F0037 |
43dd07f7 | 454 | #define SIO_PDR_SMA_TX_CFG__A 0x7F0038 |