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ca3355a9 DH |
1 | /* |
2 | Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. | |
3 | All rights reserved. | |
4 | ||
5 | Redistribution and use in source and binary forms, with or without | |
6 | modification, are permitted provided that the following conditions are met: | |
7 | ||
8 | * Redistributions of source code must retain the above copyright notice, | |
9 | this list of conditions and the following disclaimer. | |
10 | * Redistributions in binary form must reproduce the above copyright notice, | |
11 | this list of conditions and the following disclaimer in the documentation | |
12 | and/or other materials provided with the distribution. | |
13 | * Neither the name of Trident Microsystems nor Hauppauge Computer Works | |
14 | nor the names of its contributors may be used to endorse or promote | |
15 | products derived from this software without specific prior written | |
16 | permission. | |
17 | ||
18 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
19 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
20 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
21 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE | |
22 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
23 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
24 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
25 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
26 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
27 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
28 | POSSIBILITY OF SUCH DAMAGE. | |
29 | */ | |
30 | ||
38b2df95 DH |
31 | #ifndef __DRXDRIVER_H__ |
32 | #define __DRXDRIVER_H__ | |
6c1d56c5 MCC |
33 | |
34 | #include <linux/kernel.h> | |
9482354f | 35 | #include <linux/errno.h> |
b48293db MCC |
36 | #include <linux/firmware.h> |
37 | #include <linux/i2c.h> | |
6c1d56c5 MCC |
38 | |
39 | /* | |
57afe2f0 MCC |
40 | * This structure contains the I2C address, the device ID and a user_data pointer. |
41 | * The user_data pointer can be used for application specific purposes. | |
6c1d56c5 MCC |
42 | */ |
43 | struct i2c_device_addr { | |
57afe2f0 MCC |
44 | u16 i2c_addr; /* The I2C address of the device. */ |
45 | u16 i2c_dev_id; /* The device identifier. */ | |
46 | void *user_data; /* User data pointer */ | |
6c1d56c5 MCC |
47 | }; |
48 | ||
b95b0c98 | 49 | /* |
6c1d56c5 MCC |
50 | * \def IS_I2C_10BIT( addr ) |
51 | * \brief Determine if I2C address 'addr' is a 10 bits address or not. | |
52 | * \param addr The I2C address. | |
53 | * \return int. | |
54 | * \retval 0 if address is not a 10 bits I2C address. | |
55 | * \retval 1 if address is a 10 bits I2C address. | |
56 | */ | |
57 | #define IS_I2C_10BIT(addr) \ | |
58 | (((addr) & 0xF8) == 0xF0) | |
59 | ||
60 | /*------------------------------------------------------------------------------ | |
61 | Exported FUNCTIONS | |
62 | ------------------------------------------------------------------------------*/ | |
63 | ||
b95b0c98 | 64 | /* |
57afe2f0 | 65 | * \fn drxbsp_i2c_init() |
6c1d56c5 | 66 | * \brief Initialize I2C communication module. |
61263c75 | 67 | * \return int Return status. |
9482354f MCC |
68 | * \retval 0 Initialization successful. |
69 | * \retval -EIO Initialization failed. | |
6c1d56c5 | 70 | */ |
57afe2f0 | 71 | int drxbsp_i2c_init(void); |
6c1d56c5 | 72 | |
b95b0c98 | 73 | /* |
57afe2f0 | 74 | * \fn drxbsp_i2c_term() |
6c1d56c5 | 75 | * \brief Terminate I2C communication module. |
61263c75 | 76 | * \return int Return status. |
9482354f MCC |
77 | * \retval 0 Termination successful. |
78 | * \retval -EIO Termination failed. | |
6c1d56c5 | 79 | */ |
57afe2f0 | 80 | int drxbsp_i2c_term(void); |
6c1d56c5 | 81 | |
b95b0c98 | 82 | /* |
57afe2f0 MCC |
83 | * \fn int drxbsp_i2c_write_read( struct i2c_device_addr *w_dev_addr, |
84 | * u16 w_count, | |
6c1d56c5 | 85 | * u8 * wData, |
57afe2f0 MCC |
86 | * struct i2c_device_addr *r_dev_addr, |
87 | * u16 r_count, | |
88 | * u8 * r_data) | |
6c1d56c5 | 89 | * \brief Read and/or write count bytes from I2C bus, store them in data[]. |
57afe2f0 MCC |
90 | * \param w_dev_addr The device i2c address and the device ID to write to |
91 | * \param w_count The number of bytes to write | |
6c1d56c5 | 92 | * \param wData The array to write the data to |
57afe2f0 MCC |
93 | * \param r_dev_addr The device i2c address and the device ID to read from |
94 | * \param r_count The number of bytes to read | |
95 | * \param r_data The array to read the data from | |
61263c75 | 96 | * \return int Return status. |
9482354f MCC |
97 | * \retval 0 Succes. |
98 | * \retval -EIO Failure. | |
99 | * \retval -EINVAL Parameter 'wcount' is not zero but parameter | |
6c1d56c5 MCC |
100 | * 'wdata' contains NULL. |
101 | * Idem for 'rcount' and 'rdata'. | |
57afe2f0 | 102 | * Both w_dev_addr and r_dev_addr are NULL. |
6c1d56c5 MCC |
103 | * |
104 | * This function must implement an atomic write and/or read action on the I2C bus | |
105 | * No other process may use the I2C bus when this function is executing. | |
106 | * The critical section of this function runs from and including the I2C | |
107 | * write, up to and including the I2C read action. | |
108 | * | |
109 | * The device ID can be useful if several devices share an I2C address. | |
110 | * It can be used to control a "switch" on the I2C bus to the correct device. | |
111 | */ | |
57afe2f0 MCC |
112 | int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr, |
113 | u16 w_count, | |
7ef66759 | 114 | u8 *wData, |
57afe2f0 MCC |
115 | struct i2c_device_addr *r_dev_addr, |
116 | u16 r_count, u8 *r_data); | |
6c1d56c5 | 117 | |
b95b0c98 | 118 | /* |
57afe2f0 | 119 | * \fn drxbsp_i2c_error_text() |
6c1d56c5 | 120 | * \brief Returns a human readable error. |
57afe2f0 | 121 | * Counter part of numerical drx_i2c_error_g. |
6c1d56c5 MCC |
122 | * |
123 | * \return char* Pointer to human readable error text. | |
124 | */ | |
57afe2f0 | 125 | char *drxbsp_i2c_error_text(void); |
6c1d56c5 | 126 | |
b95b0c98 | 127 | /* |
57afe2f0 | 128 | * \var drx_i2c_error_g; |
6c1d56c5 MCC |
129 | * \brief I2C specific error codes, platform dependent. |
130 | */ | |
57afe2f0 | 131 | extern int drx_i2c_error_g; |
6c1d56c5 MCC |
132 | |
133 | #define TUNER_MODE_SUB0 0x0001 /* for sub-mode (e.g. RF-AGC setting) */ | |
134 | #define TUNER_MODE_SUB1 0x0002 /* for sub-mode (e.g. RF-AGC setting) */ | |
135 | #define TUNER_MODE_SUB2 0x0004 /* for sub-mode (e.g. RF-AGC setting) */ | |
136 | #define TUNER_MODE_SUB3 0x0008 /* for sub-mode (e.g. RF-AGC setting) */ | |
137 | #define TUNER_MODE_SUB4 0x0010 /* for sub-mode (e.g. RF-AGC setting) */ | |
138 | #define TUNER_MODE_SUB5 0x0020 /* for sub-mode (e.g. RF-AGC setting) */ | |
139 | #define TUNER_MODE_SUB6 0x0040 /* for sub-mode (e.g. RF-AGC setting) */ | |
140 | #define TUNER_MODE_SUB7 0x0080 /* for sub-mode (e.g. RF-AGC setting) */ | |
141 | ||
142 | #define TUNER_MODE_DIGITAL 0x0100 /* for digital channel (e.g. DVB-T) */ | |
143 | #define TUNER_MODE_ANALOG 0x0200 /* for analog channel (e.g. PAL) */ | |
144 | #define TUNER_MODE_SWITCH 0x0400 /* during channel switch & scanning */ | |
145 | #define TUNER_MODE_LOCK 0x0800 /* after tuner has locked */ | |
146 | #define TUNER_MODE_6MHZ 0x1000 /* for 6MHz bandwidth channels */ | |
147 | #define TUNER_MODE_7MHZ 0x2000 /* for 7MHz bandwidth channels */ | |
148 | #define TUNER_MODE_8MHZ 0x4000 /* for 8MHz bandwidth channels */ | |
149 | ||
150 | #define TUNER_MODE_SUB_MAX 8 | |
7ef66759 | 151 | #define TUNER_MODE_SUBALL (TUNER_MODE_SUB0 | TUNER_MODE_SUB1 | \ |
6c1d56c5 MCC |
152 | TUNER_MODE_SUB2 | TUNER_MODE_SUB3 | \ |
153 | TUNER_MODE_SUB4 | TUNER_MODE_SUB5 | \ | |
7ef66759 | 154 | TUNER_MODE_SUB6 | TUNER_MODE_SUB7) |
6c1d56c5 | 155 | |
6c1d56c5 | 156 | |
61263c75 | 157 | enum tuner_lock_status { |
6c1d56c5 MCC |
158 | TUNER_LOCKED, |
159 | TUNER_NOT_LOCKED | |
61263c75 | 160 | }; |
6c1d56c5 | 161 | |
61263c75 | 162 | struct tuner_common { |
6c1d56c5 | 163 | char *name; /* Tuner brand & type name */ |
57afe2f0 MCC |
164 | s32 min_freq_rf; /* Lowest RF input frequency, in kHz */ |
165 | s32 max_freq_rf; /* Highest RF input frequency, in kHz */ | |
6c1d56c5 | 166 | |
57afe2f0 | 167 | u8 sub_mode; /* Index to sub-mode in use */ |
e33f2193 | 168 | char ***sub_mode_descriptions; /* Pointer to description of sub-modes */ |
57afe2f0 | 169 | u8 sub_modes; /* Number of available sub-modes */ |
6c1d56c5 MCC |
170 | |
171 | /* The following fields will be either 0, NULL or false and do not need | |
172 | initialisation */ | |
57afe2f0 MCC |
173 | void *self_check; /* gives proof of initialization */ |
174 | bool programmed; /* only valid if self_check is OK */ | |
175 | s32 r_ffrequency; /* only valid if programmed */ | |
176 | s32 i_ffrequency; /* only valid if programmed */ | |
6c1d56c5 | 177 | |
e33f2193 | 178 | void *my_user_data; /* pointer to associated demod instance */ |
57afe2f0 | 179 | u16 my_capabilities; /* value for storing application flags */ |
61263c75 | 180 | }; |
6c1d56c5 | 181 | |
61263c75 | 182 | struct tuner_instance; |
6c1d56c5 | 183 | |
57afe2f0 MCC |
184 | typedef int(*tuner_open_func_t) (struct tuner_instance *tuner); |
185 | typedef int(*tuner_close_func_t) (struct tuner_instance *tuner); | |
6c1d56c5 | 186 | |
57afe2f0 | 187 | typedef int(*tuner_set_frequency_func_t) (struct tuner_instance *tuner, |
61263c75 | 188 | u32 mode, |
6c1d56c5 MCC |
189 | s32 |
190 | frequency); | |
191 | ||
57afe2f0 | 192 | typedef int(*tuner_get_frequency_func_t) (struct tuner_instance *tuner, |
61263c75 | 193 | u32 mode, |
6c1d56c5 | 194 | s32 * |
57afe2f0 | 195 | r_ffrequency, |
6c1d56c5 | 196 | s32 * |
57afe2f0 | 197 | i_ffrequency); |
6c1d56c5 | 198 | |
57afe2f0 | 199 | typedef int(*tuner_lock_status_func_t) (struct tuner_instance *tuner, |
61263c75 | 200 | enum tuner_lock_status * |
57afe2f0 | 201 | lock_stat); |
6c1d56c5 | 202 | |
57afe2f0 | 203 | typedef int(*tune_ri2c_write_read_func_t) (struct tuner_instance *tuner, |
6c1d56c5 | 204 | struct i2c_device_addr * |
57afe2f0 | 205 | w_dev_addr, u16 w_count, |
7ef66759 | 206 | u8 *wData, |
6c1d56c5 | 207 | struct i2c_device_addr * |
57afe2f0 MCC |
208 | r_dev_addr, u16 r_count, |
209 | u8 *r_data); | |
6c1d56c5 | 210 | |
61263c75 | 211 | struct tuner_ops { |
57afe2f0 MCC |
212 | tuner_open_func_t open_func; |
213 | tuner_close_func_t close_func; | |
214 | tuner_set_frequency_func_t set_frequency_func; | |
215 | tuner_get_frequency_func_t get_frequency_func; | |
e33f2193 | 216 | tuner_lock_status_func_t lock_status_func; |
57afe2f0 | 217 | tune_ri2c_write_read_func_t i2c_write_read_func; |
6c1d56c5 | 218 | |
61263c75 | 219 | }; |
6c1d56c5 | 220 | |
61263c75 | 221 | struct tuner_instance { |
57afe2f0 MCC |
222 | struct i2c_device_addr my_i2c_dev_addr; |
223 | struct tuner_common *my_common_attr; | |
224 | void *my_ext_attr; | |
225 | struct tuner_ops *my_funct; | |
61263c75 | 226 | }; |
6c1d56c5 | 227 | |
57afe2f0 | 228 | int drxbsp_tuner_set_frequency(struct tuner_instance *tuner, |
61263c75 | 229 | u32 mode, |
6c1d56c5 MCC |
230 | s32 frequency); |
231 | ||
57afe2f0 | 232 | int drxbsp_tuner_get_frequency(struct tuner_instance *tuner, |
61263c75 | 233 | u32 mode, |
57afe2f0 MCC |
234 | s32 *r_ffrequency, |
235 | s32 *i_ffrequency); | |
6c1d56c5 | 236 | |
57afe2f0 MCC |
237 | int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner, |
238 | struct i2c_device_addr *w_dev_addr, | |
239 | u16 w_count, | |
7ef66759 | 240 | u8 *wData, |
57afe2f0 MCC |
241 | struct i2c_device_addr *r_dev_addr, |
242 | u16 r_count, u8 *r_data); | |
6c1d56c5 | 243 | |
b95b0c98 | 244 | /************* |
38b2df95 DH |
245 | * |
246 | * This section configures the DRX Data Access Protocols (DAPs). | |
247 | * | |
248 | **************/ | |
249 | ||
b95b0c98 | 250 | /* |
38b2df95 DH |
251 | * \def DRXDAP_SINGLE_MASTER |
252 | * \brief Enable I2C single or I2C multimaster mode on host. | |
253 | * | |
254 | * Set to 1 to enable single master mode | |
255 | * Set to 0 to enable multi master mode | |
256 | * | |
257 | * The actual DAP implementation may be restricted to only one of the modes. | |
258 | * A compiler warning or error will be generated if the DAP implementation | |
505d3085 | 259 | * overrides or cannot handle the mode defined below. |
38b2df95 DH |
260 | */ |
261 | #ifndef DRXDAP_SINGLE_MASTER | |
9e4c509d | 262 | #define DRXDAP_SINGLE_MASTER 1 |
38b2df95 DH |
263 | #endif |
264 | ||
b95b0c98 | 265 | /* |
38b2df95 DH |
266 | * \def DRXDAP_MAX_WCHUNKSIZE |
267 | * \brief Defines maximum chunksize of an i2c write action by host. | |
268 | * | |
269 | * This indicates the maximum size of data the I2C device driver is able to | |
270 | * write at a time. This includes I2C device address and register addressing. | |
271 | * | |
272 | * This maximum size may be restricted by the actual DAP implementation. | |
273 | * A compiler warning or error will be generated if the DAP implementation | |
505d3085 | 274 | * overrides or cannot handle the chunksize defined below. |
38b2df95 DH |
275 | * |
276 | * Beware that the DAP uses DRXDAP_MAX_WCHUNKSIZE to create a temporary data | |
277 | * buffer. Do not undefine or choose too large, unless your system is able to | |
278 | * handle a stack buffer of that size. | |
279 | * | |
280 | */ | |
281 | #ifndef DRXDAP_MAX_WCHUNKSIZE | |
282 | #define DRXDAP_MAX_WCHUNKSIZE 60 | |
283 | #endif | |
284 | ||
b95b0c98 | 285 | /* |
38b2df95 DH |
286 | * \def DRXDAP_MAX_RCHUNKSIZE |
287 | * \brief Defines maximum chunksize of an i2c read action by host. | |
288 | * | |
289 | * This indicates the maximum size of data the I2C device driver is able to read | |
290 | * at a time. Minimum value is 2. Also, the read chunk size must be even. | |
291 | * | |
292 | * This maximum size may be restricted by the actual DAP implementation. | |
293 | * A compiler warning or error will be generated if the DAP implementation | |
505d3085 | 294 | * overrides or cannot handle the chunksize defined below. |
38b2df95 DH |
295 | */ |
296 | #ifndef DRXDAP_MAX_RCHUNKSIZE | |
297 | #define DRXDAP_MAX_RCHUNKSIZE 60 | |
298 | #endif | |
299 | ||
b95b0c98 | 300 | /************* |
38b2df95 DH |
301 | * |
302 | * This section describes drxdriver defines. | |
303 | * | |
304 | **************/ | |
305 | ||
b95b0c98 | 306 | /* |
38b2df95 DH |
307 | * \def DRX_UNKNOWN |
308 | * \brief Generic UNKNOWN value for DRX enumerated types. | |
309 | * | |
1250a85b | 310 | * Used to indicate that the parameter value is unknown or not yet initialized. |
38b2df95 DH |
311 | */ |
312 | #ifndef DRX_UNKNOWN | |
313 | #define DRX_UNKNOWN (254) | |
314 | #endif | |
315 | ||
b95b0c98 | 316 | /* |
38b2df95 DH |
317 | * \def DRX_AUTO |
318 | * \brief Generic AUTO value for DRX enumerated types. | |
319 | * | |
320 | * Used to instruct the driver to automatically determine the value of the | |
321 | * parameter. | |
322 | */ | |
323 | #ifndef DRX_AUTO | |
324 | #define DRX_AUTO (255) | |
325 | #endif | |
326 | ||
b95b0c98 | 327 | /************* |
38b2df95 DH |
328 | * |
329 | * This section describes flag definitions for the device capbilities. | |
330 | * | |
331 | **************/ | |
332 | ||
b95b0c98 | 333 | /* |
38b2df95 DH |
334 | * \brief LNA capability flag |
335 | * | |
336 | * Device has a Low Noise Amplifier | |
337 | * | |
338 | */ | |
339 | #define DRX_CAPABILITY_HAS_LNA (1UL << 0) | |
b95b0c98 | 340 | /* |
38b2df95 DH |
341 | * \brief OOB-RX capability flag |
342 | * | |
343 | * Device has OOB-RX | |
344 | * | |
345 | */ | |
346 | #define DRX_CAPABILITY_HAS_OOBRX (1UL << 1) | |
b95b0c98 | 347 | /* |
38b2df95 DH |
348 | * \brief ATV capability flag |
349 | * | |
350 | * Device has ATV | |
351 | * | |
352 | */ | |
353 | #define DRX_CAPABILITY_HAS_ATV (1UL << 2) | |
b95b0c98 | 354 | /* |
38b2df95 DH |
355 | * \brief DVB-T capability flag |
356 | * | |
357 | * Device has DVB-T | |
358 | * | |
359 | */ | |
360 | #define DRX_CAPABILITY_HAS_DVBT (1UL << 3) | |
b95b0c98 | 361 | /* |
38b2df95 DH |
362 | * \brief ITU-B capability flag |
363 | * | |
364 | * Device has ITU-B | |
365 | * | |
366 | */ | |
367 | #define DRX_CAPABILITY_HAS_ITUB (1UL << 4) | |
b95b0c98 | 368 | /* |
38b2df95 DH |
369 | * \brief Audio capability flag |
370 | * | |
371 | * Device has Audio | |
372 | * | |
373 | */ | |
374 | #define DRX_CAPABILITY_HAS_AUD (1UL << 5) | |
b95b0c98 | 375 | /* |
38b2df95 DH |
376 | * \brief SAW switch capability flag |
377 | * | |
378 | * Device has SAW switch | |
379 | * | |
380 | */ | |
381 | #define DRX_CAPABILITY_HAS_SAWSW (1UL << 6) | |
b95b0c98 | 382 | /* |
38b2df95 DH |
383 | * \brief GPIO1 capability flag |
384 | * | |
385 | * Device has GPIO1 | |
386 | * | |
387 | */ | |
388 | #define DRX_CAPABILITY_HAS_GPIO1 (1UL << 7) | |
b95b0c98 | 389 | /* |
38b2df95 DH |
390 | * \brief GPIO2 capability flag |
391 | * | |
392 | * Device has GPIO2 | |
393 | * | |
394 | */ | |
395 | #define DRX_CAPABILITY_HAS_GPIO2 (1UL << 8) | |
b95b0c98 | 396 | /* |
38b2df95 DH |
397 | * \brief IRQN capability flag |
398 | * | |
399 | * Device has IRQN | |
400 | * | |
401 | */ | |
402 | #define DRX_CAPABILITY_HAS_IRQN (1UL << 9) | |
b95b0c98 | 403 | /* |
38b2df95 DH |
404 | * \brief 8VSB capability flag |
405 | * | |
406 | * Device has 8VSB | |
407 | * | |
408 | */ | |
409 | #define DRX_CAPABILITY_HAS_8VSB (1UL << 10) | |
b95b0c98 | 410 | /* |
38b2df95 DH |
411 | * \brief SMA-TX capability flag |
412 | * | |
413 | * Device has SMATX | |
414 | * | |
415 | */ | |
416 | #define DRX_CAPABILITY_HAS_SMATX (1UL << 11) | |
b95b0c98 | 417 | /* |
38b2df95 DH |
418 | * \brief SMA-RX capability flag |
419 | * | |
420 | * Device has SMARX | |
421 | * | |
422 | */ | |
423 | #define DRX_CAPABILITY_HAS_SMARX (1UL << 12) | |
b95b0c98 | 424 | /* |
38b2df95 DH |
425 | * \brief ITU-A/C capability flag |
426 | * | |
427 | * Device has ITU-A/C | |
428 | * | |
429 | */ | |
430 | #define DRX_CAPABILITY_HAS_ITUAC (1UL << 13) | |
431 | ||
432 | /*------------------------------------------------------------------------- | |
433 | MACROS | |
434 | -------------------------------------------------------------------------*/ | |
435 | /* Macros to stringify the version number */ | |
7ef66759 | 436 | #define DRX_VERSIONSTRING(MAJOR, MINOR, PATCH) \ |
38b2df95 DH |
437 | DRX_VERSIONSTRING_HELP(MAJOR)"." \ |
438 | DRX_VERSIONSTRING_HELP(MINOR)"." \ | |
439 | DRX_VERSIONSTRING_HELP(PATCH) | |
7ef66759 | 440 | #define DRX_VERSIONSTRING_HELP(NUM) #NUM |
38b2df95 | 441 | |
b95b0c98 | 442 | /* |
38b2df95 DH |
443 | * \brief Macro to create byte array elements from 16 bit integers. |
444 | * This macro is used to create byte arrays for block writes. | |
445 | * Block writes speed up I2C traffic between host and demod. | |
446 | * The macro takes care of the required byte order in a 16 bits word. | |
447 | * x->lowbyte(x), highbyte(x) | |
448 | */ | |
7ef66759 | 449 | #define DRX_16TO8(x) ((u8) (((u16)x) & 0xFF)), \ |
43a431e4 | 450 | ((u8)((((u16)x)>>8)&0xFF)) |
38b2df95 | 451 | |
b95b0c98 | 452 | /* |
73f7065b | 453 | * \brief Macro to convert 16 bit register value to a s32 |
38b2df95 | 454 | */ |
22892268 | 455 | #define DRX_U16TODRXFREQ(x) ((x & 0x8000) ? \ |
7ef66759 | 456 | ((s32) \ |
1bfc9e15 | 457 | (((u32) x) | 0xFFFF0000)) : \ |
22892268 | 458 | ((s32) x)) |
38b2df95 DH |
459 | |
460 | /*------------------------------------------------------------------------- | |
461 | ENUM | |
462 | -------------------------------------------------------------------------*/ | |
463 | ||
b95b0c98 | 464 | /* |
61263c75 | 465 | * \enum enum drx_standard |
38b2df95 DH |
466 | * \brief Modulation standards. |
467 | */ | |
61263c75 | 468 | enum drx_standard { |
b95b0c98 MCC |
469 | DRX_STANDARD_DVBT = 0, /*< Terrestrial DVB-T. */ |
470 | DRX_STANDARD_8VSB, /*< Terrestrial 8VSB. */ | |
471 | DRX_STANDARD_NTSC, /*< Terrestrial\Cable analog NTSC. */ | |
61263c75 | 472 | DRX_STANDARD_PAL_SECAM_BG, |
b95b0c98 | 473 | /*< Terrestrial analog PAL/SECAM B/G */ |
61263c75 | 474 | DRX_STANDARD_PAL_SECAM_DK, |
b95b0c98 | 475 | /*< Terrestrial analog PAL/SECAM D/K */ |
61263c75 | 476 | DRX_STANDARD_PAL_SECAM_I, |
b95b0c98 | 477 | /*< Terrestrial analog PAL/SECAM I */ |
61263c75 | 478 | DRX_STANDARD_PAL_SECAM_L, |
b95b0c98 | 479 | /*< Terrestrial analog PAL/SECAM L |
61263c75 MCC |
480 | with negative modulation */ |
481 | DRX_STANDARD_PAL_SECAM_LP, | |
b95b0c98 | 482 | /*< Terrestrial analog PAL/SECAM L |
61263c75 | 483 | with positive modulation */ |
b95b0c98 MCC |
484 | DRX_STANDARD_ITU_A, /*< Cable ITU ANNEX A. */ |
485 | DRX_STANDARD_ITU_B, /*< Cable ITU ANNEX B. */ | |
486 | DRX_STANDARD_ITU_C, /*< Cable ITU ANNEX C. */ | |
487 | DRX_STANDARD_ITU_D, /*< Cable ITU ANNEX D. */ | |
488 | DRX_STANDARD_FM, /*< Terrestrial\Cable FM radio */ | |
489 | DRX_STANDARD_DTMB, /*< Terrestrial DTMB standard (China)*/ | |
61263c75 | 490 | DRX_STANDARD_UNKNOWN = DRX_UNKNOWN, |
b95b0c98 | 491 | /*< Standard unknown. */ |
61263c75 | 492 | DRX_STANDARD_AUTO = DRX_AUTO |
b95b0c98 | 493 | /*< Autodetect standard. */ |
61263c75 MCC |
494 | }; |
495 | ||
b95b0c98 | 496 | /* |
61263c75 | 497 | * \enum enum drx_standard |
38b2df95 DH |
498 | * \brief Modulation sub-standards. |
499 | */ | |
61263c75 | 500 | enum drx_substandard { |
b95b0c98 | 501 | DRX_SUBSTANDARD_MAIN = 0, /*< Main subvariant of standard */ |
61263c75 MCC |
502 | DRX_SUBSTANDARD_ATV_BG_SCANDINAVIA, |
503 | DRX_SUBSTANDARD_ATV_DK_POLAND, | |
504 | DRX_SUBSTANDARD_ATV_DK_CHINA, | |
505 | DRX_SUBSTANDARD_UNKNOWN = DRX_UNKNOWN, | |
b95b0c98 | 506 | /*< Sub-standard unknown. */ |
61263c75 | 507 | DRX_SUBSTANDARD_AUTO = DRX_AUTO |
b95b0c98 | 508 | /*< Auto (default) sub-standard */ |
61263c75 MCC |
509 | }; |
510 | ||
b95b0c98 | 511 | /* |
61263c75 | 512 | * \enum enum drx_bandwidth |
38b2df95 DH |
513 | * \brief Channel bandwidth or channel spacing. |
514 | */ | |
61263c75 | 515 | enum drx_bandwidth { |
b95b0c98 MCC |
516 | DRX_BANDWIDTH_8MHZ = 0, /*< Bandwidth 8 MHz. */ |
517 | DRX_BANDWIDTH_7MHZ, /*< Bandwidth 7 MHz. */ | |
518 | DRX_BANDWIDTH_6MHZ, /*< Bandwidth 6 MHz. */ | |
61263c75 | 519 | DRX_BANDWIDTH_UNKNOWN = DRX_UNKNOWN, |
b95b0c98 | 520 | /*< Bandwidth unknown. */ |
61263c75 | 521 | DRX_BANDWIDTH_AUTO = DRX_AUTO |
b95b0c98 | 522 | /*< Auto Set Bandwidth */ |
61263c75 | 523 | }; |
38b2df95 | 524 | |
b95b0c98 | 525 | /* |
61263c75 | 526 | * \enum enum drx_mirror |
38b2df95 DH |
527 | * \brief Indicate if channel spectrum is mirrored or not. |
528 | */ | |
7ef66759 | 529 | enum drx_mirror { |
b95b0c98 MCC |
530 | DRX_MIRROR_NO = 0, /*< Spectrum is not mirrored. */ |
531 | DRX_MIRROR_YES, /*< Spectrum is mirrored. */ | |
61263c75 | 532 | DRX_MIRROR_UNKNOWN = DRX_UNKNOWN, |
b95b0c98 | 533 | /*< Unknown if spectrum is mirrored. */ |
61263c75 | 534 | DRX_MIRROR_AUTO = DRX_AUTO |
b95b0c98 | 535 | /*< Autodetect if spectrum is mirrored. */ |
61263c75 | 536 | }; |
38b2df95 | 537 | |
b95b0c98 | 538 | /* |
61263c75 | 539 | * \enum enum drx_modulation |
38b2df95 DH |
540 | * \brief Constellation type of the channel. |
541 | */ | |
61263c75 | 542 | enum drx_modulation { |
b95b0c98 MCC |
543 | DRX_CONSTELLATION_BPSK = 0, /*< Modulation is BPSK. */ |
544 | DRX_CONSTELLATION_QPSK, /*< Constellation is QPSK. */ | |
545 | DRX_CONSTELLATION_PSK8, /*< Constellation is PSK8. */ | |
546 | DRX_CONSTELLATION_QAM16, /*< Constellation is QAM16. */ | |
547 | DRX_CONSTELLATION_QAM32, /*< Constellation is QAM32. */ | |
548 | DRX_CONSTELLATION_QAM64, /*< Constellation is QAM64. */ | |
549 | DRX_CONSTELLATION_QAM128, /*< Constellation is QAM128. */ | |
550 | DRX_CONSTELLATION_QAM256, /*< Constellation is QAM256. */ | |
551 | DRX_CONSTELLATION_QAM512, /*< Constellation is QAM512. */ | |
552 | DRX_CONSTELLATION_QAM1024, /*< Constellation is QAM1024. */ | |
553 | DRX_CONSTELLATION_QPSK_NR, /*< Constellation is QPSK_NR */ | |
61263c75 | 554 | DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, |
b95b0c98 | 555 | /*< Constellation unknown. */ |
61263c75 | 556 | DRX_CONSTELLATION_AUTO = DRX_AUTO |
b95b0c98 | 557 | /*< Autodetect constellation. */ |
61263c75 MCC |
558 | }; |
559 | ||
b95b0c98 | 560 | /* |
61263c75 | 561 | * \enum enum drx_hierarchy |
38b2df95 DH |
562 | * \brief Hierarchy of the channel. |
563 | */ | |
61263c75 | 564 | enum drx_hierarchy { |
b95b0c98 MCC |
565 | DRX_HIERARCHY_NONE = 0, /*< None hierarchical channel. */ |
566 | DRX_HIERARCHY_ALPHA1, /*< Hierarchical channel, alpha=1. */ | |
567 | DRX_HIERARCHY_ALPHA2, /*< Hierarchical channel, alpha=2. */ | |
568 | DRX_HIERARCHY_ALPHA4, /*< Hierarchical channel, alpha=4. */ | |
61263c75 | 569 | DRX_HIERARCHY_UNKNOWN = DRX_UNKNOWN, |
b95b0c98 | 570 | /*< Hierarchy unknown. */ |
61263c75 | 571 | DRX_HIERARCHY_AUTO = DRX_AUTO |
b95b0c98 | 572 | /*< Autodetect hierarchy. */ |
61263c75 MCC |
573 | }; |
574 | ||
b95b0c98 | 575 | /* |
61263c75 | 576 | * \enum enum drx_priority |
38b2df95 DH |
577 | * \brief Channel priority in case of hierarchical transmission. |
578 | */ | |
61263c75 | 579 | enum drx_priority { |
b95b0c98 MCC |
580 | DRX_PRIORITY_LOW = 0, /*< Low priority channel. */ |
581 | DRX_PRIORITY_HIGH, /*< High priority channel. */ | |
61263c75 | 582 | DRX_PRIORITY_UNKNOWN = DRX_UNKNOWN |
b95b0c98 | 583 | /*< Priority unknown. */ |
61263c75 | 584 | }; |
38b2df95 | 585 | |
b95b0c98 | 586 | /* |
61263c75 | 587 | * \enum enum drx_coderate |
38b2df95 DH |
588 | * \brief Channel priority in case of hierarchical transmission. |
589 | */ | |
7ef66759 | 590 | enum drx_coderate { |
b95b0c98 MCC |
591 | DRX_CODERATE_1DIV2 = 0, /*< Code rate 1/2nd. */ |
592 | DRX_CODERATE_2DIV3, /*< Code rate 2/3nd. */ | |
593 | DRX_CODERATE_3DIV4, /*< Code rate 3/4nd. */ | |
594 | DRX_CODERATE_5DIV6, /*< Code rate 5/6nd. */ | |
595 | DRX_CODERATE_7DIV8, /*< Code rate 7/8nd. */ | |
443f18d0 | 596 | DRX_CODERATE_UNKNOWN = DRX_UNKNOWN, |
b95b0c98 | 597 | /*< Code rate unknown. */ |
443f18d0 | 598 | DRX_CODERATE_AUTO = DRX_AUTO |
b95b0c98 | 599 | /*< Autodetect code rate. */ |
61263c75 | 600 | }; |
38b2df95 | 601 | |
b95b0c98 | 602 | /* |
61263c75 | 603 | * \enum enum drx_guard |
38b2df95 DH |
604 | * \brief Guard interval of a channel. |
605 | */ | |
61263c75 | 606 | enum drx_guard { |
b95b0c98 MCC |
607 | DRX_GUARD_1DIV32 = 0, /*< Guard interval 1/32nd. */ |
608 | DRX_GUARD_1DIV16, /*< Guard interval 1/16th. */ | |
609 | DRX_GUARD_1DIV8, /*< Guard interval 1/8th. */ | |
610 | DRX_GUARD_1DIV4, /*< Guard interval 1/4th. */ | |
61263c75 | 611 | DRX_GUARD_UNKNOWN = DRX_UNKNOWN, |
b95b0c98 | 612 | /*< Guard interval unknown. */ |
61263c75 | 613 | DRX_GUARD_AUTO = DRX_AUTO |
b95b0c98 | 614 | /*< Autodetect guard interval. */ |
61263c75 MCC |
615 | }; |
616 | ||
b95b0c98 | 617 | /* |
61263c75 | 618 | * \enum enum drx_fft_mode |
38b2df95 DH |
619 | * \brief FFT mode. |
620 | */ | |
61263c75 | 621 | enum drx_fft_mode { |
b95b0c98 MCC |
622 | DRX_FFTMODE_2K = 0, /*< 2K FFT mode. */ |
623 | DRX_FFTMODE_4K, /*< 4K FFT mode. */ | |
624 | DRX_FFTMODE_8K, /*< 8K FFT mode. */ | |
61263c75 | 625 | DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, |
b95b0c98 | 626 | /*< FFT mode unknown. */ |
61263c75 | 627 | DRX_FFTMODE_AUTO = DRX_AUTO |
b95b0c98 | 628 | /*< Autodetect FFT mode. */ |
61263c75 | 629 | }; |
38b2df95 | 630 | |
b95b0c98 | 631 | /* |
61263c75 | 632 | * \enum enum drx_classification |
38b2df95 DH |
633 | * \brief Channel classification. |
634 | */ | |
61263c75 | 635 | enum drx_classification { |
b95b0c98 MCC |
636 | DRX_CLASSIFICATION_GAUSS = 0, /*< Gaussion noise. */ |
637 | DRX_CLASSIFICATION_HVY_GAUSS, /*< Heavy Gaussion noise. */ | |
638 | DRX_CLASSIFICATION_COCHANNEL, /*< Co-channel. */ | |
639 | DRX_CLASSIFICATION_STATIC, /*< Static echo. */ | |
640 | DRX_CLASSIFICATION_MOVING, /*< Moving echo. */ | |
641 | DRX_CLASSIFICATION_ZERODB, /*< Zero dB echo. */ | |
61263c75 | 642 | DRX_CLASSIFICATION_UNKNOWN = DRX_UNKNOWN, |
b95b0c98 | 643 | /*< Unknown classification */ |
61263c75 | 644 | DRX_CLASSIFICATION_AUTO = DRX_AUTO |
b95b0c98 | 645 | /*< Autodetect classification. */ |
61263c75 MCC |
646 | }; |
647 | ||
b95b0c98 | 648 | /* |
61263c75 | 649 | * /enum enum drx_interleave_mode |
38b2df95 DH |
650 | * /brief Interleave modes |
651 | */ | |
61263c75 MCC |
652 | enum drx_interleave_mode { |
653 | DRX_INTERLEAVEMODE_I128_J1 = 0, | |
654 | DRX_INTERLEAVEMODE_I128_J1_V2, | |
655 | DRX_INTERLEAVEMODE_I128_J2, | |
656 | DRX_INTERLEAVEMODE_I64_J2, | |
657 | DRX_INTERLEAVEMODE_I128_J3, | |
658 | DRX_INTERLEAVEMODE_I32_J4, | |
659 | DRX_INTERLEAVEMODE_I128_J4, | |
660 | DRX_INTERLEAVEMODE_I16_J8, | |
661 | DRX_INTERLEAVEMODE_I128_J5, | |
662 | DRX_INTERLEAVEMODE_I8_J16, | |
663 | DRX_INTERLEAVEMODE_I128_J6, | |
664 | DRX_INTERLEAVEMODE_RESERVED_11, | |
665 | DRX_INTERLEAVEMODE_I128_J7, | |
666 | DRX_INTERLEAVEMODE_RESERVED_13, | |
667 | DRX_INTERLEAVEMODE_I128_J8, | |
668 | DRX_INTERLEAVEMODE_RESERVED_15, | |
669 | DRX_INTERLEAVEMODE_I12_J17, | |
670 | DRX_INTERLEAVEMODE_I5_J4, | |
671 | DRX_INTERLEAVEMODE_B52_M240, | |
672 | DRX_INTERLEAVEMODE_B52_M720, | |
673 | DRX_INTERLEAVEMODE_B52_M48, | |
674 | DRX_INTERLEAVEMODE_B52_M0, | |
675 | DRX_INTERLEAVEMODE_UNKNOWN = DRX_UNKNOWN, | |
b95b0c98 | 676 | /*< Unknown interleave mode */ |
61263c75 | 677 | DRX_INTERLEAVEMODE_AUTO = DRX_AUTO |
b95b0c98 | 678 | /*< Autodetect interleave mode */ |
61263c75 MCC |
679 | }; |
680 | ||
b95b0c98 | 681 | /* |
61263c75 | 682 | * \enum enum drx_carrier_mode |
38b2df95 DH |
683 | * \brief Channel Carrier Mode. |
684 | */ | |
7ef66759 | 685 | enum drx_carrier_mode { |
b95b0c98 MCC |
686 | DRX_CARRIER_MULTI = 0, /*< Multi carrier mode */ |
687 | DRX_CARRIER_SINGLE, /*< Single carrier mode */ | |
61263c75 | 688 | DRX_CARRIER_UNKNOWN = DRX_UNKNOWN, |
b95b0c98 MCC |
689 | /*< Carrier mode unknown. */ |
690 | DRX_CARRIER_AUTO = DRX_AUTO /*< Autodetect carrier mode */ | |
61263c75 | 691 | }; |
38b2df95 | 692 | |
b95b0c98 | 693 | /* |
61263c75 | 694 | * \enum enum drx_frame_mode |
38b2df95 DH |
695 | * \brief Channel Frame Mode. |
696 | */ | |
7ef66759 | 697 | enum drx_frame_mode { |
b95b0c98 MCC |
698 | DRX_FRAMEMODE_420 = 0, /*< 420 with variable PN */ |
699 | DRX_FRAMEMODE_595, /*< 595 */ | |
700 | DRX_FRAMEMODE_945, /*< 945 with variable PN */ | |
61263c75 | 701 | DRX_FRAMEMODE_420_FIXED_PN, |
b95b0c98 | 702 | /*< 420 with fixed PN */ |
61263c75 | 703 | DRX_FRAMEMODE_945_FIXED_PN, |
b95b0c98 | 704 | /*< 945 with fixed PN */ |
61263c75 | 705 | DRX_FRAMEMODE_UNKNOWN = DRX_UNKNOWN, |
b95b0c98 | 706 | /*< Frame mode unknown. */ |
61263c75 | 707 | DRX_FRAMEMODE_AUTO = DRX_AUTO |
b95b0c98 | 708 | /*< Autodetect frame mode */ |
61263c75 MCC |
709 | }; |
710 | ||
b95b0c98 | 711 | /* |
61263c75 | 712 | * \enum enum drx_tps_frame |
38b2df95 DH |
713 | * \brief Frame number in current super-frame. |
714 | */ | |
7ef66759 | 715 | enum drx_tps_frame { |
b95b0c98 MCC |
716 | DRX_TPS_FRAME1 = 0, /*< TPS frame 1. */ |
717 | DRX_TPS_FRAME2, /*< TPS frame 2. */ | |
718 | DRX_TPS_FRAME3, /*< TPS frame 3. */ | |
719 | DRX_TPS_FRAME4, /*< TPS frame 4. */ | |
61263c75 | 720 | DRX_TPS_FRAME_UNKNOWN = DRX_UNKNOWN |
b95b0c98 | 721 | /*< TPS frame unknown. */ |
61263c75 | 722 | }; |
38b2df95 | 723 | |
b95b0c98 | 724 | /* |
61263c75 | 725 | * \enum enum drx_ldpc |
38b2df95 DH |
726 | * \brief TPS LDPC . |
727 | */ | |
7ef66759 | 728 | enum drx_ldpc { |
b95b0c98 MCC |
729 | DRX_LDPC_0_4 = 0, /*< LDPC 0.4 */ |
730 | DRX_LDPC_0_6, /*< LDPC 0.6 */ | |
731 | DRX_LDPC_0_8, /*< LDPC 0.8 */ | |
61263c75 | 732 | DRX_LDPC_UNKNOWN = DRX_UNKNOWN, |
b95b0c98 MCC |
733 | /*< LDPC unknown. */ |
734 | DRX_LDPC_AUTO = DRX_AUTO /*< Autodetect LDPC */ | |
61263c75 | 735 | }; |
38b2df95 | 736 | |
b95b0c98 | 737 | /* |
61263c75 | 738 | * \enum enum drx_pilot_mode |
38b2df95 DH |
739 | * \brief Pilot modes in DTMB. |
740 | */ | |
7ef66759 | 741 | enum drx_pilot_mode { |
b95b0c98 MCC |
742 | DRX_PILOT_ON = 0, /*< Pilot On */ |
743 | DRX_PILOT_OFF, /*< Pilot Off */ | |
61263c75 | 744 | DRX_PILOT_UNKNOWN = DRX_UNKNOWN, |
b95b0c98 MCC |
745 | /*< Pilot unknown. */ |
746 | DRX_PILOT_AUTO = DRX_AUTO /*< Autodetect Pilot */ | |
61263c75 | 747 | }; |
38b2df95 | 748 | |
b95b0c98 | 749 | /* |
1bfc9e15 MCC |
750 | * enum drxu_code_action - indicate if firmware has to be uploaded or verified. |
751 | * @UCODE_UPLOAD: Upload the microcode image to device | |
752 | * @UCODE_VERIFY: Compare microcode image with code on device | |
753 | */ | |
754 | enum drxu_code_action { | |
755 | UCODE_UPLOAD, | |
756 | UCODE_VERIFY | |
757 | }; | |
38b2df95 | 758 | |
b95b0c98 | 759 | /* |
1bfc9e15 | 760 | * \enum enum drx_lock_status * \brief Used to reflect current lock status of demodulator. |
38b2df95 DH |
761 | * |
762 | * The generic lock states have device dependent semantics. | |
1bfc9e15 | 763 | |
443f18d0 | 764 | DRX_NEVER_LOCK = 0, |
1bfc9e15 | 765 | **< Device will never lock on this signal * |
443f18d0 | 766 | DRX_NOT_LOCKED, |
1bfc9e15 | 767 | **< Device has no lock at all * |
443f18d0 | 768 | DRX_LOCK_STATE_1, |
1bfc9e15 | 769 | **< Generic lock state * |
443f18d0 | 770 | DRX_LOCK_STATE_2, |
1bfc9e15 | 771 | **< Generic lock state * |
443f18d0 | 772 | DRX_LOCK_STATE_3, |
1bfc9e15 | 773 | **< Generic lock state * |
443f18d0 | 774 | DRX_LOCK_STATE_4, |
1bfc9e15 | 775 | **< Generic lock state * |
443f18d0 | 776 | DRX_LOCK_STATE_5, |
1bfc9e15 | 777 | **< Generic lock state * |
443f18d0 | 778 | DRX_LOCK_STATE_6, |
1bfc9e15 | 779 | **< Generic lock state * |
443f18d0 | 780 | DRX_LOCK_STATE_7, |
1bfc9e15 | 781 | **< Generic lock state * |
443f18d0 | 782 | DRX_LOCK_STATE_8, |
1bfc9e15 | 783 | **< Generic lock state * |
443f18d0 | 784 | DRX_LOCK_STATE_9, |
1bfc9e15 MCC |
785 | **< Generic lock state * |
786 | DRX_LOCKED **< Device is in lock * | |
787 | */ | |
788 | ||
789 | enum drx_lock_status { | |
790 | DRX_NEVER_LOCK = 0, | |
791 | DRX_NOT_LOCKED, | |
792 | DRX_LOCK_STATE_1, | |
793 | DRX_LOCK_STATE_2, | |
794 | DRX_LOCK_STATE_3, | |
795 | DRX_LOCK_STATE_4, | |
796 | DRX_LOCK_STATE_5, | |
797 | DRX_LOCK_STATE_6, | |
798 | DRX_LOCK_STATE_7, | |
799 | DRX_LOCK_STATE_8, | |
800 | DRX_LOCK_STATE_9, | |
801 | DRX_LOCKED | |
802 | }; | |
803 | ||
b95b0c98 | 804 | /* |
1bfc9e15 MCC |
805 | * \enum enum drx_uio* \brief Used to address a User IO (UIO). |
806 | */ | |
807 | enum drx_uio { | |
808 | DRX_UIO1, | |
809 | DRX_UIO2, | |
810 | DRX_UIO3, | |
811 | DRX_UIO4, | |
812 | DRX_UIO5, | |
813 | DRX_UIO6, | |
814 | DRX_UIO7, | |
815 | DRX_UIO8, | |
816 | DRX_UIO9, | |
817 | DRX_UIO10, | |
818 | DRX_UIO11, | |
819 | DRX_UIO12, | |
820 | DRX_UIO13, | |
821 | DRX_UIO14, | |
822 | DRX_UIO15, | |
823 | DRX_UIO16, | |
824 | DRX_UIO17, | |
825 | DRX_UIO18, | |
826 | DRX_UIO19, | |
827 | DRX_UIO20, | |
828 | DRX_UIO21, | |
829 | DRX_UIO22, | |
830 | DRX_UIO23, | |
831 | DRX_UIO24, | |
832 | DRX_UIO25, | |
833 | DRX_UIO26, | |
834 | DRX_UIO27, | |
835 | DRX_UIO28, | |
836 | DRX_UIO29, | |
837 | DRX_UIO30, | |
838 | DRX_UIO31, | |
839 | DRX_UIO32, | |
840 | DRX_UIO_MAX = DRX_UIO32 | |
841 | }; | |
842 | ||
b95b0c98 | 843 | /* |
1bfc9e15 | 844 | * \enum enum drxuio_mode * \brief Used to configure the modus oprandi of a UIO. |
38b2df95 DH |
845 | * |
846 | * DRX_UIO_MODE_FIRMWARE is an old uio mode. | |
847 | * It is replaced by the modes DRX_UIO_MODE_FIRMWARE0 .. DRX_UIO_MODE_FIRMWARE9. | |
848 | * To be backward compatible DRX_UIO_MODE_FIRMWARE is equivalent to | |
849 | * DRX_UIO_MODE_FIRMWARE0. | |
850 | */ | |
1bfc9e15 MCC |
851 | enum drxuio_mode { |
852 | DRX_UIO_MODE_DISABLE = 0x01, | |
b95b0c98 | 853 | /*< not used, pin is configured as input */ |
1bfc9e15 | 854 | DRX_UIO_MODE_READWRITE = 0x02, |
b95b0c98 | 855 | /*< used for read/write by application */ |
1bfc9e15 | 856 | DRX_UIO_MODE_FIRMWARE = 0x04, |
b95b0c98 | 857 | /*< controlled by firmware, function 0 */ |
1bfc9e15 | 858 | DRX_UIO_MODE_FIRMWARE0 = DRX_UIO_MODE_FIRMWARE, |
b95b0c98 | 859 | /*< same as above */ |
1bfc9e15 | 860 | DRX_UIO_MODE_FIRMWARE1 = 0x08, |
b95b0c98 | 861 | /*< controlled by firmware, function 1 */ |
1bfc9e15 | 862 | DRX_UIO_MODE_FIRMWARE2 = 0x10, |
b95b0c98 | 863 | /*< controlled by firmware, function 2 */ |
1bfc9e15 | 864 | DRX_UIO_MODE_FIRMWARE3 = 0x20, |
b95b0c98 | 865 | /*< controlled by firmware, function 3 */ |
1bfc9e15 | 866 | DRX_UIO_MODE_FIRMWARE4 = 0x40, |
b95b0c98 | 867 | /*< controlled by firmware, function 4 */ |
1bfc9e15 | 868 | DRX_UIO_MODE_FIRMWARE5 = 0x80 |
b95b0c98 | 869 | /*< controlled by firmware, function 5 */ |
1bfc9e15 MCC |
870 | }; |
871 | ||
b95b0c98 | 872 | /* |
1bfc9e15 | 873 | * \enum enum drxoob_downstream_standard * \brief Used to select OOB standard. |
38b2df95 DH |
874 | * |
875 | * Based on ANSI 55-1 and 55-2 | |
876 | */ | |
1bfc9e15 MCC |
877 | enum drxoob_downstream_standard { |
878 | DRX_OOB_MODE_A = 0, | |
b95b0c98 | 879 | /*< ANSI 55-1 */ |
1bfc9e15 | 880 | DRX_OOB_MODE_B_GRADE_A, |
b95b0c98 | 881 | /*< ANSI 55-2 A */ |
1bfc9e15 | 882 | DRX_OOB_MODE_B_GRADE_B |
b95b0c98 | 883 | /*< ANSI 55-2 B */ |
1bfc9e15 | 884 | }; |
38b2df95 DH |
885 | |
886 | /*------------------------------------------------------------------------- | |
887 | STRUCTS | |
888 | -------------------------------------------------------------------------*/ | |
889 | ||
890 | /*============================================================================*/ | |
891 | /*============================================================================*/ | |
892 | /*== CTRL CFG related data structures ========================================*/ | |
893 | /*============================================================================*/ | |
894 | /*============================================================================*/ | |
895 | ||
38b2df95 | 896 | #ifndef DRX_CFG_BASE |
1bfc9e15 | 897 | #define DRX_CFG_BASE 0 |
38b2df95 DH |
898 | #endif |
899 | ||
7ef66759 MCC |
900 | #define DRX_CFG_MPEG_OUTPUT (DRX_CFG_BASE + 0) /* MPEG TS output */ |
901 | #define DRX_CFG_PKTERR (DRX_CFG_BASE + 1) /* Packet Error */ | |
902 | #define DRX_CFG_SYMCLK_OFFS (DRX_CFG_BASE + 2) /* Symbol Clk Offset */ | |
903 | #define DRX_CFG_SMA (DRX_CFG_BASE + 3) /* Smart Antenna */ | |
904 | #define DRX_CFG_PINSAFE (DRX_CFG_BASE + 4) /* Pin safe mode */ | |
905 | #define DRX_CFG_SUBSTANDARD (DRX_CFG_BASE + 5) /* substandard */ | |
906 | #define DRX_CFG_AUD_VOLUME (DRX_CFG_BASE + 6) /* volume */ | |
907 | #define DRX_CFG_AUD_RDS (DRX_CFG_BASE + 7) /* rds */ | |
908 | #define DRX_CFG_AUD_AUTOSOUND (DRX_CFG_BASE + 8) /* ASS & ASC */ | |
909 | #define DRX_CFG_AUD_ASS_THRES (DRX_CFG_BASE + 9) /* ASS Thresholds */ | |
910 | #define DRX_CFG_AUD_DEVIATION (DRX_CFG_BASE + 10) /* Deviation */ | |
911 | #define DRX_CFG_AUD_PRESCALE (DRX_CFG_BASE + 11) /* Prescale */ | |
912 | #define DRX_CFG_AUD_MIXER (DRX_CFG_BASE + 12) /* Mixer */ | |
913 | #define DRX_CFG_AUD_AVSYNC (DRX_CFG_BASE + 13) /* AVSync */ | |
914 | #define DRX_CFG_AUD_CARRIER (DRX_CFG_BASE + 14) /* Audio carriers */ | |
915 | #define DRX_CFG_I2S_OUTPUT (DRX_CFG_BASE + 15) /* I2S output */ | |
916 | #define DRX_CFG_ATV_STANDARD (DRX_CFG_BASE + 16) /* ATV standard */ | |
917 | #define DRX_CFG_SQI_SPEED (DRX_CFG_BASE + 17) /* SQI speed */ | |
918 | #define DRX_CTRL_CFG_MAX (DRX_CFG_BASE + 18) /* never to be used */ | |
38b2df95 DH |
919 | |
920 | #define DRX_CFG_PINS_SAFE_MODE DRX_CFG_PINSAFE | |
921 | /*============================================================================*/ | |
922 | /*============================================================================*/ | |
923 | /*== CTRL related data structures ============================================*/ | |
924 | /*============================================================================*/ | |
925 | /*============================================================================*/ | |
926 | ||
b95b0c98 | 927 | /* |
b48293db MCC |
928 | * struct drxu_code_info Parameters for microcode upload and verfiy. |
929 | * | |
930 | * @mc_file: microcode file name | |
931 | * | |
932 | * Used by DRX_CTRL_LOAD_UCODE and DRX_CTRL_VERIFY_UCODE | |
933 | */ | |
1bfc9e15 | 934 | struct drxu_code_info { |
b48293db | 935 | char *mc_file; |
1bfc9e15 | 936 | }; |
38b2df95 | 937 | |
b95b0c98 | 938 | /* |
57afe2f0 | 939 | * \struct drx_mc_version_rec_t |
38b2df95 DH |
940 | * \brief Microcode version record |
941 | * Version numbers are stored in BCD format, as usual: | |
942 | * o major number = bits 31-20 (first three nibbles of MSW) | |
943 | * o minor number = bits 19-16 (fourth nibble of MSW) | |
944 | * o patch number = bits 15-0 (remaining nibbles in LSW) | |
945 | * | |
946 | * The device type indicates for which the device is meant. It is based on the | |
947 | * JTAG ID, using everything except the bond ID and the metal fix. | |
948 | * | |
949 | * Special values: | |
57afe2f0 MCC |
950 | * - mc_dev_type == 0 => any device allowed |
951 | * - mc_base_version == 0.0.0 => full microcode (mc_version is the version) | |
952 | * - mc_base_version != 0.0.0 => patch microcode, the base microcode version | |
953 | * (mc_version is the version) | |
38b2df95 DH |
954 | */ |
955 | #define AUX_VER_RECORD 0x8000 | |
956 | ||
1bfc9e15 MCC |
957 | struct drx_mc_version_rec { |
958 | u16 aux_type; /* type of aux data - 0x8000 for version record */ | |
959 | u32 mc_dev_type; /* device type, based on JTAG ID */ | |
960 | u32 mc_version; /* version of microcode */ | |
961 | u32 mc_base_version; /* in case of patch: the original microcode version */ | |
962 | }; | |
38b2df95 DH |
963 | |
964 | /*========================================*/ | |
965 | ||
b95b0c98 | 966 | /* |
57afe2f0 | 967 | * \struct drx_filter_info_t |
38b2df95 DH |
968 | * \brief Parameters for loading filter coefficients |
969 | * | |
970 | * Used by DRX_CTRL_LOAD_FILTER | |
971 | */ | |
1bfc9e15 MCC |
972 | struct drx_filter_info { |
973 | u8 *data_re; | |
b95b0c98 | 974 | /*< pointer to coefficients for RE */ |
1bfc9e15 | 975 | u8 *data_im; |
b95b0c98 | 976 | /*< pointer to coefficients for IM */ |
1bfc9e15 | 977 | u16 size_re; |
b95b0c98 | 978 | /*< size of coefficients for RE */ |
1bfc9e15 | 979 | u16 size_im; |
b95b0c98 | 980 | /*< size of coefficients for IM */ |
1bfc9e15 | 981 | }; |
38b2df95 DH |
982 | |
983 | /*========================================*/ | |
984 | ||
b95b0c98 | 985 | /* |
1bfc9e15 | 986 | * \struct struct drx_channel * \brief The set of parameters describing a single channel. |
38b2df95 DH |
987 | * |
988 | * Used by DRX_CTRL_SET_CHANNEL and DRX_CTRL_GET_CHANNEL. | |
989 | * Only certain fields need to be used for a specfic standard. | |
990 | * | |
991 | */ | |
1bfc9e15 MCC |
992 | struct drx_channel { |
993 | s32 frequency; | |
b95b0c98 | 994 | /*< frequency in kHz */ |
1bfc9e15 | 995 | enum drx_bandwidth bandwidth; |
b95b0c98 MCC |
996 | /*< bandwidth */ |
997 | enum drx_mirror mirror; /*< mirrored or not on RF */ | |
1bfc9e15 | 998 | enum drx_modulation constellation; |
b95b0c98 | 999 | /*< constellation */ |
1bfc9e15 | 1000 | enum drx_hierarchy hierarchy; |
b95b0c98 MCC |
1001 | /*< hierarchy */ |
1002 | enum drx_priority priority; /*< priority */ | |
1003 | enum drx_coderate coderate; /*< coderate */ | |
1004 | enum drx_guard guard; /*< guard interval */ | |
1005 | enum drx_fft_mode fftmode; /*< fftmode */ | |
1bfc9e15 | 1006 | enum drx_classification classification; |
b95b0c98 | 1007 | /*< classification */ |
1bfc9e15 | 1008 | u32 symbolrate; |
b95b0c98 | 1009 | /*< symbolrate in symbols/sec */ |
1bfc9e15 | 1010 | enum drx_interleave_mode interleavemode; |
b95b0c98 MCC |
1011 | /*< interleaveMode QAM */ |
1012 | enum drx_ldpc ldpc; /*< ldpc */ | |
1013 | enum drx_carrier_mode carrier; /*< carrier */ | |
1bfc9e15 | 1014 | enum drx_frame_mode framemode; |
b95b0c98 MCC |
1015 | /*< frame mode */ |
1016 | enum drx_pilot_mode pilot; /*< pilot mode */ | |
1bfc9e15 | 1017 | }; |
38b2df95 DH |
1018 | |
1019 | /*========================================*/ | |
1020 | ||
1bfc9e15 MCC |
1021 | enum drx_cfg_sqi_speed { |
1022 | DRX_SQI_SPEED_FAST = 0, | |
1023 | DRX_SQI_SPEED_MEDIUM, | |
1024 | DRX_SQI_SPEED_SLOW, | |
1025 | DRX_SQI_SPEED_UNKNOWN = DRX_UNKNOWN | |
1026 | }; | |
38b2df95 DH |
1027 | |
1028 | /*========================================*/ | |
1029 | ||
b95b0c98 | 1030 | /* |
1bfc9e15 | 1031 | * \struct struct drx_complex * A complex number. |
38b2df95 DH |
1032 | * |
1033 | * Used by DRX_CTRL_CONSTEL. | |
1034 | */ | |
1bfc9e15 MCC |
1035 | struct drx_complex { |
1036 | s16 im; | |
b95b0c98 | 1037 | /*< Imaginary part. */ |
1bfc9e15 | 1038 | s16 re; |
b95b0c98 | 1039 | /*< Real part. */ |
1bfc9e15 | 1040 | }; |
38b2df95 DH |
1041 | |
1042 | /*========================================*/ | |
1043 | ||
b95b0c98 | 1044 | /* |
1bfc9e15 | 1045 | * \struct struct drx_frequency_plan * Array element of a frequency plan. |
38b2df95 DH |
1046 | * |
1047 | * Used by DRX_CTRL_SCAN_INIT. | |
1048 | */ | |
1bfc9e15 MCC |
1049 | struct drx_frequency_plan { |
1050 | s32 first; | |
b95b0c98 | 1051 | /*< First centre frequency in this band */ |
1bfc9e15 | 1052 | s32 last; |
b95b0c98 | 1053 | /*< Last centre frequency in this band */ |
1bfc9e15 | 1054 | s32 step; |
b95b0c98 | 1055 | /*< Stepping frequency in this band */ |
1bfc9e15 | 1056 | enum drx_bandwidth bandwidth; |
b95b0c98 | 1057 | /*< Bandwidth within this frequency band */ |
1bfc9e15 | 1058 | u16 ch_number; |
b95b0c98 | 1059 | /*< First channel number in this band, or first |
1bfc9e15 MCC |
1060 | index in ch_names */ |
1061 | char **ch_names; | |
b95b0c98 | 1062 | /*< Optional list of channel names in this |
1bfc9e15 MCC |
1063 | band */ |
1064 | }; | |
38b2df95 DH |
1065 | |
1066 | /*========================================*/ | |
1067 | ||
b95b0c98 | 1068 | /* |
1bfc9e15 | 1069 | * \struct struct drx_scan_param * Parameters for channel scan. |
38b2df95 DH |
1070 | * |
1071 | * Used by DRX_CTRL_SCAN_INIT. | |
1072 | */ | |
1bfc9e15 MCC |
1073 | struct drx_scan_param { |
1074 | struct drx_frequency_plan *frequency_plan; | |
b95b0c98 MCC |
1075 | /*< Frequency plan (array)*/ |
1076 | u16 frequency_plan_size; /*< Number of bands */ | |
1077 | u32 num_tries; /*< Max channels tried */ | |
1078 | s32 skip; /*< Minimum frequency step to take | |
1bfc9e15 | 1079 | after a channel is found */ |
b95b0c98 | 1080 | void *ext_params; /*< Standard specific params */ |
1bfc9e15 | 1081 | }; |
38b2df95 DH |
1082 | |
1083 | /*========================================*/ | |
1084 | ||
b95b0c98 | 1085 | /* |
38b2df95 DH |
1086 | * \brief Scan commands. |
1087 | * Used by scanning algorithms. | |
1088 | */ | |
1bfc9e15 | 1089 | enum drx_scan_command { |
b95b0c98 MCC |
1090 | DRX_SCAN_COMMAND_INIT = 0,/*< Initialize scanning */ |
1091 | DRX_SCAN_COMMAND_NEXT, /*< Next scan */ | |
1092 | DRX_SCAN_COMMAND_STOP /*< Stop scanning */ | |
1bfc9e15 | 1093 | }; |
38b2df95 DH |
1094 | |
1095 | /*========================================*/ | |
1096 | ||
b95b0c98 | 1097 | /* |
38b2df95 DH |
1098 | * \brief Inner scan function prototype. |
1099 | */ | |
1bfc9e15 MCC |
1100 | typedef int(*drx_scan_func_t) (void *scan_context, |
1101 | enum drx_scan_command scan_command, | |
1102 | struct drx_channel *scan_channel, | |
1103 | bool *get_next_channel); | |
38b2df95 DH |
1104 | |
1105 | /*========================================*/ | |
1106 | ||
b95b0c98 | 1107 | /* |
1bfc9e15 | 1108 | * \struct struct drxtps_info * TPS information, DVB-T specific. |
38b2df95 DH |
1109 | * |
1110 | * Used by DRX_CTRL_TPS_INFO. | |
1111 | */ | |
1bfc9e15 | 1112 | struct drxtps_info { |
b95b0c98 MCC |
1113 | enum drx_fft_mode fftmode; /*< Fft mode */ |
1114 | enum drx_guard guard; /*< Guard interval */ | |
61263c75 | 1115 | enum drx_modulation constellation; |
b95b0c98 | 1116 | /*< Constellation */ |
61263c75 | 1117 | enum drx_hierarchy hierarchy; |
b95b0c98 | 1118 | /*< Hierarchy */ |
57afe2f0 | 1119 | enum drx_coderate high_coderate; |
b95b0c98 | 1120 | /*< High code rate */ |
57afe2f0 | 1121 | enum drx_coderate low_coderate; |
b95b0c98 MCC |
1122 | /*< Low cod rate */ |
1123 | enum drx_tps_frame frame; /*< Tps frame */ | |
1124 | u8 length; /*< Length */ | |
1125 | u16 cell_id; /*< Cell id */ | |
1bfc9e15 | 1126 | }; |
38b2df95 DH |
1127 | |
1128 | /*========================================*/ | |
1129 | ||
b95b0c98 | 1130 | /* |
38b2df95 DH |
1131 | * \brief Power mode of device. |
1132 | * | |
1133 | * Used by DRX_CTRL_SET_POWER_MODE. | |
1134 | */ | |
1bfc9e15 | 1135 | enum drx_power_mode { |
443f18d0 | 1136 | DRX_POWER_UP = 0, |
b95b0c98 | 1137 | /*< Generic , Power Up Mode */ |
443f18d0 | 1138 | DRX_POWER_MODE_1, |
b95b0c98 | 1139 | /*< Device specific , Power Up Mode */ |
443f18d0 | 1140 | DRX_POWER_MODE_2, |
b95b0c98 | 1141 | /*< Device specific , Power Up Mode */ |
443f18d0 | 1142 | DRX_POWER_MODE_3, |
b95b0c98 | 1143 | /*< Device specific , Power Up Mode */ |
443f18d0 | 1144 | DRX_POWER_MODE_4, |
b95b0c98 | 1145 | /*< Device specific , Power Up Mode */ |
443f18d0 | 1146 | DRX_POWER_MODE_5, |
b95b0c98 | 1147 | /*< Device specific , Power Up Mode */ |
443f18d0 | 1148 | DRX_POWER_MODE_6, |
b95b0c98 | 1149 | /*< Device specific , Power Up Mode */ |
443f18d0 | 1150 | DRX_POWER_MODE_7, |
b95b0c98 | 1151 | /*< Device specific , Power Up Mode */ |
443f18d0 | 1152 | DRX_POWER_MODE_8, |
b95b0c98 | 1153 | /*< Device specific , Power Up Mode */ |
443f18d0 MCC |
1154 | |
1155 | DRX_POWER_MODE_9, | |
b95b0c98 | 1156 | /*< Device specific , Power Down Mode */ |
443f18d0 | 1157 | DRX_POWER_MODE_10, |
b95b0c98 | 1158 | /*< Device specific , Power Down Mode */ |
443f18d0 | 1159 | DRX_POWER_MODE_11, |
b95b0c98 | 1160 | /*< Device specific , Power Down Mode */ |
443f18d0 | 1161 | DRX_POWER_MODE_12, |
b95b0c98 | 1162 | /*< Device specific , Power Down Mode */ |
443f18d0 | 1163 | DRX_POWER_MODE_13, |
b95b0c98 | 1164 | /*< Device specific , Power Down Mode */ |
443f18d0 | 1165 | DRX_POWER_MODE_14, |
b95b0c98 | 1166 | /*< Device specific , Power Down Mode */ |
443f18d0 | 1167 | DRX_POWER_MODE_15, |
b95b0c98 | 1168 | /*< Device specific , Power Down Mode */ |
443f18d0 | 1169 | DRX_POWER_MODE_16, |
b95b0c98 | 1170 | /*< Device specific , Power Down Mode */ |
443f18d0 | 1171 | DRX_POWER_DOWN = 255 |
b95b0c98 | 1172 | /*< Generic , Power Down Mode */ |
1bfc9e15 | 1173 | }; |
38b2df95 DH |
1174 | |
1175 | /*========================================*/ | |
1176 | ||
b95b0c98 | 1177 | /* |
1bfc9e15 | 1178 | * \enum enum drx_module * \brief Software module identification. |
38b2df95 DH |
1179 | * |
1180 | * Used by DRX_CTRL_VERSION. | |
1181 | */ | |
1bfc9e15 | 1182 | enum drx_module { |
443f18d0 MCC |
1183 | DRX_MODULE_DEVICE, |
1184 | DRX_MODULE_MICROCODE, | |
1185 | DRX_MODULE_DRIVERCORE, | |
1186 | DRX_MODULE_DEVICEDRIVER, | |
1187 | DRX_MODULE_DAP, | |
1188 | DRX_MODULE_BSP_I2C, | |
1189 | DRX_MODULE_BSP_TUNER, | |
1190 | DRX_MODULE_BSP_HOST, | |
1191 | DRX_MODULE_UNKNOWN | |
1bfc9e15 | 1192 | }; |
38b2df95 | 1193 | |
b95b0c98 | 1194 | /* |
1bfc9e15 | 1195 | * \enum struct drx_version * \brief Version information of one software module. |
38b2df95 DH |
1196 | * |
1197 | * Used by DRX_CTRL_VERSION. | |
1198 | */ | |
1bfc9e15 MCC |
1199 | struct drx_version { |
1200 | enum drx_module module_type; | |
b95b0c98 | 1201 | /*< Type identifier of the module */ |
57afe2f0 | 1202 | char *module_name; |
b95b0c98 MCC |
1203 | /*< Name or description of module */ |
1204 | u16 v_major; /*< Major version number */ | |
1205 | u16 v_minor; /*< Minor version number */ | |
1206 | u16 v_patch; /*< Patch version number */ | |
1207 | char *v_string; /*< Version as text string */ | |
1bfc9e15 | 1208 | }; |
38b2df95 | 1209 | |
b95b0c98 | 1210 | /* |
1bfc9e15 | 1211 | * \enum struct drx_version_list * \brief List element of NULL terminated, linked list for version information. |
38b2df95 DH |
1212 | * |
1213 | * Used by DRX_CTRL_VERSION. | |
1214 | */ | |
1bfc9e15 | 1215 | struct drx_version_list { |
b95b0c98 | 1216 | struct drx_version *version;/*< Version information */ |
1bfc9e15 | 1217 | struct drx_version_list *next; |
b95b0c98 | 1218 | /*< Next list element */ |
1bfc9e15 | 1219 | }; |
38b2df95 DH |
1220 | |
1221 | /*========================================*/ | |
1222 | ||
b95b0c98 | 1223 | /* |
38b2df95 DH |
1224 | * \brief Parameters needed to confiugure a UIO. |
1225 | * | |
1226 | * Used by DRX_CTRL_UIO_CFG. | |
1227 | */ | |
1bfc9e15 MCC |
1228 | struct drxuio_cfg { |
1229 | enum drx_uio uio; | |
b95b0c98 | 1230 | /*< UIO identifier */ |
1bfc9e15 | 1231 | enum drxuio_mode mode; |
b95b0c98 | 1232 | /*< UIO operational mode */ |
1bfc9e15 | 1233 | }; |
38b2df95 DH |
1234 | |
1235 | /*========================================*/ | |
1236 | ||
b95b0c98 | 1237 | /* |
38b2df95 DH |
1238 | * \brief Parameters needed to read from or write to a UIO. |
1239 | * | |
1240 | * Used by DRX_CTRL_UIO_READ and DRX_CTRL_UIO_WRITE. | |
1241 | */ | |
1bfc9e15 MCC |
1242 | struct drxuio_data { |
1243 | enum drx_uio uio; | |
b95b0c98 | 1244 | /*< UIO identifier */ |
73f7065b | 1245 | bool value; |
b95b0c98 | 1246 | /*< UIO value (true=1, false=0) */ |
1bfc9e15 | 1247 | }; |
38b2df95 DH |
1248 | |
1249 | /*========================================*/ | |
1250 | ||
b95b0c98 | 1251 | /* |
38b2df95 DH |
1252 | * \brief Parameters needed to configure OOB. |
1253 | * | |
1254 | * Used by DRX_CTRL_SET_OOB. | |
1255 | */ | |
1bfc9e15 | 1256 | struct drxoob { |
b95b0c98 | 1257 | s32 frequency; /*< Frequency in kHz */ |
1bfc9e15 | 1258 | enum drxoob_downstream_standard standard; |
b95b0c98 MCC |
1259 | /*< OOB standard */ |
1260 | bool spectrum_inverted; /*< If true, then spectrum | |
38b2df95 | 1261 | is inverted */ |
1bfc9e15 | 1262 | }; |
38b2df95 DH |
1263 | |
1264 | /*========================================*/ | |
1265 | ||
b95b0c98 | 1266 | /* |
38b2df95 DH |
1267 | * \brief Metrics from OOB. |
1268 | * | |
1269 | * Used by DRX_CTRL_GET_OOB. | |
1270 | */ | |
1bfc9e15 | 1271 | struct drxoob_status { |
b95b0c98 MCC |
1272 | s32 frequency; /*< Frequency in Khz */ |
1273 | enum drx_lock_status lock; /*< Lock status */ | |
1274 | u32 mer; /*< MER */ | |
1275 | s32 symbol_rate_offset; /*< Symbolrate offset in ppm */ | |
1bfc9e15 | 1276 | }; |
38b2df95 DH |
1277 | |
1278 | /*========================================*/ | |
1279 | ||
b95b0c98 | 1280 | /* |
38b2df95 DH |
1281 | * \brief Device dependent configuration data. |
1282 | * | |
1283 | * Used by DRX_CTRL_SET_CFG and DRX_CTRL_GET_CFG. | |
57afe2f0 | 1284 | * A sort of nested drx_ctrl() functionality for device specific controls. |
38b2df95 | 1285 | */ |
1bfc9e15 MCC |
1286 | struct drx_cfg { |
1287 | u32 cfg_type; | |
b95b0c98 | 1288 | /*< Function identifier */ |
57afe2f0 | 1289 | void *cfg_data; |
b95b0c98 | 1290 | /*< Function data */ |
1bfc9e15 | 1291 | }; |
38b2df95 DH |
1292 | |
1293 | /*========================================*/ | |
1294 | ||
b95b0c98 | 1295 | /* |
38b2df95 DH |
1296 | * /struct DRXMpegStartWidth_t |
1297 | * MStart width [nr MCLK cycles] for serial MPEG output. | |
1298 | */ | |
1299 | ||
1bfc9e15 | 1300 | enum drxmpeg_str_width { |
443f18d0 MCC |
1301 | DRX_MPEG_STR_WIDTH_1, |
1302 | DRX_MPEG_STR_WIDTH_8 | |
1bfc9e15 | 1303 | }; |
38b2df95 | 1304 | |
2c149601 | 1305 | /* CTRL CFG MPEG output */ |
b95b0c98 | 1306 | /* |
2c149601 | 1307 | * \struct struct drx_cfg_mpeg_output * \brief Configuration parameters for MPEG output control. |
38b2df95 DH |
1308 | * |
1309 | * Used by DRX_CFG_MPEG_OUTPUT, in combination with DRX_CTRL_SET_CFG and | |
1310 | * DRX_CTRL_GET_CFG. | |
1311 | */ | |
1312 | ||
1bfc9e15 | 1313 | struct drx_cfg_mpeg_output { |
b95b0c98 MCC |
1314 | bool enable_mpeg_output;/*< If true, enable MPEG output */ |
1315 | bool insert_rs_byte; /*< If true, insert RS byte */ | |
1316 | bool enable_parallel; /*< If true, parallel out otherwise | |
38b2df95 | 1317 | serial */ |
b95b0c98 MCC |
1318 | bool invert_data; /*< If true, invert DATA signals */ |
1319 | bool invert_err; /*< If true, invert ERR signal */ | |
1320 | bool invert_str; /*< If true, invert STR signals */ | |
1321 | bool invert_val; /*< If true, invert VAL signals */ | |
1322 | bool invert_clk; /*< If true, invert CLK signals */ | |
1323 | bool static_clk; /*< If true, static MPEG clockrate | |
38b2df95 DH |
1324 | will be used, otherwise clockrate |
1325 | will adapt to the bitrate of the | |
1326 | TS */ | |
b95b0c98 | 1327 | u32 bitrate; /*< Maximum bitrate in b/s in case |
38b2df95 | 1328 | static clockrate is selected */ |
1bfc9e15 | 1329 | enum drxmpeg_str_width width_str; |
b95b0c98 | 1330 | /*< MPEG start width */ |
1bfc9e15 | 1331 | }; |
38b2df95 | 1332 | |
38b2df95 DH |
1333 | |
1334 | /*========================================*/ | |
1335 | ||
b95b0c98 | 1336 | /* |
1bfc9e15 | 1337 | * \struct struct drxi2c_data * \brief Data for I2C via 2nd or 3rd or etc I2C port. |
38b2df95 DH |
1338 | * |
1339 | * Used by DRX_CTRL_I2C_READWRITE. | |
57afe2f0 | 1340 | * If port_nr is equal to primairy port_nr BSPI2C will be used. |
38b2df95 DH |
1341 | * |
1342 | */ | |
1bfc9e15 | 1343 | struct drxi2c_data { |
b95b0c98 | 1344 | u16 port_nr; /*< I2C port number */ |
57afe2f0 | 1345 | struct i2c_device_addr *w_dev_addr; |
b95b0c98 MCC |
1346 | /*< Write device address */ |
1347 | u16 w_count; /*< Size of write data in bytes */ | |
1348 | u8 *wData; /*< Pointer to write data */ | |
57afe2f0 | 1349 | struct i2c_device_addr *r_dev_addr; |
b95b0c98 MCC |
1350 | /*< Read device address */ |
1351 | u16 r_count; /*< Size of data to read in bytes */ | |
1352 | u8 *r_data; /*< Pointer to read buffer */ | |
1bfc9e15 | 1353 | }; |
38b2df95 DH |
1354 | |
1355 | /*========================================*/ | |
1356 | ||
b95b0c98 | 1357 | /* |
1bfc9e15 | 1358 | * \enum enum drx_aud_standard * \brief Audio standard identifier. |
38b2df95 DH |
1359 | * |
1360 | * Used by DRX_CTRL_SET_AUD. | |
1361 | */ | |
1bfc9e15 | 1362 | enum drx_aud_standard { |
b95b0c98 MCC |
1363 | DRX_AUD_STANDARD_BTSC, /*< set BTSC standard (USA) */ |
1364 | DRX_AUD_STANDARD_A2, /*< set A2-Korea FM Stereo */ | |
1365 | DRX_AUD_STANDARD_EIAJ, /*< set to Japanese FM Stereo */ | |
1366 | DRX_AUD_STANDARD_FM_STEREO,/*< set to FM-Stereo Radio */ | |
1367 | DRX_AUD_STANDARD_M_MONO, /*< for 4.5 MHz mono detected */ | |
1368 | DRX_AUD_STANDARD_D_K_MONO, /*< for 6.5 MHz mono detected */ | |
1369 | DRX_AUD_STANDARD_BG_FM, /*< set BG_FM standard */ | |
1370 | DRX_AUD_STANDARD_D_K1, /*< set D_K1 standard */ | |
1371 | DRX_AUD_STANDARD_D_K2, /*< set D_K2 standard */ | |
1372 | DRX_AUD_STANDARD_D_K3, /*< set D_K3 standard */ | |
443f18d0 | 1373 | DRX_AUD_STANDARD_BG_NICAM_FM, |
b95b0c98 | 1374 | /*< set BG_NICAM_FM standard */ |
443f18d0 | 1375 | DRX_AUD_STANDARD_L_NICAM_AM, |
b95b0c98 | 1376 | /*< set L_NICAM_AM standard */ |
443f18d0 | 1377 | DRX_AUD_STANDARD_I_NICAM_FM, |
b95b0c98 | 1378 | /*< set I_NICAM_FM standard */ |
443f18d0 | 1379 | DRX_AUD_STANDARD_D_K_NICAM_FM, |
b95b0c98 MCC |
1380 | /*< set D_K_NICAM_FM standard */ |
1381 | DRX_AUD_STANDARD_NOT_READY,/*< used to detect audio standard */ | |
443f18d0 | 1382 | DRX_AUD_STANDARD_AUTO = DRX_AUTO, |
b95b0c98 | 1383 | /*< Automatic Standard Detection */ |
443f18d0 | 1384 | DRX_AUD_STANDARD_UNKNOWN = DRX_UNKNOWN |
b95b0c98 | 1385 | /*< used as auto and for readback */ |
1bfc9e15 | 1386 | }; |
38b2df95 | 1387 | |
1bfc9e15 | 1388 | /* CTRL_AUD_GET_STATUS - struct drx_aud_status */ |
b95b0c98 | 1389 | /* |
1bfc9e15 | 1390 | * \enum enum drx_aud_nicam_status * \brief Status of NICAM carrier. |
38b2df95 | 1391 | */ |
1bfc9e15 | 1392 | enum drx_aud_nicam_status { |
443f18d0 | 1393 | DRX_AUD_NICAM_DETECTED = 0, |
b95b0c98 | 1394 | /*< NICAM carrier detected */ |
443f18d0 | 1395 | DRX_AUD_NICAM_NOT_DETECTED, |
b95b0c98 MCC |
1396 | /*< NICAM carrier not detected */ |
1397 | DRX_AUD_NICAM_BAD /*< NICAM carrier bad quality */ | |
1bfc9e15 | 1398 | }; |
38b2df95 | 1399 | |
b95b0c98 | 1400 | /* |
1bfc9e15 | 1401 | * \struct struct drx_aud_status * \brief Audio status characteristics. |
38b2df95 | 1402 | */ |
1bfc9e15 | 1403 | struct drx_aud_status { |
b95b0c98 MCC |
1404 | bool stereo; /*< stereo detection */ |
1405 | bool carrier_a; /*< carrier A detected */ | |
1406 | bool carrier_b; /*< carrier B detected */ | |
1407 | bool sap; /*< sap / bilingual detection */ | |
1408 | bool rds; /*< RDS data array present */ | |
1bfc9e15 | 1409 | enum drx_aud_nicam_status nicam_status; |
b95b0c98 MCC |
1410 | /*< status of NICAM carrier */ |
1411 | s8 fm_ident; /*< FM Identification value */ | |
1bfc9e15 | 1412 | }; |
38b2df95 DH |
1413 | |
1414 | /* CTRL_AUD_READ_RDS - DRXRDSdata_t */ | |
1415 | ||
b95b0c98 | 1416 | /* |
38b2df95 DH |
1417 | * \struct DRXRDSdata_t |
1418 | * \brief Raw RDS data array. | |
1419 | */ | |
1bfc9e15 | 1420 | struct drx_cfg_aud_rds { |
b95b0c98 MCC |
1421 | bool valid; /*< RDS data validation */ |
1422 | u16 data[18]; /*< data from one RDS data array */ | |
1bfc9e15 | 1423 | }; |
38b2df95 | 1424 | |
1bfc9e15 | 1425 | /* DRX_CFG_AUD_VOLUME - struct drx_cfg_aud_volume - set/get */ |
b95b0c98 | 1426 | /* |
38b2df95 DH |
1427 | * \enum DRXAudAVCDecayTime_t |
1428 | * \brief Automatic volume control configuration. | |
1429 | */ | |
1bfc9e15 | 1430 | enum drx_aud_avc_mode { |
b95b0c98 MCC |
1431 | DRX_AUD_AVC_OFF, /*< Automatic volume control off */ |
1432 | DRX_AUD_AVC_DECAYTIME_8S, /*< level volume in 8 seconds */ | |
1433 | DRX_AUD_AVC_DECAYTIME_4S, /*< level volume in 4 seconds */ | |
1434 | DRX_AUD_AVC_DECAYTIME_2S, /*< level volume in 2 seconds */ | |
1435 | DRX_AUD_AVC_DECAYTIME_20MS/*< level volume in 20 millisec */ | |
1bfc9e15 | 1436 | }; |
38b2df95 | 1437 | |
b95b0c98 | 1438 | /* |
38b2df95 DH |
1439 | * /enum DRXAudMaxAVCGain_t |
1440 | * /brief Automatic volume control max gain in audio baseband. | |
1441 | */ | |
1bfc9e15 | 1442 | enum drx_aud_avc_max_gain { |
b95b0c98 MCC |
1443 | DRX_AUD_AVC_MAX_GAIN_0DB, /*< maximum AVC gain 0 dB */ |
1444 | DRX_AUD_AVC_MAX_GAIN_6DB, /*< maximum AVC gain 6 dB */ | |
1445 | DRX_AUD_AVC_MAX_GAIN_12DB /*< maximum AVC gain 12 dB */ | |
1bfc9e15 | 1446 | }; |
38b2df95 | 1447 | |
b95b0c98 | 1448 | /* |
38b2df95 DH |
1449 | * /enum DRXAudMaxAVCAtten_t |
1450 | * /brief Automatic volume control max attenuation in audio baseband. | |
1451 | */ | |
1bfc9e15 | 1452 | enum drx_aud_avc_max_atten { |
443f18d0 | 1453 | DRX_AUD_AVC_MAX_ATTEN_12DB, |
b95b0c98 | 1454 | /*< maximum AVC attenuation 12 dB */ |
443f18d0 | 1455 | DRX_AUD_AVC_MAX_ATTEN_18DB, |
b95b0c98 MCC |
1456 | /*< maximum AVC attenuation 18 dB */ |
1457 | DRX_AUD_AVC_MAX_ATTEN_24DB/*< maximum AVC attenuation 24 dB */ | |
1bfc9e15 | 1458 | }; |
b95b0c98 | 1459 | /* |
1bfc9e15 | 1460 | * \struct struct drx_cfg_aud_volume * \brief Audio volume configuration. |
38b2df95 | 1461 | */ |
1bfc9e15 | 1462 | struct drx_cfg_aud_volume { |
b95b0c98 MCC |
1463 | bool mute; /*< mute overrides volume setting */ |
1464 | s16 volume; /*< volume, range -114 to 12 dB */ | |
1465 | enum drx_aud_avc_mode avc_mode; /*< AVC auto volume control mode */ | |
1466 | u16 avc_ref_level; /*< AVC reference level */ | |
1bfc9e15 | 1467 | enum drx_aud_avc_max_gain avc_max_gain; |
b95b0c98 | 1468 | /*< AVC max gain selection */ |
1bfc9e15 | 1469 | enum drx_aud_avc_max_atten avc_max_atten; |
b95b0c98 MCC |
1470 | /*< AVC max attenuation selection */ |
1471 | s16 strength_left; /*< quasi-peak, left speaker */ | |
1472 | s16 strength_right; /*< quasi-peak, right speaker */ | |
1bfc9e15 | 1473 | }; |
38b2df95 | 1474 | |
1bfc9e15 | 1475 | /* DRX_CFG_I2S_OUTPUT - struct drx_cfg_i2s_output - set/get */ |
b95b0c98 | 1476 | /* |
1bfc9e15 | 1477 | * \enum enum drxi2s_mode * \brief I2S output mode. |
38b2df95 | 1478 | */ |
1bfc9e15 | 1479 | enum drxi2s_mode { |
b95b0c98 MCC |
1480 | DRX_I2S_MODE_MASTER, /*< I2S is in master mode */ |
1481 | DRX_I2S_MODE_SLAVE /*< I2S is in slave mode */ | |
1bfc9e15 | 1482 | }; |
38b2df95 | 1483 | |
b95b0c98 | 1484 | /* |
1bfc9e15 | 1485 | * \enum enum drxi2s_word_length * \brief Width of I2S data. |
38b2df95 | 1486 | */ |
1bfc9e15 | 1487 | enum drxi2s_word_length { |
b95b0c98 MCC |
1488 | DRX_I2S_WORDLENGTH_32 = 0,/*< I2S data is 32 bit wide */ |
1489 | DRX_I2S_WORDLENGTH_16 = 1 /*< I2S data is 16 bit wide */ | |
1bfc9e15 | 1490 | }; |
38b2df95 | 1491 | |
b95b0c98 | 1492 | /* |
1bfc9e15 | 1493 | * \enum enum drxi2s_format * \brief Data wordstrobe alignment for I2S. |
38b2df95 | 1494 | */ |
1bfc9e15 | 1495 | enum drxi2s_format { |
443f18d0 | 1496 | DRX_I2S_FORMAT_WS_WITH_DATA, |
b95b0c98 | 1497 | /*< I2S data and wordstrobe are aligned */ |
443f18d0 | 1498 | DRX_I2S_FORMAT_WS_ADVANCED |
b95b0c98 | 1499 | /*< I2S data one cycle after wordstrobe */ |
1bfc9e15 | 1500 | }; |
38b2df95 | 1501 | |
b95b0c98 | 1502 | /* |
1bfc9e15 | 1503 | * \enum enum drxi2s_polarity * \brief Polarity of I2S data. |
38b2df95 | 1504 | */ |
1bfc9e15 | 1505 | enum drxi2s_polarity { |
b95b0c98 MCC |
1506 | DRX_I2S_POLARITY_RIGHT,/*< wordstrobe - right high, left low */ |
1507 | DRX_I2S_POLARITY_LEFT /*< wordstrobe - right low, left high */ | |
1bfc9e15 | 1508 | }; |
38b2df95 | 1509 | |
b95b0c98 | 1510 | /* |
1bfc9e15 | 1511 | * \struct struct drx_cfg_i2s_output * \brief I2S output configuration. |
38b2df95 | 1512 | */ |
1bfc9e15 | 1513 | struct drx_cfg_i2s_output { |
b95b0c98 MCC |
1514 | bool output_enable; /*< I2S output enable */ |
1515 | u32 frequency; /*< range from 8000-48000 Hz */ | |
1516 | enum drxi2s_mode mode; /*< I2S mode, master or slave */ | |
1bfc9e15 | 1517 | enum drxi2s_word_length word_length; |
b95b0c98 MCC |
1518 | /*< I2S wordlength, 16 or 32 bits */ |
1519 | enum drxi2s_polarity polarity;/*< I2S wordstrobe polarity */ | |
1520 | enum drxi2s_format format; /*< I2S wordstrobe delay to data */ | |
1bfc9e15 | 1521 | }; |
38b2df95 DH |
1522 | |
1523 | /* ------------------------------expert interface-----------------------------*/ | |
b95b0c98 | 1524 | /* |
1bfc9e15 | 1525 | * /enum enum drx_aud_fm_deemphasis * setting for FM-Deemphasis in audio demodulator. |
38b2df95 DH |
1526 | * |
1527 | */ | |
1bfc9e15 | 1528 | enum drx_aud_fm_deemphasis { |
443f18d0 MCC |
1529 | DRX_AUD_FM_DEEMPH_50US, |
1530 | DRX_AUD_FM_DEEMPH_75US, | |
1531 | DRX_AUD_FM_DEEMPH_OFF | |
1bfc9e15 | 1532 | }; |
38b2df95 | 1533 | |
b95b0c98 | 1534 | /* |
38b2df95 DH |
1535 | * /enum DRXAudDeviation_t |
1536 | * setting for deviation mode in audio demodulator. | |
1537 | * | |
1538 | */ | |
1bfc9e15 | 1539 | enum drx_cfg_aud_deviation { |
443f18d0 MCC |
1540 | DRX_AUD_DEVIATION_NORMAL, |
1541 | DRX_AUD_DEVIATION_HIGH | |
1bfc9e15 | 1542 | }; |
38b2df95 | 1543 | |
b95b0c98 | 1544 | /* |
1bfc9e15 | 1545 | * /enum enum drx_no_carrier_option * setting for carrier, mute/noise. |
38b2df95 DH |
1546 | * |
1547 | */ | |
1bfc9e15 | 1548 | enum drx_no_carrier_option { |
443f18d0 MCC |
1549 | DRX_NO_CARRIER_MUTE, |
1550 | DRX_NO_CARRIER_NOISE | |
1bfc9e15 | 1551 | }; |
38b2df95 | 1552 | |
b95b0c98 | 1553 | /* |
38b2df95 DH |
1554 | * \enum DRXAudAutoSound_t |
1555 | * \brief Automatic Sound | |
1556 | */ | |
1bfc9e15 | 1557 | enum drx_cfg_aud_auto_sound { |
443f18d0 MCC |
1558 | DRX_AUD_AUTO_SOUND_OFF = 0, |
1559 | DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON, | |
1560 | DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF | |
1bfc9e15 | 1561 | }; |
38b2df95 | 1562 | |
b95b0c98 | 1563 | /* |
38b2df95 DH |
1564 | * \enum DRXAudASSThres_t |
1565 | * \brief Automatic Sound Select Thresholds | |
1566 | */ | |
1bfc9e15 | 1567 | struct drx_cfg_aud_ass_thres { |
43a431e4 MCC |
1568 | u16 a2; /* A2 Threshold for ASS configuration */ |
1569 | u16 btsc; /* BTSC Threshold for ASS configuration */ | |
1570 | u16 nicam; /* Nicam Threshold for ASS configuration */ | |
1bfc9e15 | 1571 | }; |
38b2df95 | 1572 | |
b95b0c98 | 1573 | /* |
1bfc9e15 | 1574 | * \struct struct drx_aud_carrier * \brief Carrier detection related parameters |
38b2df95 | 1575 | */ |
1bfc9e15 | 1576 | struct drx_aud_carrier { |
43a431e4 | 1577 | u16 thres; /* carrier detetcion threshold for primary carrier (A) */ |
1bfc9e15 | 1578 | enum drx_no_carrier_option opt; /* Mute or noise at no carrier detection (A) */ |
73f7065b MCC |
1579 | s32 shift; /* DC level of incoming signal (A) */ |
1580 | s32 dco; /* frequency adjustment (A) */ | |
1bfc9e15 | 1581 | }; |
38b2df95 | 1582 | |
b95b0c98 | 1583 | /* |
1bfc9e15 | 1584 | * \struct struct drx_cfg_aud_carriers * \brief combining carrier A & B to one struct |
38b2df95 | 1585 | */ |
1bfc9e15 MCC |
1586 | struct drx_cfg_aud_carriers { |
1587 | struct drx_aud_carrier a; | |
1588 | struct drx_aud_carrier b; | |
1589 | }; | |
38b2df95 | 1590 | |
b95b0c98 | 1591 | /* |
1bfc9e15 | 1592 | * /enum enum drx_aud_i2s_src * Selection of audio source |
38b2df95 | 1593 | */ |
1bfc9e15 | 1594 | enum drx_aud_i2s_src { |
443f18d0 MCC |
1595 | DRX_AUD_SRC_MONO, |
1596 | DRX_AUD_SRC_STEREO_OR_AB, | |
1597 | DRX_AUD_SRC_STEREO_OR_A, | |
1bfc9e15 | 1598 | DRX_AUD_SRC_STEREO_OR_B}; |
38b2df95 | 1599 | |
b95b0c98 | 1600 | /* |
1bfc9e15 | 1601 | * \enum enum drx_aud_i2s_matrix * \brief Used for selecting I2S output. |
38b2df95 | 1602 | */ |
1bfc9e15 | 1603 | enum drx_aud_i2s_matrix { |
443f18d0 | 1604 | DRX_AUD_I2S_MATRIX_A_MONO, |
b95b0c98 | 1605 | /*< A sound only, stereo or mono */ |
443f18d0 | 1606 | DRX_AUD_I2S_MATRIX_B_MONO, |
b95b0c98 | 1607 | /*< B sound only, stereo or mono */ |
443f18d0 | 1608 | DRX_AUD_I2S_MATRIX_STEREO, |
b95b0c98 MCC |
1609 | /*< A+B sound, transparant */ |
1610 | DRX_AUD_I2S_MATRIX_MONO /*< A+B mixed to mono sum, (L+R)/2 */}; | |
38b2df95 | 1611 | |
b95b0c98 | 1612 | /* |
1bfc9e15 | 1613 | * /enum enum drx_aud_fm_matrix * setting for FM-Matrix in audio demodulator. |
38b2df95 DH |
1614 | * |
1615 | */ | |
1bfc9e15 | 1616 | enum drx_aud_fm_matrix { |
443f18d0 MCC |
1617 | DRX_AUD_FM_MATRIX_NO_MATRIX, |
1618 | DRX_AUD_FM_MATRIX_GERMAN, | |
1619 | DRX_AUD_FM_MATRIX_KOREAN, | |
1620 | DRX_AUD_FM_MATRIX_SOUND_A, | |
1bfc9e15 | 1621 | DRX_AUD_FM_MATRIX_SOUND_B}; |
38b2df95 | 1622 | |
b95b0c98 | 1623 | /* |
38b2df95 DH |
1624 | * \struct DRXAudMatrices_t |
1625 | * \brief Mixer settings | |
1626 | */ | |
1bfc9e15 MCC |
1627 | struct drx_cfg_aud_mixer { |
1628 | enum drx_aud_i2s_src source_i2s; | |
1629 | enum drx_aud_i2s_matrix matrix_i2s; | |
1630 | enum drx_aud_fm_matrix matrix_fm; | |
1631 | }; | |
38b2df95 | 1632 | |
b95b0c98 | 1633 | /* |
38b2df95 DH |
1634 | * \enum DRXI2SVidSync_t |
1635 | * \brief Audio/video synchronization, interacts with I2S mode. | |
1636 | * AUTO_1 and AUTO_2 are for automatic video standard detection with preference | |
1637 | * for NTSC or Monochrome, because the frequencies are too close (59.94 & 60 Hz) | |
1638 | */ | |
1bfc9e15 | 1639 | enum drx_cfg_aud_av_sync { |
b95b0c98 | 1640 | DRX_AUD_AVSYNC_OFF,/*< audio/video synchronization is off */ |
443f18d0 | 1641 | DRX_AUD_AVSYNC_NTSC, |
b95b0c98 | 1642 | /*< it is an NTSC system */ |
443f18d0 | 1643 | DRX_AUD_AVSYNC_MONOCHROME, |
b95b0c98 | 1644 | /*< it is a MONOCHROME system */ |
443f18d0 | 1645 | DRX_AUD_AVSYNC_PAL_SECAM |
b95b0c98 | 1646 | /*< it is a PAL/SECAM system */}; |
38b2df95 | 1647 | |
b95b0c98 | 1648 | /* |
1bfc9e15 | 1649 | * \struct struct drx_cfg_aud_prescale * \brief Prescalers |
38b2df95 | 1650 | */ |
1bfc9e15 MCC |
1651 | struct drx_cfg_aud_prescale { |
1652 | u16 fm_deviation; | |
1653 | s16 nicam_gain; | |
1654 | }; | |
38b2df95 | 1655 | |
b95b0c98 | 1656 | /* |
1bfc9e15 | 1657 | * \struct struct drx_aud_beep * \brief Beep |
38b2df95 | 1658 | */ |
1bfc9e15 MCC |
1659 | struct drx_aud_beep { |
1660 | s16 volume; /* dB */ | |
1661 | u16 frequency; /* Hz */ | |
1662 | bool mute; | |
1663 | }; | |
38b2df95 | 1664 | |
b95b0c98 | 1665 | /* |
1bfc9e15 | 1666 | * \enum enum drx_aud_btsc_detect * \brief BTSC detetcion mode |
38b2df95 | 1667 | */ |
1bfc9e15 | 1668 | enum drx_aud_btsc_detect { |
443f18d0 | 1669 | DRX_BTSC_STEREO, |
1bfc9e15 MCC |
1670 | DRX_BTSC_MONO_AND_SAP}; |
1671 | ||
b95b0c98 | 1672 | /* |
1bfc9e15 MCC |
1673 | * \struct struct drx_aud_data * \brief Audio data structure |
1674 | */ | |
1675 | struct drx_aud_data { | |
1676 | /* audio storage */ | |
1677 | bool audio_is_active; | |
1678 | enum drx_aud_standard audio_standard; | |
1679 | struct drx_cfg_i2s_output i2sdata; | |
1680 | struct drx_cfg_aud_volume volume; | |
1681 | enum drx_cfg_aud_auto_sound auto_sound; | |
1682 | struct drx_cfg_aud_ass_thres ass_thresholds; | |
1683 | struct drx_cfg_aud_carriers carriers; | |
1684 | struct drx_cfg_aud_mixer mixer; | |
1685 | enum drx_cfg_aud_deviation deviation; | |
1686 | enum drx_cfg_aud_av_sync av_sync; | |
1687 | struct drx_cfg_aud_prescale prescale; | |
1688 | enum drx_aud_fm_deemphasis deemph; | |
1689 | enum drx_aud_btsc_detect btsc_detect; | |
1690 | /* rds */ | |
1691 | u16 rds_data_counter; | |
1692 | bool rds_data_present; | |
1693 | }; | |
1694 | ||
b95b0c98 | 1695 | /* |
1bfc9e15 MCC |
1696 | * \enum enum drx_qam_lock_range * \brief QAM lock range mode |
1697 | */ | |
1698 | enum drx_qam_lock_range { | |
443f18d0 | 1699 | DRX_QAM_LOCKRANGE_NORMAL, |
1bfc9e15 | 1700 | DRX_QAM_LOCKRANGE_EXTENDED}; |
38b2df95 DH |
1701 | |
1702 | /*============================================================================*/ | |
1703 | /*============================================================================*/ | |
1704 | /*== Data access structures ==================================================*/ | |
1705 | /*============================================================================*/ | |
1706 | /*============================================================================*/ | |
1707 | ||
1708 | /* Address on device */ | |
57afe2f0 | 1709 | typedef u32 dr_xaddr_t, *pdr_xaddr_t; |
38b2df95 DH |
1710 | |
1711 | /* Protocol specific flags */ | |
57afe2f0 | 1712 | typedef u32 dr_xflags_t, *pdr_xflags_t; |
38b2df95 DH |
1713 | |
1714 | /* Write block of data to device */ | |
57afe2f0 | 1715 | typedef int(*drx_write_block_func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ |
1bfc9e15 | 1716 | u32 addr, /* address of register/memory */ |
43a431e4 MCC |
1717 | u16 datasize, /* size of data in bytes */ |
1718 | u8 *data, /* data to send */ | |
1bfc9e15 | 1719 | u32 flags); |
38b2df95 DH |
1720 | |
1721 | /* Read block of data from device */ | |
57afe2f0 | 1722 | typedef int(*drx_read_block_func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ |
1bfc9e15 | 1723 | u32 addr, /* address of register/memory */ |
43a431e4 MCC |
1724 | u16 datasize, /* size of data in bytes */ |
1725 | u8 *data, /* receive buffer */ | |
1bfc9e15 | 1726 | u32 flags); |
38b2df95 DH |
1727 | |
1728 | /* Write 8-bits value to device */ | |
57afe2f0 | 1729 | typedef int(*drx_write_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ |
1bfc9e15 | 1730 | u32 addr, /* address of register/memory */ |
43a431e4 | 1731 | u8 data, /* data to send */ |
1bfc9e15 | 1732 | u32 flags); |
38b2df95 DH |
1733 | |
1734 | /* Read 8-bits value to device */ | |
57afe2f0 | 1735 | typedef int(*drx_read_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ |
1bfc9e15 | 1736 | u32 addr, /* address of register/memory */ |
43a431e4 | 1737 | u8 *data, /* receive buffer */ |
1bfc9e15 | 1738 | u32 flags); |
38b2df95 DH |
1739 | |
1740 | /* Read modify write 8-bits value to device */ | |
57afe2f0 | 1741 | typedef int(*drx_read_modify_write_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ |
1bfc9e15 MCC |
1742 | u32 waddr, /* write address of register */ |
1743 | u32 raddr, /* read address of register */ | |
43a431e4 MCC |
1744 | u8 wdata, /* data to write */ |
1745 | u8 *rdata); /* data to read */ | |
38b2df95 DH |
1746 | |
1747 | /* Write 16-bits value to device */ | |
57afe2f0 | 1748 | typedef int(*drx_write_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ |
1bfc9e15 | 1749 | u32 addr, /* address of register/memory */ |
43a431e4 | 1750 | u16 data, /* data to send */ |
1bfc9e15 | 1751 | u32 flags); |
38b2df95 DH |
1752 | |
1753 | /* Read 16-bits value to device */ | |
57afe2f0 | 1754 | typedef int(*drx_read_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ |
1bfc9e15 | 1755 | u32 addr, /* address of register/memory */ |
43a431e4 | 1756 | u16 *data, /* receive buffer */ |
1bfc9e15 | 1757 | u32 flags); |
38b2df95 DH |
1758 | |
1759 | /* Read modify write 16-bits value to device */ | |
57afe2f0 | 1760 | typedef int(*drx_read_modify_write_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ |
1bfc9e15 MCC |
1761 | u32 waddr, /* write address of register */ |
1762 | u32 raddr, /* read address of register */ | |
43a431e4 MCC |
1763 | u16 wdata, /* data to write */ |
1764 | u16 *rdata); /* data to read */ | |
38b2df95 DH |
1765 | |
1766 | /* Write 32-bits value to device */ | |
57afe2f0 | 1767 | typedef int(*drx_write_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ |
1bfc9e15 | 1768 | u32 addr, /* address of register/memory */ |
43a431e4 | 1769 | u32 data, /* data to send */ |
1bfc9e15 | 1770 | u32 flags); |
38b2df95 DH |
1771 | |
1772 | /* Read 32-bits value to device */ | |
57afe2f0 | 1773 | typedef int(*drx_read_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ |
1bfc9e15 | 1774 | u32 addr, /* address of register/memory */ |
43a431e4 | 1775 | u32 *data, /* receive buffer */ |
1bfc9e15 | 1776 | u32 flags); |
38b2df95 DH |
1777 | |
1778 | /* Read modify write 32-bits value to device */ | |
57afe2f0 | 1779 | typedef int(*drx_read_modify_write_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */ |
1bfc9e15 MCC |
1780 | u32 waddr, /* write address of register */ |
1781 | u32 raddr, /* read address of register */ | |
43a431e4 MCC |
1782 | u32 wdata, /* data to write */ |
1783 | u32 *rdata); /* data to read */ | |
38b2df95 | 1784 | |
b95b0c98 | 1785 | /* |
1bfc9e15 MCC |
1786 | * \struct struct drx_access_func * \brief Interface to an access protocol. |
1787 | */ | |
1788 | struct drx_access_func { | |
1bfc9e15 MCC |
1789 | drx_write_block_func_t write_block_func; |
1790 | drx_read_block_func_t read_block_func; | |
1791 | drx_write_reg8func_t write_reg8func; | |
1792 | drx_read_reg8func_t read_reg8func; | |
1793 | drx_read_modify_write_reg8func_t read_modify_write_reg8func; | |
1794 | drx_write_reg16func_t write_reg16func; | |
1795 | drx_read_reg16func_t read_reg16func; | |
1796 | drx_read_modify_write_reg16func_t read_modify_write_reg16func; | |
1797 | drx_write_reg32func_t write_reg32func; | |
1798 | drx_read_reg32func_t read_reg32func; | |
1799 | drx_read_modify_write_reg32func_t read_modify_write_reg32func; | |
1800 | }; | |
38b2df95 DH |
1801 | |
1802 | /* Register address and data for register dump function */ | |
1bfc9e15 MCC |
1803 | struct drx_reg_dump { |
1804 | u32 address; | |
1805 | u32 data; | |
1806 | }; | |
38b2df95 DH |
1807 | |
1808 | /*============================================================================*/ | |
1809 | /*============================================================================*/ | |
1810 | /*== Demod instance data structures ==========================================*/ | |
1811 | /*============================================================================*/ | |
1812 | /*============================================================================*/ | |
1813 | ||
b95b0c98 | 1814 | /* |
1bfc9e15 | 1815 | * \struct struct drx_common_attr * \brief Set of common attributes, shared by all DRX devices. |
38b2df95 | 1816 | */ |
1bfc9e15 | 1817 | struct drx_common_attr { |
443f18d0 | 1818 | /* Microcode (firmware) attributes */ |
b95b0c98 | 1819 | char *microcode_file; /*< microcode filename */ |
57afe2f0 | 1820 | bool verify_microcode; |
b95b0c98 | 1821 | /*< Use microcode verify or not. */ |
1bfc9e15 | 1822 | struct drx_mc_version_rec mcversion; |
b95b0c98 | 1823 | /*< Version record of microcode from file */ |
443f18d0 MCC |
1824 | |
1825 | /* Clocks and tuner attributes */ | |
57afe2f0 | 1826 | s32 intermediate_freq; |
b95b0c98 | 1827 | /*< IF,if tuner instance not used. (kHz)*/ |
57afe2f0 | 1828 | s32 sys_clock_freq; |
b95b0c98 | 1829 | /*< Systemclock frequency. (kHz) */ |
57afe2f0 | 1830 | s32 osc_clock_freq; |
b95b0c98 | 1831 | /*< Oscillator clock frequency. (kHz) */ |
57afe2f0 | 1832 | s16 osc_clock_deviation; |
b95b0c98 | 1833 | /*< Oscillator clock deviation. (ppm) */ |
57afe2f0 | 1834 | bool mirror_freq_spect; |
b95b0c98 | 1835 | /*< Mirror IF frequency spectrum or not.*/ |
443f18d0 MCC |
1836 | |
1837 | /* Initial MPEG output attributes */ | |
1bfc9e15 | 1838 | struct drx_cfg_mpeg_output mpeg_cfg; |
b95b0c98 | 1839 | /*< MPEG configuration */ |
443f18d0 | 1840 | |
b95b0c98 | 1841 | bool is_opened; /*< if true instance is already opened. */ |
443f18d0 MCC |
1842 | |
1843 | /* Channel scan */ | |
1bfc9e15 | 1844 | struct drx_scan_param *scan_param; |
b95b0c98 | 1845 | /*< scan parameters */ |
57afe2f0 | 1846 | u16 scan_freq_plan_index; |
b95b0c98 | 1847 | /*< next index in freq plan */ |
57afe2f0 | 1848 | s32 scan_next_frequency; |
b95b0c98 MCC |
1849 | /*< next freq to scan */ |
1850 | bool scan_ready; /*< scan ready flag */ | |
1851 | u32 scan_max_channels;/*< number of channels in freqplan */ | |
e33f2193 | 1852 | u32 scan_channels_scanned; |
b95b0c98 | 1853 | /*< number of channels scanned */ |
443f18d0 | 1854 | /* Channel scan - inner loop: demod related */ |
57afe2f0 | 1855 | drx_scan_func_t scan_function; |
b95b0c98 | 1856 | /*< function to check channel */ |
443f18d0 | 1857 | /* Channel scan - inner loop: SYSObj related */ |
b95b0c98 | 1858 | void *scan_context; /*< Context Pointer of SYSObj */ |
443f18d0 | 1859 | /* Channel scan - parameters for default DTV scan function in core driver */ |
57afe2f0 | 1860 | u16 scan_demod_lock_timeout; |
b95b0c98 | 1861 | /*< millisecs to wait for lock */ |
1bfc9e15 | 1862 | enum drx_lock_status scan_desired_lock; |
b95b0c98 | 1863 | /*< lock requirement for channel found */ |
57afe2f0 | 1864 | /* scan_active can be used by SetChannel to decide how to program the tuner, |
443f18d0 | 1865 | fast or slow (but stable). Usually fast during scan. */ |
b95b0c98 | 1866 | bool scan_active; /*< true when scan routines are active */ |
443f18d0 MCC |
1867 | |
1868 | /* Power management */ | |
1bfc9e15 | 1869 | enum drx_power_mode current_power_mode; |
b95b0c98 | 1870 | /*< current power management mode */ |
443f18d0 MCC |
1871 | |
1872 | /* Tuner */ | |
b95b0c98 | 1873 | u8 tuner_port_nr; /*< nr of I2C port to wich tuner is */ |
57afe2f0 | 1874 | s32 tuner_min_freq_rf; |
b95b0c98 | 1875 | /*< minimum RF input frequency, in kHz */ |
57afe2f0 | 1876 | s32 tuner_max_freq_rf; |
b95b0c98 MCC |
1877 | /*< maximum RF input frequency, in kHz */ |
1878 | bool tuner_rf_agc_pol; /*< if true invert RF AGC polarity */ | |
1879 | bool tuner_if_agc_pol; /*< if true invert IF AGC polarity */ | |
1880 | bool tuner_slow_mode; /*< if true invert IF AGC polarity */ | |
443f18d0 | 1881 | |
1bfc9e15 | 1882 | struct drx_channel current_channel; |
b95b0c98 | 1883 | /*< current channel parameters */ |
57afe2f0 | 1884 | enum drx_standard current_standard; |
b95b0c98 | 1885 | /*< current standard selection */ |
57afe2f0 | 1886 | enum drx_standard prev_standard; |
b95b0c98 | 1887 | /*< previous standard selection */ |
57afe2f0 | 1888 | enum drx_standard di_cache_standard; |
b95b0c98 MCC |
1889 | /*< standard in DI cache if available */ |
1890 | bool use_bootloader; /*< use bootloader in open */ | |
1891 | u32 capabilities; /*< capabilities flags */ | |
1892 | u32 product_id; /*< product ID inc. metal fix number */}; | |
38b2df95 DH |
1893 | |
1894 | /* | |
1895 | * Generic functions for DRX devices. | |
1896 | */ | |
38b2df95 | 1897 | |
1bfc9e15 MCC |
1898 | struct drx_demod_instance; |
1899 | ||
b95b0c98 | 1900 | /* |
1bfc9e15 | 1901 | * \struct struct drx_demod_instance * \brief Top structure of demodulator instance. |
38b2df95 | 1902 | */ |
b48293db | 1903 | struct drx_demod_instance { |
b95b0c98 | 1904 | /*< data access protocol functions */ |
b48293db | 1905 | struct i2c_device_addr *my_i2c_dev_addr; |
b95b0c98 | 1906 | /*< i2c address and device identifier */ |
b48293db | 1907 | struct drx_common_attr *my_common_attr; |
b95b0c98 MCC |
1908 | /*< common DRX attributes */ |
1909 | void *my_ext_attr; /*< device specific attributes */ | |
b48293db MCC |
1910 | /* generic demodulator data */ |
1911 | ||
1912 | struct i2c_adapter *i2c; | |
1913 | const struct firmware *firmware; | |
1914 | }; | |
38b2df95 DH |
1915 | |
1916 | /*------------------------------------------------------------------------- | |
1917 | MACROS | |
1918 | Conversion from enum values to human readable form. | |
1919 | -------------------------------------------------------------------------*/ | |
1920 | ||
1921 | /* standard */ | |
1922 | ||
1923 | #define DRX_STR_STANDARD(x) ( \ | |
2f1f7333 MCC |
1924 | (x == DRX_STANDARD_DVBT) ? "DVB-T" : \ |
1925 | (x == DRX_STANDARD_8VSB) ? "8VSB" : \ | |
1926 | (x == DRX_STANDARD_NTSC) ? "NTSC" : \ | |
1927 | (x == DRX_STANDARD_PAL_SECAM_BG) ? "PAL/SECAM B/G" : \ | |
1928 | (x == DRX_STANDARD_PAL_SECAM_DK) ? "PAL/SECAM D/K" : \ | |
1929 | (x == DRX_STANDARD_PAL_SECAM_I) ? "PAL/SECAM I" : \ | |
1930 | (x == DRX_STANDARD_PAL_SECAM_L) ? "PAL/SECAM L" : \ | |
1931 | (x == DRX_STANDARD_PAL_SECAM_LP) ? "PAL/SECAM LP" : \ | |
1932 | (x == DRX_STANDARD_ITU_A) ? "ITU-A" : \ | |
1933 | (x == DRX_STANDARD_ITU_B) ? "ITU-B" : \ | |
1934 | (x == DRX_STANDARD_ITU_C) ? "ITU-C" : \ | |
1935 | (x == DRX_STANDARD_ITU_D) ? "ITU-D" : \ | |
1936 | (x == DRX_STANDARD_FM) ? "FM" : \ | |
1937 | (x == DRX_STANDARD_DTMB) ? "DTMB" : \ | |
1938 | (x == DRX_STANDARD_AUTO) ? "Auto" : \ | |
1939 | (x == DRX_STANDARD_UNKNOWN) ? "Unknown" : \ | |
1940 | "(Invalid)") | |
38b2df95 DH |
1941 | |
1942 | /* channel */ | |
1943 | ||
1944 | #define DRX_STR_BANDWIDTH(x) ( \ | |
2f1f7333 MCC |
1945 | (x == DRX_BANDWIDTH_8MHZ) ? "8 MHz" : \ |
1946 | (x == DRX_BANDWIDTH_7MHZ) ? "7 MHz" : \ | |
1947 | (x == DRX_BANDWIDTH_6MHZ) ? "6 MHz" : \ | |
1948 | (x == DRX_BANDWIDTH_AUTO) ? "Auto" : \ | |
1949 | (x == DRX_BANDWIDTH_UNKNOWN) ? "Unknown" : \ | |
1950 | "(Invalid)") | |
38b2df95 | 1951 | #define DRX_STR_FFTMODE(x) ( \ |
2f1f7333 MCC |
1952 | (x == DRX_FFTMODE_2K) ? "2k" : \ |
1953 | (x == DRX_FFTMODE_4K) ? "4k" : \ | |
1954 | (x == DRX_FFTMODE_8K) ? "8k" : \ | |
1955 | (x == DRX_FFTMODE_AUTO) ? "Auto" : \ | |
1956 | (x == DRX_FFTMODE_UNKNOWN) ? "Unknown" : \ | |
1957 | "(Invalid)") | |
38b2df95 | 1958 | #define DRX_STR_GUARD(x) ( \ |
2f1f7333 MCC |
1959 | (x == DRX_GUARD_1DIV32) ? "1/32nd" : \ |
1960 | (x == DRX_GUARD_1DIV16) ? "1/16th" : \ | |
1961 | (x == DRX_GUARD_1DIV8) ? "1/8th" : \ | |
1962 | (x == DRX_GUARD_1DIV4) ? "1/4th" : \ | |
1963 | (x == DRX_GUARD_AUTO) ? "Auto" : \ | |
1964 | (x == DRX_GUARD_UNKNOWN) ? "Unknown" : \ | |
1965 | "(Invalid)") | |
38b2df95 | 1966 | #define DRX_STR_CONSTELLATION(x) ( \ |
2f1f7333 MCC |
1967 | (x == DRX_CONSTELLATION_BPSK) ? "BPSK" : \ |
1968 | (x == DRX_CONSTELLATION_QPSK) ? "QPSK" : \ | |
1969 | (x == DRX_CONSTELLATION_PSK8) ? "PSK8" : \ | |
1970 | (x == DRX_CONSTELLATION_QAM16) ? "QAM16" : \ | |
1971 | (x == DRX_CONSTELLATION_QAM32) ? "QAM32" : \ | |
1972 | (x == DRX_CONSTELLATION_QAM64) ? "QAM64" : \ | |
1973 | (x == DRX_CONSTELLATION_QAM128) ? "QAM128" : \ | |
1974 | (x == DRX_CONSTELLATION_QAM256) ? "QAM256" : \ | |
1975 | (x == DRX_CONSTELLATION_QAM512) ? "QAM512" : \ | |
1976 | (x == DRX_CONSTELLATION_QAM1024) ? "QAM1024" : \ | |
1977 | (x == DRX_CONSTELLATION_QPSK_NR) ? "QPSK_NR" : \ | |
1978 | (x == DRX_CONSTELLATION_AUTO) ? "Auto" : \ | |
1979 | (x == DRX_CONSTELLATION_UNKNOWN) ? "Unknown" : \ | |
1980 | "(Invalid)") | |
38b2df95 | 1981 | #define DRX_STR_CODERATE(x) ( \ |
2f1f7333 MCC |
1982 | (x == DRX_CODERATE_1DIV2) ? "1/2nd" : \ |
1983 | (x == DRX_CODERATE_2DIV3) ? "2/3rd" : \ | |
1984 | (x == DRX_CODERATE_3DIV4) ? "3/4th" : \ | |
1985 | (x == DRX_CODERATE_5DIV6) ? "5/6th" : \ | |
1986 | (x == DRX_CODERATE_7DIV8) ? "7/8th" : \ | |
1987 | (x == DRX_CODERATE_AUTO) ? "Auto" : \ | |
1988 | (x == DRX_CODERATE_UNKNOWN) ? "Unknown" : \ | |
1989 | "(Invalid)") | |
38b2df95 | 1990 | #define DRX_STR_HIERARCHY(x) ( \ |
2f1f7333 MCC |
1991 | (x == DRX_HIERARCHY_NONE) ? "None" : \ |
1992 | (x == DRX_HIERARCHY_ALPHA1) ? "Alpha=1" : \ | |
1993 | (x == DRX_HIERARCHY_ALPHA2) ? "Alpha=2" : \ | |
1994 | (x == DRX_HIERARCHY_ALPHA4) ? "Alpha=4" : \ | |
1995 | (x == DRX_HIERARCHY_AUTO) ? "Auto" : \ | |
1996 | (x == DRX_HIERARCHY_UNKNOWN) ? "Unknown" : \ | |
1997 | "(Invalid)") | |
38b2df95 | 1998 | #define DRX_STR_PRIORITY(x) ( \ |
2f1f7333 MCC |
1999 | (x == DRX_PRIORITY_LOW) ? "Low" : \ |
2000 | (x == DRX_PRIORITY_HIGH) ? "High" : \ | |
2001 | (x == DRX_PRIORITY_UNKNOWN) ? "Unknown" : \ | |
2002 | "(Invalid)") | |
38b2df95 | 2003 | #define DRX_STR_MIRROR(x) ( \ |
2f1f7333 MCC |
2004 | (x == DRX_MIRROR_NO) ? "Normal" : \ |
2005 | (x == DRX_MIRROR_YES) ? "Mirrored" : \ | |
2006 | (x == DRX_MIRROR_AUTO) ? "Auto" : \ | |
2007 | (x == DRX_MIRROR_UNKNOWN) ? "Unknown" : \ | |
2008 | "(Invalid)") | |
38b2df95 | 2009 | #define DRX_STR_CLASSIFICATION(x) ( \ |
2f1f7333 MCC |
2010 | (x == DRX_CLASSIFICATION_GAUSS) ? "Gaussion" : \ |
2011 | (x == DRX_CLASSIFICATION_HVY_GAUSS) ? "Heavy Gaussion" : \ | |
2012 | (x == DRX_CLASSIFICATION_COCHANNEL) ? "Co-channel" : \ | |
2013 | (x == DRX_CLASSIFICATION_STATIC) ? "Static echo" : \ | |
2014 | (x == DRX_CLASSIFICATION_MOVING) ? "Moving echo" : \ | |
2015 | (x == DRX_CLASSIFICATION_ZERODB) ? "Zero dB echo" : \ | |
2016 | (x == DRX_CLASSIFICATION_UNKNOWN) ? "Unknown" : \ | |
2017 | (x == DRX_CLASSIFICATION_AUTO) ? "Auto" : \ | |
2018 | "(Invalid)") | |
38b2df95 DH |
2019 | |
2020 | #define DRX_STR_INTERLEAVEMODE(x) ( \ | |
2f1f7333 MCC |
2021 | (x == DRX_INTERLEAVEMODE_I128_J1) ? "I128_J1" : \ |
2022 | (x == DRX_INTERLEAVEMODE_I128_J1_V2) ? "I128_J1_V2" : \ | |
2023 | (x == DRX_INTERLEAVEMODE_I128_J2) ? "I128_J2" : \ | |
2024 | (x == DRX_INTERLEAVEMODE_I64_J2) ? "I64_J2" : \ | |
2025 | (x == DRX_INTERLEAVEMODE_I128_J3) ? "I128_J3" : \ | |
2026 | (x == DRX_INTERLEAVEMODE_I32_J4) ? "I32_J4" : \ | |
2027 | (x == DRX_INTERLEAVEMODE_I128_J4) ? "I128_J4" : \ | |
2028 | (x == DRX_INTERLEAVEMODE_I16_J8) ? "I16_J8" : \ | |
2029 | (x == DRX_INTERLEAVEMODE_I128_J5) ? "I128_J5" : \ | |
2030 | (x == DRX_INTERLEAVEMODE_I8_J16) ? "I8_J16" : \ | |
2031 | (x == DRX_INTERLEAVEMODE_I128_J6) ? "I128_J6" : \ | |
2032 | (x == DRX_INTERLEAVEMODE_RESERVED_11) ? "Reserved 11" : \ | |
2033 | (x == DRX_INTERLEAVEMODE_I128_J7) ? "I128_J7" : \ | |
2034 | (x == DRX_INTERLEAVEMODE_RESERVED_13) ? "Reserved 13" : \ | |
2035 | (x == DRX_INTERLEAVEMODE_I128_J8) ? "I128_J8" : \ | |
2036 | (x == DRX_INTERLEAVEMODE_RESERVED_15) ? "Reserved 15" : \ | |
2037 | (x == DRX_INTERLEAVEMODE_I12_J17) ? "I12_J17" : \ | |
2038 | (x == DRX_INTERLEAVEMODE_I5_J4) ? "I5_J4" : \ | |
2039 | (x == DRX_INTERLEAVEMODE_B52_M240) ? "B52_M240" : \ | |
2040 | (x == DRX_INTERLEAVEMODE_B52_M720) ? "B52_M720" : \ | |
2041 | (x == DRX_INTERLEAVEMODE_B52_M48) ? "B52_M48" : \ | |
2042 | (x == DRX_INTERLEAVEMODE_B52_M0) ? "B52_M0" : \ | |
2043 | (x == DRX_INTERLEAVEMODE_UNKNOWN) ? "Unknown" : \ | |
2044 | (x == DRX_INTERLEAVEMODE_AUTO) ? "Auto" : \ | |
2045 | "(Invalid)") | |
38b2df95 DH |
2046 | |
2047 | #define DRX_STR_LDPC(x) ( \ | |
2f1f7333 MCC |
2048 | (x == DRX_LDPC_0_4) ? "0.4" : \ |
2049 | (x == DRX_LDPC_0_6) ? "0.6" : \ | |
2050 | (x == DRX_LDPC_0_8) ? "0.8" : \ | |
2051 | (x == DRX_LDPC_AUTO) ? "Auto" : \ | |
2052 | (x == DRX_LDPC_UNKNOWN) ? "Unknown" : \ | |
2053 | "(Invalid)") | |
38b2df95 DH |
2054 | |
2055 | #define DRX_STR_CARRIER(x) ( \ | |
2f1f7333 MCC |
2056 | (x == DRX_CARRIER_MULTI) ? "Multi" : \ |
2057 | (x == DRX_CARRIER_SINGLE) ? "Single" : \ | |
2058 | (x == DRX_CARRIER_AUTO) ? "Auto" : \ | |
2059 | (x == DRX_CARRIER_UNKNOWN) ? "Unknown" : \ | |
2060 | "(Invalid)") | |
38b2df95 DH |
2061 | |
2062 | #define DRX_STR_FRAMEMODE(x) ( \ | |
2f1f7333 MCC |
2063 | (x == DRX_FRAMEMODE_420) ? "420" : \ |
2064 | (x == DRX_FRAMEMODE_595) ? "595" : \ | |
2065 | (x == DRX_FRAMEMODE_945) ? "945" : \ | |
2066 | (x == DRX_FRAMEMODE_420_FIXED_PN) ? "420 with fixed PN" : \ | |
2067 | (x == DRX_FRAMEMODE_945_FIXED_PN) ? "945 with fixed PN" : \ | |
2068 | (x == DRX_FRAMEMODE_AUTO) ? "Auto" : \ | |
2069 | (x == DRX_FRAMEMODE_UNKNOWN) ? "Unknown" : \ | |
2070 | "(Invalid)") | |
38b2df95 DH |
2071 | |
2072 | #define DRX_STR_PILOT(x) ( \ | |
2f1f7333 MCC |
2073 | (x == DRX_PILOT_ON) ? "On" : \ |
2074 | (x == DRX_PILOT_OFF) ? "Off" : \ | |
2075 | (x == DRX_PILOT_AUTO) ? "Auto" : \ | |
2076 | (x == DRX_PILOT_UNKNOWN) ? "Unknown" : \ | |
2077 | "(Invalid)") | |
38b2df95 DH |
2078 | /* TPS */ |
2079 | ||
2080 | #define DRX_STR_TPS_FRAME(x) ( \ | |
2f1f7333 MCC |
2081 | (x == DRX_TPS_FRAME1) ? "Frame1" : \ |
2082 | (x == DRX_TPS_FRAME2) ? "Frame2" : \ | |
2083 | (x == DRX_TPS_FRAME3) ? "Frame3" : \ | |
2084 | (x == DRX_TPS_FRAME4) ? "Frame4" : \ | |
2085 | (x == DRX_TPS_FRAME_UNKNOWN) ? "Unknown" : \ | |
2086 | "(Invalid)") | |
38b2df95 DH |
2087 | |
2088 | /* lock status */ | |
2089 | ||
2090 | #define DRX_STR_LOCKSTATUS(x) ( \ | |
2f1f7333 MCC |
2091 | (x == DRX_NEVER_LOCK) ? "Never" : \ |
2092 | (x == DRX_NOT_LOCKED) ? "No" : \ | |
2093 | (x == DRX_LOCKED) ? "Locked" : \ | |
2094 | (x == DRX_LOCK_STATE_1) ? "Lock state 1" : \ | |
2095 | (x == DRX_LOCK_STATE_2) ? "Lock state 2" : \ | |
2096 | (x == DRX_LOCK_STATE_3) ? "Lock state 3" : \ | |
2097 | (x == DRX_LOCK_STATE_4) ? "Lock state 4" : \ | |
2098 | (x == DRX_LOCK_STATE_5) ? "Lock state 5" : \ | |
2099 | (x == DRX_LOCK_STATE_6) ? "Lock state 6" : \ | |
2100 | (x == DRX_LOCK_STATE_7) ? "Lock state 7" : \ | |
2101 | (x == DRX_LOCK_STATE_8) ? "Lock state 8" : \ | |
2102 | (x == DRX_LOCK_STATE_9) ? "Lock state 9" : \ | |
2103 | "(Invalid)") | |
38b2df95 DH |
2104 | |
2105 | /* version information , modules */ | |
2106 | #define DRX_STR_MODULE(x) ( \ | |
2f1f7333 MCC |
2107 | (x == DRX_MODULE_DEVICE) ? "Device" : \ |
2108 | (x == DRX_MODULE_MICROCODE) ? "Microcode" : \ | |
2109 | (x == DRX_MODULE_DRIVERCORE) ? "CoreDriver" : \ | |
2110 | (x == DRX_MODULE_DEVICEDRIVER) ? "DeviceDriver" : \ | |
2111 | (x == DRX_MODULE_BSP_I2C) ? "BSP I2C" : \ | |
2112 | (x == DRX_MODULE_BSP_TUNER) ? "BSP Tuner" : \ | |
2113 | (x == DRX_MODULE_BSP_HOST) ? "BSP Host" : \ | |
2114 | (x == DRX_MODULE_DAP) ? "Data Access Protocol" : \ | |
2115 | (x == DRX_MODULE_UNKNOWN) ? "Unknown" : \ | |
2116 | "(Invalid)") | |
38b2df95 DH |
2117 | |
2118 | #define DRX_STR_POWER_MODE(x) ( \ | |
2f1f7333 MCC |
2119 | (x == DRX_POWER_UP) ? "DRX_POWER_UP " : \ |
2120 | (x == DRX_POWER_MODE_1) ? "DRX_POWER_MODE_1" : \ | |
2121 | (x == DRX_POWER_MODE_2) ? "DRX_POWER_MODE_2" : \ | |
2122 | (x == DRX_POWER_MODE_3) ? "DRX_POWER_MODE_3" : \ | |
2123 | (x == DRX_POWER_MODE_4) ? "DRX_POWER_MODE_4" : \ | |
2124 | (x == DRX_POWER_MODE_5) ? "DRX_POWER_MODE_5" : \ | |
2125 | (x == DRX_POWER_MODE_6) ? "DRX_POWER_MODE_6" : \ | |
2126 | (x == DRX_POWER_MODE_7) ? "DRX_POWER_MODE_7" : \ | |
2127 | (x == DRX_POWER_MODE_8) ? "DRX_POWER_MODE_8" : \ | |
2128 | (x == DRX_POWER_MODE_9) ? "DRX_POWER_MODE_9" : \ | |
2129 | (x == DRX_POWER_MODE_10) ? "DRX_POWER_MODE_10" : \ | |
2130 | (x == DRX_POWER_MODE_11) ? "DRX_POWER_MODE_11" : \ | |
2131 | (x == DRX_POWER_MODE_12) ? "DRX_POWER_MODE_12" : \ | |
2132 | (x == DRX_POWER_MODE_13) ? "DRX_POWER_MODE_13" : \ | |
2133 | (x == DRX_POWER_MODE_14) ? "DRX_POWER_MODE_14" : \ | |
2134 | (x == DRX_POWER_MODE_15) ? "DRX_POWER_MODE_15" : \ | |
2135 | (x == DRX_POWER_MODE_16) ? "DRX_POWER_MODE_16" : \ | |
2136 | (x == DRX_POWER_DOWN) ? "DRX_POWER_DOWN " : \ | |
2137 | "(Invalid)") | |
38b2df95 DH |
2138 | |
2139 | #define DRX_STR_OOB_STANDARD(x) ( \ | |
2f1f7333 MCC |
2140 | (x == DRX_OOB_MODE_A) ? "ANSI 55-1 " : \ |
2141 | (x == DRX_OOB_MODE_B_GRADE_A) ? "ANSI 55-2 A" : \ | |
2142 | (x == DRX_OOB_MODE_B_GRADE_B) ? "ANSI 55-2 B" : \ | |
2143 | "(Invalid)") | |
38b2df95 DH |
2144 | |
2145 | #define DRX_STR_AUD_STANDARD(x) ( \ | |
2f1f7333 MCC |
2146 | (x == DRX_AUD_STANDARD_BTSC) ? "BTSC" : \ |
2147 | (x == DRX_AUD_STANDARD_A2) ? "A2" : \ | |
2148 | (x == DRX_AUD_STANDARD_EIAJ) ? "EIAJ" : \ | |
2149 | (x == DRX_AUD_STANDARD_FM_STEREO) ? "FM Stereo" : \ | |
2150 | (x == DRX_AUD_STANDARD_AUTO) ? "Auto" : \ | |
2151 | (x == DRX_AUD_STANDARD_M_MONO) ? "M-Standard Mono" : \ | |
2152 | (x == DRX_AUD_STANDARD_D_K_MONO) ? "D/K Mono FM" : \ | |
2153 | (x == DRX_AUD_STANDARD_BG_FM) ? "B/G-Dual Carrier FM (A2)" : \ | |
2154 | (x == DRX_AUD_STANDARD_D_K1) ? "D/K1-Dual Carrier FM" : \ | |
2155 | (x == DRX_AUD_STANDARD_D_K2) ? "D/K2-Dual Carrier FM" : \ | |
2156 | (x == DRX_AUD_STANDARD_D_K3) ? "D/K3-Dual Carrier FM" : \ | |
2157 | (x == DRX_AUD_STANDARD_BG_NICAM_FM) ? "B/G-NICAM-FM" : \ | |
2158 | (x == DRX_AUD_STANDARD_L_NICAM_AM) ? "L-NICAM-AM" : \ | |
2159 | (x == DRX_AUD_STANDARD_I_NICAM_FM) ? "I-NICAM-FM" : \ | |
2160 | (x == DRX_AUD_STANDARD_D_K_NICAM_FM) ? "D/K-NICAM-FM" : \ | |
2161 | (x == DRX_AUD_STANDARD_UNKNOWN) ? "Unknown" : \ | |
2162 | "(Invalid)") | |
38b2df95 | 2163 | #define DRX_STR_AUD_STEREO(x) ( \ |
2f1f7333 MCC |
2164 | (x == true) ? "Stereo" : \ |
2165 | (x == false) ? "Mono" : \ | |
2166 | "(Invalid)") | |
38b2df95 DH |
2167 | |
2168 | #define DRX_STR_AUD_SAP(x) ( \ | |
2f1f7333 MCC |
2169 | (x == true) ? "Present" : \ |
2170 | (x == false) ? "Not present" : \ | |
2171 | "(Invalid)") | |
38b2df95 DH |
2172 | |
2173 | #define DRX_STR_AUD_CARRIER(x) ( \ | |
2f1f7333 MCC |
2174 | (x == true) ? "Present" : \ |
2175 | (x == false) ? "Not present" : \ | |
2176 | "(Invalid)") | |
38b2df95 DH |
2177 | |
2178 | #define DRX_STR_AUD_RDS(x) ( \ | |
2f1f7333 MCC |
2179 | (x == true) ? "Available" : \ |
2180 | (x == false) ? "Not Available" : \ | |
2181 | "(Invalid)") | |
38b2df95 DH |
2182 | |
2183 | #define DRX_STR_AUD_NICAM_STATUS(x) ( \ | |
2f1f7333 MCC |
2184 | (x == DRX_AUD_NICAM_DETECTED) ? "Detected" : \ |
2185 | (x == DRX_AUD_NICAM_NOT_DETECTED) ? "Not detected" : \ | |
2186 | (x == DRX_AUD_NICAM_BAD) ? "Bad" : \ | |
2187 | "(Invalid)") | |
38b2df95 DH |
2188 | |
2189 | #define DRX_STR_RDS_VALID(x) ( \ | |
2f1f7333 MCC |
2190 | (x == true) ? "Valid" : \ |
2191 | (x == false) ? "Not Valid" : \ | |
2192 | "(Invalid)") | |
38b2df95 DH |
2193 | |
2194 | /*------------------------------------------------------------------------- | |
2195 | Access macros | |
2196 | -------------------------------------------------------------------------*/ | |
2197 | ||
b95b0c98 | 2198 | /* |
38b2df95 DH |
2199 | * \brief Create a compilable reference to the microcode attribute |
2200 | * \param d pointer to demod instance | |
2201 | * | |
2202 | * Used as main reference to an attribute field. | |
2203 | * Used by both macro implementation and function implementation. | |
2204 | * These macros are defined to avoid duplication of code in macro and function | |
2205 | * definitions that handle access of demod common or extended attributes. | |
2206 | * | |
2207 | */ | |
2208 | ||
57afe2f0 MCC |
2209 | #define DRX_ATTR_MCRECORD(d) ((d)->my_common_attr->mcversion) |
2210 | #define DRX_ATTR_MIRRORFREQSPECT(d) ((d)->my_common_attr->mirror_freq_spect) | |
2211 | #define DRX_ATTR_CURRENTPOWERMODE(d)((d)->my_common_attr->current_power_mode) | |
2212 | #define DRX_ATTR_ISOPENED(d) ((d)->my_common_attr->is_opened) | |
2213 | #define DRX_ATTR_USEBOOTLOADER(d) ((d)->my_common_attr->use_bootloader) | |
2214 | #define DRX_ATTR_CURRENTSTANDARD(d) ((d)->my_common_attr->current_standard) | |
2215 | #define DRX_ATTR_PREVSTANDARD(d) ((d)->my_common_attr->prev_standard) | |
2216 | #define DRX_ATTR_CACHESTANDARD(d) ((d)->my_common_attr->di_cache_standard) | |
2217 | #define DRX_ATTR_CURRENTCHANNEL(d) ((d)->my_common_attr->current_channel) | |
2218 | #define DRX_ATTR_MICROCODE(d) ((d)->my_common_attr->microcode) | |
57afe2f0 MCC |
2219 | #define DRX_ATTR_VERIFYMICROCODE(d) ((d)->my_common_attr->verify_microcode) |
2220 | #define DRX_ATTR_CAPABILITIES(d) ((d)->my_common_attr->capabilities) | |
2221 | #define DRX_ATTR_PRODUCTID(d) ((d)->my_common_attr->product_id) | |
2222 | #define DRX_ATTR_INTERMEDIATEFREQ(d) ((d)->my_common_attr->intermediate_freq) | |
2223 | #define DRX_ATTR_SYSCLOCKFREQ(d) ((d)->my_common_attr->sys_clock_freq) | |
2224 | #define DRX_ATTR_TUNERRFAGCPOL(d) ((d)->my_common_attr->tuner_rf_agc_pol) | |
2225 | #define DRX_ATTR_TUNERIFAGCPOL(d) ((d)->my_common_attr->tuner_if_agc_pol) | |
2226 | #define DRX_ATTR_TUNERSLOWMODE(d) ((d)->my_common_attr->tuner_slow_mode) | |
2227 | #define DRX_ATTR_TUNERSPORTNR(d) ((d)->my_common_attr->tuner_port_nr) | |
57afe2f0 MCC |
2228 | #define DRX_ATTR_I2CADDR(d) ((d)->my_i2c_dev_addr->i2c_addr) |
2229 | #define DRX_ATTR_I2CDEVID(d) ((d)->my_i2c_dev_addr->i2c_dev_id) | |
38b2df95 DH |
2230 | #define DRX_ISMCVERTYPE(x) ((x) == AUX_VER_RECORD) |
2231 | ||
b95b0c98 | 2232 | /*************************/ |
38b2df95 | 2233 | |
38b2df95 DH |
2234 | /* Macros with device-specific handling are converted to CFG functions */ |
2235 | ||
57afe2f0 | 2236 | #define DRX_ACCESSMACRO_SET(demod, value, cfg_name, data_type) \ |
2f1f7333 MCC |
2237 | do { \ |
2238 | struct drx_cfg config; \ | |
2239 | data_type cfg_data; \ | |
2240 | config.cfg_type = cfg_name; \ | |
2241 | config.cfg_data = &cfg_data; \ | |
2242 | cfg_data = value; \ | |
2243 | drx_ctrl(demod, DRX_CTRL_SET_CFG, &config); \ | |
2244 | } while (0) | |
38b2df95 | 2245 | |
57afe2f0 | 2246 | #define DRX_ACCESSMACRO_GET(demod, value, cfg_name, data_type, error_value) \ |
2f1f7333 MCC |
2247 | do { \ |
2248 | int cfg_status; \ | |
2249 | struct drx_cfg config; \ | |
2250 | data_type cfg_data; \ | |
2251 | config.cfg_type = cfg_name; \ | |
2252 | config.cfg_data = &cfg_data; \ | |
2253 | cfg_status = drx_ctrl(demod, DRX_CTRL_GET_CFG, &config); \ | |
2254 | if (cfg_status == 0) { \ | |
2255 | value = cfg_data; \ | |
2256 | } else { \ | |
2257 | value = (data_type)error_value; \ | |
2258 | } \ | |
2259 | } while (0) | |
38b2df95 | 2260 | |
38b2df95 DH |
2261 | /* Configuration functions for usage by Access (XS) Macros */ |
2262 | ||
2263 | #ifndef DRX_XS_CFG_BASE | |
2264 | #define DRX_XS_CFG_BASE (500) | |
2265 | #endif | |
2266 | ||
7ef66759 MCC |
2267 | #define DRX_XS_CFG_PRESET (DRX_XS_CFG_BASE + 0) |
2268 | #define DRX_XS_CFG_AUD_BTSC_DETECT (DRX_XS_CFG_BASE + 1) | |
2269 | #define DRX_XS_CFG_QAM_LOCKRANGE (DRX_XS_CFG_BASE + 2) | |
38b2df95 DH |
2270 | |
2271 | /* Access Macros with device-specific handling */ | |
2272 | ||
7ef66759 | 2273 | #define DRX_SET_PRESET(d, x) \ |
2f1f7333 | 2274 | DRX_ACCESSMACRO_SET((d), (x), DRX_XS_CFG_PRESET, char*) |
7ef66759 | 2275 | #define DRX_GET_PRESET(d, x) \ |
2f1f7333 | 2276 | DRX_ACCESSMACRO_GET((d), (x), DRX_XS_CFG_PRESET, char*, "ERROR") |
38b2df95 | 2277 | |
22892268 | 2278 | #define DRX_SET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_SET((d), (x), \ |
1bfc9e15 | 2279 | DRX_XS_CFG_AUD_BTSC_DETECT, enum drx_aud_btsc_detect) |
22892268 | 2280 | #define DRX_GET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_GET((d), (x), \ |
1bfc9e15 | 2281 | DRX_XS_CFG_AUD_BTSC_DETECT, enum drx_aud_btsc_detect, DRX_UNKNOWN) |
38b2df95 | 2282 | |
22892268 | 2283 | #define DRX_SET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_SET((d), (x), \ |
1bfc9e15 | 2284 | DRX_XS_CFG_QAM_LOCKRANGE, enum drx_qam_lock_range) |
22892268 | 2285 | #define DRX_GET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_GET((d), (x), \ |
1bfc9e15 | 2286 | DRX_XS_CFG_QAM_LOCKRANGE, enum drx_qam_lock_range, DRX_UNKNOWN) |
38b2df95 | 2287 | |
b95b0c98 | 2288 | /* |
38b2df95 | 2289 | * \brief Macro to check if std is an ATV standard |
73f7065b MCC |
2290 | * \retval true std is an ATV standard |
2291 | * \retval false std is an ATV standard | |
38b2df95 | 2292 | */ |
1bfc9e15 | 2293 | #define DRX_ISATVSTD(std) (((std) == DRX_STANDARD_PAL_SECAM_BG) || \ |
7ef66759 MCC |
2294 | ((std) == DRX_STANDARD_PAL_SECAM_DK) || \ |
2295 | ((std) == DRX_STANDARD_PAL_SECAM_I) || \ | |
2296 | ((std) == DRX_STANDARD_PAL_SECAM_L) || \ | |
2297 | ((std) == DRX_STANDARD_PAL_SECAM_LP) || \ | |
2298 | ((std) == DRX_STANDARD_NTSC) || \ | |
22892268 | 2299 | ((std) == DRX_STANDARD_FM)) |
38b2df95 | 2300 | |
b95b0c98 | 2301 | /* |
38b2df95 | 2302 | * \brief Macro to check if std is an QAM standard |
73f7065b MCC |
2303 | * \retval true std is an QAM standards |
2304 | * \retval false std is an QAM standards | |
38b2df95 | 2305 | */ |
1bfc9e15 | 2306 | #define DRX_ISQAMSTD(std) (((std) == DRX_STANDARD_ITU_A) || \ |
7ef66759 MCC |
2307 | ((std) == DRX_STANDARD_ITU_B) || \ |
2308 | ((std) == DRX_STANDARD_ITU_C) || \ | |
2309 | ((std) == DRX_STANDARD_ITU_D)) | |
38b2df95 | 2310 | |
b95b0c98 | 2311 | /* |
38b2df95 | 2312 | * \brief Macro to check if std is VSB standard |
73f7065b MCC |
2313 | * \retval true std is VSB standard |
2314 | * \retval false std is not VSB standard | |
38b2df95 | 2315 | */ |
22892268 | 2316 | #define DRX_ISVSBSTD(std) ((std) == DRX_STANDARD_8VSB) |
38b2df95 | 2317 | |
b95b0c98 | 2318 | /* |
38b2df95 | 2319 | * \brief Macro to check if std is DVBT standard |
73f7065b MCC |
2320 | * \retval true std is DVBT standard |
2321 | * \retval false std is not DVBT standard | |
38b2df95 | 2322 | */ |
22892268 | 2323 | #define DRX_ISDVBTSTD(std) ((std) == DRX_STANDARD_DVBT) |
38b2df95 | 2324 | |
38b2df95 DH |
2325 | /*------------------------------------------------------------------------- |
2326 | THE END | |
2327 | -------------------------------------------------------------------------*/ | |
443f18d0 | 2328 | #endif /* __DRXDRIVER_H__ */ |