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a10e763b | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
1da177e4 LT |
2 | /* |
3 | * dib3000mb_priv.h | |
4 | * | |
99e44da7 | 5 | * Copyright (C) 2004 Patrick Boettcher (patrick.boettcher@posteo.de) |
1da177e4 | 6 | * |
1da177e4 LT |
7 | * for more information see dib3000mb.c . |
8 | */ | |
9 | ||
10 | #ifndef __DIB3000MB_PRIV_H_INCLUDED__ | |
11 | #define __DIB3000MB_PRIV_H_INCLUDED__ | |
12 | ||
74340b0a PB |
13 | /* handy shortcuts */ |
14 | #define rd(reg) dib3000_read_reg(state,reg) | |
15 | ||
16 | #define wr(reg,val) if (dib3000_write_reg(state,reg,val)) \ | |
585e3227 | 17 | { pr_err("while sending 0x%04x to 0x%04x.", val, reg); return -EREMOTEIO; } |
74340b0a PB |
18 | |
19 | #define wr_foreach(a,v) { int i; \ | |
20 | if (sizeof(a) != sizeof(v)) \ | |
585e3227 | 21 | pr_err("sizeof: %zu %zu is different", sizeof(a), sizeof(v));\ |
74340b0a PB |
22 | for (i=0; i < sizeof(a)/sizeof(u16); i++) \ |
23 | wr(a[i],v[i]); \ | |
24 | } | |
25 | ||
26 | #define set_or(reg,val) wr(reg,rd(reg) | val) | |
27 | ||
28 | #define set_and(reg,val) wr(reg,rd(reg) & val) | |
29 | ||
30 | /* debug */ | |
31 | ||
585e3227 MCC |
32 | #define dprintk(level, fmt, arg...) do { \ |
33 | if (debug & level) \ | |
34 | printk(KERN_DEBUG pr_fmt("%s: " fmt), \ | |
35 | __func__, ##arg); \ | |
36 | } while (0) | |
74340b0a PB |
37 | |
38 | /* mask for enabling a specific pid for the pid_filter */ | |
39 | #define DIB3000_ACTIVATE_PID_FILTERING (0x2000) | |
40 | ||
41 | /* common values for tuning */ | |
42 | #define DIB3000_ALPHA_0 ( 0) | |
43 | #define DIB3000_ALPHA_1 ( 1) | |
44 | #define DIB3000_ALPHA_2 ( 2) | |
45 | #define DIB3000_ALPHA_4 ( 4) | |
46 | ||
47 | #define DIB3000_CONSTELLATION_QPSK ( 0) | |
48 | #define DIB3000_CONSTELLATION_16QAM ( 1) | |
49 | #define DIB3000_CONSTELLATION_64QAM ( 2) | |
50 | ||
51 | #define DIB3000_GUARD_TIME_1_32 ( 0) | |
52 | #define DIB3000_GUARD_TIME_1_16 ( 1) | |
53 | #define DIB3000_GUARD_TIME_1_8 ( 2) | |
54 | #define DIB3000_GUARD_TIME_1_4 ( 3) | |
55 | ||
56 | #define DIB3000_TRANSMISSION_MODE_2K ( 0) | |
57 | #define DIB3000_TRANSMISSION_MODE_8K ( 1) | |
58 | ||
59 | #define DIB3000_SELECT_LP ( 0) | |
60 | #define DIB3000_SELECT_HP ( 1) | |
61 | ||
62 | #define DIB3000_FEC_1_2 ( 1) | |
63 | #define DIB3000_FEC_2_3 ( 2) | |
64 | #define DIB3000_FEC_3_4 ( 3) | |
65 | #define DIB3000_FEC_5_6 ( 5) | |
66 | #define DIB3000_FEC_7_8 ( 7) | |
67 | ||
68 | #define DIB3000_HRCH_OFF ( 0) | |
69 | #define DIB3000_HRCH_ON ( 1) | |
70 | ||
71 | #define DIB3000_DDS_INVERSION_OFF ( 0) | |
72 | #define DIB3000_DDS_INVERSION_ON ( 1) | |
73 | ||
74 | #define DIB3000_TUNER_WRITE_ENABLE(a) (0xffff & (a << 8)) | |
75 | #define DIB3000_TUNER_WRITE_DISABLE(a) (0xffff & ((a << 8) | (1 << 7))) | |
76 | ||
74340b0a PB |
77 | #define DIB3000_REG_MANUFACTOR_ID ( 1025) |
78 | #define DIB3000_I2C_ID_DIBCOM (0x01b3) | |
79 | ||
80 | #define DIB3000_REG_DEVICE_ID ( 1026) | |
81 | #define DIB3000MB_DEVICE_ID (0x3000) | |
82 | #define DIB3000MC_DEVICE_ID (0x3001) | |
83 | #define DIB3000P_DEVICE_ID (0x3002) | |
84 | ||
85 | /* frontend state */ | |
86 | struct dib3000_state { | |
87 | struct i2c_adapter* i2c; | |
88 | ||
89 | /* configuration settings */ | |
90 | struct dib3000_config config; | |
91 | ||
92 | struct dvb_frontend frontend; | |
93 | int timing_offset; | |
94 | int timing_offset_comp_done; | |
95 | ||
c6f56e7d | 96 | u32 last_tuned_bw; |
74340b0a PB |
97 | u32 last_tuned_freq; |
98 | }; | |
99 | ||
1da177e4 LT |
100 | /* register addresses and some of their default values */ |
101 | ||
102 | /* restart subsystems */ | |
103 | #define DIB3000MB_REG_RESTART ( 0) | |
104 | ||
105 | #define DIB3000MB_RESTART_OFF ( 0) | |
106 | #define DIB3000MB_RESTART_AUTO_SEARCH (1 << 1) | |
107 | #define DIB3000MB_RESTART_CTRL (1 << 2) | |
108 | #define DIB3000MB_RESTART_AGC (1 << 3) | |
109 | ||
110 | /* FFT size */ | |
111 | #define DIB3000MB_REG_FFT ( 1) | |
112 | ||
113 | /* Guard time */ | |
114 | #define DIB3000MB_REG_GUARD_TIME ( 2) | |
115 | ||
116 | /* QAM */ | |
117 | #define DIB3000MB_REG_QAM ( 3) | |
118 | ||
119 | /* Alpha coefficient high priority Viterbi algorithm */ | |
120 | #define DIB3000MB_REG_VIT_ALPHA ( 4) | |
121 | ||
122 | /* spectrum inversion */ | |
123 | #define DIB3000MB_REG_DDS_INV ( 5) | |
124 | ||
125 | /* DDS frequency value (IF position) ad ? values don't match reg_3000mb.txt */ | |
126 | #define DIB3000MB_REG_DDS_FREQ_MSB ( 6) | |
127 | #define DIB3000MB_REG_DDS_FREQ_LSB ( 7) | |
128 | #define DIB3000MB_DDS_FREQ_MSB ( 178) | |
129 | #define DIB3000MB_DDS_FREQ_LSB ( 8990) | |
130 | ||
131 | /* timing frequency (carrier spacing) */ | |
132 | static u16 dib3000mb_reg_timing_freq[] = { 8,9 }; | |
133 | static u16 dib3000mb_timing_freq[][2] = { | |
134 | { 126 , 48873 }, /* 6 MHz */ | |
135 | { 147 , 57019 }, /* 7 MHz */ | |
136 | { 168 , 65164 }, /* 8 MHz */ | |
137 | }; | |
138 | ||
139 | /* impulse noise parameter */ | |
140 | /* 36 ??? */ | |
141 | ||
142 | static u16 dib3000mb_reg_impulse_noise[] = { 10,11,12,15,36 }; | |
143 | ||
144 | enum dib3000mb_impulse_noise_type { | |
145 | DIB3000MB_IMPNOISE_OFF, | |
146 | DIB3000MB_IMPNOISE_MOBILE, | |
147 | DIB3000MB_IMPNOISE_FIXED, | |
148 | DIB3000MB_IMPNOISE_DEFAULT | |
149 | }; | |
150 | ||
151 | static u16 dib3000mb_impulse_noise_values[][5] = { | |
152 | { 0x0000, 0x0004, 0x0014, 0x01ff, 0x0399 }, /* off */ | |
153 | { 0x0001, 0x0004, 0x0014, 0x01ff, 0x037b }, /* mobile */ | |
154 | { 0x0001, 0x0004, 0x0020, 0x01bd, 0x0399 }, /* fixed */ | |
155 | { 0x0000, 0x0002, 0x000a, 0x01ff, 0x0399 }, /* default */ | |
156 | }; | |
157 | ||
158 | /* | |
159 | * Dual Automatic-Gain-Control | |
160 | * - gains RF in tuner (AGC1) | |
161 | * - gains IF after filtering (AGC2) | |
162 | */ | |
163 | ||
164 | /* also from 16 to 18 */ | |
165 | static u16 dib3000mb_reg_agc_gain[] = { | |
166 | 19,20,21,22,23,24,25,26,27,28,29,30,31,32 | |
167 | }; | |
168 | ||
169 | static u16 dib3000mb_default_agc_gain[] = | |
170 | { 0x0001, 52429, 623, 128, 166, 195, 61, /* RF ??? */ | |
171 | 0x0001, 53766, 38011, 0, 90, 33, 23 }; /* IF ??? */ | |
172 | ||
173 | /* phase noise */ | |
174 | /* 36 is set when setting the impulse noise */ | |
175 | static u16 dib3000mb_reg_phase_noise[] = { 33,34,35,37,38 }; | |
176 | ||
177 | static u16 dib3000mb_default_noise_phase[] = { 2, 544, 0, 5, 4 }; | |
178 | ||
179 | /* lock duration */ | |
180 | static u16 dib3000mb_reg_lock_duration[] = { 39,40 }; | |
181 | static u16 dib3000mb_default_lock_duration[] = { 135, 135 }; | |
182 | ||
183 | /* AGC loop bandwidth */ | |
184 | static u16 dib3000mb_reg_agc_bandwidth[] = { 43,44,45,46,47,48,49,50 }; | |
185 | ||
186 | static u16 dib3000mb_agc_bandwidth_low[] = | |
187 | { 2088, 10, 2088, 10, 3448, 5, 3448, 5 }; | |
188 | static u16 dib3000mb_agc_bandwidth_high[] = | |
189 | { 2349, 5, 2349, 5, 2586, 2, 2586, 2 }; | |
190 | ||
191 | /* | |
192 | * lock0 definition (coff_lock) | |
193 | */ | |
194 | #define DIB3000MB_REG_LOCK0_MASK ( 51) | |
195 | #define DIB3000MB_LOCK0_DEFAULT ( 4) | |
196 | ||
197 | /* | |
198 | * lock1 definition (cpil_lock) | |
199 | * for auto search | |
200 | * which values hide behind the lock masks | |
201 | */ | |
202 | #define DIB3000MB_REG_LOCK1_MASK ( 52) | |
203 | #define DIB3000MB_LOCK1_SEARCH_4 (0x0004) | |
204 | #define DIB3000MB_LOCK1_SEARCH_2048 (0x0800) | |
205 | #define DIB3000MB_LOCK1_DEFAULT (0x0001) | |
206 | ||
207 | /* | |
208 | * lock2 definition (fec_lock) */ | |
209 | #define DIB3000MB_REG_LOCK2_MASK ( 53) | |
210 | #define DIB3000MB_LOCK2_DEFAULT (0x0080) | |
211 | ||
212 | /* | |
213 | * SEQ ? what was that again ... :) | |
214 | * changes when, inversion, guard time and fft is | |
215 | * either automatically detected or not | |
216 | */ | |
217 | #define DIB3000MB_REG_SEQ ( 54) | |
218 | ||
219 | /* bandwidth */ | |
220 | static u16 dib3000mb_reg_bandwidth[] = { 55,56,57,58,59,60,61,62,63,64,65,66,67 }; | |
221 | static u16 dib3000mb_bandwidth_6mhz[] = | |
222 | { 0, 33, 53312, 112, 46635, 563, 36565, 0, 1000, 0, 1010, 1, 45264 }; | |
223 | ||
224 | static u16 dib3000mb_bandwidth_7mhz[] = | |
225 | { 0, 28, 64421, 96, 39973, 483, 3255, 0, 1000, 0, 1010, 1, 45264 }; | |
226 | ||
227 | static u16 dib3000mb_bandwidth_8mhz[] = | |
228 | { 0, 25, 23600, 84, 34976, 422, 43808, 0, 1000, 0, 1010, 1, 45264 }; | |
229 | ||
230 | #define DIB3000MB_REG_UNK_68 ( 68) | |
231 | #define DIB3000MB_UNK_68 ( 0) | |
232 | ||
233 | #define DIB3000MB_REG_UNK_69 ( 69) | |
234 | #define DIB3000MB_UNK_69 ( 0) | |
235 | ||
236 | #define DIB3000MB_REG_UNK_71 ( 71) | |
237 | #define DIB3000MB_UNK_71 ( 0) | |
238 | ||
239 | #define DIB3000MB_REG_UNK_77 ( 77) | |
240 | #define DIB3000MB_UNK_77 ( 6) | |
241 | ||
242 | #define DIB3000MB_REG_UNK_78 ( 78) | |
243 | #define DIB3000MB_UNK_78 (0x0080) | |
244 | ||
245 | /* isi */ | |
246 | #define DIB3000MB_REG_ISI ( 79) | |
247 | #define DIB3000MB_ISI_ACTIVATE ( 0) | |
248 | #define DIB3000MB_ISI_INHIBIT ( 1) | |
249 | ||
250 | /* sync impovement */ | |
251 | #define DIB3000MB_REG_SYNC_IMPROVEMENT ( 84) | |
252 | #define DIB3000MB_SYNC_IMPROVE_2K_1_8 ( 3) | |
253 | #define DIB3000MB_SYNC_IMPROVE_DEFAULT ( 0) | |
254 | ||
255 | /* phase noise compensation inhibition */ | |
256 | #define DIB3000MB_REG_PHASE_NOISE ( 87) | |
257 | #define DIB3000MB_PHASE_NOISE_DEFAULT ( 0) | |
258 | ||
259 | #define DIB3000MB_REG_UNK_92 ( 92) | |
260 | #define DIB3000MB_UNK_92 (0x0080) | |
261 | ||
262 | #define DIB3000MB_REG_UNK_96 ( 96) | |
263 | #define DIB3000MB_UNK_96 (0x0010) | |
264 | ||
265 | #define DIB3000MB_REG_UNK_97 ( 97) | |
266 | #define DIB3000MB_UNK_97 (0x0009) | |
267 | ||
268 | /* mobile mode ??? */ | |
269 | #define DIB3000MB_REG_MOBILE_MODE ( 101) | |
270 | #define DIB3000MB_MOBILE_MODE_ON ( 1) | |
271 | #define DIB3000MB_MOBILE_MODE_OFF ( 0) | |
272 | ||
273 | #define DIB3000MB_REG_UNK_106 ( 106) | |
274 | #define DIB3000MB_UNK_106 (0x0080) | |
275 | ||
276 | #define DIB3000MB_REG_UNK_107 ( 107) | |
277 | #define DIB3000MB_UNK_107 (0x0080) | |
278 | ||
279 | #define DIB3000MB_REG_UNK_108 ( 108) | |
280 | #define DIB3000MB_UNK_108 (0x0080) | |
281 | ||
282 | /* fft */ | |
283 | #define DIB3000MB_REG_UNK_121 ( 121) | |
284 | #define DIB3000MB_UNK_121_2K ( 7) | |
285 | #define DIB3000MB_UNK_121_DEFAULT ( 5) | |
286 | ||
287 | #define DIB3000MB_REG_UNK_122 ( 122) | |
288 | #define DIB3000MB_UNK_122 ( 2867) | |
289 | ||
290 | /* QAM for mobile mode */ | |
291 | #define DIB3000MB_REG_MOBILE_MODE_QAM ( 126) | |
292 | #define DIB3000MB_MOBILE_MODE_QAM_64 ( 3) | |
293 | #define DIB3000MB_MOBILE_MODE_QAM_QPSK_16 ( 1) | |
294 | #define DIB3000MB_MOBILE_MODE_QAM_OFF ( 0) | |
295 | ||
296 | /* | |
297 | * data diversity when having more than one chip on-board | |
298 | * see also DIB3000MB_OUTPUT_MODE_DATA_DIVERSITY | |
299 | */ | |
300 | #define DIB3000MB_REG_DATA_IN_DIVERSITY ( 127) | |
301 | #define DIB3000MB_DATA_DIVERSITY_IN_OFF ( 0) | |
302 | #define DIB3000MB_DATA_DIVERSITY_IN_ON ( 2) | |
303 | ||
304 | /* vit hrch */ | |
305 | #define DIB3000MB_REG_VIT_HRCH ( 128) | |
306 | ||
307 | /* vit code rate */ | |
308 | #define DIB3000MB_REG_VIT_CODE_RATE ( 129) | |
309 | ||
310 | /* vit select hp */ | |
311 | #define DIB3000MB_REG_VIT_HP ( 130) | |
312 | ||
313 | /* time frame for Bit-Error-Rate calculation */ | |
314 | #define DIB3000MB_REG_BERLEN ( 135) | |
315 | #define DIB3000MB_BERLEN_LONG ( 0) | |
316 | #define DIB3000MB_BERLEN_DEFAULT ( 1) | |
317 | #define DIB3000MB_BERLEN_MEDIUM ( 2) | |
318 | #define DIB3000MB_BERLEN_SHORT ( 3) | |
319 | ||
320 | /* 142 - 152 FIFO parameters | |
321 | * which is what ? | |
322 | */ | |
323 | ||
324 | #define DIB3000MB_REG_FIFO_142 ( 142) | |
325 | #define DIB3000MB_FIFO_142 ( 0) | |
326 | ||
327 | /* MPEG2 TS output mode */ | |
328 | #define DIB3000MB_REG_MPEG2_OUT_MODE ( 143) | |
329 | #define DIB3000MB_MPEG2_OUT_MODE_204 ( 0) | |
330 | #define DIB3000MB_MPEG2_OUT_MODE_188 ( 1) | |
331 | ||
332 | #define DIB3000MB_REG_PID_PARSE ( 144) | |
333 | #define DIB3000MB_PID_PARSE_INHIBIT ( 0) | |
334 | #define DIB3000MB_PID_PARSE_ACTIVATE ( 1) | |
335 | ||
336 | #define DIB3000MB_REG_FIFO ( 145) | |
337 | #define DIB3000MB_FIFO_INHIBIT ( 1) | |
338 | #define DIB3000MB_FIFO_ACTIVATE ( 0) | |
339 | ||
340 | #define DIB3000MB_REG_FIFO_146 ( 146) | |
341 | #define DIB3000MB_FIFO_146 ( 3) | |
342 | ||
343 | #define DIB3000MB_REG_FIFO_147 ( 147) | |
344 | #define DIB3000MB_FIFO_147 (0x0100) | |
345 | ||
346 | /* | |
347 | * pidfilter | |
348 | * it is not a hardware pidfilter but a filter which drops all pids | |
349 | * except the ones set. Necessary because of the limited USB1.1 bandwidth. | |
350 | * regs 153-168 | |
351 | */ | |
352 | ||
353 | #define DIB3000MB_REG_FIRST_PID ( 153) | |
354 | #define DIB3000MB_NUM_PIDS ( 16) | |
355 | ||
356 | /* | |
357 | * output mode | |
358 | * USB devices have to use 'slave'-mode | |
359 | * see also DIB3000MB_REG_ELECT_OUT_MODE | |
360 | */ | |
361 | #define DIB3000MB_REG_OUTPUT_MODE ( 169) | |
362 | #define DIB3000MB_OUTPUT_MODE_GATED_CLK ( 0) | |
363 | #define DIB3000MB_OUTPUT_MODE_CONT_CLK ( 1) | |
364 | #define DIB3000MB_OUTPUT_MODE_SERIAL ( 2) | |
365 | #define DIB3000MB_OUTPUT_MODE_DATA_DIVERSITY ( 5) | |
366 | #define DIB3000MB_OUTPUT_MODE_SLAVE ( 6) | |
367 | ||
368 | /* irq event mask */ | |
369 | #define DIB3000MB_REG_IRQ_EVENT_MASK ( 170) | |
370 | #define DIB3000MB_IRQ_EVENT_MASK ( 0) | |
371 | ||
372 | /* filter coefficients */ | |
373 | static u16 dib3000mb_reg_filter_coeffs[] = { | |
374 | 171, 172, 173, 174, 175, 176, 177, 178, | |
375 | 179, 180, 181, 182, 183, 184, 185, 186, | |
376 | 188, 189, 190, 191, 192, 194 | |
377 | }; | |
378 | ||
379 | static u16 dib3000mb_filter_coeffs[] = { | |
380 | 226, 160, 29, | |
776338e1 | 381 | 979, 998, 19, |
1da177e4 LT |
382 | 22, 1019, 1006, |
383 | 1022, 12, 6, | |
384 | 1017, 1017, 3, | |
385 | 6, 1019, | |
386 | 1021, 2, 3, | |
387 | 1, 0, | |
388 | }; | |
389 | ||
390 | /* | |
391 | * mobile algorithm (when you are moving with your device) | |
392 | * but not faster than 90 km/h | |
393 | */ | |
394 | #define DIB3000MB_REG_MOBILE_ALGO ( 195) | |
395 | #define DIB3000MB_MOBILE_ALGO_ON ( 0) | |
396 | #define DIB3000MB_MOBILE_ALGO_OFF ( 1) | |
397 | ||
398 | /* multiple demodulators algorithm */ | |
399 | #define DIB3000MB_REG_MULTI_DEMOD_MSB ( 206) | |
400 | #define DIB3000MB_REG_MULTI_DEMOD_LSB ( 207) | |
401 | ||
402 | /* terminator, no more demods */ | |
403 | #define DIB3000MB_MULTI_DEMOD_MSB ( 32767) | |
404 | #define DIB3000MB_MULTI_DEMOD_LSB ( 4095) | |
405 | ||
406 | /* bring the device into a known */ | |
407 | #define DIB3000MB_REG_RESET_DEVICE ( 1024) | |
408 | #define DIB3000MB_RESET_DEVICE (0x812c) | |
409 | #define DIB3000MB_RESET_DEVICE_RST ( 0) | |
410 | ||
411 | /* hardware clock configuration */ | |
412 | #define DIB3000MB_REG_CLOCK ( 1027) | |
413 | #define DIB3000MB_CLOCK_DEFAULT (0x9000) | |
414 | #define DIB3000MB_CLOCK_DIVERSITY (0x92b0) | |
415 | ||
416 | /* power down config */ | |
417 | #define DIB3000MB_REG_POWER_CONTROL ( 1028) | |
418 | #define DIB3000MB_POWER_DOWN ( 1) | |
419 | #define DIB3000MB_POWER_UP ( 0) | |
420 | ||
421 | /* electrical output mode */ | |
422 | #define DIB3000MB_REG_ELECT_OUT_MODE ( 1029) | |
423 | #define DIB3000MB_ELECT_OUT_MODE_OFF ( 0) | |
424 | #define DIB3000MB_ELECT_OUT_MODE_ON ( 1) | |
425 | ||
426 | /* set the tuner i2c address */ | |
427 | #define DIB3000MB_REG_TUNER ( 1089) | |
428 | ||
429 | /* monitoring registers (read only) */ | |
430 | ||
431 | /* agc loop locked (size: 1) */ | |
432 | #define DIB3000MB_REG_AGC_LOCK ( 324) | |
433 | ||
434 | /* agc power (size: 16) */ | |
435 | #define DIB3000MB_REG_AGC_POWER ( 325) | |
436 | ||
437 | /* agc1 value (16) */ | |
438 | #define DIB3000MB_REG_AGC1_VALUE ( 326) | |
439 | ||
440 | /* agc2 value (16) */ | |
441 | #define DIB3000MB_REG_AGC2_VALUE ( 327) | |
442 | ||
443 | /* total RF power (16), can be used for signal strength */ | |
444 | #define DIB3000MB_REG_RF_POWER ( 328) | |
445 | ||
446 | /* dds_frequency with offset (24) */ | |
447 | #define DIB3000MB_REG_DDS_VALUE_MSB ( 339) | |
448 | #define DIB3000MB_REG_DDS_VALUE_LSB ( 340) | |
449 | ||
450 | /* timing offset signed (24) */ | |
451 | #define DIB3000MB_REG_TIMING_OFFSET_MSB ( 341) | |
452 | #define DIB3000MB_REG_TIMING_OFFSET_LSB ( 342) | |
453 | ||
454 | /* fft start position (13) */ | |
455 | #define DIB3000MB_REG_FFT_WINDOW_POS ( 353) | |
456 | ||
457 | /* carriers locked (1) */ | |
458 | #define DIB3000MB_REG_CARRIER_LOCK ( 355) | |
459 | ||
460 | /* noise power (24) */ | |
461 | #define DIB3000MB_REG_NOISE_POWER_MSB ( 372) | |
462 | #define DIB3000MB_REG_NOISE_POWER_LSB ( 373) | |
463 | ||
464 | #define DIB3000MB_REG_MOBILE_NOISE_MSB ( 374) | |
465 | #define DIB3000MB_REG_MOBILE_NOISE_LSB ( 375) | |
466 | ||
467 | /* | |
468 | * signal power (16), this and the above can be | |
469 | * used to calculate the signal/noise - ratio | |
470 | */ | |
471 | #define DIB3000MB_REG_SIGNAL_POWER ( 380) | |
472 | ||
473 | /* mer (24) */ | |
474 | #define DIB3000MB_REG_MER_MSB ( 381) | |
475 | #define DIB3000MB_REG_MER_LSB ( 382) | |
476 | ||
477 | /* | |
478 | * Transmission Parameter Signalling (TPS) | |
479 | * the following registers can be used to get TPS-information. | |
480 | * The values are according to the DVB-T standard. | |
481 | */ | |
482 | ||
483 | /* TPS locked (1) */ | |
484 | #define DIB3000MB_REG_TPS_LOCK ( 394) | |
485 | ||
486 | /* QAM from TPS (2) (values according to DIB3000MB_REG_QAM) */ | |
487 | #define DIB3000MB_REG_TPS_QAM ( 398) | |
488 | ||
489 | /* hierarchy from TPS (1) */ | |
490 | #define DIB3000MB_REG_TPS_HRCH ( 399) | |
491 | ||
492 | /* alpha from TPS (3) (values according to DIB3000MB_REG_VIT_ALPHA) */ | |
493 | #define DIB3000MB_REG_TPS_VIT_ALPHA ( 400) | |
494 | ||
495 | /* code rate high priority from TPS (3) (values according to DIB3000MB_FEC_*) */ | |
496 | #define DIB3000MB_REG_TPS_CODE_RATE_HP ( 401) | |
497 | ||
498 | /* code rate low priority from TPS (3) if DIB3000MB_REG_TPS_VIT_ALPHA */ | |
499 | #define DIB3000MB_REG_TPS_CODE_RATE_LP ( 402) | |
500 | ||
501 | /* guard time from TPS (2) (values according to DIB3000MB_REG_GUARD_TIME */ | |
502 | #define DIB3000MB_REG_TPS_GUARD_TIME ( 403) | |
503 | ||
504 | /* fft size from TPS (2) (values according to DIB3000MB_REG_FFT) */ | |
505 | #define DIB3000MB_REG_TPS_FFT ( 404) | |
506 | ||
507 | /* cell id from TPS (16) */ | |
508 | #define DIB3000MB_REG_TPS_CELL_ID ( 406) | |
509 | ||
510 | /* TPS (68) */ | |
511 | #define DIB3000MB_REG_TPS_1 ( 408) | |
512 | #define DIB3000MB_REG_TPS_2 ( 409) | |
513 | #define DIB3000MB_REG_TPS_3 ( 410) | |
514 | #define DIB3000MB_REG_TPS_4 ( 411) | |
515 | #define DIB3000MB_REG_TPS_5 ( 412) | |
516 | ||
517 | /* bit error rate (before RS correction) (21) */ | |
518 | #define DIB3000MB_REG_BER_MSB ( 414) | |
519 | #define DIB3000MB_REG_BER_LSB ( 415) | |
520 | ||
521 | /* packet error rate (uncorrected TS packets) (16) */ | |
522 | #define DIB3000MB_REG_PACKET_ERROR_RATE ( 417) | |
523 | ||
524 | /* uncorrected packet count (16) */ | |
525 | #define DIB3000MB_REG_UNC ( 420) | |
526 | ||
527 | /* viterbi locked (1) */ | |
528 | #define DIB3000MB_REG_VIT_LCK ( 421) | |
529 | ||
530 | /* viterbi inidcator (16) */ | |
531 | #define DIB3000MB_REG_VIT_INDICATOR ( 422) | |
532 | ||
533 | /* transport stream sync lock (1) */ | |
534 | #define DIB3000MB_REG_TS_SYNC_LOCK ( 423) | |
535 | ||
536 | /* transport stream RS lock (1) */ | |
537 | #define DIB3000MB_REG_TS_RS_LOCK ( 424) | |
538 | ||
539 | /* lock mask 0 value (1) */ | |
540 | #define DIB3000MB_REG_LOCK0_VALUE ( 425) | |
541 | ||
542 | /* lock mask 1 value (1) */ | |
543 | #define DIB3000MB_REG_LOCK1_VALUE ( 426) | |
544 | ||
545 | /* lock mask 2 value (1) */ | |
546 | #define DIB3000MB_REG_LOCK2_VALUE ( 427) | |
547 | ||
548 | /* interrupt pending for auto search */ | |
549 | #define DIB3000MB_REG_AS_IRQ_PENDING ( 434) | |
550 | ||
551 | #endif |