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fc7669c6 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1da177e4 LT |
2 | /* |
3 | * Frontend driver for mobile DVB-T demodulator DiBcom 3000M-B | |
4 | * DiBcom (http://www.dibcom.fr/) | |
5 | * | |
99e44da7 | 6 | * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@posteo.de) |
1da177e4 LT |
7 | * |
8 | * based on GPL code from DibCom, which has | |
9 | * | |
99e44da7 | 10 | * Copyright (C) 2004 Amaury Demol for DiBcom |
1da177e4 | 11 | * |
1da177e4 LT |
12 | * Acknowledgements |
13 | * | |
99e44da7 | 14 | * Amaury Demol from DiBcom for providing specs and driver |
1da177e4 LT |
15 | * sources, on which this driver (and the dvb-dibusb) are based. |
16 | * | |
577a7ad3 | 17 | * see Documentation/driver-api/media/drivers/dvb-usb.rst for more information |
1da177e4 LT |
18 | */ |
19 | ||
585e3227 MCC |
20 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
21 | ||
1da177e4 | 22 | #include <linux/kernel.h> |
1da177e4 | 23 | #include <linux/module.h> |
1da177e4 LT |
24 | #include <linux/init.h> |
25 | #include <linux/delay.h> | |
4e57b681 TS |
26 | #include <linux/string.h> |
27 | #include <linux/slab.h> | |
1da177e4 | 28 | |
fada1935 | 29 | #include <media/dvb_frontend.h> |
74340b0a | 30 | |
1da177e4 | 31 | #include "dib3000.h" |
74340b0a | 32 | #include "dib3000mb_priv.h" |
1da177e4 LT |
33 | |
34 | /* Version information */ | |
35 | #define DRIVER_VERSION "0.1" | |
36 | #define DRIVER_DESC "DiBcom 3000M-B DVB-T demodulator" | |
99e44da7 | 37 | #define DRIVER_AUTHOR "Patrick Boettcher, patrick.boettcher@posteo.de" |
1da177e4 | 38 | |
1da177e4 LT |
39 | static int debug; |
40 | module_param(debug, int, 0644); | |
41 | MODULE_PARM_DESC(debug, "set debugging level (1=info,2=xfer,4=setfe,8=getfe (|-able))."); | |
9059cd44 | 42 | |
585e3227 MCC |
43 | #define deb_info(args...) dprintk(0x01, args) |
44 | #define deb_i2c(args...) dprintk(0x02, args) | |
45 | #define deb_srch(args...) dprintk(0x04, args) | |
46 | #define deb_info(args...) dprintk(0x01, args) | |
47 | #define deb_xfer(args...) dprintk(0x02, args) | |
48 | #define deb_setf(args...) dprintk(0x04, args) | |
49 | #define deb_getf(args...) dprintk(0x08, args) | |
1da177e4 | 50 | |
74340b0a PB |
51 | static int dib3000_read_reg(struct dib3000_state *state, u16 reg) |
52 | { | |
53 | u8 wb[] = { ((reg >> 8) | 0x80) & 0xff, reg & 0xff }; | |
54 | u8 rb[2]; | |
55 | struct i2c_msg msg[] = { | |
56 | { .addr = state->config.demod_address, .flags = 0, .buf = wb, .len = 2 }, | |
57 | { .addr = state->config.demod_address, .flags = I2C_M_RD, .buf = rb, .len = 2 }, | |
58 | }; | |
59 | ||
60 | if (i2c_transfer(state->i2c, msg, 2) != 2) | |
61 | deb_i2c("i2c read error\n"); | |
62 | ||
63 | deb_i2c("reading i2c bus (reg: %5d 0x%04x, val: %5d 0x%04x)\n",reg,reg, | |
64 | (rb[0] << 8) | rb[1],(rb[0] << 8) | rb[1]); | |
65 | ||
66 | return (rb[0] << 8) | rb[1]; | |
67 | } | |
68 | ||
69 | static int dib3000_write_reg(struct dib3000_state *state, u16 reg, u16 val) | |
70 | { | |
71 | u8 b[] = { | |
72 | (reg >> 8) & 0xff, reg & 0xff, | |
73 | (val >> 8) & 0xff, val & 0xff, | |
74 | }; | |
75 | struct i2c_msg msg[] = { | |
76 | { .addr = state->config.demod_address, .flags = 0, .buf = b, .len = 4 } | |
77 | }; | |
78 | deb_i2c("writing i2c bus (reg: %5d 0x%04x, val: %5d 0x%04x)\n",reg,reg,val,val); | |
79 | ||
80 | return i2c_transfer(state->i2c,msg, 1) != 1 ? -EREMOTEIO : 0; | |
81 | } | |
82 | ||
83 | static int dib3000_search_status(u16 irq,u16 lock) | |
84 | { | |
85 | if (irq & 0x02) { | |
86 | if (lock & 0x01) { | |
87 | deb_srch("auto search succeeded\n"); | |
88 | return 1; // auto search succeeded | |
89 | } else { | |
90 | deb_srch("auto search not successful\n"); | |
91 | return 0; // auto search failed | |
92 | } | |
93 | } else if (irq & 0x01) { | |
94 | deb_srch("auto search failed\n"); | |
95 | return 0; // auto search failed | |
96 | } | |
97 | return -1; // try again | |
98 | } | |
99 | ||
100 | /* for auto search */ | |
101 | static u16 dib3000_seq[2][2][2] = /* fft,gua, inv */ | |
102 | { /* fft */ | |
103 | { /* gua */ | |
104 | { 0, 1 }, /* 0 0 { 0,1 } */ | |
105 | { 3, 9 }, /* 0 1 { 0,1 } */ | |
106 | }, | |
107 | { | |
108 | { 2, 5 }, /* 1 0 { 0,1 } */ | |
109 | { 6, 11 }, /* 1 1 { 0,1 } */ | |
110 | } | |
111 | }; | |
112 | ||
7e3e68bc MCC |
113 | static int dib3000mb_get_frontend(struct dvb_frontend* fe, |
114 | struct dtv_frontend_properties *c); | |
1da177e4 | 115 | |
fe084929 | 116 | static int dib3000mb_set_frontend(struct dvb_frontend *fe, int tuner) |
1da177e4 | 117 | { |
b8742700 | 118 | struct dib3000_state* state = fe->demodulator_priv; |
fe084929 | 119 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
0df289a2 | 120 | enum fe_code_rate fe_cr = FEC_NONE; |
1da177e4 LT |
121 | int search_state, seq; |
122 | ||
dea74869 | 123 | if (tuner && fe->ops.tuner_ops.set_params) { |
14d24d14 | 124 | fe->ops.tuner_ops.set_params(fe); |
dea74869 | 125 | if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); |
1da177e4 | 126 | |
fe084929 MCC |
127 | switch (c->bandwidth_hz) { |
128 | case 8000000: | |
1da177e4 LT |
129 | wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]); |
130 | wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz); | |
131 | break; | |
fe084929 | 132 | case 7000000: |
1da177e4 LT |
133 | wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[1]); |
134 | wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_7mhz); | |
135 | break; | |
fe084929 | 136 | case 6000000: |
1da177e4 LT |
137 | wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[0]); |
138 | wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_6mhz); | |
139 | break; | |
fe084929 | 140 | case 0: |
1da177e4 LT |
141 | return -EOPNOTSUPP; |
142 | default: | |
585e3227 | 143 | pr_err("unknown bandwidth value.\n"); |
1da177e4 LT |
144 | return -EINVAL; |
145 | } | |
585e3227 | 146 | deb_setf("bandwidth: %d MHZ\n", c->bandwidth_hz / 1000000); |
1da177e4 LT |
147 | } |
148 | wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4); | |
149 | ||
fe084929 | 150 | switch (c->transmission_mode) { |
1da177e4 | 151 | case TRANSMISSION_MODE_2K: |
585e3227 | 152 | deb_setf("transmission mode: 2k\n"); |
1da177e4 LT |
153 | wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_2K); |
154 | break; | |
155 | case TRANSMISSION_MODE_8K: | |
585e3227 | 156 | deb_setf("transmission mode: 8k\n"); |
1da177e4 LT |
157 | wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_8K); |
158 | break; | |
159 | case TRANSMISSION_MODE_AUTO: | |
585e3227 | 160 | deb_setf("transmission mode: auto\n"); |
1da177e4 LT |
161 | break; |
162 | default: | |
163 | return -EINVAL; | |
164 | } | |
165 | ||
fe084929 | 166 | switch (c->guard_interval) { |
1da177e4 | 167 | case GUARD_INTERVAL_1_32: |
585e3227 | 168 | deb_setf("guard 1_32\n"); |
1da177e4 LT |
169 | wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_32); |
170 | break; | |
171 | case GUARD_INTERVAL_1_16: | |
585e3227 | 172 | deb_setf("guard 1_16\n"); |
1da177e4 LT |
173 | wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_16); |
174 | break; | |
175 | case GUARD_INTERVAL_1_8: | |
585e3227 | 176 | deb_setf("guard 1_8\n"); |
1da177e4 LT |
177 | wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_8); |
178 | break; | |
179 | case GUARD_INTERVAL_1_4: | |
585e3227 | 180 | deb_setf("guard 1_4\n"); |
1da177e4 LT |
181 | wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_4); |
182 | break; | |
183 | case GUARD_INTERVAL_AUTO: | |
585e3227 | 184 | deb_setf("guard auto\n"); |
1da177e4 LT |
185 | break; |
186 | default: | |
187 | return -EINVAL; | |
188 | } | |
189 | ||
fe084929 | 190 | switch (c->inversion) { |
1da177e4 | 191 | case INVERSION_OFF: |
585e3227 | 192 | deb_setf("inversion off\n"); |
1da177e4 LT |
193 | wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_OFF); |
194 | break; | |
195 | case INVERSION_AUTO: | |
585e3227 | 196 | deb_setf("inversion auto\n"); |
1da177e4 LT |
197 | break; |
198 | case INVERSION_ON: | |
585e3227 | 199 | deb_setf("inversion on\n"); |
1da177e4 LT |
200 | wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_ON); |
201 | break; | |
202 | default: | |
203 | return -EINVAL; | |
204 | } | |
205 | ||
fe084929 | 206 | switch (c->modulation) { |
1da177e4 | 207 | case QPSK: |
585e3227 | 208 | deb_setf("modulation: qpsk\n"); |
1da177e4 LT |
209 | wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_QPSK); |
210 | break; | |
211 | case QAM_16: | |
585e3227 | 212 | deb_setf("modulation: qam16\n"); |
1da177e4 LT |
213 | wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_16QAM); |
214 | break; | |
215 | case QAM_64: | |
585e3227 | 216 | deb_setf("modulation: qam64\n"); |
1da177e4 LT |
217 | wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_64QAM); |
218 | break; | |
219 | case QAM_AUTO: | |
220 | break; | |
221 | default: | |
222 | return -EINVAL; | |
223 | } | |
fe084929 | 224 | switch (c->hierarchy) { |
1da177e4 | 225 | case HIERARCHY_NONE: |
585e3227 | 226 | deb_setf("hierarchy: none\n"); |
df561f66 | 227 | fallthrough; |
1da177e4 | 228 | case HIERARCHY_1: |
585e3227 | 229 | deb_setf("hierarchy: alpha=1\n"); |
1da177e4 LT |
230 | wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_1); |
231 | break; | |
232 | case HIERARCHY_2: | |
585e3227 | 233 | deb_setf("hierarchy: alpha=2\n"); |
1da177e4 LT |
234 | wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_2); |
235 | break; | |
236 | case HIERARCHY_4: | |
585e3227 | 237 | deb_setf("hierarchy: alpha=4\n"); |
1da177e4 LT |
238 | wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_4); |
239 | break; | |
240 | case HIERARCHY_AUTO: | |
585e3227 | 241 | deb_setf("hierarchy: alpha=auto\n"); |
1da177e4 LT |
242 | break; |
243 | default: | |
244 | return -EINVAL; | |
245 | } | |
246 | ||
fe084929 | 247 | if (c->hierarchy == HIERARCHY_NONE) { |
1da177e4 LT |
248 | wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_OFF); |
249 | wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_HP); | |
fe084929 MCC |
250 | fe_cr = c->code_rate_HP; |
251 | } else if (c->hierarchy != HIERARCHY_AUTO) { | |
1da177e4 LT |
252 | wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_ON); |
253 | wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_LP); | |
fe084929 | 254 | fe_cr = c->code_rate_LP; |
1da177e4 | 255 | } |
1da177e4 LT |
256 | switch (fe_cr) { |
257 | case FEC_1_2: | |
585e3227 | 258 | deb_setf("fec: 1_2\n"); |
1da177e4 LT |
259 | wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_1_2); |
260 | break; | |
261 | case FEC_2_3: | |
585e3227 | 262 | deb_setf("fec: 2_3\n"); |
1da177e4 LT |
263 | wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_2_3); |
264 | break; | |
265 | case FEC_3_4: | |
585e3227 | 266 | deb_setf("fec: 3_4\n"); |
1da177e4 LT |
267 | wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_3_4); |
268 | break; | |
269 | case FEC_5_6: | |
585e3227 | 270 | deb_setf("fec: 5_6\n"); |
1da177e4 LT |
271 | wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_5_6); |
272 | break; | |
273 | case FEC_7_8: | |
585e3227 | 274 | deb_setf("fec: 7_8\n"); |
1da177e4 LT |
275 | wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_7_8); |
276 | break; | |
277 | case FEC_NONE: | |
585e3227 | 278 | deb_setf("fec: none\n"); |
1da177e4 LT |
279 | break; |
280 | case FEC_AUTO: | |
585e3227 | 281 | deb_setf("fec: auto\n"); |
1da177e4 LT |
282 | break; |
283 | default: | |
284 | return -EINVAL; | |
285 | } | |
286 | ||
287 | seq = dib3000_seq | |
fe084929 MCC |
288 | [c->transmission_mode == TRANSMISSION_MODE_AUTO] |
289 | [c->guard_interval == GUARD_INTERVAL_AUTO] | |
290 | [c->inversion == INVERSION_AUTO]; | |
1da177e4 LT |
291 | |
292 | deb_setf("seq? %d\n", seq); | |
293 | ||
294 | wr(DIB3000MB_REG_SEQ, seq); | |
295 | ||
296 | wr(DIB3000MB_REG_ISI, seq ? DIB3000MB_ISI_INHIBIT : DIB3000MB_ISI_ACTIVATE); | |
297 | ||
fe084929 MCC |
298 | if (c->transmission_mode == TRANSMISSION_MODE_2K) { |
299 | if (c->guard_interval == GUARD_INTERVAL_1_8) { | |
1da177e4 LT |
300 | wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_2K_1_8); |
301 | } else { | |
302 | wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_DEFAULT); | |
303 | } | |
304 | ||
305 | wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_2K); | |
306 | } else { | |
307 | wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_DEFAULT); | |
308 | } | |
309 | ||
310 | wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_OFF); | |
311 | wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF); | |
312 | wr(DIB3000MB_REG_MOBILE_MODE, DIB3000MB_MOBILE_MODE_OFF); | |
313 | ||
314 | wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_high); | |
315 | ||
316 | wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_ACTIVATE); | |
317 | ||
318 | wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC + DIB3000MB_RESTART_CTRL); | |
319 | wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF); | |
320 | ||
321 | /* wait for AGC lock */ | |
322 | msleep(70); | |
323 | ||
324 | wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low); | |
325 | ||
326 | /* something has to be auto searched */ | |
fe084929 MCC |
327 | if (c->modulation == QAM_AUTO || |
328 | c->hierarchy == HIERARCHY_AUTO || | |
1da177e4 | 329 | fe_cr == FEC_AUTO || |
fe084929 | 330 | c->inversion == INVERSION_AUTO) { |
1da177e4 LT |
331 | int as_count=0; |
332 | ||
333 | deb_setf("autosearch enabled.\n"); | |
334 | ||
335 | wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT); | |
336 | ||
337 | wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AUTO_SEARCH); | |
338 | wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF); | |
339 | ||
340 | while ((search_state = | |
341 | dib3000_search_status( | |
342 | rd(DIB3000MB_REG_AS_IRQ_PENDING), | |
343 | rd(DIB3000MB_REG_LOCK2_VALUE))) < 0 && as_count++ < 100) | |
344 | msleep(1); | |
345 | ||
585e3227 MCC |
346 | deb_setf("search_state after autosearch %d after %d checks\n", |
347 | search_state, as_count); | |
1da177e4 LT |
348 | |
349 | if (search_state == 1) { | |
7e3e68bc | 350 | if (dib3000mb_get_frontend(fe, c) == 0) { |
1da177e4 | 351 | deb_setf("reading tuning data from frontend succeeded.\n"); |
fe084929 | 352 | return dib3000mb_set_frontend(fe, 0); |
1da177e4 LT |
353 | } |
354 | } | |
355 | ||
356 | } else { | |
357 | wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_CTRL); | |
358 | wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF); | |
359 | } | |
360 | ||
361 | return 0; | |
362 | } | |
363 | ||
364 | static int dib3000mb_fe_init(struct dvb_frontend* fe, int mobile_mode) | |
365 | { | |
b8742700 | 366 | struct dib3000_state* state = fe->demodulator_priv; |
1da177e4 LT |
367 | |
368 | deb_info("dib3000mb is getting up.\n"); | |
369 | wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_UP); | |
370 | ||
371 | wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC); | |
372 | ||
373 | wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE); | |
374 | wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE_RST); | |
375 | ||
376 | wr(DIB3000MB_REG_CLOCK, DIB3000MB_CLOCK_DEFAULT); | |
377 | ||
378 | wr(DIB3000MB_REG_ELECT_OUT_MODE, DIB3000MB_ELECT_OUT_MODE_ON); | |
379 | ||
380 | wr(DIB3000MB_REG_DDS_FREQ_MSB, DIB3000MB_DDS_FREQ_MSB); | |
381 | wr(DIB3000MB_REG_DDS_FREQ_LSB, DIB3000MB_DDS_FREQ_LSB); | |
382 | ||
383 | wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]); | |
384 | ||
385 | wr_foreach(dib3000mb_reg_impulse_noise, | |
386 | dib3000mb_impulse_noise_values[DIB3000MB_IMPNOISE_OFF]); | |
387 | ||
388 | wr_foreach(dib3000mb_reg_agc_gain, dib3000mb_default_agc_gain); | |
389 | ||
390 | wr(DIB3000MB_REG_PHASE_NOISE, DIB3000MB_PHASE_NOISE_DEFAULT); | |
391 | ||
392 | wr_foreach(dib3000mb_reg_phase_noise, dib3000mb_default_noise_phase); | |
393 | ||
394 | wr_foreach(dib3000mb_reg_lock_duration, dib3000mb_default_lock_duration); | |
395 | ||
396 | wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low); | |
397 | ||
398 | wr(DIB3000MB_REG_LOCK0_MASK, DIB3000MB_LOCK0_DEFAULT); | |
399 | wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4); | |
400 | wr(DIB3000MB_REG_LOCK2_MASK, DIB3000MB_LOCK2_DEFAULT); | |
401 | wr(DIB3000MB_REG_SEQ, dib3000_seq[1][1][1]); | |
402 | ||
403 | wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz); | |
404 | ||
405 | wr(DIB3000MB_REG_UNK_68, DIB3000MB_UNK_68); | |
406 | wr(DIB3000MB_REG_UNK_69, DIB3000MB_UNK_69); | |
407 | wr(DIB3000MB_REG_UNK_71, DIB3000MB_UNK_71); | |
408 | wr(DIB3000MB_REG_UNK_77, DIB3000MB_UNK_77); | |
409 | wr(DIB3000MB_REG_UNK_78, DIB3000MB_UNK_78); | |
410 | wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT); | |
411 | wr(DIB3000MB_REG_UNK_92, DIB3000MB_UNK_92); | |
412 | wr(DIB3000MB_REG_UNK_96, DIB3000MB_UNK_96); | |
413 | wr(DIB3000MB_REG_UNK_97, DIB3000MB_UNK_97); | |
414 | wr(DIB3000MB_REG_UNK_106, DIB3000MB_UNK_106); | |
415 | wr(DIB3000MB_REG_UNK_107, DIB3000MB_UNK_107); | |
416 | wr(DIB3000MB_REG_UNK_108, DIB3000MB_UNK_108); | |
417 | wr(DIB3000MB_REG_UNK_122, DIB3000MB_UNK_122); | |
418 | wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF); | |
419 | wr(DIB3000MB_REG_BERLEN, DIB3000MB_BERLEN_DEFAULT); | |
420 | ||
421 | wr_foreach(dib3000mb_reg_filter_coeffs, dib3000mb_filter_coeffs); | |
422 | ||
423 | wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_ON); | |
424 | wr(DIB3000MB_REG_MULTI_DEMOD_MSB, DIB3000MB_MULTI_DEMOD_MSB); | |
425 | wr(DIB3000MB_REG_MULTI_DEMOD_LSB, DIB3000MB_MULTI_DEMOD_LSB); | |
426 | ||
427 | wr(DIB3000MB_REG_OUTPUT_MODE, DIB3000MB_OUTPUT_MODE_SLAVE); | |
428 | ||
429 | wr(DIB3000MB_REG_FIFO_142, DIB3000MB_FIFO_142); | |
430 | wr(DIB3000MB_REG_MPEG2_OUT_MODE, DIB3000MB_MPEG2_OUT_MODE_188); | |
431 | wr(DIB3000MB_REG_PID_PARSE, DIB3000MB_PID_PARSE_ACTIVATE); | |
432 | wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT); | |
433 | wr(DIB3000MB_REG_FIFO_146, DIB3000MB_FIFO_146); | |
434 | wr(DIB3000MB_REG_FIFO_147, DIB3000MB_FIFO_147); | |
435 | ||
436 | wr(DIB3000MB_REG_DATA_IN_DIVERSITY, DIB3000MB_DATA_DIVERSITY_IN_OFF); | |
437 | ||
1da177e4 LT |
438 | return 0; |
439 | } | |
440 | ||
7e3e68bc MCC |
441 | static int dib3000mb_get_frontend(struct dvb_frontend* fe, |
442 | struct dtv_frontend_properties *c) | |
1da177e4 | 443 | { |
b8742700 | 444 | struct dib3000_state* state = fe->demodulator_priv; |
0df289a2 | 445 | enum fe_code_rate *cr; |
1da177e4 LT |
446 | u16 tps_val; |
447 | int inv_test1,inv_test2; | |
448 | u32 dds_val, threshold = 0x800000; | |
449 | ||
450 | if (!rd(DIB3000MB_REG_TPS_LOCK)) | |
451 | return 0; | |
452 | ||
453 | dds_val = ((rd(DIB3000MB_REG_DDS_VALUE_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_VALUE_LSB); | |
585e3227 | 454 | deb_getf("DDS_VAL: %x %x %x\n", dds_val, rd(DIB3000MB_REG_DDS_VALUE_MSB), rd(DIB3000MB_REG_DDS_VALUE_LSB)); |
1da177e4 LT |
455 | if (dds_val < threshold) |
456 | inv_test1 = 0; | |
457 | else if (dds_val == threshold) | |
458 | inv_test1 = 1; | |
459 | else | |
460 | inv_test1 = 2; | |
461 | ||
462 | dds_val = ((rd(DIB3000MB_REG_DDS_FREQ_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_FREQ_LSB); | |
585e3227 | 463 | deb_getf("DDS_FREQ: %x %x %x\n", dds_val, rd(DIB3000MB_REG_DDS_FREQ_MSB), rd(DIB3000MB_REG_DDS_FREQ_LSB)); |
1da177e4 LT |
464 | if (dds_val < threshold) |
465 | inv_test2 = 0; | |
466 | else if (dds_val == threshold) | |
467 | inv_test2 = 1; | |
468 | else | |
469 | inv_test2 = 2; | |
470 | ||
fe084929 | 471 | c->inversion = |
1da177e4 LT |
472 | ((inv_test2 == 2) && (inv_test1==1 || inv_test1==0)) || |
473 | ((inv_test2 == 0) && (inv_test1==1 || inv_test1==2)) ? | |
474 | INVERSION_ON : INVERSION_OFF; | |
475 | ||
fe084929 | 476 | deb_getf("inversion %d %d, %d\n", inv_test2, inv_test1, c->inversion); |
1da177e4 LT |
477 | |
478 | switch ((tps_val = rd(DIB3000MB_REG_TPS_QAM))) { | |
479 | case DIB3000_CONSTELLATION_QPSK: | |
585e3227 | 480 | deb_getf("QPSK\n"); |
fe084929 | 481 | c->modulation = QPSK; |
1da177e4 LT |
482 | break; |
483 | case DIB3000_CONSTELLATION_16QAM: | |
585e3227 | 484 | deb_getf("QAM16\n"); |
fe084929 | 485 | c->modulation = QAM_16; |
1da177e4 LT |
486 | break; |
487 | case DIB3000_CONSTELLATION_64QAM: | |
585e3227 | 488 | deb_getf("QAM64\n"); |
fe084929 | 489 | c->modulation = QAM_64; |
1da177e4 LT |
490 | break; |
491 | default: | |
585e3227 | 492 | pr_err("Unexpected constellation returned by TPS (%d)\n", tps_val); |
1da177e4 LT |
493 | break; |
494 | } | |
495 | deb_getf("TPS: %d\n", tps_val); | |
496 | ||
497 | if (rd(DIB3000MB_REG_TPS_HRCH)) { | |
498 | deb_getf("HRCH ON\n"); | |
fe084929 MCC |
499 | cr = &c->code_rate_LP; |
500 | c->code_rate_HP = FEC_NONE; | |
1da177e4 LT |
501 | switch ((tps_val = rd(DIB3000MB_REG_TPS_VIT_ALPHA))) { |
502 | case DIB3000_ALPHA_0: | |
585e3227 | 503 | deb_getf("HIERARCHY_NONE\n"); |
fe084929 | 504 | c->hierarchy = HIERARCHY_NONE; |
1da177e4 LT |
505 | break; |
506 | case DIB3000_ALPHA_1: | |
585e3227 | 507 | deb_getf("HIERARCHY_1\n"); |
fe084929 | 508 | c->hierarchy = HIERARCHY_1; |
1da177e4 LT |
509 | break; |
510 | case DIB3000_ALPHA_2: | |
585e3227 | 511 | deb_getf("HIERARCHY_2\n"); |
fe084929 | 512 | c->hierarchy = HIERARCHY_2; |
1da177e4 LT |
513 | break; |
514 | case DIB3000_ALPHA_4: | |
585e3227 | 515 | deb_getf("HIERARCHY_4\n"); |
fe084929 | 516 | c->hierarchy = HIERARCHY_4; |
1da177e4 LT |
517 | break; |
518 | default: | |
585e3227 | 519 | pr_err("Unexpected ALPHA value returned by TPS (%d)\n", tps_val); |
1da177e4 LT |
520 | break; |
521 | } | |
522 | deb_getf("TPS: %d\n", tps_val); | |
523 | ||
524 | tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_LP); | |
525 | } else { | |
526 | deb_getf("HRCH OFF\n"); | |
fe084929 MCC |
527 | cr = &c->code_rate_HP; |
528 | c->code_rate_LP = FEC_NONE; | |
529 | c->hierarchy = HIERARCHY_NONE; | |
1da177e4 LT |
530 | |
531 | tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_HP); | |
532 | } | |
533 | ||
534 | switch (tps_val) { | |
535 | case DIB3000_FEC_1_2: | |
585e3227 | 536 | deb_getf("FEC_1_2\n"); |
1da177e4 LT |
537 | *cr = FEC_1_2; |
538 | break; | |
539 | case DIB3000_FEC_2_3: | |
585e3227 | 540 | deb_getf("FEC_2_3\n"); |
1da177e4 LT |
541 | *cr = FEC_2_3; |
542 | break; | |
543 | case DIB3000_FEC_3_4: | |
585e3227 | 544 | deb_getf("FEC_3_4\n"); |
1da177e4 LT |
545 | *cr = FEC_3_4; |
546 | break; | |
547 | case DIB3000_FEC_5_6: | |
585e3227 | 548 | deb_getf("FEC_5_6\n"); |
1da177e4 LT |
549 | *cr = FEC_4_5; |
550 | break; | |
551 | case DIB3000_FEC_7_8: | |
585e3227 | 552 | deb_getf("FEC_7_8\n"); |
1da177e4 LT |
553 | *cr = FEC_7_8; |
554 | break; | |
555 | default: | |
585e3227 | 556 | pr_err("Unexpected FEC returned by TPS (%d)\n", tps_val); |
1da177e4 LT |
557 | break; |
558 | } | |
559 | deb_getf("TPS: %d\n",tps_val); | |
560 | ||
561 | switch ((tps_val = rd(DIB3000MB_REG_TPS_GUARD_TIME))) { | |
562 | case DIB3000_GUARD_TIME_1_32: | |
585e3227 | 563 | deb_getf("GUARD_INTERVAL_1_32\n"); |
fe084929 | 564 | c->guard_interval = GUARD_INTERVAL_1_32; |
1da177e4 LT |
565 | break; |
566 | case DIB3000_GUARD_TIME_1_16: | |
585e3227 | 567 | deb_getf("GUARD_INTERVAL_1_16\n"); |
fe084929 | 568 | c->guard_interval = GUARD_INTERVAL_1_16; |
1da177e4 LT |
569 | break; |
570 | case DIB3000_GUARD_TIME_1_8: | |
585e3227 | 571 | deb_getf("GUARD_INTERVAL_1_8\n"); |
fe084929 | 572 | c->guard_interval = GUARD_INTERVAL_1_8; |
1da177e4 LT |
573 | break; |
574 | case DIB3000_GUARD_TIME_1_4: | |
585e3227 | 575 | deb_getf("GUARD_INTERVAL_1_4\n"); |
fe084929 | 576 | c->guard_interval = GUARD_INTERVAL_1_4; |
1da177e4 LT |
577 | break; |
578 | default: | |
585e3227 | 579 | pr_err("Unexpected Guard Time returned by TPS (%d)\n", tps_val); |
1da177e4 LT |
580 | break; |
581 | } | |
582 | deb_getf("TPS: %d\n", tps_val); | |
583 | ||
584 | switch ((tps_val = rd(DIB3000MB_REG_TPS_FFT))) { | |
585 | case DIB3000_TRANSMISSION_MODE_2K: | |
585e3227 | 586 | deb_getf("TRANSMISSION_MODE_2K\n"); |
fe084929 | 587 | c->transmission_mode = TRANSMISSION_MODE_2K; |
1da177e4 LT |
588 | break; |
589 | case DIB3000_TRANSMISSION_MODE_8K: | |
585e3227 | 590 | deb_getf("TRANSMISSION_MODE_8K\n"); |
fe084929 | 591 | c->transmission_mode = TRANSMISSION_MODE_8K; |
1da177e4 LT |
592 | break; |
593 | default: | |
585e3227 | 594 | pr_err("unexpected transmission mode return by TPS (%d)\n", tps_val); |
1da177e4 LT |
595 | break; |
596 | } | |
597 | deb_getf("TPS: %d\n", tps_val); | |
598 | ||
599 | return 0; | |
600 | } | |
601 | ||
0df289a2 MCC |
602 | static int dib3000mb_read_status(struct dvb_frontend *fe, |
603 | enum fe_status *stat) | |
1da177e4 | 604 | { |
b8742700 | 605 | struct dib3000_state* state = fe->demodulator_priv; |
1da177e4 LT |
606 | |
607 | *stat = 0; | |
608 | ||
609 | if (rd(DIB3000MB_REG_AGC_LOCK)) | |
610 | *stat |= FE_HAS_SIGNAL; | |
611 | if (rd(DIB3000MB_REG_CARRIER_LOCK)) | |
612 | *stat |= FE_HAS_CARRIER; | |
613 | if (rd(DIB3000MB_REG_VIT_LCK)) | |
614 | *stat |= FE_HAS_VITERBI; | |
615 | if (rd(DIB3000MB_REG_TS_SYNC_LOCK)) | |
616 | *stat |= (FE_HAS_SYNC | FE_HAS_LOCK); | |
617 | ||
618 | deb_getf("actual status is %2x\n",*stat); | |
619 | ||
620 | deb_getf("autoval: tps: %d, qam: %d, hrch: %d, alpha: %d, hp: %d, lp: %d, guard: %d, fft: %d cell: %d\n", | |
621 | rd(DIB3000MB_REG_TPS_LOCK), | |
622 | rd(DIB3000MB_REG_TPS_QAM), | |
623 | rd(DIB3000MB_REG_TPS_HRCH), | |
624 | rd(DIB3000MB_REG_TPS_VIT_ALPHA), | |
625 | rd(DIB3000MB_REG_TPS_CODE_RATE_HP), | |
626 | rd(DIB3000MB_REG_TPS_CODE_RATE_LP), | |
627 | rd(DIB3000MB_REG_TPS_GUARD_TIME), | |
628 | rd(DIB3000MB_REG_TPS_FFT), | |
629 | rd(DIB3000MB_REG_TPS_CELL_ID)); | |
630 | ||
631 | //*stat = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK; | |
632 | return 0; | |
633 | } | |
634 | ||
635 | static int dib3000mb_read_ber(struct dvb_frontend* fe, u32 *ber) | |
636 | { | |
b8742700 | 637 | struct dib3000_state* state = fe->demodulator_priv; |
1da177e4 LT |
638 | |
639 | *ber = ((rd(DIB3000MB_REG_BER_MSB) << 16) | rd(DIB3000MB_REG_BER_LSB)); | |
640 | return 0; | |
641 | } | |
642 | ||
643 | /* see dib3000-watch dvb-apps for exact calcuations of signal_strength and snr */ | |
644 | static int dib3000mb_read_signal_strength(struct dvb_frontend* fe, u16 *strength) | |
645 | { | |
b8742700 | 646 | struct dib3000_state* state = fe->demodulator_priv; |
1da177e4 LT |
647 | |
648 | *strength = rd(DIB3000MB_REG_SIGNAL_POWER) * 0xffff / 0x170; | |
649 | return 0; | |
650 | } | |
651 | ||
652 | static int dib3000mb_read_snr(struct dvb_frontend* fe, u16 *snr) | |
653 | { | |
b8742700 | 654 | struct dib3000_state* state = fe->demodulator_priv; |
1da177e4 LT |
655 | short sigpow = rd(DIB3000MB_REG_SIGNAL_POWER); |
656 | int icipow = ((rd(DIB3000MB_REG_NOISE_POWER_MSB) & 0xff) << 16) | | |
657 | rd(DIB3000MB_REG_NOISE_POWER_LSB); | |
658 | *snr = (sigpow << 8) / ((icipow > 0) ? icipow : 1); | |
659 | return 0; | |
660 | } | |
661 | ||
662 | static int dib3000mb_read_unc_blocks(struct dvb_frontend* fe, u32 *unc) | |
663 | { | |
b8742700 | 664 | struct dib3000_state* state = fe->demodulator_priv; |
1da177e4 | 665 | |
776338e1 | 666 | *unc = rd(DIB3000MB_REG_PACKET_ERROR_RATE); |
1da177e4 LT |
667 | return 0; |
668 | } | |
669 | ||
670 | static int dib3000mb_sleep(struct dvb_frontend* fe) | |
671 | { | |
b8742700 | 672 | struct dib3000_state* state = fe->demodulator_priv; |
1da177e4 LT |
673 | deb_info("dib3000mb is going to bed.\n"); |
674 | wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_DOWN); | |
675 | return 0; | |
676 | } | |
677 | ||
678 | static int dib3000mb_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune) | |
679 | { | |
680 | tune->min_delay_ms = 800; | |
1da177e4 LT |
681 | return 0; |
682 | } | |
683 | ||
684 | static int dib3000mb_fe_init_nonmobile(struct dvb_frontend* fe) | |
685 | { | |
686 | return dib3000mb_fe_init(fe, 0); | |
687 | } | |
688 | ||
fe084929 | 689 | static int dib3000mb_set_frontend_and_tuner(struct dvb_frontend *fe) |
1da177e4 | 690 | { |
fe084929 | 691 | return dib3000mb_set_frontend(fe, 1); |
1da177e4 LT |
692 | } |
693 | ||
694 | static void dib3000mb_release(struct dvb_frontend* fe) | |
695 | { | |
b8742700 | 696 | struct dib3000_state *state = fe->demodulator_priv; |
1da177e4 LT |
697 | kfree(state); |
698 | } | |
699 | ||
700 | /* pid filter and transfer stuff */ | |
701 | static int dib3000mb_pid_control(struct dvb_frontend *fe,int index, int pid,int onoff) | |
702 | { | |
703 | struct dib3000_state *state = fe->demodulator_priv; | |
704 | pid = (onoff ? pid | DIB3000_ACTIVATE_PID_FILTERING : 0); | |
705 | wr(index+DIB3000MB_REG_FIRST_PID,pid); | |
706 | return 0; | |
707 | } | |
708 | ||
709 | static int dib3000mb_fifo_control(struct dvb_frontend *fe, int onoff) | |
710 | { | |
b8742700 | 711 | struct dib3000_state *state = fe->demodulator_priv; |
1da177e4 LT |
712 | |
713 | deb_xfer("%s fifo\n",onoff ? "enabling" : "disabling"); | |
714 | if (onoff) { | |
715 | wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_ACTIVATE); | |
716 | } else { | |
717 | wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT); | |
718 | } | |
719 | return 0; | |
720 | } | |
721 | ||
722 | static int dib3000mb_pid_parse(struct dvb_frontend *fe, int onoff) | |
723 | { | |
724 | struct dib3000_state *state = fe->demodulator_priv; | |
725 | deb_xfer("%s pid parsing\n",onoff ? "enabling" : "disabling"); | |
726 | wr(DIB3000MB_REG_PID_PARSE,onoff); | |
727 | return 0; | |
728 | } | |
729 | ||
730 | static int dib3000mb_tuner_pass_ctrl(struct dvb_frontend *fe, int onoff, u8 pll_addr) | |
731 | { | |
b8742700 | 732 | struct dib3000_state *state = fe->demodulator_priv; |
1da177e4 LT |
733 | if (onoff) { |
734 | wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_ENABLE(pll_addr)); | |
735 | } else { | |
736 | wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_DISABLE(pll_addr)); | |
737 | } | |
738 | return 0; | |
739 | } | |
740 | ||
bd336e63 | 741 | static const struct dvb_frontend_ops dib3000mb_ops; |
1da177e4 LT |
742 | |
743 | struct dvb_frontend* dib3000mb_attach(const struct dib3000_config* config, | |
744 | struct i2c_adapter* i2c, struct dib_fe_xfer_ops *xfer_ops) | |
745 | { | |
746 | struct dib3000_state* state = NULL; | |
747 | ||
748 | /* allocate memory for the internal state */ | |
7408187d | 749 | state = kzalloc(sizeof(struct dib3000_state), GFP_KERNEL); |
1da177e4 LT |
750 | if (state == NULL) |
751 | goto error; | |
1da177e4 LT |
752 | |
753 | /* setup the state */ | |
754 | state->i2c = i2c; | |
755 | memcpy(&state->config,config,sizeof(struct dib3000_config)); | |
1da177e4 LT |
756 | |
757 | /* check for the correct demod */ | |
758 | if (rd(DIB3000_REG_MANUFACTOR_ID) != DIB3000_I2C_ID_DIBCOM) | |
759 | goto error; | |
760 | ||
761 | if (rd(DIB3000_REG_DEVICE_ID) != DIB3000MB_DEVICE_ID) | |
762 | goto error; | |
763 | ||
764 | /* create dvb_frontend */ | |
dea74869 | 765 | memcpy(&state->frontend.ops, &dib3000mb_ops, sizeof(struct dvb_frontend_ops)); |
1da177e4 LT |
766 | state->frontend.demodulator_priv = state; |
767 | ||
768 | /* set the xfer operations */ | |
769 | xfer_ops->pid_parse = dib3000mb_pid_parse; | |
770 | xfer_ops->fifo_ctrl = dib3000mb_fifo_control; | |
771 | xfer_ops->pid_ctrl = dib3000mb_pid_control; | |
772 | xfer_ops->tuner_pass_ctrl = dib3000mb_tuner_pass_ctrl; | |
773 | ||
774 | return &state->frontend; | |
775 | ||
776 | error: | |
777 | kfree(state); | |
778 | return NULL; | |
779 | } | |
780 | ||
bd336e63 | 781 | static const struct dvb_frontend_ops dib3000mb_ops = { |
fe084929 | 782 | .delsys = { SYS_DVBT }, |
1da177e4 LT |
783 | .info = { |
784 | .name = "DiBcom 3000M-B DVB-T", | |
f1b1eabf MCC |
785 | .frequency_min_hz = 44250 * kHz, |
786 | .frequency_max_hz = 867250 * kHz, | |
787 | .frequency_stepsize_hz = 62500, | |
1da177e4 LT |
788 | .caps = FE_CAN_INVERSION_AUTO | |
789 | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | | |
790 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | | |
791 | FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | | |
792 | FE_CAN_TRANSMISSION_MODE_AUTO | | |
793 | FE_CAN_GUARD_INTERVAL_AUTO | | |
794 | FE_CAN_RECOVER | | |
795 | FE_CAN_HIERARCHY_AUTO, | |
796 | }, | |
797 | ||
798 | .release = dib3000mb_release, | |
799 | ||
800 | .init = dib3000mb_fe_init_nonmobile, | |
801 | .sleep = dib3000mb_sleep, | |
802 | ||
fe084929 MCC |
803 | .set_frontend = dib3000mb_set_frontend_and_tuner, |
804 | .get_frontend = dib3000mb_get_frontend, | |
1da177e4 LT |
805 | .get_tune_settings = dib3000mb_fe_get_tune_settings, |
806 | ||
807 | .read_status = dib3000mb_read_status, | |
808 | .read_ber = dib3000mb_read_ber, | |
809 | .read_signal_strength = dib3000mb_read_signal_strength, | |
810 | .read_snr = dib3000mb_read_snr, | |
811 | .read_ucblocks = dib3000mb_read_unc_blocks, | |
812 | }; | |
813 | ||
814 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
815 | MODULE_DESCRIPTION(DRIVER_DESC); | |
816 | MODULE_LICENSE("GPL"); | |
817 | ||
86495af1 | 818 | EXPORT_SYMBOL_GPL(dib3000mb_attach); |