[linux-block.git] / drivers / media / dvb-frontends / cxd2820r_t.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Sony CXD2820R demodulator driver
 *
 * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
 */


#include "cxd2820r_priv.h"

int cxd2820r_set_frontend_t(struct dvb_frontend *fe)
{
	struct cxd2820r_priv *priv = fe->demodulator_priv;
	struct i2c_client *client = priv->client[0];
	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
	int ret, bw_i;
	unsigned int utmp;
	u32 if_frequency;
	u8 buf[3], bw_param;
	u8 bw_params1[][5] = {
		{ 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */
		{ 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */
		{ 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */
	};
	u8 bw_params2[][2] = {
		{ 0x1f, 0xdc }, /* 6 MHz */
		{ 0x12, 0xf8 }, /* 7 MHz */
		{ 0x01, 0xe0 }, /* 8 MHz */
	};
	struct reg_val_mask tab[] = {
		{ 0x00080, 0x00, 0xff },
		{ 0x00081, 0x03, 0xff },
		{ 0x00085, 0x07, 0xff },
		{ 0x00088, 0x01, 0xff },

		{ 0x00070, priv->ts_mode, 0xff },
		{ 0x00071, !priv->ts_clk_inv << 4, 0x10 },
		{ 0x000cb, priv->if_agc_polarity << 6, 0x40 },
		{ 0x000a5, 0x00, 0x01 },
		{ 0x00082, 0x20, 0x60 },
		{ 0x000c2, 0xc3, 0xff },
		{ 0x0016a, 0x50, 0xff },
		{ 0x00427, 0x41, 0xff },
	};

	dev_dbg(&client->dev,
		"delivery_system=%d modulation=%d frequency=%u bandwidth_hz=%u inversion=%d\n",
		c->delivery_system, c->modulation, c->frequency,
		c->bandwidth_hz, c->inversion);

	switch (c->bandwidth_hz) {
	case 6000000:
		bw_i = 0;
		bw_param = 2;
		break;
	case 7000000:
		bw_i = 1;
		bw_param = 1;
		break;
	case 8000000:
		bw_i = 2;
		bw_param = 0;
		break;
	default:
		return -EINVAL;
	}

	/* program tuner */
	if (fe->ops.tuner_ops.set_params)
		fe->ops.tuner_ops.set_params(fe);

	if (priv->delivery_system != SYS_DVBT) {
		ret = cxd2820r_wr_reg_val_mask_tab(priv, tab, ARRAY_SIZE(tab));
		if (ret)
			goto error;
	}

	priv->delivery_system = SYS_DVBT;
	priv->ber_running = false; /* tune stops BER counter */

	/* program IF frequency */
	if (fe->ops.tuner_ops.get_if_frequency) {
		ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
		if (ret)
			goto error;
		dev_dbg(&client->dev, "if_frequency=%u\n", if_frequency);
	} else {
		ret = -EINVAL;
		goto error;
	}

	utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x1000000, CXD2820R_CLK);
	buf[0] = (utmp >> 16) & 0xff;
	buf[1] = (utmp >>  8) & 0xff;
	buf[2] = (utmp >>  0) & 0xff;
	ret = regmap_bulk_write(priv->regmap[0], 0x00b6, buf, 3);
	if (ret)
		goto error;

	ret = regmap_bulk_write(priv->regmap[0], 0x009f, bw_params1[bw_i], 5);
	if (ret)
		goto error;

	ret = regmap_update_bits(priv->regmap[0], 0x00d7, 0xc0, bw_param << 6);
	if (ret)
		goto error;

	ret = regmap_bulk_write(priv->regmap[0], 0x00d9, bw_params2[bw_i], 2);
	if (ret)
		goto error;

	ret = regmap_write(priv->regmap[0], 0x00ff, 0x08);
	if (ret)
		goto error;

	ret = regmap_write(priv->regmap[0], 0x00fe, 0x01);
	if (ret)
		goto error;

	return ret;
error:
	dev_dbg(&client->dev, "failed=%d\n", ret);
	return ret;
}

int cxd2820r_get_frontend_t(struct dvb_frontend *fe,
			    struct dtv_frontend_properties *c)
{
	struct cxd2820r_priv *priv = fe->demodulator_priv;
	struct i2c_client *client = priv->client[0];
	int ret;
	unsigned int utmp;
	u8 buf[2];

	dev_dbg(&client->dev, "\n");

	ret = regmap_bulk_read(priv->regmap[0], 0x002f, buf, sizeof(buf));
	if (ret)
		goto error;

	switch ((buf[0] >> 6) & 0x03) {
	case 0:
		c->modulation = QPSK;
		break;
	case 1:
		c->modulation = QAM_16;
		break;
	case 2:
		c->modulation = QAM_64;
		break;
	}

	switch ((buf[1] >> 1) & 0x03) {
	case 0:
		c->transmission_mode = TRANSMISSION_MODE_2K;
		break;
	case 1:
		c->transmission_mode = TRANSMISSION_MODE_8K;
		break;
	}

	switch ((buf[1] >> 3) & 0x03) {
	case 0:
		c->guard_interval = GUARD_INTERVAL_1_32;
		break;
	case 1:
		c->guard_interval = GUARD_INTERVAL_1_16;
		break;
	case 2:
		c->guard_interval = GUARD_INTERVAL_1_8;
		break;
	case 3:
		c->guard_interval = GUARD_INTERVAL_1_4;
		break;
	}

	switch ((buf[0] >> 3) & 0x07) {
	case 0:
		c->hierarchy = HIERARCHY_NONE;
		break;
	case 1:
		c->hierarchy = HIERARCHY_1;
		break;
	case 2:
		c->hierarchy = HIERARCHY_2;
		break;
	case 3:
		c->hierarchy = HIERARCHY_4;
		break;
	}

	switch ((buf[0] >> 0) & 0x07) {
	case 0:
		c->code_rate_HP = FEC_1_2;
		break;
	case 1:
		c->code_rate_HP = FEC_2_3;
		break;
	case 2:
		c->code_rate_HP = FEC_3_4;
		break;
	case 3:
		c->code_rate_HP = FEC_5_6;
		break;
	case 4:
		c->code_rate_HP = FEC_7_8;
		break;
	}

	switch ((buf[1] >> 5) & 0x07) {
	case 0:
		c->code_rate_LP = FEC_1_2;
		break;
	case 1:
		c->code_rate_LP = FEC_2_3;
		break;
	case 2:
		c->code_rate_LP = FEC_3_4;
		break;
	case 3:
		c->code_rate_LP = FEC_5_6;
		break;
	case 4:
		c->code_rate_LP = FEC_7_8;
		break;
	}

	ret = regmap_read(priv->regmap[0], 0x07c6, &utmp);
	if (ret)
		goto error;

	switch ((utmp >> 0) & 0x01) {
	case 0:
		c->inversion = INVERSION_OFF;
		break;
	case 1:
		c->inversion = INVERSION_ON;
		break;
	}

	return ret;
error:
	dev_dbg(&client->dev, "failed=%d\n", ret);
	return ret;
}

int cxd2820r_read_status_t(struct dvb_frontend *fe, enum fe_status *status)
{
	struct cxd2820r_priv *priv = fe->demodulator_priv;
	struct i2c_client *client = priv->client[0];
	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
	int ret;
	unsigned int utmp, utmp1, utmp2;
	u8 buf[3];

	/* Lock detection */
	ret = regmap_bulk_read(priv->regmap[0], 0x0010, &buf[0], 1);
	if (ret)
		goto error;
	ret = regmap_bulk_read(priv->regmap[0], 0x0073, &buf[1], 1);
	if (ret)
		goto error;

	utmp1 = (buf[0] >> 0) & 0x07;
	utmp2 = (buf[1] >> 3) & 0x01;

	if (utmp1 == 6 && utmp2 == 1) {
		*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
			  FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
	} else if (utmp1 == 6 || utmp2 == 1) {
		*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
			  FE_HAS_VITERBI | FE_HAS_SYNC;
	} else {
		*status = 0;
	}

	dev_dbg(&client->dev, "status=%02x raw=%*ph sync=%u ts=%u\n",
		*status, 2, buf, utmp1, utmp2);

	/* Signal strength */
	if (*status & FE_HAS_SIGNAL) {
		unsigned int strength;

		ret = regmap_bulk_read(priv->regmap[0], 0x0026, buf, 2);
		if (ret)
			goto error;

		utmp = buf[0] << 8 | buf[1] << 0;
		utmp = ~utmp & 0x0fff;
		/* Scale value to 0x0000-0xffff */
		strength = utmp << 4 | utmp >> 8;

		c->strength.len = 1;
		c->strength.stat[0].scale = FE_SCALE_RELATIVE;
		c->strength.stat[0].uvalue = strength;
	} else {
		c->strength.len = 1;
		c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
	}

	/* CNR */
	if (*status & FE_HAS_VITERBI) {
		unsigned int cnr;

		ret = regmap_bulk_read(priv->regmap[0], 0x002c, buf, 2);
		if (ret)
			goto error;

		utmp = buf[0] << 8 | buf[1] << 0;
		if (utmp)
			cnr = div_u64((u64)(intlog10(utmp)
				      - intlog10(32000 - utmp) + 55532585)
				      * 10000, (1 << 24));
		else
			cnr = 0;

		c->cnr.len = 1;
		c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
		c->cnr.stat[0].svalue = cnr;
	} else {
		c->cnr.len = 1;
		c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
	}

	/* BER */
	if (*status & FE_HAS_SYNC) {
		unsigned int post_bit_error;
		bool start_ber;

		if (priv->ber_running) {
			ret = regmap_bulk_read(priv->regmap[0], 0x0076, buf, 3);
			if (ret)
				goto error;

			if ((buf[2] >> 7) & 0x01) {
				post_bit_error = buf[2] << 16 | buf[1] << 8 |
						 buf[0] << 0;
				post_bit_error &= 0x0fffff;
				start_ber = true;
			} else {
				post_bit_error = 0;
				start_ber = false;
			}
		} else {
			post_bit_error = 0;
			start_ber = true;
		}

		if (start_ber) {
			ret = regmap_write(priv->regmap[0], 0x0079, 0x01);
			if (ret)
				goto error;
			priv->ber_running = true;
		}

		priv->post_bit_error += post_bit_error;

		c->post_bit_error.len = 1;
		c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
		c->post_bit_error.stat[0].uvalue = priv->post_bit_error;
	} else {
		c->post_bit_error.len = 1;
		c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
	}

	return ret;
error:
	dev_dbg(&client->dev, "failed=%d\n", ret);
	return ret;
}

int cxd2820r_init_t(struct dvb_frontend *fe)
{
	struct cxd2820r_priv *priv = fe->demodulator_priv;
	struct i2c_client *client = priv->client[0];
	int ret;

	dev_dbg(&client->dev, "\n");

	ret = regmap_write(priv->regmap[0], 0x0085, 0x07);
	if (ret)
		goto error;

	return ret;
error:
	dev_dbg(&client->dev, "failed=%d\n", ret);
	return ret;
}

int cxd2820r_sleep_t(struct dvb_frontend *fe)
{
	struct cxd2820r_priv *priv = fe->demodulator_priv;
	struct i2c_client *client = priv->client[0];
	int ret;
	static struct reg_val_mask tab[] = {
		{ 0x000ff, 0x1f, 0xff },
		{ 0x00085, 0x00, 0xff },
		{ 0x00088, 0x01, 0xff },
		{ 0x00081, 0x00, 0xff },
		{ 0x00080, 0x00, 0xff },
	};

	dev_dbg(&client->dev, "\n");

	priv->delivery_system = SYS_UNDEFINED;

	ret = cxd2820r_wr_reg_val_mask_tab(priv, tab, ARRAY_SIZE(tab));
	if (ret)
		goto error;

	return ret;
error:
	dev_dbg(&client->dev, "failed=%d\n", ret);
	return ret;
}

int cxd2820r_get_tune_settings_t(struct dvb_frontend *fe,
	struct dvb_frontend_tune_settings *s)
{
	s->min_delay_ms = 500;
	s->step_size = fe->ops.info.frequency_stepsize_hz * 2;
	s->max_drift = (fe->ops.info.frequency_stepsize_hz * 2) + 1;

	return 0;
}
Commit	Line	Data
16216333	1	// SPDX-License-Identifier: GPL-2.0-or-later
27cfc85e AP	2	/*
	3	* Sony CXD2820R demodulator driver
	4	*
	5	* Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
27cfc85e AP	6	*/
	7
	8
9ac51c5e SK	9	#include "cxd2820r_priv.h"
9ac51c5e SK	10
f311f68a	11	int cxd2820r_set_frontend_t(struct dvb_frontend *fe)
27cfc85e AP	12	{
27cfc85e AP	13	struct cxd2820r_priv *priv = fe->demodulator_priv;
c98975f9	14	struct i2c_client *client = priv->client[0];
27cfc85e	15	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
43e2ea63	16	int ret, bw_i;
fcd09f65 AP	17	unsigned int utmp;
fcd09f65 AP	18	u32 if_frequency;
27cfc85e AP	19	u8 buf[3], bw_param;
	20	u8 bw_params1[][5] = {
	21	{ 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */
	22	{ 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */
	23	{ 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */
	24	};
	25	u8 bw_params2[][2] = {
	26	{ 0x1f, 0xdc }, /* 6 MHz */
	27	{ 0x12, 0xf8 }, /* 7 MHz */
	28	{ 0x01, 0xe0 }, /* 8 MHz */
	29	};
	30	struct reg_val_mask tab[] = {
	31	{ 0x00080, 0x00, 0xff },
	32	{ 0x00081, 0x03, 0xff },
	33	{ 0x00085, 0x07, 0xff },
	34	{ 0x00088, 0x01, 0xff },
	35
07fdf7d9 AP	36	{ 0x00070, priv->ts_mode, 0xff },
	37	{ 0x00071, !priv->ts_clk_inv << 4, 0x10 },
	38	{ 0x000cb, priv->if_agc_polarity << 6, 0x40 },
27cfc85e AP	39	{ 0x000a5, 0x00, 0x01 },
	40	{ 0x00082, 0x20, 0x60 },
	41	{ 0x000c2, 0xc3, 0xff },
	42	{ 0x0016a, 0x50, 0xff },
	43	{ 0x00427, 0x41, 0xff },
	44	};
	45
c98975f9 AP	46	dev_dbg(&client->dev,
	47	"delivery_system=%d modulation=%d frequency=%u bandwidth_hz=%u inversion=%d\n",
	48	c->delivery_system, c->modulation, c->frequency,
	49	c->bandwidth_hz, c->inversion);
27cfc85e	50
13d723ba AP	51	switch (c->bandwidth_hz) {
	52	case 6000000:
	53	bw_i = 0;
	54	bw_param = 2;
	55	break;
	56	case 7000000:
	57	bw_i = 1;
	58	bw_param = 1;
	59	break;
	60	case 8000000:
	61	bw_i = 2;
	62	bw_param = 0;
	63	break;
	64	default:
	65	return -EINVAL;
	66	}
	67
27cfc85e AP	68	/* program tuner */
27cfc85e AP	69	if (fe->ops.tuner_ops.set_params)
14d24d14	70	fe->ops.tuner_ops.set_params(fe);
27cfc85e AP	71
27cfc85e AP	72	if (priv->delivery_system != SYS_DVBT) {
43e2ea63 AP	73	ret = cxd2820r_wr_reg_val_mask_tab(priv, tab, ARRAY_SIZE(tab));
	74	if (ret)
	75	goto error;
27cfc85e AP	76	}
	77
	78	priv->delivery_system = SYS_DVBT;
285c0b00	79	priv->ber_running = false; /* tune stops BER counter */
27cfc85e	80
fda23faa AP	81	/* program IF frequency */
fda23faa AP	82	if (fe->ops.tuner_ops.get_if_frequency) {
fcd09f65	83	ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
fda23faa AP	84	if (ret)
fda23faa AP	85	goto error;
c98975f9	86	dev_dbg(&client->dev, "if_frequency=%u\n", if_frequency);
fcd09f65 AP	87	} else {
	88	ret = -EINVAL;
	89	goto error;
	90	}
27cfc85e	91
fcd09f65 AP	92	utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x1000000, CXD2820R_CLK);
	93	buf[0] = (utmp >> 16) & 0xff;
	94	buf[1] = (utmp >> 8) & 0xff;
	95	buf[2] = (utmp >> 0) & 0xff;
43e2ea63	96	ret = regmap_bulk_write(priv->regmap[0], 0x00b6, buf, 3);
27cfc85e AP	97	if (ret)
	98	goto error;
	99
43e2ea63	100	ret = regmap_bulk_write(priv->regmap[0], 0x009f, bw_params1[bw_i], 5);
27cfc85e AP	101	if (ret)
	102	goto error;
	103
43e2ea63	104	ret = regmap_update_bits(priv->regmap[0], 0x00d7, 0xc0, bw_param << 6);
27cfc85e AP	105	if (ret)
	106	goto error;
	107
43e2ea63	108	ret = regmap_bulk_write(priv->regmap[0], 0x00d9, bw_params2[bw_i], 2);
27cfc85e AP	109	if (ret)
	110	goto error;
	111
43e2ea63	112	ret = regmap_write(priv->regmap[0], 0x00ff, 0x08);
27cfc85e AP	113	if (ret)
	114	goto error;
	115
43e2ea63	116	ret = regmap_write(priv->regmap[0], 0x00fe, 0x01);
27cfc85e AP	117	if (ret)
	118	goto error;
	119
	120	return ret;
	121	error:
c98975f9	122	dev_dbg(&client->dev, "failed=%d\n", ret);
27cfc85e AP	123	return ret;
	124	}
	125
7e3e68bc MCC	126	int cxd2820r_get_frontend_t(struct dvb_frontend *fe,
7e3e68bc MCC	127	struct dtv_frontend_properties *c)
27cfc85e AP	128	{
27cfc85e AP	129	struct cxd2820r_priv *priv = fe->demodulator_priv;
c98975f9	130	struct i2c_client *client = priv->client[0];
27cfc85e	131	int ret;
43e2ea63	132	unsigned int utmp;
27cfc85e AP	133	u8 buf[2];
27cfc85e AP	134
c98975f9 AP	135	dev_dbg(&client->dev, "\n");
c98975f9 AP	136
43e2ea63	137	ret = regmap_bulk_read(priv->regmap[0], 0x002f, buf, sizeof(buf));
27cfc85e AP	138	if (ret)
	139	goto error;
	140
	141	switch ((buf[0] >> 6) & 0x03) {
	142	case 0:
	143	c->modulation = QPSK;
	144	break;
	145	case 1:
	146	c->modulation = QAM_16;
	147	break;
	148	case 2:
	149	c->modulation = QAM_64;
	150	break;
	151	}
	152
	153	switch ((buf[1] >> 1) & 0x03) {
	154	case 0:
	155	c->transmission_mode = TRANSMISSION_MODE_2K;
	156	break;
	157	case 1:
	158	c->transmission_mode = TRANSMISSION_MODE_8K;
	159	break;
	160	}
	161
	162	switch ((buf[1] >> 3) & 0x03) {
	163	case 0:
	164	c->guard_interval = GUARD_INTERVAL_1_32;
	165	break;
	166	case 1:
	167	c->guard_interval = GUARD_INTERVAL_1_16;
	168	break;
	169	case 2:
	170	c->guard_interval = GUARD_INTERVAL_1_8;
	171	break;
	172	case 3:
	173	c->guard_interval = GUARD_INTERVAL_1_4;
	174	break;
	175	}
	176
	177	switch ((buf[0] >> 3) & 0x07) {
	178	case 0:
	179	c->hierarchy = HIERARCHY_NONE;
	180	break;
	181	case 1:
	182	c->hierarchy = HIERARCHY_1;
	183	break;
	184	case 2:
	185	c->hierarchy = HIERARCHY_2;
	186	break;
	187	case 3:
	188	c->hierarchy = HIERARCHY_4;
	189	break;
	190	}
	191
	192	switch ((buf[0] >> 0) & 0x07) {
	193	case 0:
	194	c->code_rate_HP = FEC_1_2;
	195	break;
	196	case 1:
	197	c->code_rate_HP = FEC_2_3;
	198	break;
	199	case 2:
	200	c->code_rate_HP = FEC_3_4;
	201	break;
202	case 3:
203	c->code_rate_HP = FEC_5_6;
204	break;
205	case 4:
206	c->code_rate_HP = FEC_7_8;
207	break;
208	}
209
210	switch ((buf[1] >> 5) & 0x07) {
211	case 0:
212	c->code_rate_LP = FEC_1_2;
213	break;
214	case 1:
215	c->code_rate_LP = FEC_2_3;
216	break;
217	case 2:
218	c->code_rate_LP = FEC_3_4;
219	break;
220	case 3:
221	c->code_rate_LP = FEC_5_6;
222	break;
223	case 4:
224	c->code_rate_LP = FEC_7_8;
225	break;
226	}
227
43e2ea63	228	ret = regmap_read(priv->regmap[0], 0x07c6, &utmp);
27cfc85e AP	229	if (ret)
	230	goto error;
	231
43e2ea63	232	switch ((utmp >> 0) & 0x01) {
27cfc85e AP	233	case 0:
	234	c->inversion = INVERSION_OFF;
	235	break;
	236	case 1:
	237	c->inversion = INVERSION_ON;
	238	break;
	239	}
	240
	241	return ret;
	242	error:
c98975f9	243	dev_dbg(&client->dev, "failed=%d\n", ret);
27cfc85e AP	244	return ret;
	245	}
	246
0df289a2	247	int cxd2820r_read_status_t(struct dvb_frontend fe, enum fe_status status)
27cfc85e AP	248	{
27cfc85e AP	249	struct cxd2820r_priv *priv = fe->demodulator_priv;
c98975f9	250	struct i2c_client *client = priv->client[0];
2832fd31	251	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
27cfc85e	252	int ret;
d51dc917 AP	253	unsigned int utmp, utmp1, utmp2;
d51dc917 AP	254	u8 buf[3];
27cfc85e	255
d51dc917	256	/* Lock detection */
43e2ea63	257	ret = regmap_bulk_read(priv->regmap[0], 0x0010, &buf[0], 1);
d51dc917 AP	258	if (ret)
d51dc917 AP	259	goto error;
43e2ea63	260	ret = regmap_bulk_read(priv->regmap[0], 0x0073, &buf[1], 1);
27cfc85e AP	261	if (ret)
	262	goto error;
	263
d51dc917 AP	264	utmp1 = (buf[0] >> 0) & 0x07;
d51dc917 AP	265	utmp2 = (buf[1] >> 3) & 0x01;
27cfc85e	266
d51dc917 AP	267	if (utmp1 == 6 && utmp2 == 1) {
	268	*status = FE_HAS_SIGNAL \| FE_HAS_CARRIER \|
	269	FE_HAS_VITERBI \| FE_HAS_SYNC \| FE_HAS_LOCK;
	270	} else if (utmp1 == 6 \|\| utmp2 == 1) {
	271	*status = FE_HAS_SIGNAL \| FE_HAS_CARRIER \|
	272	FE_HAS_VITERBI \| FE_HAS_SYNC;
27cfc85e	273	} else {
d51dc917	274	*status = 0;
27cfc85e AP	275	}
27cfc85e AP	276
d51dc917 AP	277	dev_dbg(&client->dev, "status=%02x raw=%*ph sync=%u ts=%u\n",
d51dc917 AP	278	*status, 2, buf, utmp1, utmp2);
27cfc85e	279
2832fd31 AP	280	/* Signal strength */
	281	if (*status & FE_HAS_SIGNAL) {
	282	unsigned int strength;
	283
43e2ea63	284	ret = regmap_bulk_read(priv->regmap[0], 0x0026, buf, 2);
2832fd31 AP	285	if (ret)
	286	goto error;
	287
	288	utmp = buf[0] << 8 \| buf[1] << 0;
	289	utmp = ~utmp & 0x0fff;
	290	/* Scale value to 0x0000-0xffff */
	291	strength = utmp << 4 \| utmp >> 8;
	292
	293	c->strength.len = 1;
	294	c->strength.stat[0].scale = FE_SCALE_RELATIVE;
	295	c->strength.stat[0].uvalue = strength;
	296	} else {
	297	c->strength.len = 1;
	298	c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
	299	}
	300
	301	/* CNR */
	302	if (*status & FE_HAS_VITERBI) {
	303	unsigned int cnr;
	304
43e2ea63	305	ret = regmap_bulk_read(priv->regmap[0], 0x002c, buf, 2);
2832fd31 AP	306	if (ret)
	307	goto error;
	308
	309	utmp = buf[0] << 8 \| buf[1] << 0;
	310	if (utmp)
	311	cnr = div_u64((u64)(intlog10(utmp)
	312	- intlog10(32000 - utmp) + 55532585)
	313	* 10000, (1 << 24));
	314	else
	315	cnr = 0;
	316
	317	c->cnr.len = 1;
	318	c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
	319	c->cnr.stat[0].svalue = cnr;
	320	} else {
	321	c->cnr.len = 1;
	322	c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
	323	}
	324
	325	/* BER */
	326	if (*status & FE_HAS_SYNC) {
	327	unsigned int post_bit_error;
	328	bool start_ber;
	329
	330	if (priv->ber_running) {
43e2ea63	331	ret = regmap_bulk_read(priv->regmap[0], 0x0076, buf, 3);
2832fd31 AP	332	if (ret)
	333	goto error;
	334
	335	if ((buf[2] >> 7) & 0x01) {
	336	post_bit_error = buf[2] << 16 \| buf[1] << 8 \|
	337	buf[0] << 0;
	338	post_bit_error &= 0x0fffff;
	339	start_ber = true;
	340	} else {
	341	post_bit_error = 0;
	342	start_ber = false;
	343	}
	344	} else {
	345	post_bit_error = 0;
	346	start_ber = true;
	347	}
	348
	349	if (start_ber) {
43e2ea63	350	ret = regmap_write(priv->regmap[0], 0x0079, 0x01);
2832fd31 AP	351	if (ret)
	352	goto error;
	353	priv->ber_running = true;
	354	}
	355
	356	priv->post_bit_error += post_bit_error;
	357
	358	c->post_bit_error.len = 1;
	359	c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
	360	c->post_bit_error.stat[0].uvalue = priv->post_bit_error;
	361	} else {
	362	c->post_bit_error.len = 1;
	363	c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
	364	}
	365
27cfc85e AP	366	return ret;
27cfc85e AP	367	error:
c98975f9	368	dev_dbg(&client->dev, "failed=%d\n", ret);
27cfc85e AP	369	return ret;
	370	}
	371
9ac51c5e	372	int cxd2820r_init_t(struct dvb_frontend *fe)
27cfc85e AP	373	{
27cfc85e AP	374	struct cxd2820r_priv *priv = fe->demodulator_priv;
c98975f9	375	struct i2c_client *client = priv->client[0];
27cfc85e AP	376	int ret;
27cfc85e AP	377
c98975f9 AP	378	dev_dbg(&client->dev, "\n");
c98975f9 AP	379
43e2ea63	380	ret = regmap_write(priv->regmap[0], 0x0085, 0x07);
27cfc85e AP	381	if (ret)
	382	goto error;
	383
	384	return ret;
	385	error:
c98975f9	386	dev_dbg(&client->dev, "failed=%d\n", ret);
27cfc85e AP	387	return ret;
	388	}
	389
9ac51c5e	390	int cxd2820r_sleep_t(struct dvb_frontend *fe)
27cfc85e AP	391	{
27cfc85e AP	392	struct cxd2820r_priv *priv = fe->demodulator_priv;
c98975f9	393	struct i2c_client *client = priv->client[0];
43e2ea63	394	int ret;
ed4e1569	395	static struct reg_val_mask tab[] = {
27cfc85e AP	396	{ 0x000ff, 0x1f, 0xff },
	397	{ 0x00085, 0x00, 0xff },
	398	{ 0x00088, 0x01, 0xff },
	399	{ 0x00081, 0x00, 0xff },
	400	{ 0x00080, 0x00, 0xff },
	401	};
	402
c98975f9	403	dev_dbg(&client->dev, "\n");
27cfc85e AP	404
	405	priv->delivery_system = SYS_UNDEFINED;
	406
43e2ea63 AP	407	ret = cxd2820r_wr_reg_val_mask_tab(priv, tab, ARRAY_SIZE(tab));
	408	if (ret)
	409	goto error;
27cfc85e AP	410
	411	return ret;
	412	error:
c98975f9	413	dev_dbg(&client->dev, "failed=%d\n", ret);
27cfc85e AP	414	return ret;
	415	}
	416
9ac51c5e	417	int cxd2820r_get_tune_settings_t(struct dvb_frontend *fe,
27cfc85e AP	418	struct dvb_frontend_tune_settings *s)
	419	{
	420	s->min_delay_ms = 500;
f1b1eabf MCC	421	s->step_size = fe->ops.info.frequency_stepsize_hz * 2;
f1b1eabf MCC	422	s->max_drift = (fe->ops.info.frequency_stepsize_hz * 2) + 1;
27cfc85e AP	423
	424	return 0;
	425	}