[linux-2.6-block.git] / drivers / media / dvb-frontends / cxd2820r_t.c

/*
 * Sony CXD2820R demodulator driver
 *
 * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
 *
 *    This program is free software; you can redistribute it and/or modify
 *    it under the terms of the GNU General Public License as published by
 *    the Free Software Foundation; either version 2 of the License, or
 *    (at your option) any later version.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *    GNU General Public License for more details.
 *
 *    You should have received a copy of the GNU General Public License along
 *    with this program; if not, write to the Free Software Foundation, Inc.,
 *    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 */


#include "cxd2820r_priv.h"

int cxd2820r_set_frontend_t(struct dvb_frontend *fe)
{
	struct cxd2820r_priv *priv = fe->demodulator_priv;
	struct i2c_client *client = priv->client[0];
	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
	int ret, bw_i;
	unsigned int utmp;
	u32 if_frequency;
	u8 buf[3], bw_param;
	u8 bw_params1[][5] = {
		{ 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */
		{ 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */
		{ 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */
	};
	u8 bw_params2[][2] = {
		{ 0x1f, 0xdc }, /* 6 MHz */
		{ 0x12, 0xf8 }, /* 7 MHz */
		{ 0x01, 0xe0 }, /* 8 MHz */
	};
	struct reg_val_mask tab[] = {
		{ 0x00080, 0x00, 0xff },
		{ 0x00081, 0x03, 0xff },
		{ 0x00085, 0x07, 0xff },
		{ 0x00088, 0x01, 0xff },

		{ 0x00070, priv->ts_mode, 0xff },
		{ 0x00071, !priv->ts_clk_inv << 4, 0x10 },
		{ 0x000cb, priv->if_agc_polarity << 6, 0x40 },
		{ 0x000a5, 0x00, 0x01 },
		{ 0x00082, 0x20, 0x60 },
		{ 0x000c2, 0xc3, 0xff },
		{ 0x0016a, 0x50, 0xff },
		{ 0x00427, 0x41, 0xff },
	};

	dev_dbg(&client->dev,
		"delivery_system=%d modulation=%d frequency=%u bandwidth_hz=%u inversion=%d\n",
		c->delivery_system, c->modulation, c->frequency,
		c->bandwidth_hz, c->inversion);

	switch (c->bandwidth_hz) {
	case 6000000:
		bw_i = 0;
		bw_param = 2;
		break;
	case 7000000:
		bw_i = 1;
		bw_param = 1;
		break;
	case 8000000:
		bw_i = 2;
		bw_param = 0;
		break;
	default:
		return -EINVAL;
	}

	/* program tuner */
	if (fe->ops.tuner_ops.set_params)
		fe->ops.tuner_ops.set_params(fe);

	if (priv->delivery_system != SYS_DVBT) {
		ret = cxd2820r_wr_reg_val_mask_tab(priv, tab, ARRAY_SIZE(tab));
		if (ret)
			goto error;
	}

	priv->delivery_system = SYS_DVBT;
	priv->ber_running = false; /* tune stops BER counter */

	/* program IF frequency */
	if (fe->ops.tuner_ops.get_if_frequency) {
		ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
		if (ret)
			goto error;
		dev_dbg(&client->dev, "if_frequency=%u\n", if_frequency);
	} else {
		ret = -EINVAL;
		goto error;
	}

	utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x1000000, CXD2820R_CLK);
	buf[0] = (utmp >> 16) & 0xff;
	buf[1] = (utmp >>  8) & 0xff;
	buf[2] = (utmp >>  0) & 0xff;
	ret = regmap_bulk_write(priv->regmap[0], 0x00b6, buf, 3);
	if (ret)
		goto error;

	ret = regmap_bulk_write(priv->regmap[0], 0x009f, bw_params1[bw_i], 5);
	if (ret)
		goto error;

	ret = regmap_update_bits(priv->regmap[0], 0x00d7, 0xc0, bw_param << 6);
	if (ret)
		goto error;

	ret = regmap_bulk_write(priv->regmap[0], 0x00d9, bw_params2[bw_i], 2);
	if (ret)
		goto error;

	ret = regmap_write(priv->regmap[0], 0x00ff, 0x08);
	if (ret)
		goto error;

	ret = regmap_write(priv->regmap[0], 0x00fe, 0x01);
	if (ret)
		goto error;

	return ret;
error:
	dev_dbg(&client->dev, "failed=%d\n", ret);
	return ret;
}

int cxd2820r_get_frontend_t(struct dvb_frontend *fe,
			    struct dtv_frontend_properties *c)
{
	struct cxd2820r_priv *priv = fe->demodulator_priv;
	struct i2c_client *client = priv->client[0];
	int ret;
	unsigned int utmp;
	u8 buf[2];

	dev_dbg(&client->dev, "\n");

	ret = regmap_bulk_read(priv->regmap[0], 0x002f, buf, sizeof(buf));
	if (ret)
		goto error;

	switch ((buf[0] >> 6) & 0x03) {
	case 0:
		c->modulation = QPSK;
		break;
	case 1:
		c->modulation = QAM_16;
		break;
	case 2:
		c->modulation = QAM_64;
		break;
	}

	switch ((buf[1] >> 1) & 0x03) {
	case 0:
		c->transmission_mode = TRANSMISSION_MODE_2K;
		break;
	case 1:
		c->transmission_mode = TRANSMISSION_MODE_8K;
		break;
	}

	switch ((buf[1] >> 3) & 0x03) {
	case 0:
		c->guard_interval = GUARD_INTERVAL_1_32;
		break;
	case 1:
		c->guard_interval = GUARD_INTERVAL_1_16;
		break;
	case 2:
		c->guard_interval = GUARD_INTERVAL_1_8;
		break;
	case 3:
		c->guard_interval = GUARD_INTERVAL_1_4;
		break;
	}

	switch ((buf[0] >> 3) & 0x07) {
	case 0:
		c->hierarchy = HIERARCHY_NONE;
		break;
	case 1:
		c->hierarchy = HIERARCHY_1;
		break;
	case 2:
		c->hierarchy = HIERARCHY_2;
		break;
	case 3:
		c->hierarchy = HIERARCHY_4;
		break;
	}

	switch ((buf[0] >> 0) & 0x07) {
	case 0:
		c->code_rate_HP = FEC_1_2;
		break;
	case 1:
		c->code_rate_HP = FEC_2_3;
		break;
	case 2:
		c->code_rate_HP = FEC_3_4;
		break;
	case 3:
		c->code_rate_HP = FEC_5_6;
		break;
	case 4:
		c->code_rate_HP = FEC_7_8;
		break;
	}

	switch ((buf[1] >> 5) & 0x07) {
	case 0:
		c->code_rate_LP = FEC_1_2;
		break;
	case 1:
		c->code_rate_LP = FEC_2_3;
		break;
	case 2:
		c->code_rate_LP = FEC_3_4;
		break;
	case 3:
		c->code_rate_LP = FEC_5_6;
		break;
	case 4:
		c->code_rate_LP = FEC_7_8;
		break;
	}

	ret = regmap_read(priv->regmap[0], 0x07c6, &utmp);
	if (ret)
		goto error;

	switch ((utmp >> 0) & 0x01) {
	case 0:
		c->inversion = INVERSION_OFF;
		break;
	case 1:
		c->inversion = INVERSION_ON;
		break;
	}

	return ret;
error:
	dev_dbg(&client->dev, "failed=%d\n", ret);
	return ret;
}

int cxd2820r_read_status_t(struct dvb_frontend *fe, enum fe_status *status)
{
	struct cxd2820r_priv *priv = fe->demodulator_priv;
	struct i2c_client *client = priv->client[0];
	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
	int ret;
	unsigned int utmp, utmp1, utmp2;
	u8 buf[3];

	/* Lock detection */
	ret = regmap_bulk_read(priv->regmap[0], 0x0010, &buf[0], 1);
	if (ret)
		goto error;
	ret = regmap_bulk_read(priv->regmap[0], 0x0073, &buf[1], 1);
	if (ret)
		goto error;

	utmp1 = (buf[0] >> 0) & 0x07;
	utmp2 = (buf[1] >> 3) & 0x01;

	if (utmp1 == 6 && utmp2 == 1) {
		*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
			  FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
	} else if (utmp1 == 6 || utmp2 == 1) {
		*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
			  FE_HAS_VITERBI | FE_HAS_SYNC;
	} else {
		*status = 0;
	}

	dev_dbg(&client->dev, "status=%02x raw=%*ph sync=%u ts=%u\n",
		*status, 2, buf, utmp1, utmp2);

	/* Signal strength */
	if (*status & FE_HAS_SIGNAL) {
		unsigned int strength;

		ret = regmap_bulk_read(priv->regmap[0], 0x0026, buf, 2);
		if (ret)
			goto error;

		utmp = buf[0] << 8 | buf[1] << 0;
		utmp = ~utmp & 0x0fff;
		/* Scale value to 0x0000-0xffff */
		strength = utmp << 4 | utmp >> 8;

		c->strength.len = 1;
		c->strength.stat[0].scale = FE_SCALE_RELATIVE;
		c->strength.stat[0].uvalue = strength;
	} else {
		c->strength.len = 1;
		c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
	}

	/* CNR */
	if (*status & FE_HAS_VITERBI) {
		unsigned int cnr;

		ret = regmap_bulk_read(priv->regmap[0], 0x002c, buf, 2);
		if (ret)
			goto error;

		utmp = buf[0] << 8 | buf[1] << 0;
		if (utmp)
			cnr = div_u64((u64)(intlog10(utmp)
				      - intlog10(32000 - utmp) + 55532585)
				      * 10000, (1 << 24));
		else
			cnr = 0;

		c->cnr.len = 1;
		c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
		c->cnr.stat[0].svalue = cnr;
	} else {
		c->cnr.len = 1;
		c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
	}

	/* BER */
	if (*status & FE_HAS_SYNC) {
		unsigned int post_bit_error;
		bool start_ber;

		if (priv->ber_running) {
			ret = regmap_bulk_read(priv->regmap[0], 0x0076, buf, 3);
			if (ret)
				goto error;

			if ((buf[2] >> 7) & 0x01) {
				post_bit_error = buf[2] << 16 | buf[1] << 8 |
						 buf[0] << 0;
				post_bit_error &= 0x0fffff;
				start_ber = true;
			} else {
				post_bit_error = 0;
				start_ber = false;
			}
		} else {
			post_bit_error = 0;
			start_ber = true;
		}

		if (start_ber) {
			ret = regmap_write(priv->regmap[0], 0x0079, 0x01);
			if (ret)
				goto error;
			priv->ber_running = true;
		}

		priv->post_bit_error += post_bit_error;

		c->post_bit_error.len = 1;
		c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
		c->post_bit_error.stat[0].uvalue = priv->post_bit_error;
	} else {
		c->post_bit_error.len = 1;
		c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
	}

	return ret;
error:
	dev_dbg(&client->dev, "failed=%d\n", ret);
	return ret;
}

int cxd2820r_init_t(struct dvb_frontend *fe)
{
	struct cxd2820r_priv *priv = fe->demodulator_priv;
	struct i2c_client *client = priv->client[0];
	int ret;

	dev_dbg(&client->dev, "\n");

	ret = regmap_write(priv->regmap[0], 0x0085, 0x07);
	if (ret)
		goto error;

	return ret;
error:
	dev_dbg(&client->dev, "failed=%d\n", ret);
	return ret;
}

int cxd2820r_sleep_t(struct dvb_frontend *fe)
{
	struct cxd2820r_priv *priv = fe->demodulator_priv;
	struct i2c_client *client = priv->client[0];
	int ret;
	struct reg_val_mask tab[] = {
		{ 0x000ff, 0x1f, 0xff },
		{ 0x00085, 0x00, 0xff },
		{ 0x00088, 0x01, 0xff },
		{ 0x00081, 0x00, 0xff },
		{ 0x00080, 0x00, 0xff },
	};

	dev_dbg(&client->dev, "\n");

	priv->delivery_system = SYS_UNDEFINED;

	ret = cxd2820r_wr_reg_val_mask_tab(priv, tab, ARRAY_SIZE(tab));
	if (ret)
		goto error;

	return ret;
error:
	dev_dbg(&client->dev, "failed=%d\n", ret);
	return ret;
}

int cxd2820r_get_tune_settings_t(struct dvb_frontend *fe,
	struct dvb_frontend_tune_settings *s)
{
	s->min_delay_ms = 500;
	s->step_size = fe->ops.info.frequency_stepsize_hz * 2;
	s->max_drift = (fe->ops.info.frequency_stepsize_hz * 2) + 1;

	return 0;
}
Commit	Line	Data
27cfc85e AP	1	/*
	2	* Sony CXD2820R demodulator driver
	3	*
	4	* Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along
	17	* with this program; if not, write to the Free Software Foundation, Inc.,
	18	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
	19	*/
	20
	21
9ac51c5e SK	22	#include "cxd2820r_priv.h"
9ac51c5e SK	23
f311f68a	24	int cxd2820r_set_frontend_t(struct dvb_frontend *fe)
27cfc85e AP	25	{
27cfc85e AP	26	struct cxd2820r_priv *priv = fe->demodulator_priv;
c98975f9	27	struct i2c_client *client = priv->client[0];
27cfc85e	28	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
43e2ea63	29	int ret, bw_i;
fcd09f65 AP	30	unsigned int utmp;
fcd09f65 AP	31	u32 if_frequency;
27cfc85e AP	32	u8 buf[3], bw_param;
	33	u8 bw_params1[][5] = {
	34	{ 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */
	35	{ 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */
	36	{ 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */
	37	};
	38	u8 bw_params2[][2] = {
	39	{ 0x1f, 0xdc }, /* 6 MHz */
	40	{ 0x12, 0xf8 }, /* 7 MHz */
	41	{ 0x01, 0xe0 }, /* 8 MHz */
	42	};
	43	struct reg_val_mask tab[] = {
	44	{ 0x00080, 0x00, 0xff },
	45	{ 0x00081, 0x03, 0xff },
	46	{ 0x00085, 0x07, 0xff },
	47	{ 0x00088, 0x01, 0xff },
	48
07fdf7d9 AP	49	{ 0x00070, priv->ts_mode, 0xff },
	50	{ 0x00071, !priv->ts_clk_inv << 4, 0x10 },
	51	{ 0x000cb, priv->if_agc_polarity << 6, 0x40 },
27cfc85e AP	52	{ 0x000a5, 0x00, 0x01 },
	53	{ 0x00082, 0x20, 0x60 },
	54	{ 0x000c2, 0xc3, 0xff },
	55	{ 0x0016a, 0x50, 0xff },
	56	{ 0x00427, 0x41, 0xff },
	57	};
	58
c98975f9 AP	59	dev_dbg(&client->dev,
	60	"delivery_system=%d modulation=%d frequency=%u bandwidth_hz=%u inversion=%d\n",
	61	c->delivery_system, c->modulation, c->frequency,
	62	c->bandwidth_hz, c->inversion);
27cfc85e	63
13d723ba AP	64	switch (c->bandwidth_hz) {
	65	case 6000000:
	66	bw_i = 0;
	67	bw_param = 2;
	68	break;
	69	case 7000000:
	70	bw_i = 1;
	71	bw_param = 1;
	72	break;
	73	case 8000000:
	74	bw_i = 2;
	75	bw_param = 0;
	76	break;
	77	default:
	78	return -EINVAL;
	79	}
	80
27cfc85e AP	81	/* program tuner */
27cfc85e AP	82	if (fe->ops.tuner_ops.set_params)
14d24d14	83	fe->ops.tuner_ops.set_params(fe);
27cfc85e AP	84
27cfc85e AP	85	if (priv->delivery_system != SYS_DVBT) {
43e2ea63 AP	86	ret = cxd2820r_wr_reg_val_mask_tab(priv, tab, ARRAY_SIZE(tab));
	87	if (ret)
	88	goto error;
27cfc85e AP	89	}
	90
	91	priv->delivery_system = SYS_DVBT;
285c0b00	92	priv->ber_running = false; /* tune stops BER counter */
27cfc85e	93
fda23faa AP	94	/* program IF frequency */
fda23faa AP	95	if (fe->ops.tuner_ops.get_if_frequency) {
fcd09f65	96	ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
fda23faa AP	97	if (ret)
fda23faa AP	98	goto error;
c98975f9	99	dev_dbg(&client->dev, "if_frequency=%u\n", if_frequency);
fcd09f65 AP	100	} else {
	101	ret = -EINVAL;
	102	goto error;
	103	}
27cfc85e	104
fcd09f65 AP	105	utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x1000000, CXD2820R_CLK);
	106	buf[0] = (utmp >> 16) & 0xff;
	107	buf[1] = (utmp >> 8) & 0xff;
	108	buf[2] = (utmp >> 0) & 0xff;
43e2ea63	109	ret = regmap_bulk_write(priv->regmap[0], 0x00b6, buf, 3);
27cfc85e AP	110	if (ret)
	111	goto error;
	112
43e2ea63	113	ret = regmap_bulk_write(priv->regmap[0], 0x009f, bw_params1[bw_i], 5);
27cfc85e AP	114	if (ret)
	115	goto error;
	116
43e2ea63	117	ret = regmap_update_bits(priv->regmap[0], 0x00d7, 0xc0, bw_param << 6);
27cfc85e AP	118	if (ret)
	119	goto error;
	120
43e2ea63	121	ret = regmap_bulk_write(priv->regmap[0], 0x00d9, bw_params2[bw_i], 2);
27cfc85e AP	122	if (ret)
	123	goto error;
	124
43e2ea63	125	ret = regmap_write(priv->regmap[0], 0x00ff, 0x08);
27cfc85e AP	126	if (ret)
	127	goto error;
	128
43e2ea63	129	ret = regmap_write(priv->regmap[0], 0x00fe, 0x01);
27cfc85e AP	130	if (ret)
	131	goto error;
	132
	133	return ret;
	134	error:
c98975f9	135	dev_dbg(&client->dev, "failed=%d\n", ret);
27cfc85e AP	136	return ret;
	137	}
	138
7e3e68bc MCC	139	int cxd2820r_get_frontend_t(struct dvb_frontend *fe,
7e3e68bc MCC	140	struct dtv_frontend_properties *c)
27cfc85e AP	141	{
27cfc85e AP	142	struct cxd2820r_priv *priv = fe->demodulator_priv;
c98975f9	143	struct i2c_client *client = priv->client[0];
27cfc85e	144	int ret;
43e2ea63	145	unsigned int utmp;
27cfc85e AP	146	u8 buf[2];
27cfc85e AP	147
c98975f9 AP	148	dev_dbg(&client->dev, "\n");
c98975f9 AP	149
43e2ea63	150	ret = regmap_bulk_read(priv->regmap[0], 0x002f, buf, sizeof(buf));
27cfc85e AP	151	if (ret)
	152	goto error;
	153
	154	switch ((buf[0] >> 6) & 0x03) {
	155	case 0:
	156	c->modulation = QPSK;
	157	break;
	158	case 1:
	159	c->modulation = QAM_16;
	160	break;
	161	case 2:
	162	c->modulation = QAM_64;
	163	break;
	164	}
	165
	166	switch ((buf[1] >> 1) & 0x03) {
	167	case 0:
	168	c->transmission_mode = TRANSMISSION_MODE_2K;
	169	break;
	170	case 1:
	171	c->transmission_mode = TRANSMISSION_MODE_8K;
	172	break;
	173	}
	174
	175	switch ((buf[1] >> 3) & 0x03) {
	176	case 0:
	177	c->guard_interval = GUARD_INTERVAL_1_32;
	178	break;
	179	case 1:
	180	c->guard_interval = GUARD_INTERVAL_1_16;
	181	break;
	182	case 2:
	183	c->guard_interval = GUARD_INTERVAL_1_8;
	184	break;
	185	case 3:
	186	c->guard_interval = GUARD_INTERVAL_1_4;
	187	break;
	188	}
	189
	190	switch ((buf[0] >> 3) & 0x07) {
	191	case 0:
	192	c->hierarchy = HIERARCHY_NONE;
	193	break;
	194	case 1:
	195	c->hierarchy = HIERARCHY_1;
	196	break;
	197	case 2:
	198	c->hierarchy = HIERARCHY_2;
	199	break;
	200	case 3:
	201	c->hierarchy = HIERARCHY_4;
	202	break;
	203	}
	204
	205	switch ((buf[0] >> 0) & 0x07) {
	206	case 0:
	207	c->code_rate_HP = FEC_1_2;
	208	break;
	209	case 1:
	210	c->code_rate_HP = FEC_2_3;
	211	break;
	212	case 2:
	213	c->code_rate_HP = FEC_3_4;
	214	break;
215	case 3:
216	c->code_rate_HP = FEC_5_6;
217	break;
218	case 4:
219	c->code_rate_HP = FEC_7_8;
220	break;
221	}
222
223	switch ((buf[1] >> 5) & 0x07) {
224	case 0:
225	c->code_rate_LP = FEC_1_2;
226	break;
227	case 1:
228	c->code_rate_LP = FEC_2_3;
229	break;
230	case 2:
231	c->code_rate_LP = FEC_3_4;
232	break;
233	case 3:
234	c->code_rate_LP = FEC_5_6;
235	break;
236	case 4:
237	c->code_rate_LP = FEC_7_8;
238	break;
239	}
240
43e2ea63	241	ret = regmap_read(priv->regmap[0], 0x07c6, &utmp);
27cfc85e AP	242	if (ret)
	243	goto error;
	244
43e2ea63	245	switch ((utmp >> 0) & 0x01) {
27cfc85e AP	246	case 0:
	247	c->inversion = INVERSION_OFF;
	248	break;
	249	case 1:
	250	c->inversion = INVERSION_ON;
	251	break;
	252	}
	253
	254	return ret;
	255	error:
c98975f9	256	dev_dbg(&client->dev, "failed=%d\n", ret);
27cfc85e AP	257	return ret;
	258	}
	259
0df289a2	260	int cxd2820r_read_status_t(struct dvb_frontend fe, enum fe_status status)
27cfc85e AP	261	{
27cfc85e AP	262	struct cxd2820r_priv *priv = fe->demodulator_priv;
c98975f9	263	struct i2c_client *client = priv->client[0];
2832fd31	264	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
27cfc85e	265	int ret;
d51dc917 AP	266	unsigned int utmp, utmp1, utmp2;
d51dc917 AP	267	u8 buf[3];
27cfc85e	268
d51dc917	269	/* Lock detection */
43e2ea63	270	ret = regmap_bulk_read(priv->regmap[0], 0x0010, &buf[0], 1);
d51dc917 AP	271	if (ret)
d51dc917 AP	272	goto error;
43e2ea63	273	ret = regmap_bulk_read(priv->regmap[0], 0x0073, &buf[1], 1);
27cfc85e AP	274	if (ret)
	275	goto error;
	276
d51dc917 AP	277	utmp1 = (buf[0] >> 0) & 0x07;
d51dc917 AP	278	utmp2 = (buf[1] >> 3) & 0x01;
27cfc85e	279
d51dc917 AP	280	if (utmp1 == 6 && utmp2 == 1) {
	281	*status = FE_HAS_SIGNAL \| FE_HAS_CARRIER \|
	282	FE_HAS_VITERBI \| FE_HAS_SYNC \| FE_HAS_LOCK;
	283	} else if (utmp1 == 6 \|\| utmp2 == 1) {
	284	*status = FE_HAS_SIGNAL \| FE_HAS_CARRIER \|
	285	FE_HAS_VITERBI \| FE_HAS_SYNC;
27cfc85e	286	} else {
d51dc917	287	*status = 0;
27cfc85e AP	288	}
27cfc85e AP	289
d51dc917 AP	290	dev_dbg(&client->dev, "status=%02x raw=%*ph sync=%u ts=%u\n",
d51dc917 AP	291	*status, 2, buf, utmp1, utmp2);
27cfc85e	292
2832fd31 AP	293	/* Signal strength */
	294	if (*status & FE_HAS_SIGNAL) {
	295	unsigned int strength;
	296
43e2ea63	297	ret = regmap_bulk_read(priv->regmap[0], 0x0026, buf, 2);
2832fd31 AP	298	if (ret)
	299	goto error;
	300
	301	utmp = buf[0] << 8 \| buf[1] << 0;
	302	utmp = ~utmp & 0x0fff;
	303	/* Scale value to 0x0000-0xffff */
	304	strength = utmp << 4 \| utmp >> 8;
	305
	306	c->strength.len = 1;
	307	c->strength.stat[0].scale = FE_SCALE_RELATIVE;
	308	c->strength.stat[0].uvalue = strength;
	309	} else {
	310	c->strength.len = 1;
	311	c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
	312	}
	313
	314	/* CNR */
	315	if (*status & FE_HAS_VITERBI) {
	316	unsigned int cnr;
	317
43e2ea63	318	ret = regmap_bulk_read(priv->regmap[0], 0x002c, buf, 2);
2832fd31 AP	319	if (ret)
	320	goto error;
	321
	322	utmp = buf[0] << 8 \| buf[1] << 0;
	323	if (utmp)
	324	cnr = div_u64((u64)(intlog10(utmp)
	325	- intlog10(32000 - utmp) + 55532585)
	326	* 10000, (1 << 24));
	327	else
	328	cnr = 0;
	329
	330	c->cnr.len = 1;
	331	c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
	332	c->cnr.stat[0].svalue = cnr;
	333	} else {
	334	c->cnr.len = 1;
	335	c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
	336	}
	337
	338	/* BER */
	339	if (*status & FE_HAS_SYNC) {
	340	unsigned int post_bit_error;
	341	bool start_ber;
	342
	343	if (priv->ber_running) {
43e2ea63	344	ret = regmap_bulk_read(priv->regmap[0], 0x0076, buf, 3);
2832fd31 AP	345	if (ret)
	346	goto error;
	347
	348	if ((buf[2] >> 7) & 0x01) {
	349	post_bit_error = buf[2] << 16 \| buf[1] << 8 \|
	350	buf[0] << 0;
	351	post_bit_error &= 0x0fffff;
	352	start_ber = true;
	353	} else {
	354	post_bit_error = 0;
	355	start_ber = false;
	356	}
	357	} else {
	358	post_bit_error = 0;
	359	start_ber = true;
	360	}
	361
	362	if (start_ber) {
43e2ea63	363	ret = regmap_write(priv->regmap[0], 0x0079, 0x01);
2832fd31 AP	364	if (ret)
	365	goto error;
	366	priv->ber_running = true;
	367	}
	368
	369	priv->post_bit_error += post_bit_error;
	370
	371	c->post_bit_error.len = 1;
	372	c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
	373	c->post_bit_error.stat[0].uvalue = priv->post_bit_error;
	374	} else {
	375	c->post_bit_error.len = 1;
	376	c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
	377	}
	378
27cfc85e AP	379	return ret;
27cfc85e AP	380	error:
c98975f9	381	dev_dbg(&client->dev, "failed=%d\n", ret);
27cfc85e AP	382	return ret;
	383	}
	384
9ac51c5e	385	int cxd2820r_init_t(struct dvb_frontend *fe)
27cfc85e AP	386	{
27cfc85e AP	387	struct cxd2820r_priv *priv = fe->demodulator_priv;
c98975f9	388	struct i2c_client *client = priv->client[0];
27cfc85e AP	389	int ret;
27cfc85e AP	390
c98975f9 AP	391	dev_dbg(&client->dev, "\n");
c98975f9 AP	392
43e2ea63	393	ret = regmap_write(priv->regmap[0], 0x0085, 0x07);
27cfc85e AP	394	if (ret)
	395	goto error;
	396
	397	return ret;
	398	error:
c98975f9	399	dev_dbg(&client->dev, "failed=%d\n", ret);
27cfc85e AP	400	return ret;
	401	}
	402
9ac51c5e	403	int cxd2820r_sleep_t(struct dvb_frontend *fe)
27cfc85e AP	404	{
27cfc85e AP	405	struct cxd2820r_priv *priv = fe->demodulator_priv;
c98975f9	406	struct i2c_client *client = priv->client[0];
43e2ea63	407	int ret;
27cfc85e AP	408	struct reg_val_mask tab[] = {
	409	{ 0x000ff, 0x1f, 0xff },
	410	{ 0x00085, 0x00, 0xff },
	411	{ 0x00088, 0x01, 0xff },
	412	{ 0x00081, 0x00, 0xff },
	413	{ 0x00080, 0x00, 0xff },
	414	};
	415
c98975f9	416	dev_dbg(&client->dev, "\n");
27cfc85e AP	417
	418	priv->delivery_system = SYS_UNDEFINED;
	419
43e2ea63 AP	420	ret = cxd2820r_wr_reg_val_mask_tab(priv, tab, ARRAY_SIZE(tab));
	421	if (ret)
	422	goto error;
27cfc85e AP	423
	424	return ret;
	425	error:
c98975f9	426	dev_dbg(&client->dev, "failed=%d\n", ret);
27cfc85e AP	427	return ret;
	428	}
	429
9ac51c5e	430	int cxd2820r_get_tune_settings_t(struct dvb_frontend *fe,
27cfc85e AP	431	struct dvb_frontend_tune_settings *s)
	432	{
	433	s->min_delay_ms = 500;
f1b1eabf MCC	434	s->step_size = fe->ops.info.frequency_stepsize_hz * 2;
f1b1eabf MCC	435	s->max_drift = (fe->ops.info.frequency_stepsize_hz * 2) + 1;
27cfc85e AP	436
	437	return 0;
	438	}