[linux-2.6-block.git] / drivers / media / dvb-frontends / cxd2099.c

/*
 * cxd2099.c: Driver for the CXD2099AR Common Interface Controller
 *
 * Copyright (C) 2010-2013 Digital Devices GmbH
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 only, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/wait.h>
#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/io.h>

#include "cxd2099.h"

static int buffermode;
module_param(buffermode, int, 0444);
MODULE_PARM_DESC(buffermode, "Enable CXD2099AR buffer mode (default: disabled)");

static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount);

struct cxd {
	struct dvb_ca_en50221 en;

	struct cxd2099_cfg cfg;
	struct i2c_client *client;
	struct regmap *regmap;

	u8     regs[0x23];
	u8     lastaddress;
	u8     clk_reg_f;
	u8     clk_reg_b;
	int    mode;
	int    ready;
	int    dr;
	int    write_busy;
	int    slot_stat;

	u8     amem[1024];
	int    amem_read;

	int    cammode;
	struct mutex lock; /* device access lock */

	u8     rbuf[1028];
	u8     wbuf[1028];
};

static int read_block(struct cxd *ci, u8 adr, u8 *data, u16 n)
{
	int status = 0;

	if (ci->lastaddress != adr)
		status = regmap_write(ci->regmap, 0, adr);
	if (!status) {
		ci->lastaddress = adr;

		while (n) {
			int len = n;

			if (ci->cfg.max_i2c && len > ci->cfg.max_i2c)
				len = ci->cfg.max_i2c;
			status = regmap_raw_read(ci->regmap, 1, data, len);
			if (status)
				return status;
			data += len;
			n -= len;
		}
	}
	return status;
}

static int read_reg(struct cxd *ci, u8 reg, u8 *val)
{
	return read_block(ci, reg, val, 1);
}

static int read_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
{
	int status;
	u8 addr[2] = {address & 0xff, address >> 8};

	status = regmap_raw_write(ci->regmap, 2, addr, 2);
	if (!status)
		status = regmap_raw_read(ci->regmap, 3, data, n);
	return status;
}

static int write_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
{
	int status;
	u8 addr[2] = {address & 0xff, address >> 8};

	status = regmap_raw_write(ci->regmap, 2, addr, 2);
	if (!status) {
		u8 buf[256];

		memcpy(buf, data, n);
		status = regmap_raw_write(ci->regmap, 3, buf, n);
	}
	return status;
}

static int read_io(struct cxd *ci, u16 address, unsigned int *val)
{
	int status;
	u8 addr[2] = {address & 0xff, address >> 8};

	status = regmap_raw_write(ci->regmap, 2, addr, 2);
	if (!status)
		status = regmap_read(ci->regmap, 3, val);
	return status;
}

static int write_io(struct cxd *ci, u16 address, u8 val)
{
	int status;
	u8 addr[2] = {address & 0xff, address >> 8};

	status = regmap_raw_write(ci->regmap, 2, addr, 2);
	if (!status)
		status = regmap_write(ci->regmap, 3, val);
	return status;
}

static int write_regm(struct cxd *ci, u8 reg, u8 val, u8 mask)
{
	int status = 0;
	unsigned int regval;

	if (ci->lastaddress != reg)
		status = regmap_write(ci->regmap, 0, reg);
	if (!status && reg >= 6 && reg <= 8 && mask != 0xff) {
		status = regmap_read(ci->regmap, 1, &regval);
		ci->regs[reg] = regval;
	}
	ci->lastaddress = reg;
	ci->regs[reg] = (ci->regs[reg] & (~mask)) | val;
	if (!status)
		status = regmap_write(ci->regmap, 1, ci->regs[reg]);
	if (reg == 0x20)
		ci->regs[reg] &= 0x7f;
	return status;
}

static int write_reg(struct cxd *ci, u8 reg, u8 val)
{
	return write_regm(ci, reg, val, 0xff);
}

static int write_block(struct cxd *ci, u8 adr, u8 *data, u16 n)
{
	int status = 0;
	u8 *buf = ci->wbuf;

	if (ci->lastaddress != adr)
		status = regmap_write(ci->regmap, 0, adr);
	if (status)
		return status;

	ci->lastaddress = adr;
	while (n) {
		int len = n;

		if (ci->cfg.max_i2c && (len + 1 > ci->cfg.max_i2c))
			len = ci->cfg.max_i2c - 1;
		memcpy(buf, data, len);
		status = regmap_raw_write(ci->regmap, 1, buf, len);
		if (status)
			return status;
		n -= len;
		data += len;
	}
	return status;
}

static void set_mode(struct cxd *ci, int mode)
{
	if (mode == ci->mode)
		return;

	switch (mode) {
	case 0x00: /* IO mem */
		write_regm(ci, 0x06, 0x00, 0x07);
		break;
	case 0x01: /* ATT mem */
		write_regm(ci, 0x06, 0x02, 0x07);
		break;
	default:
		break;
	}
	ci->mode = mode;
}

static void cam_mode(struct cxd *ci, int mode)
{
	u8 dummy;

	if (mode == ci->cammode)
		return;

	switch (mode) {
	case 0x00:
		write_regm(ci, 0x20, 0x80, 0x80);
		break;
	case 0x01:
		if (!ci->en.read_data)
			return;
		ci->write_busy = 0;
		dev_info(&ci->client->dev, "enable cam buffer mode\n");
		write_reg(ci, 0x0d, 0x00);
		write_reg(ci, 0x0e, 0x01);
		write_regm(ci, 0x08, 0x40, 0x40);
		read_reg(ci, 0x12, &dummy);
		write_regm(ci, 0x08, 0x80, 0x80);
		break;
	default:
		break;
	}
	ci->cammode = mode;
}

static int init(struct cxd *ci)
{
	int status;

	mutex_lock(&ci->lock);
	ci->mode = -1;
	do {
		status = write_reg(ci, 0x00, 0x00);
		if (status < 0)
			break;
		status = write_reg(ci, 0x01, 0x00);
		if (status < 0)
			break;
		status = write_reg(ci, 0x02, 0x10);
		if (status < 0)
			break;
		status = write_reg(ci, 0x03, 0x00);
		if (status < 0)
			break;
		status = write_reg(ci, 0x05, 0xFF);
		if (status < 0)
			break;
		status = write_reg(ci, 0x06, 0x1F);
		if (status < 0)
			break;
		status = write_reg(ci, 0x07, 0x1F);
		if (status < 0)
			break;
		status = write_reg(ci, 0x08, 0x28);
		if (status < 0)
			break;
		status = write_reg(ci, 0x14, 0x20);
		if (status < 0)
			break;

		/* TOSTRT = 8, Mode B (gated clock), falling Edge,
		 * Serial, POL=HIGH, MSB
		 */
		status = write_reg(ci, 0x0A, 0xA7);
		if (status < 0)
			break;

		status = write_reg(ci, 0x0B, 0x33);
		if (status < 0)
			break;
		status = write_reg(ci, 0x0C, 0x33);
		if (status < 0)
			break;

		status = write_regm(ci, 0x14, 0x00, 0x0F);
		if (status < 0)
			break;
		status = write_reg(ci, 0x15, ci->clk_reg_b);
		if (status < 0)
			break;
		status = write_regm(ci, 0x16, 0x00, 0x0F);
		if (status < 0)
			break;
		status = write_reg(ci, 0x17, ci->clk_reg_f);
		if (status < 0)
			break;

		if (ci->cfg.clock_mode == 2) {
			/* bitrate*2^13/ 72000 */
			u32 reg = ((ci->cfg.bitrate << 13) + 71999) / 72000;

			if (ci->cfg.polarity) {
				status = write_reg(ci, 0x09, 0x6f);
				if (status < 0)
					break;
			} else {
				status = write_reg(ci, 0x09, 0x6d);
				if (status < 0)
					break;
			}
			status = write_reg(ci, 0x20, 0x08);
			if (status < 0)
				break;
			status = write_reg(ci, 0x21, (reg >> 8) & 0xff);
			if (status < 0)
				break;
			status = write_reg(ci, 0x22, reg & 0xff);
			if (status < 0)
				break;
		} else if (ci->cfg.clock_mode == 1) {
			if (ci->cfg.polarity) {
				status = write_reg(ci, 0x09, 0x6f); /* D */
				if (status < 0)
					break;
			} else {
				status = write_reg(ci, 0x09, 0x6d);
				if (status < 0)
					break;
			}
			status = write_reg(ci, 0x20, 0x68);
			if (status < 0)
				break;
			status = write_reg(ci, 0x21, 0x00);
			if (status < 0)
				break;
			status = write_reg(ci, 0x22, 0x02);
			if (status < 0)
				break;
		} else {
			if (ci->cfg.polarity) {
				status = write_reg(ci, 0x09, 0x4f); /* C */
				if (status < 0)
					break;
			} else {
				status = write_reg(ci, 0x09, 0x4d);
				if (status < 0)
					break;
			}
			status = write_reg(ci, 0x20, 0x28);
			if (status < 0)
				break;
			status = write_reg(ci, 0x21, 0x00);
			if (status < 0)
				break;
			status = write_reg(ci, 0x22, 0x07);
			if (status < 0)
				break;
		}

		status = write_regm(ci, 0x20, 0x80, 0x80);
		if (status < 0)
			break;
		status = write_regm(ci, 0x03, 0x02, 0x02);
		if (status < 0)
			break;
		status = write_reg(ci, 0x01, 0x04);
		if (status < 0)
			break;
		status = write_reg(ci, 0x00, 0x31);
		if (status < 0)
			break;

		/* Put TS in bypass */
		status = write_regm(ci, 0x09, 0x08, 0x08);
		if (status < 0)
			break;
		ci->cammode = -1;
		cam_mode(ci, 0);
	} while (0);
	mutex_unlock(&ci->lock);

	return 0;
}

static int read_attribute_mem(struct dvb_ca_en50221 *ca,
			      int slot, int address)
{
	struct cxd *ci = ca->data;
	u8 val;

	mutex_lock(&ci->lock);
	set_mode(ci, 1);
	read_pccard(ci, address, &val, 1);
	mutex_unlock(&ci->lock);
	return val;
}

static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot,
			       int address, u8 value)
{
	struct cxd *ci = ca->data;

	mutex_lock(&ci->lock);
	set_mode(ci, 1);
	write_pccard(ci, address, &value, 1);
	mutex_unlock(&ci->lock);
	return 0;
}

static int read_cam_control(struct dvb_ca_en50221 *ca,
			    int slot, u8 address)
{
	struct cxd *ci = ca->data;
	unsigned int val;

	mutex_lock(&ci->lock);
	set_mode(ci, 0);
	read_io(ci, address, &val);
	mutex_unlock(&ci->lock);
	return val;
}

static int write_cam_control(struct dvb_ca_en50221 *ca, int slot,
			     u8 address, u8 value)
{
	struct cxd *ci = ca->data;

	mutex_lock(&ci->lock);
	set_mode(ci, 0);
	write_io(ci, address, value);
	mutex_unlock(&ci->lock);
	return 0;
}

static int slot_reset(struct dvb_ca_en50221 *ca, int slot)
{
	struct cxd *ci = ca->data;

	if (ci->cammode)
		read_data(ca, slot, ci->rbuf, 0);

	mutex_lock(&ci->lock);
	cam_mode(ci, 0);
	write_reg(ci, 0x00, 0x21);
	write_reg(ci, 0x06, 0x1F);
	write_reg(ci, 0x00, 0x31);
	write_regm(ci, 0x20, 0x80, 0x80);
	write_reg(ci, 0x03, 0x02);
	ci->ready = 0;
	ci->mode = -1;
	{
		int i;

		for (i = 0; i < 100; i++) {
			usleep_range(10000, 11000);
			if (ci->ready)
				break;
		}
	}
	mutex_unlock(&ci->lock);
	return 0;
}

static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot)
{
	struct cxd *ci = ca->data;

	dev_dbg(&ci->client->dev, "%s\n", __func__);
	if (ci->cammode)
		read_data(ca, slot, ci->rbuf, 0);
	mutex_lock(&ci->lock);
	write_reg(ci, 0x00, 0x21);
	write_reg(ci, 0x06, 0x1F);
	msleep(300);

	write_regm(ci, 0x09, 0x08, 0x08);
	write_regm(ci, 0x20, 0x80, 0x80); /* Reset CAM Mode */
	write_regm(ci, 0x06, 0x07, 0x07); /* Clear IO Mode */

	ci->mode = -1;
	ci->write_busy = 0;
	mutex_unlock(&ci->lock);
	return 0;
}

static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot)
{
	struct cxd *ci = ca->data;

	mutex_lock(&ci->lock);
	write_regm(ci, 0x09, 0x00, 0x08);
	set_mode(ci, 0);
	cam_mode(ci, 1);
	mutex_unlock(&ci->lock);
	return 0;
}

static int campoll(struct cxd *ci)
{
	u8 istat;

	read_reg(ci, 0x04, &istat);
	if (!istat)
		return 0;
	write_reg(ci, 0x05, istat);

	if (istat & 0x40)
		ci->dr = 1;
	if (istat & 0x20)
		ci->write_busy = 0;

	if (istat & 2) {
		u8 slotstat;

		read_reg(ci, 0x01, &slotstat);
		if (!(2 & slotstat)) {
			if (!ci->slot_stat) {
				ci->slot_stat |=
					      DVB_CA_EN50221_POLL_CAM_PRESENT;
				write_regm(ci, 0x03, 0x08, 0x08);
			}

		} else {
			if (ci->slot_stat) {
				ci->slot_stat = 0;
				write_regm(ci, 0x03, 0x00, 0x08);
				dev_info(&ci->client->dev, "NO CAM\n");
				ci->ready = 0;
			}
		}
		if ((istat & 8) &&
		    ci->slot_stat == DVB_CA_EN50221_POLL_CAM_PRESENT) {
			ci->ready = 1;
			ci->slot_stat |= DVB_CA_EN50221_POLL_CAM_READY;
		}
	}
	return 0;
}

static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open)
{
	struct cxd *ci = ca->data;
	u8 slotstat;

	mutex_lock(&ci->lock);
	campoll(ci);
	read_reg(ci, 0x01, &slotstat);
	mutex_unlock(&ci->lock);

	return ci->slot_stat;
}

static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
{
	struct cxd *ci = ca->data;
	u8 msb, lsb;
	u16 len;

	mutex_lock(&ci->lock);
	campoll(ci);
	mutex_unlock(&ci->lock);

	if (!ci->dr)
		return 0;

	mutex_lock(&ci->lock);
	read_reg(ci, 0x0f, &msb);
	read_reg(ci, 0x10, &lsb);
	len = ((u16)msb << 8) | lsb;
	if (len > ecount || len < 2) {
		/* read it anyway or cxd may hang */
		read_block(ci, 0x12, ci->rbuf, len);
		mutex_unlock(&ci->lock);
		return -EIO;
	}
	read_block(ci, 0x12, ebuf, len);
	ci->dr = 0;
	mutex_unlock(&ci->lock);
	return len;
}

static int write_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
{
	struct cxd *ci = ca->data;

	if (ci->write_busy)
		return -EAGAIN;
	mutex_lock(&ci->lock);
	write_reg(ci, 0x0d, ecount >> 8);
	write_reg(ci, 0x0e, ecount & 0xff);
	write_block(ci, 0x11, ebuf, ecount);
	ci->write_busy = 1;
	mutex_unlock(&ci->lock);
	return ecount;
}

static struct dvb_ca_en50221 en_templ = {
	.read_attribute_mem  = read_attribute_mem,
	.write_attribute_mem = write_attribute_mem,
	.read_cam_control    = read_cam_control,
	.write_cam_control   = write_cam_control,
	.slot_reset          = slot_reset,
	.slot_shutdown       = slot_shutdown,
	.slot_ts_enable      = slot_ts_enable,
	.poll_slot_status    = poll_slot_status,
	.read_data           = read_data,
	.write_data          = write_data,
};

static int cxd2099_probe(struct i2c_client *client,
			 const struct i2c_device_id *id)
{
	struct cxd *ci;
	struct cxd2099_cfg *cfg = client->dev.platform_data;
	static const struct regmap_config rm_cfg = {
		.reg_bits = 8,
		.val_bits = 8,
	};
	unsigned int val;
	int ret;

	ci = kzalloc(sizeof(*ci), GFP_KERNEL);
	if (!ci) {
		ret = -ENOMEM;
		goto err;
	}

	ci->client = client;
	memcpy(&ci->cfg, cfg, sizeof(ci->cfg));

	ci->regmap = regmap_init_i2c(client, &rm_cfg);
	if (IS_ERR(ci->regmap)) {
		ret = PTR_ERR(ci->regmap);
		goto err_kfree;
	}

	ret = regmap_read(ci->regmap, 0x00, &val);
	if (ret < 0) {
		dev_info(&client->dev, "No CXD2099AR detected at 0x%02x\n",
			 client->addr);
		goto err_rmexit;
	}

	mutex_init(&ci->lock);
	ci->lastaddress = 0xff;
	ci->clk_reg_b = 0x4a;
	ci->clk_reg_f = 0x1b;

	ci->en = en_templ;
	ci->en.data = ci;
	init(ci);
	dev_info(&client->dev, "Attached CXD2099AR at 0x%02x\n", client->addr);

	*cfg->en = &ci->en;

	if (!buffermode) {
		ci->en.read_data = NULL;
		ci->en.write_data = NULL;
	} else {
		dev_info(&client->dev, "Using CXD2099AR buffer mode");
	}

	i2c_set_clientdata(client, ci);

	return 0;

err_rmexit:
	regmap_exit(ci->regmap);
err_kfree:
	kfree(ci);
err:

	return ret;
}

static int cxd2099_remove(struct i2c_client *client)
{
	struct cxd *ci = i2c_get_clientdata(client);

	regmap_exit(ci->regmap);
	kfree(ci);

	return 0;
}

static const struct i2c_device_id cxd2099_id[] = {
	{"cxd2099", 0},
	{}
};
MODULE_DEVICE_TABLE(i2c, cxd2099_id);

static struct i2c_driver cxd2099_driver = {
	.driver = {
		.name	= "cxd2099",
	},
	.probe		= cxd2099_probe,
	.remove		= cxd2099_remove,
	.id_table	= cxd2099_id,
};

module_i2c_driver(cxd2099_driver);

MODULE_DESCRIPTION("CXD2099AR Common Interface controller driver");
MODULE_AUTHOR("Ralph Metzler");
MODULE_LICENSE("GPL");
Commit	Line	Data
0f0b270f RM	1	/*
	2	* cxd2099.c: Driver for the CXD2099AR Common Interface Controller
	3	*
dd3c5d00	4	* Copyright (C) 2010-2013 Digital Devices GmbH
0f0b270f	5	*
0f0b270f RM	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* version 2 only, as published by the Free Software Foundation.
	9	*
0f0b270f RM	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
0f0b270f RM	14	*/
0f0b270f RM	15
0f0b270f RM	16	#include <linux/slab.h>
	17	#include <linux/kernel.h>
	18	#include <linux/module.h>
0f0b270f	19	#include <linux/i2c.h>
81a70591	20	#include <linux/regmap.h>
0f0b270f RM	21	#include <linux/wait.h>
	22	#include <linux/delay.h>
	23	#include <linux/mutex.h>
	24	#include <linux/io.h>
	25
	26	#include "cxd2099.h"
	27
2b64e4de DS	28	static int buffermode;
2b64e4de DS	29	module_param(buffermode, int, 0444);
6c84bbfe	30	MODULE_PARM_DESC(buffermode, "Enable CXD2099AR buffer mode (default: disabled)");
dd3c5d00 RM	31
dd3c5d00 RM	32	static int read_data(struct dvb_ca_en50221 ca, int slot, u8 ebuf, int ecount);
0f0b270f RM	33
	34	struct cxd {
	35	struct dvb_ca_en50221 en;
	36
6eb94193	37	struct cxd2099_cfg cfg;
81a70591 DS	38	struct i2c_client *client;
81a70591 DS	39	struct regmap *regmap;
6eb94193	40
0f0b270f RM	41	u8 regs[0x23];
	42	u8 lastaddress;
	43	u8 clk_reg_f;
	44	u8 clk_reg_b;
	45	int mode;
0f0b270f RM	46	int ready;
0f0b270f RM	47	int dr;
dd3c5d00	48	int write_busy;
0f0b270f RM	49	int slot_stat;
	50
	51	u8 amem[1024];
	52	int amem_read;
	53
	54	int cammode;
65ac8c84	55	struct mutex lock; /* device access lock */
dd3c5d00 RM	56
	57	u8 rbuf[1028];
	58	u8 wbuf[1028];
0f0b270f RM	59	};
0f0b270f RM	60
dd3c5d00	61	static int read_block(struct cxd ci, u8 adr, u8 data, u16 n)
0f0b270f	62	{
dd3c5d00	63	int status = 0;
0f0b270f	64
dd3c5d00	65	if (ci->lastaddress != adr)
81a70591	66	status = regmap_write(ci->regmap, 0, adr);
0f0b270f RM	67	if (!status) {
0f0b270f RM	68	ci->lastaddress = adr;
dd3c5d00 RM	69
	70	while (n) {
	71	int len = n;
	72
65ac8c84	73	if (ci->cfg.max_i2c && len > ci->cfg.max_i2c)
dd3c5d00	74	len = ci->cfg.max_i2c;
81a70591	75	status = regmap_raw_read(ci->regmap, 1, data, len);
dd3c5d00 RM	76	if (status)
	77	return status;
	78	data += len;
	79	n -= len;
	80	}
0f0b270f RM	81	}
	82	return status;
	83	}
	84
	85	static int read_reg(struct cxd ci, u8 reg, u8 val)
	86	{
	87	return read_block(ci, reg, val, 1);
	88	}
	89
0f0b270f RM	90	static int read_pccard(struct cxd ci, u16 address, u8 data, u8 n)
	91	{
	92	int status;
81a70591	93	u8 addr[2] = {address & 0xff, address >> 8};
0f0b270f	94
81a70591	95	status = regmap_raw_write(ci->regmap, 2, addr, 2);
0f0b270f	96	if (!status)
81a70591	97	status = regmap_raw_read(ci->regmap, 3, data, n);
0f0b270f RM	98	return status;
	99	}
	100
	101	static int write_pccard(struct cxd ci, u16 address, u8 data, u8 n)
	102	{
	103	int status;
81a70591	104	u8 addr[2] = {address & 0xff, address >> 8};
0f0b270f	105
81a70591	106	status = regmap_raw_write(ci->regmap, 2, addr, 2);
0f0b270f	107	if (!status) {
81a70591	108	u8 buf[256];
fcf1b73d	109
81a70591 DS	110	memcpy(buf, data, n);
81a70591 DS	111	status = regmap_raw_write(ci->regmap, 3, buf, n);
0f0b270f RM	112	}
	113	return status;
	114	}
	115
81a70591	116	static int read_io(struct cxd ci, u16 address, unsigned int val)
0f0b270f RM	117	{
0f0b270f RM	118	int status;
81a70591	119	u8 addr[2] = {address & 0xff, address >> 8};
0f0b270f	120
81a70591	121	status = regmap_raw_write(ci->regmap, 2, addr, 2);
0f0b270f	122	if (!status)
81a70591	123	status = regmap_read(ci->regmap, 3, val);
0f0b270f RM	124	return status;
	125	}
	126
	127	static int write_io(struct cxd *ci, u16 address, u8 val)
	128	{
	129	int status;
81a70591	130	u8 addr[2] = {address & 0xff, address >> 8};
0f0b270f	131
81a70591	132	status = regmap_raw_write(ci->regmap, 2, addr, 2);
0f0b270f	133	if (!status)
81a70591	134	status = regmap_write(ci->regmap, 3, val);
0f0b270f RM	135	return status;
	136	}
	137
0f0b270f RM	138	static int write_regm(struct cxd *ci, u8 reg, u8 val, u8 mask)
0f0b270f RM	139	{
dd3c5d00	140	int status = 0;
81a70591	141	unsigned int regval;
0f0b270f	142
dd3c5d00	143	if (ci->lastaddress != reg)
81a70591 DS	144	status = regmap_write(ci->regmap, 0, reg);
	145	if (!status && reg >= 6 && reg <= 8 && mask != 0xff) {
	146	status = regmap_read(ci->regmap, 1, &regval);
	147	ci->regs[reg] = regval;
	148	}
dd3c5d00	149	ci->lastaddress = reg;
6eb94193	150	ci->regs[reg] = (ci->regs[reg] & (~mask)) \| val;
dd3c5d00	151	if (!status)
81a70591	152	status = regmap_write(ci->regmap, 1, ci->regs[reg]);
0f0b270f RM	153	if (reg == 0x20)
	154	ci->regs[reg] &= 0x7f;
	155	return status;
	156	}
	157
	158	static int write_reg(struct cxd *ci, u8 reg, u8 val)
	159	{
	160	return write_regm(ci, reg, val, 0xff);
	161	}
	162
dd3c5d00	163	static int write_block(struct cxd ci, u8 adr, u8 data, u16 n)
0f0b270f	164	{
dd3c5d00 RM	165	int status = 0;
	166	u8 *buf = ci->wbuf;
	167
	168	if (ci->lastaddress != adr)
81a70591	169	status = regmap_write(ci->regmap, 0, adr);
dd3c5d00 RM	170	if (status)
dd3c5d00 RM	171	return status;
dd3c5d00 RM	172
dd3c5d00 RM	173	ci->lastaddress = adr;
dd3c5d00 RM	174	while (n) {
	175	int len = n;
	176
	177	if (ci->cfg.max_i2c && (len + 1 > ci->cfg.max_i2c))
	178	len = ci->cfg.max_i2c - 1;
81a70591 DS	179	memcpy(buf, data, len);
81a70591 DS	180	status = regmap_raw_write(ci->regmap, 1, buf, len);
dd3c5d00 RM	181	if (status)
	182	return status;
	183	n -= len;
	184	data += len;
0f0b270f RM	185	}
	186	return status;
	187	}
0f0b270f RM	188
	189	static void set_mode(struct cxd *ci, int mode)
	190	{
	191	if (mode == ci->mode)
	192	return;
	193
	194	switch (mode) {
	195	case 0x00: /* IO mem */
	196	write_regm(ci, 0x06, 0x00, 0x07);
	197	break;
	198	case 0x01: /* ATT mem */
	199	write_regm(ci, 0x06, 0x02, 0x07);
	200	break;
	201	default:
	202	break;
	203	}
	204	ci->mode = mode;
	205	}
	206
	207	static void cam_mode(struct cxd *ci, int mode)
	208	{
dd3c5d00 RM	209	u8 dummy;
dd3c5d00 RM	210
0f0b270f RM	211	if (mode == ci->cammode)
	212	return;
	213
	214	switch (mode) {
	215	case 0x00:
	216	write_regm(ci, 0x20, 0x80, 0x80);
	217	break;
	218	case 0x01:
6eb94193 RM	219	if (!ci->en.read_data)
6eb94193 RM	220	return;
dd3c5d00	221	ci->write_busy = 0;
81a70591	222	dev_info(&ci->client->dev, "enable cam buffer mode\n");
dd3c5d00 RM	223	write_reg(ci, 0x0d, 0x00);
dd3c5d00 RM	224	write_reg(ci, 0x0e, 0x01);
0f0b270f	225	write_regm(ci, 0x08, 0x40, 0x40);
dd3c5d00	226	read_reg(ci, 0x12, &dummy);
0f0b270f RM	227	write_regm(ci, 0x08, 0x80, 0x80);
	228	break;
	229	default:
	230	break;
	231	}
	232	ci->cammode = mode;
	233	}
	234
0f0b270f RM	235	static int init(struct cxd *ci)
	236	{
	237	int status;
	238
	239	mutex_lock(&ci->lock);
	240	ci->mode = -1;
	241	do {
af070bd6 MCC	242	status = write_reg(ci, 0x00, 0x00);
	243	if (status < 0)
	244	break;
	245	status = write_reg(ci, 0x01, 0x00);
	246	if (status < 0)
	247	break;
	248	status = write_reg(ci, 0x02, 0x10);
	249	if (status < 0)
	250	break;
	251	status = write_reg(ci, 0x03, 0x00);
	252	if (status < 0)
	253	break;
	254	status = write_reg(ci, 0x05, 0xFF);
	255	if (status < 0)
	256	break;
	257	status = write_reg(ci, 0x06, 0x1F);
	258	if (status < 0)
	259	break;
	260	status = write_reg(ci, 0x07, 0x1F);
	261	if (status < 0)
	262	break;
	263	status = write_reg(ci, 0x08, 0x28);
	264	if (status < 0)
	265	break;
	266	status = write_reg(ci, 0x14, 0x20);
	267	if (status < 0)
	268	break;
	269
4fe130f2	270	/* TOSTRT = 8, Mode B (gated clock), falling Edge,
0907bb2c EL	271	* Serial, POL=HIGH, MSB
0907bb2c EL	272	*/
4fe130f2	273	status = write_reg(ci, 0x0A, 0xA7);
af070bd6 MCC	274	if (status < 0)
	275	break;
	276
	277	status = write_reg(ci, 0x0B, 0x33);
	278	if (status < 0)
	279	break;
	280	status = write_reg(ci, 0x0C, 0x33);
	281	if (status < 0)
	282	break;
	283
	284	status = write_regm(ci, 0x14, 0x00, 0x0F);
	285	if (status < 0)
	286	break;
	287	status = write_reg(ci, 0x15, ci->clk_reg_b);
	288	if (status < 0)
	289	break;
	290	status = write_regm(ci, 0x16, 0x00, 0x0F);
	291	if (status < 0)
	292	break;
	293	status = write_reg(ci, 0x17, ci->clk_reg_f);
	294	if (status < 0)
	295	break;
0f0b270f	296
dd3c5d00 RM	297	if (ci->cfg.clock_mode == 2) {
	298	/* bitrate2^13/ 72000 /
	299	u32 reg = ((ci->cfg.bitrate << 13) + 71999) / 72000;
	300
6eb94193	301	if (ci->cfg.polarity) {
af070bd6 MCC	302	status = write_reg(ci, 0x09, 0x6f);
	303	if (status < 0)
	304	break;
6eb94193	305	} else {
af070bd6 MCC	306	status = write_reg(ci, 0x09, 0x6d);
	307	if (status < 0)
	308	break;
6eb94193	309	}
dd3c5d00 RM	310	status = write_reg(ci, 0x20, 0x08);
	311	if (status < 0)
	312	break;
	313	status = write_reg(ci, 0x21, (reg >> 8) & 0xff);
	314	if (status < 0)
	315	break;
	316	status = write_reg(ci, 0x22, reg & 0xff);
	317	if (status < 0)
	318	break;
	319	} else if (ci->cfg.clock_mode == 1) {
	320	if (ci->cfg.polarity) {
	321	status = write_reg(ci, 0x09, 0x6f); /* D */
	322	if (status < 0)
	323	break;
	324	} else {
	325	status = write_reg(ci, 0x09, 0x6d);
	326	if (status < 0)
	327	break;
	328	}
af070bd6 MCC	329	status = write_reg(ci, 0x20, 0x68);
	330	if (status < 0)
	331	break;
	332	status = write_reg(ci, 0x21, 0x00);
	333	if (status < 0)
	334	break;
	335	status = write_reg(ci, 0x22, 0x02);
	336	if (status < 0)
	337	break;
6eb94193 RM	338	} else {
6eb94193 RM	339	if (ci->cfg.polarity) {
dd3c5d00	340	status = write_reg(ci, 0x09, 0x4f); /* C */
af070bd6 MCC	341	if (status < 0)
af070bd6 MCC	342	break;
6eb94193	343	} else {
af070bd6 MCC	344	status = write_reg(ci, 0x09, 0x4d);
	345	if (status < 0)
	346	break;
6eb94193	347	}
af070bd6 MCC	348	status = write_reg(ci, 0x20, 0x28);
	349	if (status < 0)
	350	break;
	351	status = write_reg(ci, 0x21, 0x00);
	352	if (status < 0)
	353	break;
	354	status = write_reg(ci, 0x22, 0x07);
	355	if (status < 0)
	356	break;
6eb94193	357	}
0f0b270f	358
af070bd6 MCC	359	status = write_regm(ci, 0x20, 0x80, 0x80);
	360	if (status < 0)
	361	break;
	362	status = write_regm(ci, 0x03, 0x02, 0x02);
	363	if (status < 0)
	364	break;
	365	status = write_reg(ci, 0x01, 0x04);
	366	if (status < 0)
	367	break;
	368	status = write_reg(ci, 0x00, 0x31);
	369	if (status < 0)
	370	break;
0f0b270f	371
6eb94193	372	/* Put TS in bypass */
af070bd6 MCC	373	status = write_regm(ci, 0x09, 0x08, 0x08);
	374	if (status < 0)
	375	break;
0f0b270f	376	ci->cammode = -1;
0f0b270f	377	cam_mode(ci, 0);
0f0b270f RM	378	} while (0);
	379	mutex_unlock(&ci->lock);
	380
	381	return 0;
	382	}
	383
0f0b270f RM	384	static int read_attribute_mem(struct dvb_ca_en50221 *ca,
	385	int slot, int address)
	386	{
	387	struct cxd *ci = ca->data;
	388	u8 val;
fcf1b73d	389
0f0b270f RM	390	mutex_lock(&ci->lock);
	391	set_mode(ci, 1);
	392	read_pccard(ci, address, &val, 1);
	393	mutex_unlock(&ci->lock);
	394	return val;
	395	}
	396
0f0b270f RM	397	static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot,
	398	int address, u8 value)
	399	{
	400	struct cxd *ci = ca->data;
	401
	402	mutex_lock(&ci->lock);
	403	set_mode(ci, 1);
	404	write_pccard(ci, address, &value, 1);
	405	mutex_unlock(&ci->lock);
	406	return 0;
	407	}
	408
	409	static int read_cam_control(struct dvb_ca_en50221 *ca,
	410	int slot, u8 address)
	411	{
	412	struct cxd *ci = ca->data;
81a70591	413	unsigned int val;
0f0b270f RM	414
	415	mutex_lock(&ci->lock);
	416	set_mode(ci, 0);
	417	read_io(ci, address, &val);
	418	mutex_unlock(&ci->lock);
	419	return val;
	420	}
	421
	422	static int write_cam_control(struct dvb_ca_en50221 *ca, int slot,
	423	u8 address, u8 value)
	424	{
	425	struct cxd *ci = ca->data;
	426
	427	mutex_lock(&ci->lock);
	428	set_mode(ci, 0);
	429	write_io(ci, address, value);
	430	mutex_unlock(&ci->lock);
	431	return 0;
	432	}
	433
	434	static int slot_reset(struct dvb_ca_en50221 *ca, int slot)
	435	{
	436	struct cxd *ci = ca->data;
	437
dd3c5d00 RM	438	if (ci->cammode)
	439	read_data(ca, slot, ci->rbuf, 0);
	440
0f0b270f RM	441	mutex_lock(&ci->lock);
	442	cam_mode(ci, 0);
	443	write_reg(ci, 0x00, 0x21);
	444	write_reg(ci, 0x06, 0x1F);
	445	write_reg(ci, 0x00, 0x31);
	446	write_regm(ci, 0x20, 0x80, 0x80);
	447	write_reg(ci, 0x03, 0x02);
	448	ci->ready = 0;
	449	ci->mode = -1;
	450	{
	451	int i;
1f9f72f4	452
0f0b270f	453	for (i = 0; i < 100; i++) {
c3cefd3c	454	usleep_range(10000, 11000);
0f0b270f RM	455	if (ci->ready)
	456	break;
	457	}
	458	}
	459	mutex_unlock(&ci->lock);
0f0b270f RM	460	return 0;
	461	}
	462
	463	static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot)
	464	{
	465	struct cxd *ci = ca->data;
	466
81a70591	467	dev_dbg(&ci->client->dev, "%s\n", __func__);
dd3c5d00 RM	468	if (ci->cammode)
dd3c5d00 RM	469	read_data(ca, slot, ci->rbuf, 0);
0f0b270f	470	mutex_lock(&ci->lock);
dd3c5d00 RM	471	write_reg(ci, 0x00, 0x21);
	472	write_reg(ci, 0x06, 0x1F);
	473	msleep(300);
	474
6eb94193 RM	475	write_regm(ci, 0x09, 0x08, 0x08);
	476	write_regm(ci, 0x20, 0x80, 0x80); /* Reset CAM Mode */
	477	write_regm(ci, 0x06, 0x07, 0x07); /* Clear IO Mode */
dd3c5d00	478
0f0b270f	479	ci->mode = -1;
dd3c5d00	480	ci->write_busy = 0;
0f0b270f	481	mutex_unlock(&ci->lock);
6eb94193	482	return 0;
0f0b270f RM	483	}
	484
	485	static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot)
	486	{
	487	struct cxd *ci = ca->data;
	488
	489	mutex_lock(&ci->lock);
	490	write_regm(ci, 0x09, 0x00, 0x08);
	491	set_mode(ci, 0);
0f0b270f	492	cam_mode(ci, 1);
0f0b270f RM	493	mutex_unlock(&ci->lock);
	494	return 0;
	495	}
	496
0f0b270f RM	497	static int campoll(struct cxd *ci)
	498	{
	499	u8 istat;
	500
	501	read_reg(ci, 0x04, &istat);
	502	if (!istat)
	503	return 0;
	504	write_reg(ci, 0x05, istat);
	505
64754837	506	if (istat & 0x40)
0f0b270f	507	ci->dr = 1;
64754837	508	if (istat & 0x20)
dd3c5d00	509	ci->write_busy = 0;
0f0b270f	510
03173b48	511	if (istat & 2) {
0f0b270f RM	512	u8 slotstat;
	513
	514	read_reg(ci, 0x01, &slotstat);
03173b48	515	if (!(2 & slotstat)) {
0f0b270f	516	if (!ci->slot_stat) {
dd3c5d00 RM	517	ci->slot_stat \|=
dd3c5d00 RM	518	DVB_CA_EN50221_POLL_CAM_PRESENT;
0f0b270f RM	519	write_regm(ci, 0x03, 0x08, 0x08);
	520	}
	521
	522	} else {
	523	if (ci->slot_stat) {
	524	ci->slot_stat = 0;
	525	write_regm(ci, 0x03, 0x00, 0x08);
81a70591	526	dev_info(&ci->client->dev, "NO CAM\n");
0f0b270f RM	527	ci->ready = 0;
	528	}
	529	}
dd3c5d00	530	if ((istat & 8) &&
65ac8c84	531	ci->slot_stat == DVB_CA_EN50221_POLL_CAM_PRESENT) {
0f0b270f RM	532	ci->ready = 1;
0f0b270f RM	533	ci->slot_stat \|= DVB_CA_EN50221_POLL_CAM_READY;
0f0b270f RM	534	}
	535	}
	536	return 0;
	537	}
	538
0f0b270f RM	539	static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open)
	540	{
	541	struct cxd *ci = ca->data;
	542	u8 slotstat;
	543
	544	mutex_lock(&ci->lock);
	545	campoll(ci);
	546	read_reg(ci, 0x01, &slotstat);
	547	mutex_unlock(&ci->lock);
	548
	549	return ci->slot_stat;
	550	}
	551
0f0b270f RM	552	static int read_data(struct dvb_ca_en50221 ca, int slot, u8 ebuf, int ecount)
	553	{
	554	struct cxd *ci = ca->data;
	555	u8 msb, lsb;
	556	u16 len;
	557
	558	mutex_lock(&ci->lock);
	559	campoll(ci);
	560	mutex_unlock(&ci->lock);
	561
0f0b270f RM	562	if (!ci->dr)
	563	return 0;
	564
	565	mutex_lock(&ci->lock);
	566	read_reg(ci, 0x0f, &msb);
	567	read_reg(ci, 0x10, &lsb);
dd3c5d00 RM	568	len = ((u16)msb << 8) \| lsb;
	569	if (len > ecount \|\| len < 2) {
	570	/* read it anyway or cxd may hang */
	571	read_block(ci, 0x12, ci->rbuf, len);
	572	mutex_unlock(&ci->lock);
	573	return -EIO;
	574	}
0f0b270f RM	575	read_block(ci, 0x12, ebuf, len);
	576	ci->dr = 0;
	577	mutex_unlock(&ci->lock);
0f0b270f RM	578	return len;
	579	}
	580
	581	static int write_data(struct dvb_ca_en50221 ca, int slot, u8 ebuf, int ecount)
	582	{
	583	struct cxd *ci = ca->data;
	584
dd3c5d00 RM	585	if (ci->write_busy)
dd3c5d00 RM	586	return -EAGAIN;
0f0b270f	587	mutex_lock(&ci->lock);
03173b48 TD	588	write_reg(ci, 0x0d, ecount >> 8);
03173b48 TD	589	write_reg(ci, 0x0e, ecount & 0xff);
0f0b270f	590	write_block(ci, 0x11, ebuf, ecount);
dd3c5d00	591	ci->write_busy = 1;
0f0b270f RM	592	mutex_unlock(&ci->lock);
	593	return ecount;
	594	}
0f0b270f RM	595
	596	static struct dvb_ca_en50221 en_templ = {
	597	.read_attribute_mem = read_attribute_mem,
	598	.write_attribute_mem = write_attribute_mem,
	599	.read_cam_control = read_cam_control,
	600	.write_cam_control = write_cam_control,
	601	.slot_reset = slot_reset,
	602	.slot_shutdown = slot_shutdown,
	603	.slot_ts_enable = slot_ts_enable,
	604	.poll_slot_status = poll_slot_status,
0f0b270f RM	605	.read_data = read_data,
0f0b270f RM	606	.write_data = write_data,
0f0b270f RM	607	};
0f0b270f RM	608
81a70591 DS	609	static int cxd2099_probe(struct i2c_client *client,
81a70591 DS	610	const struct i2c_device_id *id)
0f0b270f	611	{
4aff355c	612	struct cxd *ci;
81a70591 DS	613	struct cxd2099_cfg *cfg = client->dev.platform_data;
	614	static const struct regmap_config rm_cfg = {
	615	.reg_bits = 8,
	616	.val_bits = 8,
	617	};
	618	unsigned int val;
	619	int ret;
0f0b270f	620
81a70591 DS	621	ci = kzalloc(sizeof(*ci), GFP_KERNEL);
	622	if (!ci) {
	623	ret = -ENOMEM;
	624	goto err;
0f0b270f RM	625	}
0f0b270f RM	626
81a70591 DS	627	ci->client = client;
	628	memcpy(&ci->cfg, cfg, sizeof(ci->cfg));
	629
	630	ci->regmap = regmap_init_i2c(client, &rm_cfg);
	631	if (IS_ERR(ci->regmap)) {
	632	ret = PTR_ERR(ci->regmap);
	633	goto err_kfree;
	634	}
	635
	636	ret = regmap_read(ci->regmap, 0x00, &val);
	637	if (ret < 0) {
	638	dev_info(&client->dev, "No CXD2099AR detected at 0x%02x\n",
	639	client->addr);
	640	goto err_rmexit;
	641	}
0f0b270f RM	642
0f0b270f RM	643	mutex_init(&ci->lock);
0f0b270f RM	644	ci->lastaddress = 0xff;
	645	ci->clk_reg_b = 0x4a;
	646	ci->clk_reg_f = 0x1b;
0f0b270f	647
8d9b2584	648	ci->en = en_templ;
0f0b270f RM	649	ci->en.data = ci;
0f0b270f RM	650	init(ci);
81a70591 DS	651	dev_info(&client->dev, "Attached CXD2099AR at 0x%02x\n", client->addr);
	652
	653	*cfg->en = &ci->en;
2b64e4de DS	654
	655	if (!buffermode) {
	656	ci->en.read_data = NULL;
	657	ci->en.write_data = NULL;
	658	} else {
81a70591	659	dev_info(&client->dev, "Using CXD2099AR buffer mode");
2b64e4de DS	660	}
2b64e4de DS	661
81a70591 DS	662	i2c_set_clientdata(client, ci);
	663
	664	return 0;
	665
	666	err_rmexit:
	667	regmap_exit(ci->regmap);
	668	err_kfree:
	669	kfree(ci);
	670	err:
	671
	672	return ret;
0f0b270f	673	}
81a70591 DS	674
	675	static int cxd2099_remove(struct i2c_client *client)
	676	{
	677	struct cxd *ci = i2c_get_clientdata(client);
	678
	679	regmap_exit(ci->regmap);
	680	kfree(ci);
	681
	682	return 0;
	683	}
	684
	685	static const struct i2c_device_id cxd2099_id[] = {
	686	{"cxd2099", 0},
	687	{}
	688	};
	689	MODULE_DEVICE_TABLE(i2c, cxd2099_id);
	690
	691	static struct i2c_driver cxd2099_driver = {
	692	.driver = {
	693	.name = "cxd2099",
	694	},
	695	.probe = cxd2099_probe,
	696	.remove = cxd2099_remove,
	697	.id_table = cxd2099_id,
	698	};
	699
	700	module_i2c_driver(cxd2099_driver);
0f0b270f	701
6c84bbfe	702	MODULE_DESCRIPTION("CXD2099AR Common Interface controller driver");
6eb94193	703	MODULE_AUTHOR("Ralph Metzler");
0f0b270f	704	MODULE_LICENSE("GPL");