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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
b79cb653 | 2 | /* |
ca06fa79 PB |
3 | * Conexant cx24123/cx24109 - DVB QPSK Satellite demod/tuner driver |
4 | * | |
6d897616 | 5 | * Copyright (C) 2005 Steven Toth <stoth@linuxtv.org> |
ca06fa79 PB |
6 | * |
7 | * Support for KWorld DVB-S 100 by Vadim Catana <skystar@moldova.cc> | |
8 | * | |
9 | * Support for CX24123/CX24113-NIM by Patrick Boettcher <pb@linuxtv.org> | |
ca06fa79 | 10 | */ |
b79cb653 ST |
11 | |
12 | #include <linux/slab.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
b79cb653 | 15 | #include <linux/init.h> |
752a62b2 | 16 | #include <asm/div64.h> |
b79cb653 | 17 | |
fada1935 | 18 | #include <media/dvb_frontend.h> |
b79cb653 ST |
19 | #include "cx24123.h" |
20 | ||
a74b51fc VC |
21 | #define XTAL 10111000 |
22 | ||
70047f9c | 23 | static int force_band; |
93504abf ST |
24 | module_param(force_band, int, 0644); |
25 | MODULE_PARM_DESC(force_band, "Force a specific band select "\ | |
26 | "(1-9, default:off)."); | |
27 | ||
b79cb653 | 28 | static int debug; |
93504abf ST |
29 | module_param(debug, int, 0644); |
30 | MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)"); | |
ca06fa79 PB |
31 | |
32 | #define info(args...) do { printk(KERN_INFO "CX24123: " args); } while (0) | |
33 | #define err(args...) do { printk(KERN_ERR "CX24123: " args); } while (0) | |
34 | ||
b79cb653 ST |
35 | #define dprintk(args...) \ |
36 | do { \ | |
ca06fa79 PB |
37 | if (debug) { \ |
38 | printk(KERN_DEBUG "CX24123: %s: ", __func__); \ | |
39 | printk(args); \ | |
40 | } \ | |
b79cb653 ST |
41 | } while (0) |
42 | ||
93504abf ST |
43 | struct cx24123_state { |
44 | struct i2c_adapter *i2c; | |
45 | const struct cx24123_config *config; | |
b79cb653 ST |
46 | |
47 | struct dvb_frontend frontend; | |
48 | ||
b79cb653 ST |
49 | /* Some PLL specifics for tuning */ |
50 | u32 VCAarg; | |
51 | u32 VGAarg; | |
52 | u32 bandselectarg; | |
53 | u32 pllarg; | |
a74b51fc | 54 | u32 FILTune; |
b79cb653 | 55 | |
ca06fa79 PB |
56 | struct i2c_adapter tuner_i2c_adapter; |
57 | ||
58 | u8 demod_rev; | |
59 | ||
b79cb653 ST |
60 | /* The Demod/Tuner can't easily provide these, we cache them */ |
61 | u32 currentfreq; | |
62 | u32 currentsymbolrate; | |
63 | }; | |
64 | ||
e3b152bc | 65 | /* Various tuner defaults need to be established for a given symbol rate Sps */ |
93504abf | 66 | static struct cx24123_AGC_val { |
e3b152bc JS |
67 | u32 symbolrate_low; |
68 | u32 symbolrate_high; | |
e3b152bc JS |
69 | u32 VCAprogdata; |
70 | u32 VGAprogdata; | |
a74b51fc | 71 | u32 FILTune; |
e3b152bc JS |
72 | } cx24123_AGC_vals[] = |
73 | { | |
74 | { | |
75 | .symbolrate_low = 1000000, | |
76 | .symbolrate_high = 4999999, | |
a74b51fc VC |
77 | /* the specs recommend other values for VGA offsets, |
78 | but tests show they are wrong */ | |
0e4558ab YP |
79 | .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0, |
80 | .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x07, | |
81 | .FILTune = 0x27f /* 0.41 V */ | |
e3b152bc JS |
82 | }, |
83 | { | |
84 | .symbolrate_low = 5000000, | |
85 | .symbolrate_high = 14999999, | |
0e4558ab YP |
86 | .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0, |
87 | .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x1f, | |
a74b51fc | 88 | .FILTune = 0x317 /* 0.90 V */ |
e3b152bc JS |
89 | }, |
90 | { | |
91 | .symbolrate_low = 15000000, | |
92 | .symbolrate_high = 45000000, | |
0e4558ab YP |
93 | .VGAprogdata = (1 << 19) | (0x100 << 9) | 0x180, |
94 | .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x3f, | |
95 | .FILTune = 0x145 /* 2.70 V */ | |
e3b152bc JS |
96 | }, |
97 | }; | |
98 | ||
99 | /* | |
100 | * Various tuner defaults need to be established for a given frequency kHz. | |
101 | * fixme: The bounds on the bands do not match the doc in real life. | |
102 | * fixme: Some of them have been moved, other might need adjustment. | |
103 | */ | |
93504abf | 104 | static struct cx24123_bandselect_val { |
e3b152bc JS |
105 | u32 freq_low; |
106 | u32 freq_high; | |
e3b152bc | 107 | u32 VCOdivider; |
e3b152bc JS |
108 | u32 progdata; |
109 | } cx24123_bandselect_vals[] = | |
110 | { | |
70047f9c | 111 | /* band 1 */ |
e3b152bc JS |
112 | { |
113 | .freq_low = 950000, | |
e3b152bc | 114 | .freq_high = 1074999, |
e3b152bc | 115 | .VCOdivider = 4, |
70047f9c | 116 | .progdata = (0 << 19) | (0 << 9) | 0x40, |
e3b152bc | 117 | }, |
70047f9c YP |
118 | |
119 | /* band 2 */ | |
e3b152bc JS |
120 | { |
121 | .freq_low = 1075000, | |
70047f9c YP |
122 | .freq_high = 1177999, |
123 | .VCOdivider = 4, | |
124 | .progdata = (0 << 19) | (0 << 9) | 0x80, | |
e3b152bc | 125 | }, |
70047f9c YP |
126 | |
127 | /* band 3 */ | |
e3b152bc | 128 | { |
70047f9c YP |
129 | .freq_low = 1178000, |
130 | .freq_high = 1295999, | |
e3b152bc | 131 | .VCOdivider = 2, |
70047f9c | 132 | .progdata = (0 << 19) | (1 << 9) | 0x01, |
e3b152bc | 133 | }, |
70047f9c YP |
134 | |
135 | /* band 4 */ | |
e3b152bc | 136 | { |
70047f9c YP |
137 | .freq_low = 1296000, |
138 | .freq_high = 1431999, | |
e3b152bc | 139 | .VCOdivider = 2, |
70047f9c | 140 | .progdata = (0 << 19) | (1 << 9) | 0x02, |
e3b152bc | 141 | }, |
70047f9c YP |
142 | |
143 | /* band 5 */ | |
e3b152bc | 144 | { |
70047f9c YP |
145 | .freq_low = 1432000, |
146 | .freq_high = 1575999, | |
e3b152bc | 147 | .VCOdivider = 2, |
70047f9c | 148 | .progdata = (0 << 19) | (1 << 9) | 0x04, |
e3b152bc | 149 | }, |
70047f9c YP |
150 | |
151 | /* band 6 */ | |
e3b152bc | 152 | { |
70047f9c | 153 | .freq_low = 1576000, |
e3b152bc | 154 | .freq_high = 1717999, |
e3b152bc | 155 | .VCOdivider = 2, |
70047f9c | 156 | .progdata = (0 << 19) | (1 << 9) | 0x08, |
e3b152bc | 157 | }, |
70047f9c YP |
158 | |
159 | /* band 7 */ | |
e3b152bc JS |
160 | { |
161 | .freq_low = 1718000, | |
162 | .freq_high = 1855999, | |
e3b152bc | 163 | .VCOdivider = 2, |
70047f9c | 164 | .progdata = (0 << 19) | (1 << 9) | 0x10, |
e3b152bc | 165 | }, |
70047f9c YP |
166 | |
167 | /* band 8 */ | |
e3b152bc JS |
168 | { |
169 | .freq_low = 1856000, | |
170 | .freq_high = 2035999, | |
e3b152bc | 171 | .VCOdivider = 2, |
70047f9c | 172 | .progdata = (0 << 19) | (1 << 9) | 0x20, |
e3b152bc | 173 | }, |
70047f9c YP |
174 | |
175 | /* band 9 */ | |
e3b152bc JS |
176 | { |
177 | .freq_low = 2036000, | |
70047f9c | 178 | .freq_high = 2150000, |
e3b152bc | 179 | .VCOdivider = 2, |
70047f9c | 180 | .progdata = (0 << 19) | (1 << 9) | 0x40, |
e3b152bc JS |
181 | }, |
182 | }; | |
183 | ||
b79cb653 ST |
184 | static struct { |
185 | u8 reg; | |
186 | u8 data; | |
187 | } cx24123_regdata[] = | |
188 | { | |
189 | {0x00, 0x03}, /* Reset system */ | |
190 | {0x00, 0x00}, /* Clear reset */ | |
0e4558ab YP |
191 | {0x03, 0x07}, /* QPSK, DVB, Auto Acquisition (default) */ |
192 | {0x04, 0x10}, /* MPEG */ | |
193 | {0x05, 0x04}, /* MPEG */ | |
194 | {0x06, 0x31}, /* MPEG (default) */ | |
195 | {0x0b, 0x00}, /* Freq search start point (default) */ | |
196 | {0x0c, 0x00}, /* Demodulator sample gain (default) */ | |
d93f8860 | 197 | {0x0d, 0x7f}, /* Force driver to shift until the maximum (+-10 MHz) */ |
0e4558ab YP |
198 | {0x0e, 0x03}, /* Default non-inverted, FEC 3/4 (default) */ |
199 | {0x0f, 0xfe}, /* FEC search mask (all supported codes) */ | |
200 | {0x10, 0x01}, /* Default search inversion, no repeat (default) */ | |
201 | {0x16, 0x00}, /* Enable reading of frequency */ | |
202 | {0x17, 0x01}, /* Enable EsNO Ready Counter */ | |
203 | {0x1c, 0x80}, /* Enable error counter */ | |
204 | {0x20, 0x00}, /* Tuner burst clock rate = 500KHz */ | |
205 | {0x21, 0x15}, /* Tuner burst mode, word length = 0x15 */ | |
206 | {0x28, 0x00}, /* Enable FILTERV with positive pol., DiSEqC 2.x off */ | |
207 | {0x29, 0x00}, /* DiSEqC LNB_DC off */ | |
208 | {0x2a, 0xb0}, /* DiSEqC Parameters (default) */ | |
209 | {0x2b, 0x73}, /* DiSEqC Tone Frequency (default) */ | |
210 | {0x2c, 0x00}, /* DiSEqC Message (0x2c - 0x31) */ | |
b79cb653 ST |
211 | {0x2d, 0x00}, |
212 | {0x2e, 0x00}, | |
213 | {0x2f, 0x00}, | |
214 | {0x30, 0x00}, | |
215 | {0x31, 0x00}, | |
0e4558ab YP |
216 | {0x32, 0x8c}, /* DiSEqC Parameters (default) */ |
217 | {0x33, 0x00}, /* Interrupts off (0x33 - 0x34) */ | |
b79cb653 | 218 | {0x34, 0x00}, |
0e4558ab YP |
219 | {0x35, 0x03}, /* DiSEqC Tone Amplitude (default) */ |
220 | {0x36, 0x02}, /* DiSEqC Parameters (default) */ | |
221 | {0x37, 0x3a}, /* DiSEqC Parameters (default) */ | |
222 | {0x3a, 0x00}, /* Enable AGC accumulator (for signal strength) */ | |
223 | {0x44, 0x00}, /* Constellation (default) */ | |
224 | {0x45, 0x00}, /* Symbol count (default) */ | |
225 | {0x46, 0x0d}, /* Symbol rate estimator on (default) */ | |
18c053b3 | 226 | {0x56, 0xc1}, /* Error Counter = Viterbi BER */ |
0e4558ab | 227 | {0x57, 0xff}, /* Error Counter Window (default) */ |
d93f8860 | 228 | {0x5c, 0x20}, /* Acquisition AFC Expiration window (default is 0x10) */ |
0e4558ab | 229 | {0x67, 0x83}, /* Non-DCII symbol clock */ |
b79cb653 ST |
230 | }; |
231 | ||
ca06fa79 PB |
232 | static int cx24123_i2c_writereg(struct cx24123_state *state, |
233 | u8 i2c_addr, int reg, int data) | |
b79cb653 ST |
234 | { |
235 | u8 buf[] = { reg, data }; | |
ca06fa79 PB |
236 | struct i2c_msg msg = { |
237 | .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2 | |
238 | }; | |
b79cb653 ST |
239 | int err; |
240 | ||
ca06fa79 | 241 | /* printk(KERN_DEBUG "wr(%02x): %02x %02x\n", i2c_addr, reg, data); */ |
caf970e0 | 242 | |
93504abf ST |
243 | err = i2c_transfer(state->i2c, &msg, 1); |
244 | if (err != 1) { | |
4bd69e7b MCC |
245 | printk("%s: writereg error(err == %i, reg == 0x%02x, data == 0x%02x)\n", |
246 | __func__, err, reg, data); | |
ca06fa79 | 247 | return err; |
b79cb653 ST |
248 | } |
249 | ||
250 | return 0; | |
251 | } | |
252 | ||
ca06fa79 | 253 | static int cx24123_i2c_readreg(struct cx24123_state *state, u8 i2c_addr, u8 reg) |
b79cb653 ST |
254 | { |
255 | int ret; | |
ca06fa79 | 256 | u8 b = 0; |
b79cb653 | 257 | struct i2c_msg msg[] = { |
ca06fa79 PB |
258 | { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 }, |
259 | { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &b, .len = 1 } | |
b79cb653 ST |
260 | }; |
261 | ||
262 | ret = i2c_transfer(state->i2c, msg, 2); | |
263 | ||
264 | if (ret != 2) { | |
ca06fa79 | 265 | err("%s: reg=0x%x (error=%d)\n", __func__, reg, ret); |
b79cb653 ST |
266 | return ret; |
267 | } | |
268 | ||
ca06fa79 | 269 | /* printk(KERN_DEBUG "rd(%02x): %02x %02x\n", i2c_addr, reg, b); */ |
caf970e0 | 270 | |
ca06fa79 | 271 | return b; |
b79cb653 ST |
272 | } |
273 | ||
ca06fa79 PB |
274 | #define cx24123_readreg(state, reg) \ |
275 | cx24123_i2c_readreg(state, state->config->demod_address, reg) | |
276 | #define cx24123_writereg(state, reg, val) \ | |
277 | cx24123_i2c_writereg(state, state->config->demod_address, reg, val) | |
278 | ||
93504abf | 279 | static int cx24123_set_inversion(struct cx24123_state *state, |
0df289a2 | 280 | enum fe_spectral_inversion inversion) |
b79cb653 | 281 | { |
0e4558ab YP |
282 | u8 nom_reg = cx24123_readreg(state, 0x0e); |
283 | u8 auto_reg = cx24123_readreg(state, 0x10); | |
284 | ||
b79cb653 ST |
285 | switch (inversion) { |
286 | case INVERSION_OFF: | |
ca06fa79 | 287 | dprintk("inversion off\n"); |
0e4558ab YP |
288 | cx24123_writereg(state, 0x0e, nom_reg & ~0x80); |
289 | cx24123_writereg(state, 0x10, auto_reg | 0x80); | |
b79cb653 ST |
290 | break; |
291 | case INVERSION_ON: | |
ca06fa79 | 292 | dprintk("inversion on\n"); |
0e4558ab YP |
293 | cx24123_writereg(state, 0x0e, nom_reg | 0x80); |
294 | cx24123_writereg(state, 0x10, auto_reg | 0x80); | |
b79cb653 ST |
295 | break; |
296 | case INVERSION_AUTO: | |
ca06fa79 | 297 | dprintk("inversion auto\n"); |
0e4558ab | 298 | cx24123_writereg(state, 0x10, auto_reg & ~0x80); |
b79cb653 ST |
299 | break; |
300 | default: | |
301 | return -EINVAL; | |
302 | } | |
303 | ||
304 | return 0; | |
305 | } | |
306 | ||
93504abf | 307 | static int cx24123_get_inversion(struct cx24123_state *state, |
0df289a2 | 308 | enum fe_spectral_inversion *inversion) |
b79cb653 ST |
309 | { |
310 | u8 val; | |
311 | ||
312 | val = cx24123_readreg(state, 0x1b) >> 7; | |
313 | ||
caf970e0 | 314 | if (val == 0) { |
ca06fa79 | 315 | dprintk("read inversion off\n"); |
e3b152bc | 316 | *inversion = INVERSION_OFF; |
caf970e0 | 317 | } else { |
ca06fa79 | 318 | dprintk("read inversion on\n"); |
e3b152bc | 319 | *inversion = INVERSION_ON; |
caf970e0 | 320 | } |
b79cb653 ST |
321 | |
322 | return 0; | |
323 | } | |
324 | ||
0df289a2 | 325 | static int cx24123_set_fec(struct cx24123_state *state, enum fe_code_rate fec) |
b79cb653 | 326 | { |
0e4558ab YP |
327 | u8 nom_reg = cx24123_readreg(state, 0x0e) & ~0x07; |
328 | ||
830e4b55 | 329 | if (((int)fec < FEC_NONE) || (fec > FEC_AUTO)) |
e3b152bc | 330 | fec = FEC_AUTO; |
b79cb653 | 331 | |
d12a9b91 | 332 | /* Set the soft decision threshold */ |
93504abf ST |
333 | if (fec == FEC_1_2) |
334 | cx24123_writereg(state, 0x43, | |
335 | cx24123_readreg(state, 0x43) | 0x01); | |
d12a9b91 | 336 | else |
93504abf ST |
337 | cx24123_writereg(state, 0x43, |
338 | cx24123_readreg(state, 0x43) & ~0x01); | |
d12a9b91 | 339 | |
b79cb653 | 340 | switch (fec) { |
b79cb653 | 341 | case FEC_1_2: |
ca06fa79 | 342 | dprintk("set FEC to 1/2\n"); |
0e4558ab YP |
343 | cx24123_writereg(state, 0x0e, nom_reg | 0x01); |
344 | cx24123_writereg(state, 0x0f, 0x02); | |
345 | break; | |
b79cb653 | 346 | case FEC_2_3: |
ca06fa79 | 347 | dprintk("set FEC to 2/3\n"); |
0e4558ab YP |
348 | cx24123_writereg(state, 0x0e, nom_reg | 0x02); |
349 | cx24123_writereg(state, 0x0f, 0x04); | |
350 | break; | |
b79cb653 | 351 | case FEC_3_4: |
ca06fa79 | 352 | dprintk("set FEC to 3/4\n"); |
0e4558ab YP |
353 | cx24123_writereg(state, 0x0e, nom_reg | 0x03); |
354 | cx24123_writereg(state, 0x0f, 0x08); | |
355 | break; | |
356 | case FEC_4_5: | |
ca06fa79 | 357 | dprintk("set FEC to 4/5\n"); |
0e4558ab YP |
358 | cx24123_writereg(state, 0x0e, nom_reg | 0x04); |
359 | cx24123_writereg(state, 0x0f, 0x10); | |
360 | break; | |
361 | case FEC_5_6: | |
ca06fa79 | 362 | dprintk("set FEC to 5/6\n"); |
0e4558ab YP |
363 | cx24123_writereg(state, 0x0e, nom_reg | 0x05); |
364 | cx24123_writereg(state, 0x0f, 0x20); | |
365 | break; | |
366 | case FEC_6_7: | |
ca06fa79 | 367 | dprintk("set FEC to 6/7\n"); |
0e4558ab YP |
368 | cx24123_writereg(state, 0x0e, nom_reg | 0x06); |
369 | cx24123_writereg(state, 0x0f, 0x40); | |
370 | break; | |
371 | case FEC_7_8: | |
ca06fa79 | 372 | dprintk("set FEC to 7/8\n"); |
0e4558ab YP |
373 | cx24123_writereg(state, 0x0e, nom_reg | 0x07); |
374 | cx24123_writereg(state, 0x0f, 0x80); | |
375 | break; | |
b79cb653 | 376 | case FEC_AUTO: |
ca06fa79 | 377 | dprintk("set FEC to auto\n"); |
0e4558ab YP |
378 | cx24123_writereg(state, 0x0f, 0xfe); |
379 | break; | |
b79cb653 ST |
380 | default: |
381 | return -EOPNOTSUPP; | |
382 | } | |
0e4558ab YP |
383 | |
384 | return 0; | |
b79cb653 ST |
385 | } |
386 | ||
0df289a2 | 387 | static int cx24123_get_fec(struct cx24123_state *state, enum fe_code_rate *fec) |
b79cb653 | 388 | { |
e3b152bc | 389 | int ret; |
b79cb653 | 390 | |
93504abf | 391 | ret = cx24123_readreg(state, 0x1b); |
e3b152bc JS |
392 | if (ret < 0) |
393 | return ret; | |
a74b51fc VC |
394 | ret = ret & 0x07; |
395 | ||
396 | switch (ret) { | |
b79cb653 | 397 | case 1: |
e3b152bc JS |
398 | *fec = FEC_1_2; |
399 | break; | |
a74b51fc | 400 | case 2: |
e3b152bc JS |
401 | *fec = FEC_2_3; |
402 | break; | |
a74b51fc | 403 | case 3: |
e3b152bc JS |
404 | *fec = FEC_3_4; |
405 | break; | |
a74b51fc | 406 | case 4: |
e3b152bc JS |
407 | *fec = FEC_4_5; |
408 | break; | |
a74b51fc | 409 | case 5: |
e3b152bc JS |
410 | *fec = FEC_5_6; |
411 | break; | |
a74b51fc VC |
412 | case 6: |
413 | *fec = FEC_6_7; | |
414 | break; | |
b79cb653 | 415 | case 7: |
e3b152bc JS |
416 | *fec = FEC_7_8; |
417 | break; | |
b79cb653 | 418 | default: |
0e4558ab YP |
419 | /* this can happen when there's no lock */ |
420 | *fec = FEC_NONE; | |
b79cb653 ST |
421 | } |
422 | ||
e3b152bc | 423 | return 0; |
b79cb653 ST |
424 | } |
425 | ||
0e4558ab YP |
426 | /* Approximation of closest integer of log2(a/b). It actually gives the |
427 | lowest integer i such that 2^i >= round(a/b) */ | |
428 | static u32 cx24123_int_log2(u32 a, u32 b) | |
429 | { | |
430 | u32 exp, nearest = 0; | |
431 | u32 div = a / b; | |
93504abf ST |
432 | if (a % b >= b / 2) |
433 | ++div; | |
95c52069 | 434 | if (div < (1UL << 31)) { |
93504abf | 435 | for (exp = 1; div > exp; nearest++) |
0e4558ab YP |
436 | exp += exp; |
437 | } | |
438 | return nearest; | |
439 | } | |
440 | ||
93504abf | 441 | static int cx24123_set_symbolrate(struct cx24123_state *state, u32 srate) |
b79cb653 | 442 | { |
752a62b2 MCC |
443 | u64 tmp; |
444 | u32 sample_rate, ratio, sample_gain; | |
a74b51fc VC |
445 | u8 pll_mult; |
446 | ||
447 | /* check if symbol rate is within limits */ | |
dea74869 PB |
448 | if ((srate > state->frontend.ops.info.symbol_rate_max) || |
449 | (srate < state->frontend.ops.info.symbol_rate_min)) | |
1ebcad77 | 450 | return -EOPNOTSUPP; |
a74b51fc VC |
451 | |
452 | /* choose the sampling rate high enough for the required operation, | |
453 | while optimizing the power consumed by the demodulator */ | |
454 | if (srate < (XTAL*2)/2) | |
455 | pll_mult = 2; | |
456 | else if (srate < (XTAL*3)/2) | |
457 | pll_mult = 3; | |
458 | else if (srate < (XTAL*4)/2) | |
459 | pll_mult = 4; | |
460 | else if (srate < (XTAL*5)/2) | |
461 | pll_mult = 5; | |
462 | else if (srate < (XTAL*6)/2) | |
463 | pll_mult = 6; | |
464 | else if (srate < (XTAL*7)/2) | |
465 | pll_mult = 7; | |
466 | else if (srate < (XTAL*8)/2) | |
467 | pll_mult = 8; | |
468 | else | |
469 | pll_mult = 9; | |
470 | ||
471 | ||
472 | sample_rate = pll_mult * XTAL; | |
b79cb653 | 473 | |
752a62b2 | 474 | /* SYSSymbolRate[21:0] = (srate << 23) / sample_rate */ |
a74b51fc | 475 | |
752a62b2 MCC |
476 | tmp = ((u64)srate) << 23; |
477 | do_div(tmp, sample_rate); | |
478 | ratio = (u32) tmp; | |
a74b51fc VC |
479 | |
480 | cx24123_writereg(state, 0x01, pll_mult * 6); | |
481 | ||
93504abf ST |
482 | cx24123_writereg(state, 0x08, (ratio >> 16) & 0x3f); |
483 | cx24123_writereg(state, 0x09, (ratio >> 8) & 0xff); | |
484 | cx24123_writereg(state, 0x0a, ratio & 0xff); | |
a74b51fc | 485 | |
0e4558ab YP |
486 | /* also set the demodulator sample gain */ |
487 | sample_gain = cx24123_int_log2(sample_rate, srate); | |
488 | tmp = cx24123_readreg(state, 0x0c) & ~0xe0; | |
489 | cx24123_writereg(state, 0x0c, tmp | sample_gain << 5); | |
490 | ||
ca06fa79 PB |
491 | dprintk("srate=%d, ratio=0x%08x, sample_rate=%i sample_gain=%d\n", |
492 | srate, ratio, sample_rate, sample_gain); | |
b79cb653 ST |
493 | |
494 | return 0; | |
495 | } | |
496 | ||
497 | /* | |
93504abf ST |
498 | * Based on the required frequency and symbolrate, the tuner AGC has |
499 | * to be configured and the correct band selected. | |
500 | * Calculate those values. | |
b79cb653 | 501 | */ |
a73efc05 | 502 | static int cx24123_pll_calculate(struct dvb_frontend *fe) |
b79cb653 | 503 | { |
a73efc05 | 504 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
b79cb653 | 505 | struct cx24123_state *state = fe->demodulator_priv; |
e3b152bc JS |
506 | u32 ndiv = 0, adiv = 0, vco_div = 0; |
507 | int i = 0; | |
a74b51fc | 508 | int pump = 2; |
70047f9c | 509 | int band = 0; |
0496daa7 | 510 | int num_bands = ARRAY_SIZE(cx24123_bandselect_vals); |
93504abf ST |
511 | struct cx24123_bandselect_val *bsv = NULL; |
512 | struct cx24123_AGC_val *agcv = NULL; | |
b79cb653 ST |
513 | |
514 | /* Defaults for low freq, low rate */ | |
515 | state->VCAarg = cx24123_AGC_vals[0].VCAprogdata; | |
516 | state->VGAarg = cx24123_AGC_vals[0].VGAprogdata; | |
517 | state->bandselectarg = cx24123_bandselect_vals[0].progdata; | |
518 | vco_div = cx24123_bandselect_vals[0].VCOdivider; | |
519 | ||
93504abf ST |
520 | /* For the given symbol rate, determine the VCA, VGA and |
521 | * FILTUNE programming bits */ | |
522 | for (i = 0; i < ARRAY_SIZE(cx24123_AGC_vals); i++) { | |
523 | agcv = &cx24123_AGC_vals[i]; | |
a73efc05 MCC |
524 | if ((agcv->symbolrate_low <= p->symbol_rate) && |
525 | (agcv->symbolrate_high >= p->symbol_rate)) { | |
93504abf ST |
526 | state->VCAarg = agcv->VCAprogdata; |
527 | state->VGAarg = agcv->VGAprogdata; | |
528 | state->FILTune = agcv->FILTune; | |
b79cb653 ST |
529 | } |
530 | } | |
531 | ||
70047f9c | 532 | /* determine the band to use */ |
93504abf ST |
533 | if (force_band < 1 || force_band > num_bands) { |
534 | for (i = 0; i < num_bands; i++) { | |
535 | bsv = &cx24123_bandselect_vals[i]; | |
536 | if ((bsv->freq_low <= p->frequency) && | |
537 | (bsv->freq_high >= p->frequency)) | |
70047f9c | 538 | band = i; |
b79cb653 | 539 | } |
93504abf | 540 | } else |
70047f9c YP |
541 | band = force_band - 1; |
542 | ||
543 | state->bandselectarg = cx24123_bandselect_vals[band].progdata; | |
544 | vco_div = cx24123_bandselect_vals[band].VCOdivider; | |
545 | ||
546 | /* determine the charge pump current */ | |
93504abf ST |
547 | if (p->frequency < (cx24123_bandselect_vals[band].freq_low + |
548 | cx24123_bandselect_vals[band].freq_high) / 2) | |
70047f9c YP |
549 | pump = 0x01; |
550 | else | |
551 | pump = 0x02; | |
b79cb653 ST |
552 | |
553 | /* Determine the N/A dividers for the requested lband freq (in kHz). */ | |
93504abf ST |
554 | /* Note: the reference divider R=10, frequency is in KHz, |
555 | * XTAL is in Hz */ | |
556 | ndiv = (((p->frequency * vco_div * 10) / | |
557 | (2 * XTAL / 1000)) / 32) & 0x1ff; | |
558 | adiv = (((p->frequency * vco_div * 10) / | |
559 | (2 * XTAL / 1000)) % 32) & 0x1f; | |
b79cb653 | 560 | |
9b5a4a67 ST |
561 | if (adiv == 0 && ndiv > 0) |
562 | ndiv--; | |
b79cb653 | 563 | |
93504abf ST |
564 | /* control bits 11, refdiv 11, charge pump polarity 1, |
565 | * charge pump current, ndiv, adiv */ | |
566 | state->pllarg = (3 << 19) | (3 << 17) | (1 << 16) | | |
567 | (pump << 14) | (ndiv << 5) | adiv; | |
b79cb653 ST |
568 | |
569 | return 0; | |
570 | } | |
571 | ||
572 | /* | |
573 | * Tuner data is 21 bits long, must be left-aligned in data. | |
93504abf ST |
574 | * Tuner cx24109 is written through a dedicated 3wire interface |
575 | * on the demod chip. | |
b79cb653 | 576 | */ |
31b4f32c | 577 | static int cx24123_pll_writereg(struct dvb_frontend *fe, u32 data) |
b79cb653 ST |
578 | { |
579 | struct cx24123_state *state = fe->demodulator_priv; | |
0144f314 | 580 | unsigned long timeout; |
b79cb653 | 581 | |
ca06fa79 | 582 | dprintk("pll writereg called, data=0x%08x\n", data); |
caf970e0 | 583 | |
b79cb653 ST |
584 | /* align the 21 bytes into to bit23 boundary */ |
585 | data = data << 3; | |
586 | ||
587 | /* Reset the demod pll word length to 0x15 bits */ | |
588 | cx24123_writereg(state, 0x21, 0x15); | |
589 | ||
b79cb653 | 590 | /* write the msb 8 bits, wait for the send to be completed */ |
0144f314 | 591 | timeout = jiffies + msecs_to_jiffies(40); |
e3b152bc | 592 | cx24123_writereg(state, 0x22, (data >> 16) & 0xff); |
0144f314 ST |
593 | while ((cx24123_readreg(state, 0x20) & 0x40) == 0) { |
594 | if (time_after(jiffies, timeout)) { | |
ca06fa79 PB |
595 | err("%s: demodulator is not responding, "\ |
596 | "possibly hung, aborting.\n", __func__); | |
b79cb653 ST |
597 | return -EREMOTEIO; |
598 | } | |
0144f314 | 599 | msleep(10); |
b79cb653 ST |
600 | } |
601 | ||
b79cb653 | 602 | /* send another 8 bytes, wait for the send to be completed */ |
0144f314 | 603 | timeout = jiffies + msecs_to_jiffies(40); |
93504abf | 604 | cx24123_writereg(state, 0x22, (data >> 8) & 0xff); |
0144f314 ST |
605 | while ((cx24123_readreg(state, 0x20) & 0x40) == 0) { |
606 | if (time_after(jiffies, timeout)) { | |
ca06fa79 PB |
607 | err("%s: demodulator is not responding, "\ |
608 | "possibly hung, aborting.\n", __func__); | |
b79cb653 ST |
609 | return -EREMOTEIO; |
610 | } | |
0144f314 | 611 | msleep(10); |
b79cb653 ST |
612 | } |
613 | ||
93504abf ST |
614 | /* send the lower 5 bits of this byte, padded with 3 LBB, |
615 | * wait for the send to be completed */ | |
0144f314 | 616 | timeout = jiffies + msecs_to_jiffies(40); |
93504abf | 617 | cx24123_writereg(state, 0x22, (data) & 0xff); |
0144f314 ST |
618 | while ((cx24123_readreg(state, 0x20) & 0x80)) { |
619 | if (time_after(jiffies, timeout)) { | |
ca06fa79 PB |
620 | err("%s: demodulator is not responding," \ |
621 | "possibly hung, aborting.\n", __func__); | |
b79cb653 ST |
622 | return -EREMOTEIO; |
623 | } | |
0144f314 | 624 | msleep(10); |
b79cb653 ST |
625 | } |
626 | ||
627 | /* Trigger the demod to configure the tuner */ | |
628 | cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) | 2); | |
629 | cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) & 0xfd); | |
630 | ||
631 | return 0; | |
632 | } | |
633 | ||
a73efc05 | 634 | static int cx24123_pll_tune(struct dvb_frontend *fe) |
b79cb653 | 635 | { |
a73efc05 | 636 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
b79cb653 | 637 | struct cx24123_state *state = fe->demodulator_priv; |
a74b51fc VC |
638 | u8 val; |
639 | ||
640 | dprintk("frequency=%i\n", p->frequency); | |
b79cb653 | 641 | |
a73efc05 | 642 | if (cx24123_pll_calculate(fe) != 0) { |
f8d5219d | 643 | err("%s: cx24123_pll_calculate failed\n", __func__); |
b79cb653 ST |
644 | return -EINVAL; |
645 | } | |
646 | ||
647 | /* Write the new VCO/VGA */ | |
31b4f32c MCC |
648 | cx24123_pll_writereg(fe, state->VCAarg); |
649 | cx24123_pll_writereg(fe, state->VGAarg); | |
b79cb653 ST |
650 | |
651 | /* Write the new bandselect and pll args */ | |
31b4f32c MCC |
652 | cx24123_pll_writereg(fe, state->bandselectarg); |
653 | cx24123_pll_writereg(fe, state->pllarg); | |
b79cb653 | 654 | |
a74b51fc VC |
655 | /* set the FILTUNE voltage */ |
656 | val = cx24123_readreg(state, 0x28) & ~0x3; | |
657 | cx24123_writereg(state, 0x27, state->FILTune >> 2); | |
658 | cx24123_writereg(state, 0x28, val | (state->FILTune & 0x3)); | |
659 | ||
ca06fa79 PB |
660 | dprintk("pll tune VCA=%d, band=%d, pll=%d\n", state->VCAarg, |
661 | state->bandselectarg, state->pllarg); | |
caf970e0 | 662 | |
b79cb653 ST |
663 | return 0; |
664 | } | |
665 | ||
ca06fa79 PB |
666 | |
667 | /* | |
668 | * 0x23: | |
669 | * [7:7] = BTI enabled | |
670 | * [6:6] = I2C repeater enabled | |
671 | * [5:5] = I2C repeater start | |
672 | * [0:0] = BTI start | |
673 | */ | |
674 | ||
675 | /* mode == 1 -> i2c-repeater, 0 -> bti */ | |
676 | static int cx24123_repeater_mode(struct cx24123_state *state, u8 mode, u8 start) | |
677 | { | |
678 | u8 r = cx24123_readreg(state, 0x23) & 0x1e; | |
679 | if (mode) | |
680 | r |= (1 << 6) | (start << 5); | |
681 | else | |
682 | r |= (1 << 7) | (start); | |
683 | return cx24123_writereg(state, 0x23, r); | |
684 | } | |
685 | ||
93504abf | 686 | static int cx24123_initfe(struct dvb_frontend *fe) |
b79cb653 ST |
687 | { |
688 | struct cx24123_state *state = fe->demodulator_priv; | |
689 | int i; | |
690 | ||
ca06fa79 | 691 | dprintk("init frontend\n"); |
caf970e0 | 692 | |
b79cb653 | 693 | /* Configure the demod to a good set of defaults */ |
0496daa7 | 694 | for (i = 0; i < ARRAY_SIZE(cx24123_regdata); i++) |
93504abf ST |
695 | cx24123_writereg(state, cx24123_regdata[i].reg, |
696 | cx24123_regdata[i].data); | |
b79cb653 | 697 | |
ef76856d | 698 | /* Set the LNB polarity */ |
93504abf ST |
699 | if (state->config->lnb_polarity) |
700 | cx24123_writereg(state, 0x32, | |
701 | cx24123_readreg(state, 0x32) | 0x02); | |
ef76856d | 702 | |
ca06fa79 | 703 | if (state->config->dont_use_pll) |
93504abf | 704 | cx24123_repeater_mode(state, 1, 0); |
ca06fa79 | 705 | |
b79cb653 ST |
706 | return 0; |
707 | } | |
708 | ||
93504abf | 709 | static int cx24123_set_voltage(struct dvb_frontend *fe, |
0df289a2 | 710 | enum fe_sec_voltage voltage) |
b79cb653 ST |
711 | { |
712 | struct cx24123_state *state = fe->demodulator_priv; | |
713 | u8 val; | |
714 | ||
cd20ca9f | 715 | val = cx24123_readreg(state, 0x29) & ~0x40; |
1c956a3a | 716 | |
cd20ca9f AQ |
717 | switch (voltage) { |
718 | case SEC_VOLTAGE_13: | |
ca06fa79 | 719 | dprintk("setting voltage 13V\n"); |
ccd214b2 | 720 | return cx24123_writereg(state, 0x29, val & 0x7f); |
cd20ca9f | 721 | case SEC_VOLTAGE_18: |
ca06fa79 | 722 | dprintk("setting voltage 18V\n"); |
ccd214b2 | 723 | return cx24123_writereg(state, 0x29, val | 0x80); |
ef76856d YP |
724 | case SEC_VOLTAGE_OFF: |
725 | /* already handled in cx88-dvb */ | |
726 | return 0; | |
cd20ca9f AQ |
727 | default: |
728 | return -EINVAL; | |
2028c71d | 729 | } |
1c956a3a VC |
730 | |
731 | return 0; | |
b79cb653 ST |
732 | } |
733 | ||
dce1dfc2 YP |
734 | /* wait for diseqc queue to become ready (or timeout) */ |
735 | static void cx24123_wait_for_diseqc(struct cx24123_state *state) | |
736 | { | |
737 | unsigned long timeout = jiffies + msecs_to_jiffies(200); | |
738 | while (!(cx24123_readreg(state, 0x29) & 0x40)) { | |
93504abf | 739 | if (time_after(jiffies, timeout)) { |
ca06fa79 PB |
740 | err("%s: diseqc queue not ready, " \ |
741 | "command may be lost.\n", __func__); | |
dce1dfc2 YP |
742 | break; |
743 | } | |
744 | msleep(10); | |
745 | } | |
746 | } | |
747 | ||
93504abf ST |
748 | static int cx24123_send_diseqc_msg(struct dvb_frontend *fe, |
749 | struct dvb_diseqc_master_cmd *cmd) | |
b79cb653 | 750 | { |
a74b51fc | 751 | struct cx24123_state *state = fe->demodulator_priv; |
cd20ca9f | 752 | int i, val, tone; |
a74b51fc | 753 | |
ca06fa79 | 754 | dprintk("\n"); |
b79cb653 | 755 | |
cd20ca9f AQ |
756 | /* stop continuous tone if enabled */ |
757 | tone = cx24123_readreg(state, 0x29); | |
758 | if (tone & 0x10) | |
759 | cx24123_writereg(state, 0x29, tone & ~0x50); | |
a74b51fc | 760 | |
dce1dfc2 YP |
761 | /* wait for diseqc queue ready */ |
762 | cx24123_wait_for_diseqc(state); | |
763 | ||
a74b51fc | 764 | /* select tone mode */ |
cd20ca9f | 765 | cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb); |
a74b51fc VC |
766 | |
767 | for (i = 0; i < cmd->msg_len; i++) | |
768 | cx24123_writereg(state, 0x2C + i, cmd->msg[i]); | |
769 | ||
770 | val = cx24123_readreg(state, 0x29); | |
93504abf ST |
771 | cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40) | |
772 | ((cmd->msg_len-3) & 3)); | |
a74b51fc | 773 | |
dce1dfc2 YP |
774 | /* wait for diseqc message to finish sending */ |
775 | cx24123_wait_for_diseqc(state); | |
a74b51fc | 776 | |
cd20ca9f | 777 | /* restart continuous tone if enabled */ |
93504abf | 778 | if (tone & 0x10) |
cd20ca9f | 779 | cx24123_writereg(state, 0x29, tone & ~0x40); |
cd20ca9f | 780 | |
a74b51fc VC |
781 | return 0; |
782 | } | |
783 | ||
93504abf | 784 | static int cx24123_diseqc_send_burst(struct dvb_frontend *fe, |
0df289a2 | 785 | enum fe_sec_mini_cmd burst) |
a74b51fc VC |
786 | { |
787 | struct cx24123_state *state = fe->demodulator_priv; | |
cd20ca9f | 788 | int val, tone; |
a74b51fc | 789 | |
ca06fa79 | 790 | dprintk("\n"); |
a74b51fc | 791 | |
cd20ca9f AQ |
792 | /* stop continuous tone if enabled */ |
793 | tone = cx24123_readreg(state, 0x29); | |
794 | if (tone & 0x10) | |
795 | cx24123_writereg(state, 0x29, tone & ~0x50); | |
a74b51fc | 796 | |
cd20ca9f | 797 | /* wait for diseqc queue ready */ |
dce1dfc2 YP |
798 | cx24123_wait_for_diseqc(state); |
799 | ||
a74b51fc | 800 | /* select tone mode */ |
cd20ca9f AQ |
801 | cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) | 0x4); |
802 | msleep(30); | |
a74b51fc | 803 | val = cx24123_readreg(state, 0x29); |
a74b51fc VC |
804 | if (burst == SEC_MINI_A) |
805 | cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x00)); | |
806 | else if (burst == SEC_MINI_B) | |
807 | cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x08)); | |
808 | else | |
809 | return -EINVAL; | |
810 | ||
dce1dfc2 | 811 | cx24123_wait_for_diseqc(state); |
cd20ca9f | 812 | cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb); |
a74b51fc | 813 | |
cd20ca9f | 814 | /* restart continuous tone if enabled */ |
93504abf | 815 | if (tone & 0x10) |
cd20ca9f | 816 | cx24123_writereg(state, 0x29, tone & ~0x40); |
93504abf | 817 | |
a74b51fc | 818 | return 0; |
b79cb653 ST |
819 | } |
820 | ||
0df289a2 | 821 | static int cx24123_read_status(struct dvb_frontend *fe, enum fe_status *status) |
b79cb653 ST |
822 | { |
823 | struct cx24123_state *state = fe->demodulator_priv; | |
b79cb653 | 824 | int sync = cx24123_readreg(state, 0x14); |
b79cb653 ST |
825 | |
826 | *status = 0; | |
ca06fa79 PB |
827 | if (state->config->dont_use_pll) { |
828 | u32 tun_status = 0; | |
829 | if (fe->ops.tuner_ops.get_status) | |
830 | fe->ops.tuner_ops.get_status(fe, &tun_status); | |
831 | if (tun_status & TUNER_STATUS_LOCKED) | |
832 | *status |= FE_HAS_SIGNAL; | |
833 | } else { | |
834 | int lock = cx24123_readreg(state, 0x20); | |
835 | if (lock & 0x01) | |
836 | *status |= FE_HAS_SIGNAL; | |
837 | } | |
838 | ||
a74b51fc | 839 | if (sync & 0x02) |
d93f8860 | 840 | *status |= FE_HAS_CARRIER; /* Phase locked */ |
b79cb653 ST |
841 | if (sync & 0x04) |
842 | *status |= FE_HAS_VITERBI; | |
d93f8860 MCC |
843 | |
844 | /* Reed-Solomon Status */ | |
b79cb653 | 845 | if (sync & 0x08) |
a74b51fc | 846 | *status |= FE_HAS_SYNC; |
b79cb653 | 847 | if (sync & 0x80) |
d93f8860 | 848 | *status |= FE_HAS_LOCK; /*Full Sync */ |
b79cb653 ST |
849 | |
850 | return 0; | |
851 | } | |
852 | ||
853 | /* | |
93504abf ST |
854 | * Configured to return the measurement of errors in blocks, |
855 | * because no UCBLOCKS value is available, so this value doubles up | |
856 | * to satisfy both measurements. | |
b79cb653 | 857 | */ |
ca06fa79 | 858 | static int cx24123_read_ber(struct dvb_frontend *fe, u32 *ber) |
b79cb653 ST |
859 | { |
860 | struct cx24123_state *state = fe->demodulator_priv; | |
861 | ||
18c053b3 YP |
862 | /* The true bit error rate is this value divided by |
863 | the window size (set as 256 * 255) */ | |
864 | *ber = ((cx24123_readreg(state, 0x1c) & 0x3f) << 16) | | |
b79cb653 | 865 | (cx24123_readreg(state, 0x1d) << 8 | |
18c053b3 | 866 | cx24123_readreg(state, 0x1e)); |
caf970e0 | 867 | |
ca06fa79 | 868 | dprintk("BER = %d\n", *ber); |
b79cb653 ST |
869 | |
870 | return 0; | |
871 | } | |
872 | ||
ca06fa79 PB |
873 | static int cx24123_read_signal_strength(struct dvb_frontend *fe, |
874 | u16 *signal_strength) | |
b79cb653 ST |
875 | { |
876 | struct cx24123_state *state = fe->demodulator_priv; | |
d93f8860 | 877 | |
93504abf ST |
878 | /* larger = better */ |
879 | *signal_strength = cx24123_readreg(state, 0x3b) << 8; | |
b79cb653 | 880 | |
ca06fa79 | 881 | dprintk("Signal strength = %d\n", *signal_strength); |
caf970e0 | 882 | |
b79cb653 ST |
883 | return 0; |
884 | } | |
885 | ||
ca06fa79 | 886 | static int cx24123_read_snr(struct dvb_frontend *fe, u16 *snr) |
b79cb653 ST |
887 | { |
888 | struct cx24123_state *state = fe->demodulator_priv; | |
b79cb653 | 889 | |
18c053b3 YP |
890 | /* Inverted raw Es/N0 count, totally bogus but better than the |
891 | BER threshold. */ | |
892 | *snr = 65535 - (((u16)cx24123_readreg(state, 0x18) << 8) | | |
893 | (u16)cx24123_readreg(state, 0x19)); | |
caf970e0 | 894 | |
ca06fa79 | 895 | dprintk("read S/N index = %d\n", *snr); |
caf970e0 | 896 | |
b79cb653 ST |
897 | return 0; |
898 | } | |
899 | ||
a73efc05 | 900 | static int cx24123_set_frontend(struct dvb_frontend *fe) |
b79cb653 ST |
901 | { |
902 | struct cx24123_state *state = fe->demodulator_priv; | |
a73efc05 | 903 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
b79cb653 | 904 | |
ca06fa79 | 905 | dprintk("\n"); |
caf970e0 | 906 | |
b79cb653 ST |
907 | if (state->config->set_ts_params) |
908 | state->config->set_ts_params(fe, 0); | |
909 | ||
93504abf | 910 | state->currentfreq = p->frequency; |
a73efc05 | 911 | state->currentsymbolrate = p->symbol_rate; |
b79cb653 ST |
912 | |
913 | cx24123_set_inversion(state, p->inversion); | |
a73efc05 MCC |
914 | cx24123_set_fec(state, p->fec_inner); |
915 | cx24123_set_symbolrate(state, p->symbol_rate); | |
ca06fa79 PB |
916 | |
917 | if (!state->config->dont_use_pll) | |
a73efc05 | 918 | cx24123_pll_tune(fe); |
ca06fa79 | 919 | else if (fe->ops.tuner_ops.set_params) |
14d24d14 | 920 | fe->ops.tuner_ops.set_params(fe); |
ca06fa79 PB |
921 | else |
922 | err("it seems I don't have a tuner..."); | |
b79cb653 | 923 | |
25985edc | 924 | /* Enable automatic acquisition and reset cycle */ |
e3b152bc | 925 | cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07)); |
b79cb653 ST |
926 | cx24123_writereg(state, 0x00, 0x10); |
927 | cx24123_writereg(state, 0x00, 0); | |
928 | ||
ca06fa79 PB |
929 | if (state->config->agc_callback) |
930 | state->config->agc_callback(fe); | |
931 | ||
b79cb653 ST |
932 | return 0; |
933 | } | |
934 | ||
7e3e68bc MCC |
935 | static int cx24123_get_frontend(struct dvb_frontend *fe, |
936 | struct dtv_frontend_properties *p) | |
b79cb653 ST |
937 | { |
938 | struct cx24123_state *state = fe->demodulator_priv; | |
939 | ||
ca06fa79 | 940 | dprintk("\n"); |
caf970e0 | 941 | |
b79cb653 | 942 | if (cx24123_get_inversion(state, &p->inversion) != 0) { |
ca06fa79 | 943 | err("%s: Failed to get inversion status\n", __func__); |
b79cb653 ST |
944 | return -EREMOTEIO; |
945 | } | |
a73efc05 | 946 | if (cx24123_get_fec(state, &p->fec_inner) != 0) { |
ca06fa79 | 947 | err("%s: Failed to get fec status\n", __func__); |
b79cb653 ST |
948 | return -EREMOTEIO; |
949 | } | |
950 | p->frequency = state->currentfreq; | |
a73efc05 | 951 | p->symbol_rate = state->currentsymbolrate; |
b79cb653 ST |
952 | |
953 | return 0; | |
954 | } | |
955 | ||
0df289a2 | 956 | static int cx24123_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone) |
b79cb653 ST |
957 | { |
958 | struct cx24123_state *state = fe->demodulator_priv; | |
959 | u8 val; | |
960 | ||
cd20ca9f AQ |
961 | /* wait for diseqc queue ready */ |
962 | cx24123_wait_for_diseqc(state); | |
1c956a3a | 963 | |
cd20ca9f | 964 | val = cx24123_readreg(state, 0x29) & ~0x40; |
1c956a3a | 965 | |
cd20ca9f AQ |
966 | switch (tone) { |
967 | case SEC_TONE_ON: | |
ca06fa79 | 968 | dprintk("setting tone on\n"); |
cd20ca9f AQ |
969 | return cx24123_writereg(state, 0x29, val | 0x10); |
970 | case SEC_TONE_OFF: | |
ca06fa79 | 971 | dprintk("setting tone off\n"); |
cd20ca9f AQ |
972 | return cx24123_writereg(state, 0x29, val & 0xef); |
973 | default: | |
ca06fa79 | 974 | err("CASE reached default with tone=%d\n", tone); |
cd20ca9f | 975 | return -EINVAL; |
b79cb653 | 976 | } |
1c956a3a VC |
977 | |
978 | return 0; | |
b79cb653 ST |
979 | } |
980 | ||
93504abf | 981 | static int cx24123_tune(struct dvb_frontend *fe, |
7e072221 | 982 | bool re_tune, |
174ff219 | 983 | unsigned int mode_flags, |
3ea96615 | 984 | unsigned int *delay, |
0df289a2 | 985 | enum fe_status *status) |
174ff219 YP |
986 | { |
987 | int retval = 0; | |
988 | ||
7e072221 | 989 | if (re_tune) |
a73efc05 | 990 | retval = cx24123_set_frontend(fe); |
174ff219 YP |
991 | |
992 | if (!(mode_flags & FE_TUNE_MODE_ONESHOT)) | |
993 | cx24123_read_status(fe, status); | |
994 | *delay = HZ/10; | |
995 | ||
996 | return retval; | |
997 | } | |
998 | ||
8d718e53 | 999 | static enum dvbfe_algo cx24123_get_algo(struct dvb_frontend *fe) |
174ff219 | 1000 | { |
27460adc | 1001 | return DVBFE_ALGO_HW; |
174ff219 YP |
1002 | } |
1003 | ||
93504abf | 1004 | static void cx24123_release(struct dvb_frontend *fe) |
b79cb653 | 1005 | { |
93504abf | 1006 | struct cx24123_state *state = fe->demodulator_priv; |
ca06fa79 PB |
1007 | dprintk("\n"); |
1008 | i2c_del_adapter(&state->tuner_i2c_adapter); | |
b79cb653 ST |
1009 | kfree(state); |
1010 | } | |
1011 | ||
ca06fa79 PB |
1012 | static int cx24123_tuner_i2c_tuner_xfer(struct i2c_adapter *i2c_adap, |
1013 | struct i2c_msg msg[], int num) | |
1014 | { | |
1015 | struct cx24123_state *state = i2c_get_adapdata(i2c_adap); | |
1016 | /* this repeater closes after the first stop */ | |
93504abf | 1017 | cx24123_repeater_mode(state, 1, 1); |
ca06fa79 PB |
1018 | return i2c_transfer(state->i2c, msg, num); |
1019 | } | |
1020 | ||
1021 | static u32 cx24123_tuner_i2c_func(struct i2c_adapter *adapter) | |
1022 | { | |
1023 | return I2C_FUNC_I2C; | |
1024 | } | |
1025 | ||
6ac8b81e | 1026 | static const struct i2c_algorithm cx24123_tuner_i2c_algo = { |
ca06fa79 PB |
1027 | .master_xfer = cx24123_tuner_i2c_tuner_xfer, |
1028 | .functionality = cx24123_tuner_i2c_func, | |
1029 | }; | |
1030 | ||
1031 | struct i2c_adapter * | |
1032 | cx24123_get_tuner_i2c_adapter(struct dvb_frontend *fe) | |
1033 | { | |
1034 | struct cx24123_state *state = fe->demodulator_priv; | |
1035 | return &state->tuner_i2c_adapter; | |
1036 | } | |
1037 | EXPORT_SYMBOL(cx24123_get_tuner_i2c_adapter); | |
1038 | ||
bd336e63 | 1039 | static const struct dvb_frontend_ops cx24123_ops; |
b79cb653 | 1040 | |
93504abf ST |
1041 | struct dvb_frontend *cx24123_attach(const struct cx24123_config *config, |
1042 | struct i2c_adapter *i2c) | |
b79cb653 | 1043 | { |
8420fa7e | 1044 | /* allocate memory for the internal state */ |
ca06fa79 PB |
1045 | struct cx24123_state *state = |
1046 | kzalloc(sizeof(struct cx24123_state), GFP_KERNEL); | |
b79cb653 | 1047 | |
ca06fa79 | 1048 | dprintk("\n"); |
b79cb653 | 1049 | if (state == NULL) { |
8420fa7e | 1050 | err("Unable to kzalloc\n"); |
b79cb653 ST |
1051 | goto error; |
1052 | } | |
1053 | ||
1054 | /* setup the state */ | |
1055 | state->config = config; | |
1056 | state->i2c = i2c; | |
b79cb653 ST |
1057 | |
1058 | /* check if the demod is there */ | |
ca06fa79 PB |
1059 | state->demod_rev = cx24123_readreg(state, 0x00); |
1060 | switch (state->demod_rev) { | |
93504abf ST |
1061 | case 0xe1: |
1062 | info("detected CX24123C\n"); | |
1063 | break; | |
1064 | case 0xd1: | |
1065 | info("detected CX24123\n"); | |
1066 | break; | |
ca06fa79 PB |
1067 | default: |
1068 | err("wrong demod revision: %x\n", state->demod_rev); | |
b79cb653 ST |
1069 | goto error; |
1070 | } | |
1071 | ||
1072 | /* create dvb_frontend */ | |
93504abf ST |
1073 | memcpy(&state->frontend.ops, &cx24123_ops, |
1074 | sizeof(struct dvb_frontend_ops)); | |
b79cb653 | 1075 | state->frontend.demodulator_priv = state; |
ca06fa79 | 1076 | |
93504abf ST |
1077 | /* create tuner i2c adapter */ |
1078 | if (config->dont_use_pll) | |
1079 | cx24123_repeater_mode(state, 1, 0); | |
ca06fa79 | 1080 | |
c0decac1 | 1081 | strscpy(state->tuner_i2c_adapter.name, "CX24123 tuner I2C bus", |
1d434012 | 1082 | sizeof(state->tuner_i2c_adapter.name)); |
ca06fa79 PB |
1083 | state->tuner_i2c_adapter.algo = &cx24123_tuner_i2c_algo; |
1084 | state->tuner_i2c_adapter.algo_data = NULL; | |
fdc6b388 | 1085 | state->tuner_i2c_adapter.dev.parent = i2c->dev.parent; |
ca06fa79 PB |
1086 | i2c_set_adapdata(&state->tuner_i2c_adapter, state); |
1087 | if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) { | |
93504abf | 1088 | err("tuner i2c bus could not be initialized\n"); |
ca06fa79 PB |
1089 | goto error; |
1090 | } | |
1091 | ||
b79cb653 ST |
1092 | return &state->frontend; |
1093 | ||
1094 | error: | |
1095 | kfree(state); | |
1096 | ||
1097 | return NULL; | |
1098 | } | |
93504abf | 1099 | EXPORT_SYMBOL(cx24123_attach); |
b79cb653 | 1100 | |
bd336e63 | 1101 | static const struct dvb_frontend_ops cx24123_ops = { |
a73efc05 | 1102 | .delsys = { SYS_DVBS }, |
b79cb653 ST |
1103 | .info = { |
1104 | .name = "Conexant CX24123/CX24109", | |
f1b1eabf MCC |
1105 | .frequency_min_hz = 950 * MHz, |
1106 | .frequency_max_hz = 2150 * MHz, | |
1107 | .frequency_stepsize_hz = 1011 * kHz, | |
1108 | .frequency_tolerance_hz = 5 * MHz, | |
b79cb653 ST |
1109 | .symbol_rate_min = 1000000, |
1110 | .symbol_rate_max = 45000000, | |
1111 | .caps = FE_CAN_INVERSION_AUTO | | |
1112 | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | | |
0e4558ab YP |
1113 | FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | |
1114 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | | |
b79cb653 ST |
1115 | FE_CAN_QPSK | FE_CAN_RECOVER |
1116 | }, | |
1117 | ||
1118 | .release = cx24123_release, | |
1119 | ||
1120 | .init = cx24123_initfe, | |
a73efc05 MCC |
1121 | .set_frontend = cx24123_set_frontend, |
1122 | .get_frontend = cx24123_get_frontend, | |
b79cb653 ST |
1123 | .read_status = cx24123_read_status, |
1124 | .read_ber = cx24123_read_ber, | |
1125 | .read_signal_strength = cx24123_read_signal_strength, | |
1126 | .read_snr = cx24123_read_snr, | |
b79cb653 | 1127 | .diseqc_send_master_cmd = cx24123_send_diseqc_msg, |
a74b51fc | 1128 | .diseqc_send_burst = cx24123_diseqc_send_burst, |
b79cb653 ST |
1129 | .set_tone = cx24123_set_tone, |
1130 | .set_voltage = cx24123_set_voltage, | |
174ff219 YP |
1131 | .tune = cx24123_tune, |
1132 | .get_frontend_algo = cx24123_get_algo, | |
b79cb653 ST |
1133 | }; |
1134 | ||
ca06fa79 PB |
1135 | MODULE_DESCRIPTION("DVB Frontend module for Conexant " \ |
1136 | "CX24123/CX24109/CX24113 hardware"); | |
b79cb653 ST |
1137 | MODULE_AUTHOR("Steven Toth"); |
1138 | MODULE_LICENSE("GPL"); | |
1139 |